linux/drivers/clocksource/time-armada-370-xp.c
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   1/*
   2 * Marvell Armada 370/XP SoC timer handling.
   3 *
   4 * Copyright (C) 2012 Marvell
   5 *
   6 * Lior Amsalem <alior@marvell.com>
   7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9 *
  10 * This file is licensed under the terms of the GNU General Public
  11 * License version 2.  This program is licensed "as is" without any
  12 * warranty of any kind, whether express or implied.
  13 *
  14 * Timer 0 is used as free-running clocksource, while timer 1 is
  15 * used as clock_event_device.
  16 */
  17
  18#include <linux/init.h>
  19#include <linux/platform_device.h>
  20#include <linux/kernel.h>
  21#include <linux/timer.h>
  22#include <linux/clockchips.h>
  23#include <linux/interrupt.h>
  24#include <linux/of.h>
  25#include <linux/of_irq.h>
  26#include <linux/of_address.h>
  27#include <linux/irq.h>
  28#include <linux/module.h>
  29#include <asm/sched_clock.h>
  30
  31/*
  32 * Timer block registers.
  33 */
  34#define TIMER_CTRL_OFF          0x0000
  35#define  TIMER0_EN               0x0001
  36#define  TIMER0_RELOAD_EN        0x0002
  37#define  TIMER0_25MHZ            0x0800
  38#define  TIMER0_DIV(div)         ((div) << 19)
  39#define  TIMER1_EN               0x0004
  40#define  TIMER1_RELOAD_EN        0x0008
  41#define  TIMER1_25MHZ            0x1000
  42#define  TIMER1_DIV(div)         ((div) << 22)
  43#define TIMER_EVENTS_STATUS     0x0004
  44#define  TIMER0_CLR_MASK         (~0x1)
  45#define  TIMER1_CLR_MASK         (~0x100)
  46#define TIMER0_RELOAD_OFF       0x0010
  47#define TIMER0_VAL_OFF          0x0014
  48#define TIMER1_RELOAD_OFF       0x0018
  49#define TIMER1_VAL_OFF          0x001c
  50
  51/* Global timers are connected to the coherency fabric clock, and the
  52   below divider reduces their incrementing frequency. */
  53#define TIMER_DIVIDER_SHIFT     5
  54#define TIMER_DIVIDER           (1 << TIMER_DIVIDER_SHIFT)
  55
  56/*
  57 * SoC-specific data.
  58 */
  59static void __iomem *timer_base;
  60static int timer_irq;
  61
  62/*
  63 * Number of timer ticks per jiffy.
  64 */
  65static u32 ticks_per_jiffy;
  66
  67static u32 notrace armada_370_xp_read_sched_clock(void)
  68{
  69        return ~readl(timer_base + TIMER0_VAL_OFF);
  70}
  71
  72/*
  73 * Clockevent handling.
  74 */
  75static int
  76armada_370_xp_clkevt_next_event(unsigned long delta,
  77                                struct clock_event_device *dev)
  78{
  79        u32 u;
  80
  81        /*
  82         * Clear clockevent timer interrupt.
  83         */
  84        writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS);
  85
  86        /*
  87         * Setup new clockevent timer value.
  88         */
  89        writel(delta, timer_base + TIMER1_VAL_OFF);
  90
  91        /*
  92         * Enable the timer.
  93         */
  94        u = readl(timer_base + TIMER_CTRL_OFF);
  95        u = ((u & ~TIMER1_RELOAD_EN) | TIMER1_EN |
  96             TIMER1_DIV(TIMER_DIVIDER_SHIFT));
  97        writel(u, timer_base + TIMER_CTRL_OFF);
  98
  99        return 0;
 100}
 101
 102static void
 103armada_370_xp_clkevt_mode(enum clock_event_mode mode,
 104                          struct clock_event_device *dev)
 105{
 106        u32 u;
 107
 108        if (mode == CLOCK_EVT_MODE_PERIODIC) {
 109                /*
 110                 * Setup timer to fire at 1/HZ intervals.
 111                 */
 112                writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
 113                writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
 114
 115                /*
 116                 * Enable timer.
 117                 */
 118                u = readl(timer_base + TIMER_CTRL_OFF);
 119
 120                writel((u | TIMER1_EN | TIMER1_RELOAD_EN |
 121                        TIMER1_DIV(TIMER_DIVIDER_SHIFT)),
 122                       timer_base + TIMER_CTRL_OFF);
 123        } else {
 124                /*
 125                 * Disable timer.
 126                 */
 127                u = readl(timer_base + TIMER_CTRL_OFF);
 128                writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
 129
 130                /*
 131                 * ACK pending timer interrupt.
 132                 */
 133                writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS);
 134
 135        }
 136}
 137
 138static struct clock_event_device armada_370_xp_clkevt = {
 139        .name           = "armada_370_xp_tick",
 140        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 141        .shift          = 32,
 142        .rating         = 300,
 143        .set_next_event = writel(features  103armada_1_CLR_MASK" class="sre3href="drivers/clocksource/time-ame-armadada-370-xp.c#L45" id="L451" cla1s="lin}MER_EVENTS_STATUS);
  66
  67irq"L99">_ritel" class="srirq"L99">_ref">clock_event_device   60stat dev)
  78{
/*
 110         * ACK poherecall ass="commen         * Disable timer.
  51ass="comment">                 */
writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STAT/
  94 ce arelse {
  94 ce arIMER_EVENTS_STAT/
  55
 "L94">  94 IRQ_HANDLEDe=armada_370_xpIRQ_HANDLEDcode=u" class="sref">u;
 136}
  98
 138static q"    clock_event_device armada_370_xp_clkevt = {
 140        .name           = "armada_370_xp_tick",
 141  flag  94 IRQF_DISABLEDe=armada_370_xpIRQF_DISABLEDCLOCK_EVT_FEAT_ONESHOTIRQF__STATe=armada_370_xpIRQF__STATada_1_CLR_MASK" class="sre3href="drivers/clocksource/time-time-arma1da-370-xp.c#L62" id="L621" cla16"line" name="L142"> 142  ommen  e=armada_370_xpommen  l" cass="sref""L94">  94 ce  134
  59static vnipada_370_xp_clkec vnipef">clock_event_device  (void)
  97        u32 u;
 138static ss="sr_narmada_370_xp_clkess="sr_narmline"lock_event_devicnp  .u;
  60static int="shref="+code=timer_bas="scode=u" class="sref">u;
  60statrepada_370_xp_clkerepcode=u" class="sref">u;
  97 np  .  94 of_find_>  p nablr_narmada_370_xp_clkeof_find_>  p nablr_narml" class="sref">writNULLada_370_xp_clkeNULL"sref">TIMER1_CLR_MASNULLada_370_xp_clkeNULL"sref">name           = 
  97 K,   94 of_iomap  .writnp  .  97 K, 
 134
 108     of_find_propert="+code=ticks_peof_find_propert=l" class="sref">writnp  .TIMER1_CLR_MASNULLada_370_xp_clkeNULL"sre)_EVT_MODE_PERIODIC) {
 */
  27                u = readl(timer_base + TIMER_CTRL_OFF);
 128                writel(TIMER1_EN   TIMER1_EN |  1" name="L97">  97 K, timer_base + TIMER_CTRL_OFF);
 120         ic int="shref="+code=timer_bas="scode=u"25000000f">TIMER_CTRL_OFF);
 123        } else {
 112                u="shref="+code=tim="scode=u"0f">TIMER_CTRL_OFF);
 133         repada_370_xp_clkerepcode=f""L94">  94 of_propert=s="sre       writnp  .  94 ="shref="+code=tim="scodeef">TIMER_CTRL_OFF);
 123         WARN_Oa href="+code=TIWARN_Oal" cl!"L97">  97 ="shref="+code=tim="scode=|="sref">TIMER1_ENrepada_370_xp_clkerepcode= 0IMER_EVENTS_STAT/
 117                u = readl(timer_base + TIMER_CTRL_OFF);
writel(writelTIMER1_EN |   77 lass="sref">readl(timer_base + TIMER_CTRL_OFF);
 128         ic int="shref="+code=timer_bas="scode=u""L97">  97 ="shref="+code=tim="scode=/="L54">  54#define TIMER_CTRL_OFF);
 136}
  90
  91        
 */
  92         s */
armad 138static q" _of_parse_her_map  .writnp  .TIMER_CTRL_OFF);
 134
  95 el( 108     ic int="shref="+code=timer_bas="scode="sref">timer_basehref="+code=TIMERlass="s/ 2)=/="L54">  54#href="+code=TIMERlass="f">TIMER_CTRL_OFF);
  66
/*
  88 scaleoheren     for k.h" class="pan class="comment">/*
  51ass="comment">                 */
  95 s">  ode=armada_370_xp_read_sches">  ode=armada_3l" class="sref">writce armada_370_x,">sh128         ic int="shref="+code=timer_bas="scodeef">TIMER_CTRL_OFF);
 101
/*
  93   es e-runn    pan>
/*
  74    d)"pan class="comment">/*
 125                 */
 106        TIMER1_CLR_MASK, timer_base + TIMER0_VAL_OFF);
  97        TIMER1_CLR_MASK, timer_base + TIMER0_VAL_OFF);
  98
  79        u = readl(timer_base + TIMER_CTRL_OFF);
  90
  97        writel((u 0~TIMER1_EN 0 TIMER1_RELOAD_EN |
 112         LOAD_0NTIMER1_DIV(TIME lass="sref">readl(timer_base + TIMER_CTRL_OFF);
TIMER_CTRL_OFF);
  94 a>);
);
readl(timer_base +  1name="L112"> 11name           =  112         ic int="shref="+code=timer_bas="scode,">rat">sh128         a>);
TIMER_CTRL_OFF);
 137
                /*
  51ass="comment">   >         en     (q * ACK p-t">/*n)"pan class="comment">/*
 110                 */
  97 s">  oq  oqreadlqar0"u" cl"L94">  94 ce aref">TIMER_CTRL_OFF);
  97 ce arelse {
  97 =pumass_ofhref="+code=tim=pumass_ofl" cl0ef">TIMER_CTRL_OFF);
  94 ce ar0_xp_tick",
 1e="L96" e=name="L112"> 112         ic int="shref="+code=timer_bas="scode,"1, 0xfffffffeef">TIMER_CTRL_OFF);
 136}
  66



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