linux/include/video/omapdss.h
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   1/*
   2 * Copyright (C) 2008 Nokia Corporation
   3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License version 2 as published by
   7 * the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program.  If not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18#ifndef __OMAP_OMAPDSS_H
  19#define __OMAP_OMAPDSS_H
  20
  21#include <linux/list.h>
  22#include <linux/kobject.h>
  23#include <linux/device.h>
  24
  25#define DISPC_IRQ_FRAMEDONE             (1 << 0)
  26#define DISPC_IRQ_VSYNC                 (1 << 1)
  27#define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
  28#define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
  29#define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
  30#define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
  31#define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
  32#define DISPC_IRQ_GFX_END_WIN           (1 << 7)
  33#define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
  34#define DISPC_IRQ_OCP_ERR               (1 << 9)
  35#define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
  36#define DISPC_IRQ_VID1_END_WIN          (1 << 11)
  37#define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
  38#define DISPC_IRQ_VID2_END_WIN          (1 << 13)
  39#define DISPC_IRQ_SYNC_LOST             (1 << 14)
  40#define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
  41#define DISPC_IRQ_WAKEUP                (1 << 16)
  42#define DISPC_IRQ_SYNC_LOST2            (1 << 17)
  43#define DISPC_IRQ_VSYNC2                (1 << 18)
  44#define DISPC_IRQ_VID3_END_WIN          (1 << 19)
  45#define DISPC_IRQ_VID3_FIFO_UNDERFLOW   (1 << 20)
  46#define DISPC_IRQ_ACBIAS_COUNT_STAT2    (1 << 21)
  47#define DISPC_IRQ_FRAMEDONE2            (1 << 22)
  48#define DISPC_IRQ_FRAMEDONEWB           (1 << 23)
  49#define DISPC_IRQ_FRAMEDONETV           (1 << 24)
  50#define DISPC_IRQ_WBBUFFEROVERFLOW      (1 << 25)
  51#define DISPC_IRQ_SYNC_LOST3            (1 << 27)
  52#define DISPC_IRQ_VSYNC3                (1 << 28)
  53#define DISPC_IRQ_ACBIAS_COUNT_STAT3    (1 << 29)
  54#define DISPC_IRQ_FRAMEDONE3            (1 << 30)
  55
  56struct omap_dss_device;
  57struct omap_overlay_manager;
  58struct snd_aes_iec958;
  59struct snd_cea_861_aud_if;
  60
  61enum omap_display_type {
  62        OMAP_DISPLAY_TYPE_NONE          = 0,
  63        OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
  64        OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
  65        OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
  66        OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
  67        OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
  68        OMAP_DISPLAY_TYPE_HDMI          = 1 << 5,
  69};
  70
  71enum omap_plane {
  72        OMAP_DSS_GFX    = 0,
  73        OMAP_DSS_VIDEO1 = 1,
  74        OMAP_DSS_VIDEO2 = 2,
  75        OMAP_DSS_VIDEO3 = 3,
  76        OMAP_DSS_WB     = 4,
  77};
  78
  79enum omap_channel {
  80        OMAP_DSS_CHANNEL_LCD    = 0,
  81        OMAP_DSS_CHANNEL_DIGIT  = 1,
  82        OMAP_DSS_CHANNEL_LCD2   = 2,
  83        OMAP_DSS_CHANNEL_LCD3   = 3,
  84};
  85
  86enum omap_color_mode {
  87        OMAP_DSS_COLOR_CLUT1    = 1 << 0,  /* BITMAP 1 */
  88        OMAP_DSS_COLOR_CLUT2    = 1 << 1,  /* BITMAP 2 */
  89        OMAP_DSS_COLOR_CLUT4    = 1 << 2,  /* BITMAP 4 */
  90        OMAP_DSS_COLOR_CLUT8    = 1 << 3,  /* BITMAP 8 */
  91        OMAP_DSS_COLOR_RGB12U   = 1 << 4,  /* RGB12, 16-bit container */
  92        OMAP_DSS_COLOR_ARGB16   = 1 << 5,  /* ARGB16 */
  93        OMAP_DSS_COLOR_RGB16    = 1 << 6,  /* RGB16 */
  94        OMAP_DSS_COLOR_RGB24U   = 1 << 7,  /* RGB24, 32-bit container */
  95        OMAP_DSS_COLOR_RGB24P   = 1 << 8,  /* RGB24, 24-bit container */
  96        OMAP_DSS_COLOR_YUV2     = 1 << 9,  /* YUV2 4:2:2 co-sited */
  97        OMAP_DSS_COLOR_UYVY     = 1 << 10, /* UYVY 4:2:2 co-sited */
  98        OMAP_DSS_COLOR_ARGB32   = 1 << 11, /* ARGB32 */
  99        OMAP_DSS_COLOR_RGBA32   = 1 << 12, /* RGBA32 */
 100        OMAP_DSS_COLOR_RGBX32   = 1 << 13, /* RGBx32 */
 101        OMAP_DSS_COLOR_NV12             = 1 << 14, /* NV12 format: YUV 4:2:0 */
 102        OMAP_DSS_COLOR_RGBA16           = 1 << 15, /* RGBA16 - 4444 */
 103        OMAP_DSS_COLOR_RGBX16           = 1 << 16, /* RGBx16 - 4444 */
 104        OMAP_DSS_COLOR_ARGB16_1555      = 1 << 17, /* ARGB16 - 1555 */
 105        OMAP_DSS_COLOR_XRGB16_1555      = 1 << 18, /* xRGB16 - 1555 */
 106};
 107
 108enum omap_dss_load_mode {
 109        OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
 110        OMAP_DSS_LOAD_CLUT_ONLY         = 1,
 111        OMAP_DSS_LOAD_FRAME_ONLY        = 2,
 112        OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
 113};
 114
 115enum omap_dss_trans_key_type {
 116        OMAP_DSS_COLOR_KEY_GFX_DST = 0,
 117        OMAP_DSS_COLOR_KEY_VID_SRC = 1,
 118};
 119
 120enum omap_rfbi_te_mode {
 121        OMAP_DSS_RFBI_TE_MODE_1 = 1,
 122        OMAP_DSS_RFBI_TE_MODE_2 = 2,
 123};
 124
 125enum omap_dss_signal_level {
 126        OMAPDSS_SIG_ACTIVE_HIGH = 0,
 127        OMAPDSS_SIG_ACTIVE_LOW  = 1,
 128};
 129
 130enum omap_dss_signal_edge {
 131        OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
 132        OMAPDSS_DRIVE_SIG_RISING_EDGE,
 133        OMAPDSS_DRIVE_SIG_FALLING_EDGE,
 134};
 135
 136enum omap_dss_venc_type {
 137        OMAP_DSS_VENC_TYPE_COMPOSITE,
 138        OMAP_DSS_VENC_TYPE_SVIDEO,
 139};
 140
 141enum omap_dss_dsi_pixel_format {
 142        OMAP_DSS_DSI_FMT_RGB888,
 143        OMAP_DSS_DSI_FMT_RGB666,
 144        OMAP_DSS_DSI_FMT_RGB666_PACKED,
 145        OMAP_DSS_DSI_FMT_RGB565,
 146};
 147
 148enum omap_dss_dsi_mode {
 149        OMAP_DSS_DSI_CMD_MODE = 0,
 150        OMAP_DSS_DSI_VIDEO_MODE,
 151};
 152
 153enum omap_display_caps {
 154        OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
 155        OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
 156};
 157
 158enum omap_dss_display_state {
 159        OMAP_DSS_DISPLAY_DISABLED = 0,
 160        OMAP_DSS_DISPLAY_ACTIVE,
 161        OMAP_DSS_DISPLAY_SUSPENDED,
 162};
 163
 164enum omap_dss_audio_state {
 165        OMAP_DSS_AUDIO_DISABLED = 0,
 166        OMAP_DSS_AUDIO_ENABLED,
 167        OMAP_DSS_AUDIO_CONFIGURED,
 168        OMAP_DSS_AUDIO_PLAYING,
 169};
 170
 171enum omap_dss_rotation_type {
 172        OMAP_DSS_ROT_DMA        = 1 << 0,
 173        OMAP_DSS_ROT_VRFB       = 1 << 1,
 174        OMAP_DSS_ROT_TILER      = 1 << 2,
 175};
 176
 177/* clockwise rotation angle */
 178enum omap_dss_rotation_angle {
 179        OMAP_DSS_ROT_0   = 0,
 180        OMAP_DSS_ROT_90  = 1,
 181        OMAP_DSS_ROT_180 = 2,
 182        OMAP_DSS_ROT_270 = 3,
 183};
 184
 185enum omap_overlay_caps {
 186        OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
 187        OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
 188        OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
 189        OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
 190        OMAP_DSS_OVL_CAP_POS = 1 << 4,
 191        OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
 192};
 193
 194enum omap_overlay_manager_caps {
 195        OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
 196};
 197
 198enum omap_dss_clk_source {
 199        OMAP_DSS_CLK_SRC_FCK = 0,               /* OMAP2/3: DSS1_ALWON_FCLK
 200                                                 * OMAP4: DSS_FCLK */
 201        OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,   /* OMAP3: DSI1_PLL_FCLK
 202                                                 * OMAP4: PLL1_CLK1 */
 203        OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,     /* OMAP3: DSI2_PLL_FCLK
 204                                                 * OMAP4: PLL1_CLK2 */
 205        OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC,  /* OMAP4: PLL2_CLK1 */
 206        OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI,    /* OMAP4: PLL2_CLK2 */
 207};
 208
 209enum omap_hdmi_flags {
 210        OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
 211};
 212
 213enum omap_dss_output_id {
 214        OMAP_DSS_OUTPUT_DPI     = 1 << 0,
 215        OMAP_DSS_OUTPUT_DBI     = 1 << 1,
 216        OMAP_DSS_OUTPUT_SDI     = 1 << 2,
 217        OMAP_DSS_OUTPUT_DSI1    = 1 << 3,
 218        OMAP_DSS_OUTPUT_DSI2    = 1 << 4,
 219        OMAP_DSS_OUTPUT_VENC    = 1 << 5,
 220        OMAP_DSS_OUTPUT_HDMI    = 1 << 6,
 221};
 222
 223/* RFBI */
 224
 225struct rfbi_timings {
 226        int cs_on_time;
 227        int cs_off_time;
 228        int we_on_time;
 229        int we_off_time;
 230        int re_on_time;
 231        int re_off_time;
 232        int we_cycle_time;
 233        int re_cycle_time;
 234        int cs_pulse_width;
 235        int access_time;
 236
 237        int clk_div;
 238
 239        u32 tim[5];             /* set by rfbi_convert_timings() */
 240
 241        int converted;
 242};
 243
 244void omap_rfbi_write_command(const void *buf, u32 len);
 245void omap_rfbi_read_data(void *buf, u32 len);
 246void omap_rfbi_write_data(const void *buf, u32 len);
 247void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
 248                u16 x, u16 y,
 249                u16 w, u16 h);
 250int omap_rfbi_enable_te(bool enable, unsigned line);
 251int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
 252                             unsigned hs_pulse_time, unsigned vs_pulse_time,
 253                             int hs_pol_inv, int vs_pol_inv, int extif_div);
 254void rfbi_bus_lock(void);
 255void rfbi_bus_unlock(void);
 256
 257/* DSI */
 258
 259struct omap_dss_dsi_videomode_timings {
 260        /* DSI video mode blanking data */
 261        /* Unit: byte clock cycles */
 262        u16 hsa;
 263        u16 hfp;
 264        u16 hbp;
 265        /* Unit: line clocks */
 266        u16 vsa;
 267        u16 vfp;
 268        u16 vbp;
 269
 270        /* DSI blanking modes */
 271        int blanking_mode;
 272        int hsa_blanking_mode;
 273        int hbp_blanking_mode;
 274        int hfp_blanking_mode;
 275
 276        /* Video port sync events */
 277        bool vp_vsync_end;
 278        bool vp_hsync_end;
 279
 280        bool ddr_clk_always_on;
 281        int window_sync;
 282};
 283
 284void dsi_bus_lock(struct omap_dss_device *dssdev);
 285void dsi_bus_unlock(struct omap_dss_device *dssdev);
 286int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
 287                int len);
 288int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
 289                int len);
 290int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
 291int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
 292int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 293                u8 param);
 294int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
 295                u8 param);
 296int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
 297                u8 param1, u8 param2);
 298int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
 299                u8 *data, int len);
 300int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
 301                u8 *data, int len);
 302int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 303                u8 *buf, int buflen);
 304int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
 305                int buflen);
 306int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
 307                u8 *buf, int buflen);
 308int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
 309                u8 param1, u8 param2, u8 *buf, int buflen);
 310int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
 311                u16 len);
 312int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
 313int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
 314int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
 315void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
 316
 317/* Board specific data */
 318struct omap_dss_board_info {
 319        int (*get_context_loss_count)(struct device *dev);
 320        int num_devices;
 321        struct omap_dss_device **devices;
 322        struct omap_dss_device *default_device;
 323        int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
 324        void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
 325        int (*set_min_bus_tput)(struct device *dev, unsigned long r);
 326};
 327
 328/* Init with the board info */
 329extern int omap_display_init(struct omap_dss_board_info *board_data);
 330/* HDMI mux init*/
 331extern int omap_hdmi_init(enum omap_hdmi_flags flags);
 332
 333struct omap_video_timings {
 334        /* Unit: pixels */
 335        u16 x_res;
 336        /* Unit: pixels */
 337        u16 y_res;
 338        /* Unit: KHz */
 339        u32 pixel_clock;
 340        /* Unit: pixel clocks */
 341        u16 hsw;        /* Horizontal synchronization pulse width */
 342        /* Unit: pixel clocks */
 343        u16 hfp;        /* Horizontal front porch */
 344        /* Unit: pixel clocks */
 345        u16 hbp;        /* Horizontal back porch */
 346        /* Unit: line clocks */
 347        u16 vsw;        /* Vertical synchronization pulse width */
 348        /* Unit: line clocks */
 349        u16 vfp;        /* Vertical front porch */
 350        /* Unit: line clocks */
 351        u16 vbp;        /* Vertical back porch */
 352
 353        /* Vsync logic level */
 354        enum omap_dss_signal_level vsync_level;
 355        /* Hsync logic level */
 356        enum omap_dss_signal_level hsync_level;
 357        /* Interlaced or Progressive timings */
 358        bool interlace;
 359        /* Pixel clock edge to drive LCD data */
 360        enum omap_dss_signal_edge data_pclk_edge;
 361        /* Data enable logic level */
 362        enum omap_dss_signal_level de_level;
 363        /* Pixel clock edges to drive HSYNC and VSYNC signals */
 364        enum omap_dss_signal_edge sync_pclk_edge;
 365};
 366
 367#ifdef CONFIG_OMAP2_DSS_VENC
 368/* Hardcoded timings for tv modes. Venc only uses these to
 369 * identify the mode, and does not actually use the configs
 370 * itself. However, the configs should be something that
 371 * a normal monitor can also show */
 372extern const struct omap_video_timings omap_dss_pal_timings;
 373extern const struct omap_video_timings omap_dss_ntsc_timings;
 374#endif
 375
 376struct omap_dss_cpr_coefs {
 377        s16 rr, rg, rb;
 378        s16 gr, gg, gb;
 379        s16 br, bg, bb;
 380};
 381
 382struct omap_overlay_info {
 383        u32 paddr;
 384        u32 p_uv_addr;  /* for NV12 format */
 385        u16 screen_width;
 386        u16 width;
 387        u16 height;
 388        enum omap_color_mode color_mode;
 389        u8 rotation;
 390        enum omap_dss_rotation_type rotation_type;
 391        bool mirror;
 392
 393        u16 pos_x;
 394        u16 pos_y;
 395        u16 out_width;  /* if 0, out_width == width */
 396        u16 out_height; /* if 0, out_height == height */
 397        u8 global_alpha;
 398        u8 pre_mult_alpha;
 399        u8 zorder;
 400};
 401
 402struct omap_overlay {
 403        struct kobject kobj;
 404        struct list_head list;
 405
 406        /* static fields */
 407        const char *name;
 408        enum omap_plane id;
 409        enum omap_color_mode supported_modes;
 410        enum omap_overlay_caps caps;
 411
 412        /* dynamic fields */
 413        struct omap_overlay_manager *manager;
 414
 415        /*
 416         * The following functions do not block:
 417         *
 418         * is_enabled
 419         * set_overlay_info
 420         * get_overlay_info
 421         *
 422         * The rest of the functions may block and cannot be called from
 423         * interrupt context
 424         */
 425
 426        int (*enable)(struct omap_overlay *ovl);
 427        int (*disable)(struct omap_overlay *ovl);
 428        bool (*is_enabled)(struct omap_overlay *ovl);
 429
 430        int (*set_manager)(struct omap_overlay *ovl,
 431                struct omap_overlay_manager *mgr);
 432        int (*unset_manager)(struct omap_overlay *ovl);
 433
 434        int (*set_overlay_info)(struct omap_overlay *ovl,
 435                        struct omap_overlay_info *info);
 436        void (*get_overlay_info)(struct omap_overlay *ovl,
 437                        struct omap_overlay_info *info);
 438
 439        int (*wait_for_go)(struct omap_overlay *ovl);
 440
 441        struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
 442};
 443
 444struct omap_overlay_manager_info {
 445        u32 default_color;
 446
 447        enum omap_dss_trans_key_type trans_key_type;
 448        u32 trans_key;
 449        bool trans_enabled;
 450
 451        bool partial_alpha_enabled;
 452
 453        bool cpr_enable;
 454        struct omap_dss_cpr_coefs cpr_coefs;
 455};
 456
 457struct omap_overlay_manager {
 458        struct kobject kobj;
 459
 460        /* static fields */
 461        const char *name;
 462        enum omap_channel id;
 463        enum omap_overlay_manager_caps caps;
 464        struct list_head overlays;
 465        enum omap_display_type supported_displays;
 466        enum omap_dss_output_id supported_outputs;
 467
 468        /* dynamic fields */
 469        struct omap_dss_output *output;
 470
 471        /*
 472         * The following functions do not block:
 473         *
 474         * set_manager_info
 475         * get_manager_info
 476         * apply
 477         *
 478         * The rest of the functions may block and cannot be called from
 479         * interrupt context
 480         */
 481
 482        int (*set_output)(struct omap_overlay_manager *mgr,
 483                struct omap_dss_output *output);
 484        int (*unset_output)(struct omap_overlay_manager *mgr);
 485
 486        int (*set_manager_info)(struct omap_overlay_manager *mgr,
 487                        struct omap_overlay_manager_info *info);
 488        void (*get_manager_info)(struct omap_overlay_manager *mgr,
 489                        struct omap_overlay_manager_info *info);
 490
 491        int (*apply)(struct omap_overlay_manager *mgr);
 492        int (*wait_for_go)(struct omap_overlay_manager *mgr);
 493        int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
 494
 495        struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
 496};
 497
 498/* 22 pins means 1 clk lane and 10 data lanes */
 499#define OMAP_DSS_MAX_DSI_PINS 22
 500
 501struct omap_dsi_pin_config {
 502        int num_pins;
 503        /*
 504         * pin numbers in the following order:
 505         * clk+, clk-
 506         * data1+, data1-
 507         * data2+, data2-
 508         * ...
 509         */
 510        int pins[OMAP_DSS_MAX_DSI_PINS];
 511};
 512
 513struct omap_dss_writeback_info {
 514        u32 paddr;
 515        u32 p_uv_addr;
 516        u16 buf_width;
 517        u16 width;
 518        u16 height;
 519        enum omap_color_mode color_mode;
 520        u8 rotation;
 521        enum omap_dss_rotation_type rotation_type;
 522        bool mirror;
 523        u8 pre_mult_alpha;
 524};
 525
 526struct omap_dss_output {
 527        struct list_head list;
 528
 529        /* display type supported by the output */
 530        enum omap_display_type type;
 531
 532        /* output instance */
 533        enum omap_dss_output_id id;
 534
 535        /* output's platform device pointer */
 536        struct platform_device *pdev;
 537
 538        /* dynamic fields */
 539        struct omap_overlay_manager *manager;
 540
 541        struct omap_dss_device *device;
 542};
 543
 544struct omap_dss_device {
 545        struct device dev;
 546
 547        enum omap_display_type type;
 548
 549        enum omap_channel channel;
 550
 551        union {
 552                struct {
 553                        u8 data_lines;
 554                } dpi;
 555
 556                struct {
 557                        u8 channel;
 558                        u8 data_lines;
 559                } rfbi;
 560
 561                struct {
 562                        u8 datapairs;
 563                } sdi;
 564
 565                struct {
 566                        int module;
 567
 568                        bool ext_te;
 569                        u8 ext_te_gpio;
 570                } dsi;
 571
 572                struct {
 573                        enum omap_dss_venc_type type;
 574                        bool invert_polarity;
 575                } venc;
 576        } phy;
 577
 578        struct {
 579                struct {
 580                        struct {
 581                                u16 lck_div;
 582                                u16 pck_div;
 583                                enum omap_dss_clk_source lcd_clk_src;
 584                        } channel;
 585
 586                        enum omap_dss_clk_source dispc_fclk_src;
 587                } dispc;
 588
 589                struct {
 590                        /* regn is one greater than TRM's REGN value */
 591                        u16 regn;
 592                        u16 regm;
 593                        u16 regm_dispc;
 594                        u16 regm_dsi;
 595
 596                        u16 lp_clk_div;
 597                        enum omap_dss_clk_source dsi_fclk_src;
 598                } dsi;
 599
 600                struct {
 601                        /* regn is one greater than TRM's REGN value */
 602                        u16 regn;
 603                        u16 regm2;
 604                } hdmi;
 605        } clocks;
 606
 607        struct {
 608                struct omap_video_timings timings;
 609
 610                int acbi;       /* ac-bias pin transitions per interrupt */
 611                /* Unit: line clocks */
 612                int acb;        /* ac-bias pin frequency */
 613
 614                enum omap_dss_dsi_pixel_format dsi_pix_fmt;
 615                enum omap_dss_dsi_mode dsi_mode;
 616                struct omap_dss_dsi_videomode_timings dsi_vm_timings;
 617        } panel;
 618
 619        struct {
 620                u8 pixel_size;
 621                struct rfbi_timings rfbi_timings;
 622        } ctrl;
 623
 624        int reset_gpio;
 625
 626        int max_backlight_level;
 627
 628        const char *name;
 629
 630        /* used to match device to driver */
 631        const char *driver_name;
 632
 633        void *data;
 634
 635        struct omap_dss_driver *driver;
 636
 637        /* helper variable for driver suspend/resume */
 638        bool activate_after_resume;
 639
 640        enum omap_display_caps caps;
 641
 642        struct omap_dss_output *output;
 643
 644        enum omap_dss_display_state state;
 645
 646        enum omap_dss_audio_state audio_state;
 647
 648        /* platform specific  */
 649        int (*platform_enable)(struct omap_dss_device *dssdev);
 650        void (*platform_disable)(struct omap_dss_device *dssdev);
 651        int (*set_backlight)(struct omap_dss_device *dssdev, int level);
 652        int (*get_backlight)(struct omap_dss_device *dssdev);
 653};
 654
 655struct omap_dss_hdmi_data
 656{
 657        int ct_cp_hpd_gpio;
 658        int ls_oe_gpio;
 659        int hpd_gpio;
 660};
 661
 662struct omap_dss_audio {
 663        struct snd_aes_iec958 *iec;
 664        struct snd_cea_861_aud_if *cea;
 665};
 666
 667struct omap_dss_driver {
 668        struct device_driver driver;
 669
 670        int (*probe)(struct omap_dss_device *);
 671        void (*remove)(struct omap_dss_device *);
 672
 673        int (*enable)(struct omap_dss_device *display);
 674        void (*disable)(struct omap_dss_device *display);
 675        int (*suspend)(struct omap_dss_device *display);
 676        int (*resume)(struct omap_dss_device *display);
 677        int (*run_test)(struct omap_dss_device *display, int test);
 678
 679        int (*update)(struct omap_dss_device *dssdev,
 680                               u16 x, u16 y, u16 w, u16 h);
 681        int (*sync)(struct omap_dss_device *dssdev);
 682
 683        int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 684        int (*get_te)(struct omap_dss_device *dssdev);
 685
 686        u8 (*get_rotate)(struct omap_dss_device *dssdev);
 687        int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
 688
 689        bool (*get_mirror)(struct omap_dss_device *dssdev);
 690        int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
 691
 692        int (*memory_read)(struct omap_dss_device *dssdev,
 693                        void *buf, size_t size,
 694                        u16 x, u16 y, u16 w, u16 h);
 695
 696        void (*get_resolution)(struct omap_dss_device *dssdev,
 697                        u16 *xres, u16 *yres);
 698        void (*get_dimensions)(struct omap_dss_device *dssdev,
 699                        u32 *width, u32 *height);
 700        int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
 701
 702        int (*check_timings)(struct omap_dss_device *dssdev,
 703                        struct omap_video_timings *timings);
 704        void (*set_timings)(struct omap_dss_device *dssdev,
 705                        struct omap_video_timings *timings);
 706        void (*get_timings)(struct omap_dss_device *dssdev,
 707                        struct omap_video_timings *timings);
 708
 709        int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
 710        u32 (*get_wss)(struct omap_dss_device *dssdev);
 711
 712        int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
 713        bool (*detect)(struct omap_dss_device *dssdev);
 714
 715        /*
 716         * For display drivers that support audio. This encompasses
 717         * HDMI and DisplayPort at the moment.
 718         */
 719        /*
 720         * Note: These functions might sleep. Do not call while
 721         * holding a spinlock/readlock.
 722         */
 723        int (*audio_enable)(struct omap_dss_device *dssdev);
 724        void (*audio_disable)(struct omap_dss_device *dssdev);
 725        bool (*audio_supported)(struct omap_dss_device *dssdev);
 726        int (*audio_config)(struct omap_dss_device *dssdev,
 727                struct omap_dss_audio *audio);
 728        /* Note: These functions may not sleep */
 729        int (*audio_start)(struct omap_dss_device *dssdev);
 730        void (*audio_stop)(struct omap_dss_device *dssdev);
 731
 732};
 733
 734int omap_dss_register_driver(struct omap_dss_driver *);
 735void omap_dss_unregister_driver(struct omap_dss_driver *);
 736
 737void omap_dss_get_device(struct omap_dss_device *dssdev);
 738void omap_dss_put_device(struct omap_dss_device *dssdev);
 739#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
 740struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
 741struct omap_dss_device *omap_dss_find_device(void *data,
 742                int (*match)(struct omap_dss_device *dssdev, void *data));
 743
 744int omap_dss_start_device(struct omap_dss_device *dssdev);
 745void omap_dss_stop_device(struct omap_dss_device *dssdev);
 746
 747int omap_dss_get_num_overlay_managers(void);
 748struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
 749
 750int omap_dss_get_num_overlays(void);
 751struct omap_overlay *omap_dss_get_overlay(int num);
 752
 753struct omap_dss_output *omap_dss_get_output(enum omap_dss_output_id id);
 754int omapdss_output_set_device(struct omap_dss_output *out,
 755                struct omap_dss_device *dssdev);
 756int omapdss_output_unset_device(struct omap_dss_output *out);
 757
 758void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
 759                u16 *xres, u16 *yres);
 760int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
 761void omapdss_default_get_timings(struct omap_dss_device *dssdev,
 762                struct omap_video_timings *timings);
 763
 764typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
 765int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 766int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 767
 768int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
 769int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
 770                unsigned long timeout);
 771
 772#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
 773#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
 774
 775void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
 776                bool enable);
 777int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
 778void omapdss_dsi_set_timings(struct omap_dss_device *dssdev,
 779                struct omap_video_timings *timings);
 780void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
 781void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev,
 782                enum omap_dss_dsi_pixel_format fmt);
 783void omapdss_dsi_set_operation_mode(struct omap_dss_device *dssdev,
 784                enum omap_dss_dsi_mode mode);
 785void omapdss_dsi_set_videomode_timings(struct omap_dss_device *dssdev,
 786                struct omap_dss_dsi_videomode_timings *timings);
 787
 788int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
 789                void (*callback)(int, void *), void *data);
 790int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
 791int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
 792void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
 793int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
 794                const struct omap_dsi_pin_config *pin_cfg);
 795int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev,
 796                unsigned long ddr_clk, unsigned long lp_clk);
 797
 798int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
 799void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
 800                bool disconnect_lanes, bool enter_ulps);
 801
 802int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
 803void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
 804void omapdss_dpi_set_timings(struct omap_dss_device *dssdev,
 805                struct omap_video_timings *timings);
 806int dpi_check_timings(struct omap_dss_device *dssdev,
 807                        struct omap_video_timings *timings);
 808void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines);
 809
 810int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
 811void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
 812void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
 813                struct omap_video_timings *timings);
 814void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs);
 815
 816int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
 817void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
 818int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *),
 819                void *data);
 820int omap_rfbi_configure(struct omap_dss_device *dssdev);
 821void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
 822void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev,
 823                int pixel_size);
 824void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev,
 825                int data_lines);
 826void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev,
 827                struct rfbi_timings *timings);
 828
 829#endif
 830
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