linux/drivers/video/pxafb.h
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   1#ifndef __PXAFB_H__
   2#define __PXAFB_H__
   3
   4/*
   5 * linux/drivers/video/pxafb.h
   6 *    -- Intel PXA250/210 LCD Controller Frame Buffer Device
   7 *
   8 *  Copyright (C) 1999 Eric A. Thomas.
   9 *  Copyright (C) 2004 Jean-Frederic Clere.
  10 *  Copyright (C) 2004 Ian Campbell.
  11 *  Copyright (C) 2004 Jeff Lackey.
  12 *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
  13 *  which in turn is
  14 *   Based on acornfb.c Copyright (C) Russell King.
  15 *
  16 *  2001-08-03: Cliff Brake <cbrake@acclent.com>
  17 *       - ported SA1100 code to PXA
  18 *
  19 * This file is subject to the terms and conditions of the GNU General Public
  20 * License.  See the file COPYING in the main directory of this archive
  21 * for more details.
  22 */
  23
  24/* PXA LCD DMA descriptor */
  25struct pxafb_dma_descriptor {
  26        unsigned int fdadr;
  27        unsigned int fsadr;
  28        unsigned int fidr;
  29        unsigned int ldcmd;
  30};
  31
  32enum {
  33        PAL_NONE        = -1,
  34        PAL_BASE        = 0,
  35        PAL_OV1         = 1,
  36        PAL_OV2         = 2,
  37        PAL_MAX,
  38};
  39
  40enum {
  41        DMA_BASE        = 0,
  42        DMA_UPPER       = 0,
  43        DMA_LOWER       = 1,
  44        DMA_OV1         = 1,
  45        DMA_OV2_Y       = 2,
  46        DMA_OV2_Cb      = 3,
  47        DMA_OV2_Cr      = 4,
  48        DMA_CURSOR      = 5,
  49        DMA_CMD         = 6,
  50        DMA_MAX,
  51};
  52
  53/* maximum palette size - 256 entries, each 4 bytes long */
  54#define PALETTE_SIZE    (256 * 4)
  55#define CMD_BUFF_SIZE   (1024 * 50)
  56
  57/* NOTE: the palette and frame dma descriptors are doubled to allow
  58 * the 2nd set for branch settings (FBRx)
  59 */
  60struct pxafb_dma_buff {
  61        unsigned char palette[PAL_MAX * PALETTE_SIZE];
  62        uint16_t cmd_buff[CMD_BUFF_SIZE];
  63        struct pxafb_dma_descriptor pal_desc[PAL_MAX * 2];
  64        struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2];
  65};
  66
  67enum {
  68        OVERLAY1,
  69        OVERLAY2,
  70};
  71
  72enum {
  73        OVERLAY_FORMAT_RGB = 0,
  74        OVERLAY_FORMAT_YUV444_PACKED,
  75        OVERLAY_FORMAT_YUV444_PLANAR,
  76        OVERLAY_FORMAT_YUV422_PLANAR,
  77        OVERLAY_FORMAT_YUV420_PLANAR,
  78};
  79
  80#define NONSTD_TO_XPOS(x)       (((x) >> 0)  & 0x3ff)
  81#define NONSTD_TO_YPOS(x)       (((x) >> 10) & 0x3ff)
  82#define NONSTD_TO_PFOR(x)       (((x) >> 20) & 0x7)
  83
  84struct pxafb_layer;
  85
  86struct pxafb_layer_ops {
  87        void (*enable)(struct pxafb_layer *);
  88        void (*disable)(struct pxafb_layer *);
  89        void (*setup)(struct pxafb_layer *);
  90};
  91
  92struct pxafb_layer {
  93        struct fb_info          fb;
  94        int                     id;
  95        int                     registered;
  96        uint32_t                usage;
  97        uint32_t                control[2];
  98
  99        struct pxafb_layer_ops  *ops;
 100
 101        void __iomem            *video_mem;
 102        unsigned long           video_mem_phys;
 103        size_t                  video_mem_size;
 104        struct completion       branch_done;
 105
 106        struct pxafb_info       *fbi;
 107};
 108
 109struct pxafb_info {
 110        struct fb_info          fb;
 111        struct device           *dev;
 112        struct clk              *clk;
 113
 114        void __iomem            *mmio_base;
 115
 116        struct pxafb_dma_buff   *dma_buff;
 117        size_t                  dma_buff_size;
 118        dma_addr_t              dma_buff_phys;
 119        dma_addr_t              fdadr[DMA_MAX * 2];
 120
 121        void __iomem            *video_mem;     /* virtual address of frame buffer */
 122        unsigned long           video_mem_phys; /* physical address of frame buffer */
 123        size_t                  video_mem_size; /* size of the frame buffer */
 124        u16 *                   palette_cpu;    /* virtual address of palette memory */
 125        u_int                   palette_size;
 126
 127        u_int                   lccr0;
 128        u_int                   lccr3;
 129        u_int                   lccr4;
 130        u_int                   cmap_inverse:1,
 131                                cmap_static:1,
 132                                unused:30;
 133
 134        u_int                   reg_lccr0;
 135        u_int                   reg_lccr1;
 136        u_int                   reg_lccr2;
 137        u_int                   reg_lccr3;
 138        u_int                   reg_lccr4;
 139        u_int                   reg_cmdcr;
 140
 141        unsigned long   hsync_time;
 142
 143        volatile u_char         state;
 144        volatile u_char         task_state;
 145        struct mutex            ctrlr_lock;
 146        wait_queue_head_t       ctrlr_wait;
 147        struct work_struct      task;
 148
 149        struct completion       disable_done;
 150
 151#ifdef CONFIG_FB_PXA_SMARTPANEL
 152        uint16_t                *smart_cmds;
 153        size_t                  n_smart_cmds;
 154        struct completion       command_done;
 155        struct completion       refresh_done;
 156        struct task_struct      *smart_thread;
 157#endif
 158
 159#ifdef CONFIG_FB_PXA_OVERLAY
 160        struct pxafb_layer      overlay[2];
 161#endif
 162
 163#ifdef CONFIG_CPU_FREQ
 164        struct notifier_block   freq_transition;
 165        struct notifier_block   freq_policy;
 166#endif
 167
 168        void (*lcd_power)(int, struct fb_var_screeninfo *);
 169        void (*backlight_power)(int);
 170};
 171
 172#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
 173
 174/*
 175 * These are the actions for set_ctrlr_state
 176 */
 177#define C_DISABLE               (0)
 178#define C_ENABLE                (1)
 179#define C_DISABLE_CLKCHANGE     (2)
 180#define C_ENABLE_CLKCHANGE      (3)
 181#define C_REENABLE              (4)
 182#define C_DISABLE_PM            (5)
 183#define C_ENABLE_PM             (6)
 184#define C_STARTUP               (7)
 185
 186#define PXA_NAME        "PXA"
 187
 188/*
 189 * Minimum X and Y resolutions
 190 */
 191#define MIN_XRES        64
 192#define MIN_YRES        64
 193
 194/* maximum X and Y resolutions - note these are limits from the register
 195 * bits length instead of the real ones
 196 */
 197#define MAX_XRES        1024
 198#define MAX_YRES        1024
 199
 200#endif /* __PXAFB_H__ */
 201
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