linux/drivers/video/mx3fb.c
<<
>>
Prefs
   1/*
   2 * Copyright (C) 2008
   3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
   4 *
   5 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 */
  11
  12#include <linux/module.h>
  13#include <linux/kernel.h>
  14#include <linux/platform_device.h>
  15#include <linux/sched.h>
  16#include <linux/errno.h>
  17#include <linux/string.h>
  18#include <linux/interrupt.h>
  19#include <linux/slab.h>
  20#include <linux/fb.h>
  21#include <linux/delay.h>
  22#include <linux/init.h>
  23#include <linux/ioport.h>
  24#include <linux/dma-mapping.h>
  25#include <linux/dmaengine.h>
  26#include <linux/console.h>
  27#include <linux/clk.h>
  28#include <linux/mutex.h>
  29
  30#include <linux/platform_data/dma-imx.h>
  31#include <mach/hardware.h>
  32#include <mach/ipu.h>
  33#include <linux/platform_data/video-mx3fb.h>
  34
  35#include <asm/io.h>
  36#include <asm/uaccess.h>
  37
  38#define MX3FB_NAME              "mx3_sdc_fb"
  39
  40#define MX3FB_REG_OFFSET        0xB4
  41
  42/* SDC Registers */
  43#define SDC_COM_CONF            (0xB4 - MX3FB_REG_OFFSET)
  44#define SDC_GW_CTRL             (0xB8 - MX3FB_REG_OFFSET)
  45#define SDC_FG_POS              (0xBC - MX3FB_REG_OFFSET)
  46#define SDC_BG_POS              (0xC0 - MX3FB_REG_OFFSET)
  47#define SDC_CUR_POS             (0xC4 - MX3FB_REG_OFFSET)
  48#define SDC_PWM_CTRL            (0xC8 - MX3FB_REG_OFFSET)
  49#define SDC_CUR_MAP             (0xCC - MX3FB_REG_OFFSET)
  50#define SDC_HOR_CONF            (0xD0 - MX3FB_REG_OFFSET)
  51#define SDC_VER_CONF            (0xD4 - MX3FB_REG_OFFSET)
  52#define SDC_SHARP_CONF_1        (0xD8 - MX3FB_REG_OFFSET)
  53#define SDC_SHARP_CONF_2        (0xDC - MX3FB_REG_OFFSET)
  54
  55/* Register bits */
  56#define SDC_COM_TFT_COLOR       0x00000001UL
  57#define SDC_COM_FG_EN           0x00000010UL
  58#define SDC_COM_GWSEL           0x00000020UL
  59#define SDC_COM_GLB_A           0x00000040UL
  60#define SDC_COM_KEY_COLOR_G     0x00000080UL
  61#define SDC_COM_BG_EN           0x00000200UL
  62#define SDC_COM_SHARP           0x00001000UL
  63
  64#define SDC_V_SYNC_WIDTH_L      0x00000001UL
  65
  66/* Display Interface registers */
  67#define DI_DISP_IF_CONF         (0x0124 - MX3FB_REG_OFFSET)
  68#define DI_DISP_SIG_POL         (0x0128 - MX3FB_REG_OFFSET)
  69#define DI_SER_DISP1_CONF       (0x012C - MX3FB_REG_OFFSET)
  70#define DI_SER_DISP2_CONF       (0x0130 - MX3FB_REG_OFFSET)
  71#define DI_HSP_CLK_PER          (0x0134 - MX3FB_REG_OFFSET)
  72#define DI_DISP0_TIME_CONF_1    (0x0138 - MX3FB_REG_OFFSET)
  73#define DI_DISP0_TIME_CONF_2    (0x013C - MX3FB_REG_OFFSET)
  74#define DI_DISP0_TIME_CONF_3    (0x0140 - MX3FB_REG_OFFSET)
  75#define DI_DISP1_TIME_CONF_1    (0x0144 - MX3FB_REG_OFFSET)
  76#define DI_DISP1_TIME_CONF_2    (0x0148 - MX3FB_REG_OFFSET)
  77#define DI_DISP1_TIME_CONF_3    (0x014C - MX3FB_REG_OFFSET)
  78#define DI_DISP2_TIME_CONF_1    (0x0150 - MX3FB_REG_OFFSET)
  79#define DI_DISP2_TIME_CONF_2    (0x0154 - MX3FB_REG_OFFSET)
  80#define DI_DISP2_TIME_CONF_3    (0x0158 - MX3FB_REG_OFFSET)
  81#define DI_DISP3_TIME_CONF      (0x015C - MX3FB_REG_OFFSET)
  82#define DI_DISP0_DB0_MAP        (0x0160 - MX3FB_REG_OFFSET)
  83#define DI_DISP0_DB1_MAP        (0x0164 - MX3FB_REG_OFFSET)
  84#define DI_DISP0_DB2_MAP        (0x0168 - MX3FB_REG_OFFSET)
  85#define DI_DISP0_CB0_MAP        (0x016C - MX3FB_REG_OFFSET)
  86#define DI_DISP0_CB1_MAP        (0x0170 - MX3FB_REG_OFFSET)
  87#define DI_DISP0_CB2_MAP        (0x0174 - MX3FB_REG_OFFSET)
  88#define DI_DISP1_DB0_MAP        (0x0178 - MX3FB_REG_OFFSET)
  89#define DI_DISP1_DB1_MAP        (0x017C - MX3FB_REG_OFFSET)
  90#define DI_DISP1_DB2_MAP        (0x0180 - MX3FB_REG_OFFSET)
  91#define DI_DISP1_CB0_MAP        (0x0184 - MX3FB_REG_OFFSET)
  92#define DI_DISP1_CB1_MAP        (0x0188 - MX3FB_REG_OFFSET)
  93#define DI_DISP1_CB2_MAP        (0x018C - MX3FB_REG_OFFSET)
  94#define DI_DISP2_DB0_MAP        (0x0190 - MX3FB_REG_OFFSET)
  95#define DI_DISP2_DB1_MAP        (0x0194 - MX3FB_REG_OFFSET)
  96#define DI_DISP2_DB2_MAP        (0x0198 - MX3FB_REG_OFFSET)
  97#define DI_DISP2_CB0_MAP        (0x019C - MX3FB_REG_OFFSET)
  98#define DI_DISP2_CB1_MAP        (0x01A0 - MX3FB_REG_OFFSET)
  99#define DI_DISP2_CB2_MAP        (0x01A4 - MX3FB_REG_OFFSET)
 100#define DI_DISP3_B0_MAP         (0x01A8 - MX3FB_REG_OFFSET)
 101#define DI_DISP3_B1_MAP         (0x01AC - MX3FB_REG_OFFSET)
 102#define DI_DISP3_B2_MAP         (0x01B0 - MX3FB_REG_OFFSET)
 103#define DI_DISP_ACC_CC          (0x01B4 - MX3FB_REG_OFFSET)
 104#define DI_DISP_LLA_CONF        (0x01B8 - MX3FB_REG_OFFSET)
 105#define DI_DISP_LLA_DATA        (0x01BC - MX3FB_REG_OFFSET)
 106
 107/* DI_DISP_SIG_POL bits */
 108#define DI_D3_VSYNC_POL_SHIFT           28
 109#define DI_D3_HSYNC_POL_SHIFT           27
 110#define DI_D3_DRDY_SHARP_POL_SHIFT      26
 111#define DI_D3_CLK_POL_SHIFT             25
 112#define DI_D3_DATA_POL_SHIFT            24
 113
 114/* DI_DISP_IF_CONF bits */
 115#define DI_D3_CLK_IDLE_SHIFT            26
 116#define DI_D3_CLK_SEL_SHIFT             25
 117#define DI_D3_DATAMSK_SHIFT             24
 118
 119enum ipu_panel {
 120        IPU_PANEL_SHARP_TFT,
 121        IPU_PANEL_TFT,
 122};
 123
 124struct ipu_di_signal_cfg {
 125        unsigned datamask_en:1;
 126        unsigned clksel_en:1;
 127        unsigned clkidle_en:1;
 128        unsigned data_pol:1;    /* true = inverted */
 129        unsigned clk_pol:1;     /* true = rising edge */
 130        unsigned enable_pol:1;
 131        unsigned Hsync_pol:1;   /* true = active high */
 132        unsigned Vsync_pol:1;
 133};
 134
 135static const struct fb_videomode mx3fb_modedb[] = {
 136        {
 137                /* 240x320 @ 60 Hz */
 138                .name           = "Sharp-QVGA",
 139                .refresh        = 60,
 140                .xres           = 240,
 141                .yres           = 320,
 142                .pixclock       = 185925,
 143                .left_margin    = 9,
 144                .right_margin   = 16,
 145                .upper_margin   = 7,
 146                .lower_margin   = 9,
 147                .hsync_len      = 1,
 148                .vsync_len      = 1,
 149                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
 150                                  FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
 151                                  FB_SYNC_CLK_IDLE_EN,
 152                .vmode          = FB_VMODE_NONINTERLACED,
 153                .flag           = 0,
 154        }, {
 155                /* 240x33 @ 60 Hz */
 156                .name           = "Sharp-CLI",
 157                .refresh        = 60,
 158                .xres           = 240,
 159                .yres           = 33,
 160                .pixclock       = 185925,
 161                .left_margin    = 9,
 162                .right_margin   = 16,
 163                .upper_margin   = 7,
 164                .lower_margin   = 9 + 287,
 165                .hsync_len      = 1,
 166                .vsync_len      = 1,
 167                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
 168                                  FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
 169                                  FB_SYNC_CLK_IDLE_EN,
 170                .vmode          = FB_VMODE_NONINTERLACED,
 171                .flag           = 0,
 172        }, {
 173                /* 640x480 @ 60 Hz */
 174                .name           = "NEC-VGA",
 175                .refresh        = 60,
 176                .xres           = 640,
 177                .yres           = 480,
 178                .pixclock       = 38255,
 179                .left_margin    = 144,
 180                .right_margin   = 0,
 181                .upper_margin   = 34,
 182                .lower_margin   = 40,
 183                .hsync_len      = 1,
 184                .vsync_len      = 1,
 185                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
 186                .vmode          = FB_VMODE_NONINTERLACED,
 187                .flag           = 0,
 188        }, {
 189                /* NTSC TV output */
 190                .name           = "TV-NTSC",
 191                .refresh        = 60,
 192                .xres           = 640,
 193                .yres           = 480,
 194                .pixclock       = 37538,
 195                .left_margin    = 38,
 196                .right_margin   = 858 - 640 - 38 - 3,
 197                .upper_margin   = 36,
 198                .lower_margin   = 518 - 480 - 36 - 1,
 199                .hsync_len      = 3,
 200                .vsync_len      = 1,
 201                .sync           = 0,
 202                .vmode          = FB_VMODE_NONINTERLACED,
 203                .flag           = 0,
 204        }, {
 205                /* PAL TV output */
 206                .name           = "TV-PAL",
 207                .refresh        = 50,
 208                .xres           = 640,
 209                .yres           = 480,
 210                .pixclock       = 37538,
 211                .left_margin    = 38,
 212                .right_margin   = 960 - 640 - 38 - 32,
 213                .upper_margin   = 32,
 214                .lower_margin   = 555 - 480 - 32 - 3,
 215                .hsync_len      = 32,
 216                .vsync_len      = 3,
 217                .sync           = 0,
 218                .vmode          = FB_VMODE_NONINTERLACED,
 219                .flag           = 0,
 220        }, {
 221                /* TV output VGA mode, 640x480 @ 65 Hz */
 222                .name           = "TV-VGA",
 223                .refresh        = 60,
 224                .xres           = 640,
 225                .yres           = 480,
 226                .pixclock       = 40574,
 227                .left_margin    = 35,
 228                .right_margin   = 45,
 229                .upper_margin   = 9,
 230                .lower_margin   = 1,
 231                .hsync_len      = 46,
 232                .vsync_len      = 5,
 233                .sync           = 0,
 234                .vmode          = FB_VMODE_NONINTERLACED,
 235                .flag           = 0,
 236        },
 237};
 238
 239struct mx3fb_data {
 240        struct fb_info          *fbi;
 241        int                     backlight_level;
 242        void __iomem            *reg_base;
 243        spinlock_t              lock;
 244        struct device           *dev;
 245
 246        uint32_t                h_start_width;
 247        uint32_t                v_start_width;
 248        enum disp_data_mapping  disp_data_fmt;
 249};
 250
 251struct dma_chan_request {
 252        struct mx3fb_data       *mx3fb;
 253        enum ipu_channel        id;
 254};
 255
 256/* MX3 specific framebuffer information. */
 257struct mx3fb_info {
 258        int                             blank;
 259        enum ipu_channel                ipu_ch;
 260        uint32_t                        cur_ipu_buf;
 261
 262        u32                             pseudo_palette[16];
 263
 264        struct completion               flip_cmpl;
 265        struct mutex                    mutex;  /* Protects fb-ops */
 266        struct mx3fb_data               *mx3fb;
 267        struct idmac_channel            *idmac_channel;
 268        struct dma_async_tx_descriptor  *txd;
 269        dma_cookie_t                    cookie;
 270        struct scatterlist              sg[2];
 271
 272        struct fb_var_screeninfo        cur_var; /* current var info */
 273};
 274
 275static void mx3fb_dma_done(void *);
 276
 277/* Used fb-mode and bpp. Can be set on kernel command line, therefore file-static. */
 278static const char *fb_mode;
 279static unsigned long default_bpp = 16;
 280
 281static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg)
 282{
 283        return __raw_readl(mx3fb->reg_base + reg);
 284}
 285
 286static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg)
 287{
 288        __raw_writel(value, mx3fb->reg_base + reg);
 289}
 290
 291struct di_mapping {
 292        uint32_t b0, b1, b2;
 293};
 294
 295static const struct di_mapping di_mappings[] = {
 296        [IPU_DISP_DATA_MAPPING_RGB666] = { 0x0005000f, 0x000b000f, 0x0011000f },
 297        [IPU_DISP_DATA_MAPPING_RGB565] = { 0x0004003f, 0x000a000f, 0x000f003f },
 298        [IPU_DISP_DATA_MAPPING_RGB888] = { 0x00070000, 0x000f0000, 0x00170000 },
 299};
 300
 301static void sdc_fb_init(struct mx3fb_info *fbi)
 302{
 303        struct mx3fb_data *mx3fb = fbi->mx3fb;
 304        uint32_t reg;
 305
 306        reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
 307
 308        mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF);
 309}
 310
 311/* Returns enabled flag before uninit */
 312static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi)
 313{
 314        struct mx3fb_data *mx3fb = fbi->mx3fb;
 315        uint32_t reg;
 316
 317        reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
 318
 319        mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF);
 320
 321        return reg & SDC_COM_BG_EN;
 322}
 323
 324static void sdc_enable_channel(struct mx3fb_info *mx3_fbi)
 325{
 326        struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
 327        struct idmac_channel *ichan = mx3_fbi->idmac_channel;
 328        struct dma_chan *dma_chan = &ichan->dma_chan;
 329        unsigned long flags;
 330        dma_cookie_t cookie;
 331
 332        if (mx3_fbi->txd)
 333                dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi,
 334                        to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg);
 335        else
 336                dev_dbg(mx3fb->dev, "mx3fbi %p, txd = NULL\n", mx3_fbi);
 337
 338        /* This enables the channel */
 339        if (mx3_fbi->cookie < 0) {
 340                mx3_fbi->txd = dmaengine_prep_slave_sg(dma_chan,
 341                      &mx3_fbi->sg[0], 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 342                if (!mx3_fbi->txd) {
 343                        dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n",
 344                                dma_chan->chan_id);
 345                        return;
 346                }
 347
 348                mx3_fbi->txd->callback_param    = mx3_fbi->txd;
 349                mx3_fbi->txd->callback          = mx3fb_dma_done;
 350
 351                cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd);
 352                dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__,
 353                       mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
 354        } else {
 355                if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) {
 356                        dev_err(mx3fb->dev, "Cannot enable channel %d\n",
 357                                dma_chan->chan_id);
 358                        return;
 359                }
 360
 361                /* Just re-activate the same buffer */
 362                dma_async_issue_pending(dma_chan);
 363                cookie = mx3_fbi->cookie;
 364                dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__,
 365                       mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
 366        }
 367
 368        if (cookie >= 0) {
 369                spin_lock_irqsave(&mx3fb->lock, flags);
 370                sdc_fb_init(mx3_fbi);
 371                mx3_fbi->cookie = cookie;
 372                spin_unlock_irqrestore(&mx3fb->lock, flags);
 373        }
 374
 375        /*
 376         * Attention! Without this msleep the channel keeps generating
 377         * interrupts. Next sdc_set_brightness() is going to be called
 378         * from mx3fb_blank().
 379         */
 380        msleep(2);
 381}
 382
 383static void sdc_disable_channel(struct mx3fb_info *mx3_fbi)
 384{
 385        struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
 386        uint32_t enabled;
 387        unsigned long flags;
 388
 389        if (mx3_fbi->txd == NULL)
 390                return;
 391
 392        spin_lock_irqsave(&mx3fb->lock, flags);
 393
 394        enabled = sdc_fb_uninit(mx3_fbi);
 395
 396        spin_unlock_irqrestore(&mx3fb->lock, flags);
 397
 398        mx3_fbi->txd->chan->device->device_control(mx3_fbi->txd->chan,
 399                                                   DMA_TERMINATE_ALL, 0);
 400        mx3_fbi->txd = NULL;
 401        mx3_fbi->cookie = -EINVAL;
 402}
 403
 404/**
 405 * sdc_set_window_pos() - set window position of the respective plane.
 406 * @mx3fb:      mx3fb context.
 407 * @channel:    IPU DMAC channel ID.
 408 * @x_pos:      X coordinate relative to the top left corner to place window at.
 409 * @y_pos:      Y coordinate relative to the top left corner to place window at.
 410 * @return:     0 on success or negative error code on failure.
 411 */
 412static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel,
 413                              int16_t x_pos, int16_t y_pos)
 414{
 415        if (channel != IDMAC_SDC_0)
 416                return -EINVAL;
 417
 418        x_pos += mx3fb->h_start_width;
 419        y_pos += mx3fb->v_start_width;
 420
 421        mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS);
 422        return 0;
 423}
 424
 425/**
 426 * sdc_init_panel() - initialize a synchronous LCD panel.
 427 * @mx3fb:              mx3fb context.
 428 * @panel:              panel type.
 429 * @pixel_clk:          desired pixel clock frequency in Hz.
 430 * @width:              width of panel in pixels.
 431 * @height:             height of panel in pixels.
 432 * @h_start_width:      number of pixel clocks between the HSYNC signal pulse
 433 *                      and the start of valid data.
 434 * @h_sync_width:       width of the HSYNC signal in units of pixel clocks.
 435 * @h_end_width:        number of pixel clocks between the end of valid data
 436 *                      and the HSYNC signal for next line.
 437 * @v_start_width:      number of lines between the VSYNC signal pulse and the
 438 *                      start of valid data.
 439 * @v_sync_width:       width of the VSYNC signal in units of lines
 440 * @v_end_width:        number of lines between the end of valid data and the
 441 *                      VSYNC signal for next frame.
 442 * @sig:                bitfield of signal polarities for LCD interface.
 443 * @return:             0 on success or negative error code on failure.
 444 */
 445static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel,
 446                          uint32_t pixel_clk,
 447                          uint16_t width, uint16_t height,
 448                          uint16_t h_start_width, uint16_t h_sync_width,
 449                          uint16_t h_end_width, uint16_t v_start_width,
 450                          uint16_t v_sync_width, uint16_t v_end_width,
 451                          struct ipu_di_signal_cfg sig)
 452{
 453        unsigned long lock_flags;
 454        uint32_t reg;
 455        uint32_t old_conf;
 456        uint32_t div;
 457        struct clk *ipu_clk;
 458        const struct di_mapping *map;
 459
 460        dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height);
 461
 462        if (v_sync_width == 0 || h_sync_width == 0)
 463                return -EINVAL;
 464
 465        /* Init panel size and blanking periods */
 466        reg = ((uint32_t) (h_sync_width - 1) << 26) |
 467                ((uint32_t) (width + h_start_width + h_end_width - 1) << 16);
 468        mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
 469
 470#ifdef DEBUG
 471        printk(KERN_CONT " hor_conf %x,", reg);
 472#endif
 473
 474        reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L |
 475            ((uint32_t) (height + v_start_width + v_end_width - 1) << 16);
 476        mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
 477
 478#ifdef DEBUG
 479        printk(KERN_CONT " ver_conf %x\n", reg);
 480#endif
 481
 482        mx3fb->h_start_width = h_start_width;
 483        mx3fb->v_start_width = v_start_width;
 484
 485        switch (panel) {
 486        case IPU_PANEL_SHARP_TFT:
 487                mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
 488                mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
 489                mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
 490                break;
 491        case IPU_PANEL_TFT:
 492                mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
 493                break;
 494        default:
 495                return -EINVAL;
 496        }
 497
 498        /* Init clocking */
 499
 500        /*
 501         * Calculate divider: fractional part is 4 bits so simply multiple by
 502         * 2^4 to get fractional part, as long as we stay under ~250MHz and on
 503         * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
 504         */
 505        ipu_clk = clk_get(mx3fb->dev, NULL);
 506        if (!IS_ERR(ipu_clk)) {
 507                div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
 508                clk_put(ipu_clk);
 509        } else {
 510                div = 0;
 511        }
 512
 513        if (div < 0x40) {       /* Divider less than 4 */
 514                dev_dbg(mx3fb->dev,
 515                        "InitPanel() - Pixel clock divider less than 4\n");
 516                div = 0x40;
 517        }
 518
 519        dev_dbg(mx3fb->dev, "pixel clk = %u, divider %u.%u\n",
 520                pixel_clk, div >> 4, (div & 7) * 125);
 521
 522        spin_lock_irqsave(&mx3fb->lock, lock_flags);
 523
 524        /*
 525         * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits
 526         * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing
 527         * debug. DISP3_IF_CLK_UP_WR is 0
 528         */
 529        mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
 530
 531        /* DI settings */
 532        old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF;
 533        old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT |
 534                sig.clksel_en << DI_D3_CLK_SEL_SHIFT |
 535                sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT;
 536        mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
 537
 538        old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF;
 539        old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT |
 540                sig.clk_pol << DI_D3_CLK_POL_SHIFT |
 541                sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT |
 542                sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT |
 543                sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT;
 544        mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
 545
 546        map = &di_mappings[mx3fb->disp_data_fmt];
 547        mx3fb_write_reg(mx3fb, map->b0, DI_DISP3_B0_MAP);
 548        mx3fb_write_reg(mx3fb, map->b1, DI_DISP3_B1_MAP);
 549        mx3fb_write_reg(mx3fb, map->b2, DI_DISP3_B2_MAP);
 550
 551        spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
 552
 553        dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n",
 554                mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF));
 555        dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n",
 556                mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL));
 557        dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
 558                mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF));
 559
 560        return 0;
 561}
 562
 563/**
 564 * sdc_set_color_key() - set the transparent color key for SDC graphic plane.
 565 * @mx3fb:      mx3fb context.
 566 * @channel:    IPU DMAC channel ID.
 567 * @enable:     boolean to enable or disable color keyl.
 568 * @color_key:  24-bit RGB color to use as transparent color key.
 569 * @return:     0 on success or negative error code on failure.
 570 */
 571static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel,
 572                             bool enable, uint32_t color_key)
 573{
 574        uint32_t reg, sdc_conf;
 575        unsigned long lock_flags;
 576
 577        spin_lock_irqsave(&mx3fb->lock, lock_flags);
 578
 579        sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
 580        if (channel == IDMAC_SDC_0)
 581                sdc_conf &= ~SDC_COM_GWSEL;
 582        else
 583                sdc_conf |= SDC_COM_GWSEL;
 584
 585        if (enable) {
 586                reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L;
 587                mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL),
 588                             SDC_GW_CTRL);
 589
 590                sdc_conf |= SDC_COM_KEY_COLOR_G;
 591        } else {
 592                sdc_conf &= ~SDC_COM_KEY_COLOR_G;
 593        }
 594        mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF);
 595
 596        spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
 597
 598        return 0;
 599}
 600
 601/**
 602 * sdc_set_global_alpha() - set global alpha blending modes.
 603 * @mx3fb:      mx3fb context.
 604 * @enable:     boolean to enable or disable global alpha blending. If disabled,
 605 *              per pixel blending is used.
 606 * @alpha:      global alpha value.
 607 * @return:     0 on success or negative error code on failure.
 608 */
 609static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha)
 610{
 611        uint32_t reg;
 612        unsigned long lock_flags;
 613
 614        spin_lock_irqsave(&mx3fb->lock, lock_flags);
 615
 616        if (enable) {
 617                reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL;
 618                mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL);
 619
 620                reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
 621                mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF);
 622        } else {
 623                reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
 624                mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF);
 625        }
 626
 627        spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
 628
 629        return 0;
 630}
 631
 632static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value)
 633{
 634        dev_dbg(mx3fb->dev, "%s: value = %d\n", __func__, value);
 635        /* This might be board-specific */
 636        mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL);
 637        return;
 638}
 639
 640static uint32_t bpp_to_pixfmt(int bpp)
 641{
 642        uint32_t pixfmt = 0;
 643        switch (bpp) {
 644        case 24:
 645                pixfmt = IPU_PIX_FMT_BGR24;
 646                break;
 647        case 32:
 648                pixfmt = IPU_PIX_FMT_BGR32;
 649                break;
 650        case 16:
 651                pixfmt = IPU_PIX_FMT_RGB565;
 652                break;
 653        }
 654        return pixfmt;
 655}
 656
 657static int mx3fb_blank(int blank, struct fb_info *fbi);
 658static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
 659                                  bool lock);
 660static int mx3fb_unmap_video_memory(struct fb_info *fbi);
 661
 662/**
 663 * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings.
 664 * @info:       framebuffer information pointer
 665 * @return:     0 on success or negative error code on failure.
 666 */
 667static int mx3fb_set_fix(struct fb_info *fbi)
 668{
 669        struct fb_fix_screeninfo *fix = &fbi->fix;
 670        struct fb_var_screeninfo *var = &fbi->var;
 671
 672        strncpy(fix->id, "DISP3 BG", 8);
 673
 674        fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
 675
 676        fix->type = FB_TYPE_PACKED_PIXELS;
 677        fix->accel = FB_ACCEL_NONE;
 678        fix->visual = FB_VISUAL_TRUECOLOR;
 679        fix->xpanstep = 1;
 680        fix->ypanstep = 1;
 681
 682        return 0;
 683}
 684
 685static void mx3fb_dma_done(void *arg)
 686{
 687        struct idmac_tx_desc *tx_desc = to_tx_desc(arg);
 688        struct dma_chan *chan = tx_desc->txd.chan;
 689        struct idmac_channel *ichannel = to_idmac_chan(chan);
 690        struct mx3fb_data *mx3fb = ichannel->client;
 691        struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
 692
 693        dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq);
 694
 695        /* We only need one interrupt, it will be re-enabled as needed */
 696        disable_irq_nosync(ichannel->eof_irq);
 697
 698        complete(&mx3_fbi->flip_cmpl);
 699}
 700
 701static bool mx3fb_must_set_par(struct fb_info *fbi)
 702{
 703        struct mx3fb_info *mx3_fbi = fbi->par;
 704        struct fb_var_screeninfo old_var = mx3_fbi->cur_var;
 705        struct fb_var_screeninfo new_var = fbi->var;
 706
 707        if ((fbi->var.activate & FB_ACTIVATE_FORCE) &&
 708            (fbi->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
 709                return true;
 710
 711        /*
 712         * Ignore xoffset and yoffset update,
 713         * because pan display handles this case.
 714         */
 715        old_var.xoffset = new_var.xoffset;
 716        old_var.yoffset = new_var.yoffset;
 717
 718        return !!memcmp(&old_var, &new_var, sizeof(struct fb_var_screeninfo));
 719}
 720
 721static int __set_par(struct fb_info *fbi, bool lock)
 722{
 723        u32 mem_len, cur_xoffset, cur_yoffset;
 724        struct ipu_di_signal_cfg sig_cfg;
 725        enum ipu_panel mode = IPU_PANEL_TFT;
 726        struct mx3fb_info *mx3_fbi = fbi->par;
 727        struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
 728        struct idmac_channel *ichan = mx3_fbi->idmac_channel;
 729        struct idmac_video_param *video = &ichan->params.video;
 730        struct scatterlist *sg = mx3_fbi->sg;
 731
 732        /* Total cleanup */
 733        if (mx3_fbi->txd)
 734                sdc_disable_channel(mx3_fbi);
 735
 736        mx3fb_set_fix(fbi);
 737
 738        mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
 739        if (mem_len > fbi->fix.smem_len) {
 740                if (fbi->fix.smem_start)
 741                        mx3fb_unmap_video_memory(fbi);
 742
 743                if (mx3fb_map_video_memory(fbi, mem_len, lock) < 0)
 744                        return -ENOMEM;
 745        }
 746
 747        sg_init_table(&sg[0], 1);
 748        sg_init_table(&sg[1], 1);
 749
 750        sg_dma_address(&sg[0]) = fbi->fix.smem_start;
 751        sg_set_page(&sg[0], virt_to_page(fbi->screen_base),
 752                    fbi->fix.smem_len,
 753                    offset_in_page(fbi->screen_base));
 754
 755        if (mx3_fbi->ipu_ch == IDMAC_SDC_0) {
 756                memset(&sig_cfg, 0, sizeof(sig_cfg));
 757                if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
 758                        sig_cfg.Hsync_pol = true;
 759                if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
 760                        sig_cfg.Vsync_pol = true;
 761                if (fbi->var.sync & FB_SYNC_CLK_INVERT)
 762                        sig_cfg.clk_pol = true;
 763                if (fbi->var.sync & FB_SYNC_DATA_INVERT)
 764                        sig_cfg.data_pol = true;
 765                if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH)
 766                        sig_cfg.enable_pol = true;
 767                if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
 768                        sig_cfg.clkidle_en = true;
 769                if (fbi->var.sync & FB_SYNC_CLK_SEL_EN)
 770                        sig_cfg.clksel_en = true;
 771                if (fbi->var.sync & FB_SYNC_SHARP_MODE)
 772                        mode = IPU_PANEL_SHARP_TFT;
 773
 774                dev_dbg(fbi->device, "pixclock = %ul Hz\n",
 775                        (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
 776
 777                if (sdc_init_panel(mx3fb, mode,
 778                                   (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
 779                                   fbi->var.xres, fbi->var.yres,
 780                                   fbi->var.left_margin,
 781                                   fbi->var.hsync_len,
 782                                   fbi->var.right_margin +
 783                                   fbi->var.hsync_len,
 784                                   fbi->var.upper_margin,
 785                                   fbi->var.vsync_len,
 786                                   fbi->var.lower_margin +
 787                                   fbi->var.vsync_len, sig_cfg) != 0) {
 788                        dev_err(fbi->device,
 789                                "mx3fb: Error initializing panel.\n");
 790                        return -EINVAL;
 791                }
 792        }
 793
 794        sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0);
 795
 796        mx3_fbi->cur_ipu_buf    = 0;
 797
 798        video->out_pixel_fmt    = bpp_to_pixfmt(fbi->var.bits_per_pixel);
 799        video->out_width        = fbi->var.xres;
 800        video->out_height       = fbi->var.yres;
 801        video->out_stride       = fbi->var.xres_virtual;
 802
 803        if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
 804                sdc_enable_channel(mx3_fbi);
 805                /*
 806                 * sg[0] points to fb smem_start address
 807                 * and is actually active in controller.
 808                 */
 809                mx3_fbi->cur_var.xoffset = 0;
 810                mx3_fbi->cur_var.yoffset = 0;
 811        }
 812
 813        /*
 814         * Preserve xoffset and yoffest in case they are
 815         * inactive in controller as fb is blanked.
 816         */
 817        cur_xoffset = mx3_fbi->cur_var.xoffset;
 818        cur_yoffset = mx3_fbi->cur_var.yoffset;
 819        mx3_fbi->cur_var = fbi->var;
 820        mx3_fbi->cur_var.xoffset = cur_xoffset;
 821        mx3_fbi->cur_var.yoffset = cur_yoffset;
 822
 823        return 0;
 824}
 825
 826/**
 827 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
 828 * @fbi:        framebuffer information pointer.
 829 * @return:     0 on success or negative error code on failure.
 830 */
 831static int mx3fb_set_par(struct fb_info *fbi)
 832{
 833        struct mx3fb_info *mx3_fbi = fbi->par;
 834        struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
 835        struct idmac_channel *ichan = mx3_fbi->idmac_channel;
 836        int ret;
 837
 838        dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+');
 839
 840        mutex_lock(&mx3_fbi->mutex);
 841
 842        ret = mx3fb_must_set_par(fbi) ? __set_par(fbi, true) : 0;
 843
 844        mutex_unlock(&mx3_fbi->mutex);
 845
 846        return ret;
 847}
 848
 849/**
 850 * mx3fb_check_var() - check and adjust framebuffer variable parameters.
 851 * @var:        framebuffer variable parameters
 852 * @fbi:        framebuffer information pointer
 853 */
 854static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
 855{
 856        struct mx3fb_info *mx3_fbi = fbi->par;
 857        u32 vtotal;
 858        u32 htotal;
 859
 860        dev_dbg(fbi->device, "%s\n", __func__);
 861
 862        if (var->xres_virtual < var->xres)
 863                var->xres_virtual = var->xres;
 864        if (var->yres_virtual < var->yres)
 865                var->yres_virtual = var->yres;
 866
 867        if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
 868            (var->bits_per_pixel != 16))
 869                var->bits_per_pixel = default_bpp;
 870
 871        switch (var->bits_per_pixel) {
 872        case 16:
 873                var->red.length = 5;
 874                var->red.offset = 11;
 875                var->red.msb_right = 0;
 876
 877                var->green.length = 6;
 878                var->green.offset = 5;
 879                var->green.msb_right = 0;
 880
 881                var->blue.length = 5;
 882                var->blue.offset = 0;
 883                var->blue.msb_right = 0;
 884
 885                var->transp.length = 0;
 886                var->transp.offset = 0;
 887                var->transp.msb_right = 0;
 888                break;
 889        case 24:
 890                var->red.length = 8;
 891                var->red.offset = 16;
 892                var->red.msb_right = 0;
 893
 894                var->green.length = 8;
 895                var->green.offset = 8;
 896                var->green.msb_right = 0;
 897
 898                var->blue.length = 8;
 899                var->blue.offset = 0;
 900                var->blue.msb_right = 0;
 901
 902                var->transp.length = 0;
 903                var->transp.offset = 0;
 904                var->transp.msb_right = 0;
 905                break;
 906        case 32:
 907                var->red.length = 8;
 908                var->red.offset = 16;
 909                var->red.msb_right = 0;
 910
 911                var->green.length = 8;
 912                var->green.offset = 8;
 913                var->green.msb_right = 0;
 914
 915                var->blue.length = 8;
 916                var->blue.offset = 0;
 917                var->blue.msb_right = 0;
 918
 919                var->transp.length = 8;
 920                var->transp.offset = 24;
 921                var->transp.msb_right = 0;
 922                break;
 923        }
 924
 925        if (var->pixclock < 1000) {
 926                htotal = var->xres + var->right_margin + var->hsync_len +
 927                    var->left_margin;
 928                vtotal = var->yres + var->lower_margin + var->vsync_len +
 929                    var->upper_margin;
 930                var->pixclock = (vtotal * htotal * 6UL) / 100UL;
 931                var->pixclock = KHZ2PICOS(var->pixclock);
 932                dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n",
 933                        var->pixclock);
 934        }
 935
 936        var->height = -1;
 937        var->width = -1;
 938        var->grayscale = 0;
 939
 940        /* Preserve sync flags */
 941        var->sync |= mx3_fbi->cur_var.sync;
 942        mx3_fbi->cur_var.sync |= var->sync;
 943
 944        return 0;
 945}
 946
 947static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf)
 948{
 949        chan &= 0xffff;
 950        chan >>= 16 - bf->length;
 951        return chan << bf->offset;
 952}
 953
 954static int mx3fb_setcolreg(unsigned int regno, unsigned int red,
 955                           unsigned int green, unsigned int blue,
 956                           unsigned int trans, struct fb_info *fbi)
 957{
 958        struct mx3fb_info *mx3_fbi = fbi->par;
 959        u32 val;
 960        int ret = 1;
 961
 962        dev_dbg(fbi->device, "%s, regno = %u\n", __func__, regno);
 963
 964        mutex_lock(&mx3_fbi->mutex);
 965        /*
 966         * If greyscale is true, then we convert the RGB value
 967         * to greyscale no matter what visual we are using.
 968         */
 969        if (fbi->var.grayscale)
 970                red = green = blue = (19595 * red + 38470 * green +
 971                                      7471 * blue) >> 16;
 972        switch (fbi->fix.visual) {
 973        case FB_VISUAL_TRUECOLOR:
 974                /*
 975                 * 16-bit True Colour.  We encode the RGB value
 976                 * according to the RGB bitfield information.
 977                 */
 978                if (regno < 16) {
 979                        u32 *pal = fbi->pseudo_palette;
 980
 981                        val = chan_to_field(red, &fbi->var.red);
 982                        val |= chan_to_field(green, &fbi->var.green);
 983                        val |= chan_to_field(blue, &fbi->var.blue);
 984
 985                        pal[regno] = val;
 986
 987                        ret = 0;
 988                }
 989                break;
 990
 991        case FB_VISUAL_STATIC_PSEUDOCOLOR:
 992        case FB_VISUAL_PSEUDOCOLOR:
 993                break;
 994        }
 995        mutex_unlock(&mx3_fbi->mutex);
 996
 997        return ret;
 998}
 999
1000static void __blank(int blank, struct fb_info *fbi)
1001{
1002        struct mx3fb_info *mx3_fbi = fbi->par;
1003        struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
1004        int was_blank = mx3_fbi->blank;
1005
1006        mx3_fbi->blank = blank;
1007
1008        /* Attention!
1009         * Do not call sdc_disable_channel() for a channel that is disabled
1010         * already! This will result in a kernel NULL pointer dereference
1011         * (mx3_fbi->txd is NULL). Hide the fact, that all blank modes are
1012         * handled equally by this driver.
1013         */
1014        if (blank > FB_BLANK_UNBLANK && was_blank > FB_BLANK_UNBLANK)
1015                return;
1016
1017        switch (blank) {
1018        case FB_BLANK_POWERDOWN:
1019        case FB_BLANK_VSYNC_SUSPEND:
1020        case FB_BLANK_HSYNC_SUSPEND:
1021        case FB_BLANK_NORMAL:
1022                sdc_set_brightness(mx3fb, 0);
1023                memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
1024                /* Give LCD time to update - enough for 50 and 60 Hz */
1025                msleep(25);
1026                sdc_disable_channel(mx3_fbi);
1027                break;
1028        case FB_BLANK_UNBLANK:
1029                sdc_enable_channel(mx3_fbi);
1030                sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1031                break;
1032        }
1033}
1034
1035/**
1036 * mx3fb_blank() - blank the display.
1037 */
1038static int mx3fb_blank(int blank, struct fb_info *fbi)
1039{
1040        struct mx3fb_info *mx3_fbi = fbi->par;
1041
1042        dev_dbg(fbi->device, "%s, blank = %d, base %p, len %u\n", __func__,
1043                blank, fbi->screen_base, fbi->fix.smem_len);
1044
1045        if (mx3_fbi->blank == blank)
1046                return 0;
1047
1048        mutex_lock(&mx3_fbi->mutex);
1049        __blank(blank, fbi);
1050        mutex_unlock(&mx3_fbi->mutex);
1051
1052        return 0;
1053}
1054
1055/**
1056 * mx3fb_pan_display() - pan or wrap the display
1057 * @var:        variable screen buffer information.
1058 * @info:       framebuffer information pointer.
1059 *
1060 * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1061 */
1062static int mx3fb_pan_display(struct fb_var_screeninfo *var,
1063                             struct fb_info *fbi)
1064{
1065        struct mx3fb_info *mx3_fbi = fbi->par;
1066        u32 y_bottom;
1067        unsigned long base;
1068        off_t offset;
1069        dma_cookie_t cookie;
1070        struct scatterlist *sg = mx3_fbi->sg;
1071        struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan;
1072        struct dma_async_tx_descriptor *txd;
1073        int ret;
1074
1075        dev_dbg(fbi->device, "%s [%c]\n", __func__,
1076                list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+');
1077
1078        if (var->xoffset > 0) {
1079                dev_dbg(fbi->device, "x panning not supported\n");
1080                return -EINVAL;
1081        }
1082
1083        if (mx3_fbi->cur_var.xoffset == var->xoffset &&
1084            mx3_fbi->cur_var.yoffset == var->yoffset)
1085                return 0;       /* No change, do nothing */
1086
1087        y_bottom = var->yoffset;
1088
1089        if (!(var->vmode & FB_VMODE_YWRAP))
1090                y_bottom += fbi->var.yres;
1091
1092        if (y_bottom > fbi->var.yres_virtual)
1093                return -EINVAL;
1094
1095        mutex_lock(&mx3_fbi->mutex);
1096
1097        offset = var->yoffset * fbi->fix.line_length
1098               + var->xoffset * (fbi->var.bits_per_pixel / 8);
1099        base = fbi->fix.smem_start + offset;
1100
1101        dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n",
1102                mx3_fbi->cur_ipu_buf, base);
1103
1104        /*
1105         * We enable the End of Frame interrupt, which will free a tx-descriptor,
1106         * which we will need for the next device_prep_slave_sg(). The
1107         * IRQ-handler will disable the IRQ again.
1108         */
1109        init_completion(&mx3_fbi->flip_cmpl);
1110        enable_irq(mx3_fbi->idmac_channel->eof_irq);
1111
1112        ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10);
1113        if (ret <= 0) {
1114                mutex_unlock(&mx3_fbi->mutex);
1115                dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ?
1116                         "user interrupt" : "timeout");
1117                disable_irq(mx3_fbi->idmac_channel->eof_irq);
1118                return ret ? : -ETIMEDOUT;
1119        }
1120
1121        mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf;
1122
1123        sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base;
1124        sg_set_page(&sg[mx3_fbi->cur_ipu_buf],
1125                    virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len,
1126                    offset_in_page(fbi->screen_base + offset));
1127
1128        if (mx3_fbi->txd)
1129                async_tx_ack(mx3_fbi->txd);
1130
1131        txd = dmaengine_prep_slave_sg(dma_chan, sg +
1132                mx3_fbi->cur_ipu_buf, 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
1133        if (!txd) {
1134                dev_err(fbi->device,
1135                        "Error preparing a DMA transaction descriptor.\n");
1136                mutex_unlock(&mx3_fbi->mutex);
1137                return -EIO;
1138        }
1139
1140        txd->callback_param     = txd;
1141        txd->callback           = mx3fb_dma_done;
1142
1143        /*
1144         * Emulate original mx3fb behaviour: each new call to idmac_tx_submit()
1145         * should switch to another buffer
1146         */
1147        cookie = txd->tx_submit(txd);
1148        dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie);
1149        if (cookie < 0) {
1150                dev_err(fbi->device,
1151                        "Error updating SDC buf %d to address=0x%08lX\n",
1152                        mx3_fbi->cur_ipu_buf, base);
1153                mutex_unlock(&mx3_fbi->mutex);
1154                return -EIO;
1155        }
1156
1157        mx3_fbi->txd = txd;
1158
1159        fbi->var.xoffset = var->xoffset;
1160        fbi->var.yoffset = var->yoffset;
1161
1162        if (var->vmode & FB_VMODE_YWRAP)
1163                fbi->var.vmode |= FB_VMODE_YWRAP;
1164        else
1165                fbi->var.vmode &= ~FB_VMODE_YWRAP;
1166
1167        mx3_fbi->cur_var = fbi->var;
1168
1169        mutex_unlock(&mx3_fbi->mutex);
1170
1171        dev_dbg(fbi->device, "Update complete\n");
1172
1173        return 0;
1174}
1175
1176/*
1177 * This structure contains the pointers to the control functions that are
1178 * invoked by the core framebuffer driver to perform operations like
1179 * blitting, rectangle filling, copy regions and cursor definition.
1180 */
1181static struct fb_ops mx3fb_ops = {
1182        .owner = THIS_MODULE,
1183        .fb_set_par = mx3fb_set_par,
1184        .fb_check_var = mx3fb_check_var,
1185        .fb_setcolreg = mx3fb_setcolreg,
1186        .fb_pan_display = mx3fb_pan_display,
1187        .fb_fillrect = cfb_fillrect,
1188        .fb_copyarea = cfb_copyarea,
1189        .fb_imageblit = cfb_imageblit,
1190        .fb_blank = mx3fb_blank,
1191};
1192
1193#ifdef CONFIG_PM
1194/*
1195 * Power management hooks.      Note that we won't be called from IRQ context,
1196 * unlike the blank functions above, so we may sleep.
1197 */
1198
1199/*
1200 * Suspends the framebuffer and blanks the screen. Power management support
1201 */
1202static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state)
1203{
1204        struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1205        struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1206
1207        console_lock();
1208        fb_set_suspend(mx3fb->fbi, 1);
1209        console_unlock();
1210
1211        if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1212                sdc_disable_channel(mx3_fbi);
1213                sdc_set_brightness(mx3fb, 0);
1214
1215        }
1216        return 0;
1217}
1218
1219/*
1220 * Resumes the framebuffer and unblanks the screen. Power management support
1221 */
1222static int mx3fb_resume(struct platform_device *pdev)
1223{
1224        struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1225        struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1226
1227        if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1228                sdc_enable_channel(mx3_fbi);
1229                sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1230        }
1231
1232        console_lock();
1233        fb_set_suspend(mx3fb->fbi, 0);
1234        console_unlock();
1235
1236        return 0;
1237}
1238#else
1239#define mx3fb_suspend   NULL
1240#define mx3fb_resume    NULL
1241#endif
1242
1243/*
1244 * Main framebuffer functions
1245 */
1246
1247/**
1248 * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer.
1249 * @fbi:        framebuffer information pointer
1250 * @mem_len:    length of mapped memory
1251 * @lock:       do not lock during initialisation
1252 * @return:     Error code indicating success or failure
1253 *
1254 * This buffer is remapped into a non-cached, non-buffered, memory region to
1255 * allow palette and pixel writes to occur without flushing the cache. Once this
1256 * area is remapped, all virtual memory access to the video memory should occur
1257 * at the new region.
1258 */
1259static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
1260                                  bool lock)
1261{
1262        int retval = 0;
1263        dma_addr_t addr;
1264
1265        fbi->screen_base = dma_alloc_writecombine(fbi->device,
1266                                                  mem_len,
1267                                                  &addr, GFP_DMA);
1268
1269        if (!fbi->screen_base) {
1270                dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n",
1271                        mem_len);
1272                retval = -EBUSY;
1273                goto err0;
1274        }
1275
1276        if (lock)
1277                mutex_lock(&fbi->mm_lock);
1278        fbi->fix.smem_start = addr;
1279        fbi->fix.smem_len = mem_len;
1280        if (lock)
1281                mutex_unlock(&fbi->mm_lock);
1282
1283        dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n",
1284                (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len);
1285
1286        fbi->screen_size = fbi->fix.smem_len;
1287
1288        /* Clear the screen */
1289        memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
1290
1291        return 0;
1292
1293err0:
1294        fbi->fix.smem_len = 0;
1295        fbi->fix.smem_start = 0;
1296        fbi->screen_base = NULL;
1297        return retval;
1298}
1299
1300/**
1301 * mx3fb_unmap_video_memory() - de-allocate frame buffer memory.
1302 * @fbi:        framebuffer information pointer
1303 * @return:     error code indicating success or failure
1304 */
1305static int mx3fb_unmap_video_memory(struct fb_info *fbi)
1306{
1307        dma_free_writecombine(fbi->device, fbi->fix.smem_len,
1308                              fbi->screen_base, fbi->fix.smem_start);
1309
1310        fbi->screen_base = 0;
1311        mutex_lock(&fbi->mm_lock);
1312        fbi->fix.smem_start = 0;
1313        fbi->fix.smem_len = 0;
1314        mutex_unlock(&fbi->mm_lock);
1315        return 0;
1316}
1317
1318/**
1319 * mx3fb_init_fbinfo() - initialize framebuffer information object.
1320 * @return:     initialized framebuffer structure.
1321 */
1322static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops)
1323{
1324        struct fb_info *fbi;
1325        struct mx3fb_info *mx3fbi;
1326        int ret;
1327
1328        /* Allocate sufficient memory for the fb structure */
1329        fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev);
1330        if (!fbi)
1331                return NULL;
1332
1333        mx3fbi                  = fbi->par;
1334        mx3fbi->cookie          = -EINVAL;
1335        mx3fbi->cur_ipu_buf     = 0;
1336
1337        fbi->var.activate       = FB_ACTIVATE_NOW;
1338
1339        fbi->fbops              = ops;
1340        fbi->flags              = FBINFO_FLAG_DEFAULT;
1341        fbi->pseudo_palette     = mx3fbi->pseudo_palette;
1342
1343        mutex_init(&mx3fbi->mutex);
1344
1345        /* Allocate colormap */
1346        ret = fb_alloc_cmap(&fbi->cmap, 16, 0);
1347        if (ret < 0) {
1348                framebuffer_release(fbi);
1349                return NULL;
1350        }
1351
1352        return fbi;
1353}
1354
1355static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan)
1356{
1357        struct device *dev = mx3fb->dev;
1358        struct mx3fb_platform_data *mx3fb_pdata = dev->platform_data;
1359        const char *name = mx3fb_pdata->name;
1360        unsigned int irq;
1361        struct fb_info *fbi;
1362        struct mx3fb_info *mx3fbi;
1363        const struct fb_videomode *mode;
1364        int ret, num_modes;
1365
1366        if (mx3fb_pdata->disp_data_fmt >= ARRAY_SIZE(di_mappings)) {
1367                dev_err(dev, "Illegal display data format %d\n",
1368                                mx3fb_pdata->disp_data_fmt);
1369                return -EINVAL;
1370        }
1371
1372        ichan->client = mx3fb;
1373        irq = ichan->eof_irq;
1374
1375        if (ichan->dma_chan.chan_id != IDMAC_SDC_0)
1376                return -EINVAL;
1377
1378        fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops);
1379        if (!fbi)
1380                return -ENOMEM;
1381
1382        if (!fb_mode)
1383                fb_mode = name;
1384
1385        if (!fb_mode) {
1386                ret = -EINVAL;
1387                goto emode;
1388        }
1389
1390        if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) {
1391                mode = mx3fb_pdata->mode;
1392                num_modes = mx3fb_pdata->num_modes;
1393        } else {
1394                mode = mx3fb_modedb;
1395                num_modes = ARRAY_SIZE(mx3fb_modedb);
1396        }
1397
1398        if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode,
1399                          num_modes, NULL, default_bpp)) {
1400                ret = -EBUSY;
1401                goto emode;
1402        }
1403
1404        fb_videomode_to_modelist(mode, num_modes, &fbi->modelist);
1405
1406        /* Default Y virtual size is 2x panel size */
1407        fbi->var.yres_virtual = fbi->var.yres * 2;
1408
1409        mx3fb->fbi = fbi;
1410
1411        /* set Display Interface clock period */
1412        mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER);
1413        /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
1414
1415        sdc_set_brightness(mx3fb, 255);
1416        sdc_set_global_alpha(mx3fb, true, 0xFF);
1417        sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0);
1418
1419        mx3fbi                  = fbi->par;
1420        mx3fbi->idmac_channel   = ichan;
1421        mx3fbi->ipu_ch          = ichan->dma_chan.chan_id;
1422        mx3fbi->mx3fb           = mx3fb;
1423        mx3fbi->blank           = FB_BLANK_NORMAL;
1424
1425        mx3fb->disp_data_fmt    = mx3fb_pdata->disp_data_fmt;
1426
1427        init_completion(&mx3fbi->flip_cmpl);
1428        disable_irq(ichan->eof_irq);
1429        dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq);
1430        ret = __set_par(fbi, false);
1431        if (ret < 0)
1432                goto esetpar;
1433
1434        __blank(FB_BLANK_UNBLANK, fbi);
1435
1436        dev_info(dev, "registered, using mode %s\n", fb_mode);
1437
1438        ret = register_framebuffer(fbi);
1439        if (ret < 0)
1440                goto erfb;
1441
1442        return 0;
1443
1444erfb:
1445esetpar:
1446emode:
1447        fb_dealloc_cmap(&fbi->cmap);
1448        framebuffer_release(fbi);
1449
1450        return ret;
1451}
1452
1453static bool chan_filter(struct dma_chan *chan, void *arg)
1454{
1455        struct dma_chan_request *rq = arg;
1456        struct device *dev;
1457        struct mx3fb_platform_data *mx3fb_pdata;
1458
1459        if (!imx_dma_is_ipu(chan))
1460                return false;
1461
1462        if (!rq)
1463                return false;
1464
1465        dev = rq->mx3fb->dev;
1466        mx3fb_pdata = dev->platform_data;
1467
1468        return rq->id == chan->chan_id &&
1469                mx3fb_pdata->dma_dev == chan->device->dev;
1470}
1471
1472static void release_fbi(struct fb_info *fbi)
1473{
1474        mx3fb_unmap_video_memory(fbi);
1475
1476        fb_dealloc_cmap(&fbi->cmap);
1477
1478        unregister_framebuffer(fbi);
1479        framebuffer_release(fbi);
1480}
1481
1482static int mx3fb_probe(struct platform_device *pdev)
1483{
1484        struct device *dev = &pdev->dev;
1485        int ret;
1486        struct resource *sdc_reg;
1487        struct mx3fb_data *mx3fb;
1488        dma_cap_mask_t mask;
1489        struct dma_chan *chan;
1490        struct dma_chan_request rq;
1491
1492        /*
1493         * Display Interface (DI) and Synchronous Display Controller (SDC)
1494         * registers
1495         */
1496        sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1497        if (!sdc_reg)
1498                return -EINVAL;
1499
1500        mx3fb = kzalloc(sizeof(*mx3fb), GFP_KERNEL);
1501        if (!mx3fb)
1502                return -ENOMEM;
1503
1504        spin_lock_init(&mx3fb->lock);
1505
1506        mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg));
1507        if (!mx3fb->reg_base) {
1508                ret = -ENOMEM;
1509                goto eremap;
1510        }
1511
1512        pr_debug("Remapped %pR at %p\n", sdc_reg, mx3fb->reg_base);
1513
1514        /* IDMAC interface */
1515        dmaengine_get();
1516
1517        mx3fb->dev = dev;
1518        platform_set_drvdata(pdev, mx3fb);
1519
1520        rq.mx3fb = mx3fb;
1521
1522        dma_cap_zero(mask);
1523        dma_cap_set(DMA_SLAVE, mask);
1524        dma_cap_set(DMA_PRIVATE, mask);
1525        rq.id = IDMAC_SDC_0;
1526        chan = dma_request_channel(mask, chan_filter, &rq);
1527        if (!chan) {
1528                ret = -EBUSY;
1529                goto ersdc0;
1530        }
1531
1532        mx3fb->backlight_level = 255;
1533
1534        ret = init_fb_chan(mx3fb, to_idmac_chan(chan));
1535        if (ret < 0)
1536                goto eisdc0;
1537
1538        return 0;
1539
1540eisdc0:
1541        dma_release_channel(chan);
1542ersdc0:
1543        dmaengine_put();
1544        iounmap(mx3fb->reg_base);
1545eremap:
1546        kfree(mx3fb);
1547        dev_err(dev, "mx3fb: failed to register fb\n");
1548        return ret;
1549}
1550
1551static int mx3fb_remove(struct platform_device *dev)
1552{
1553        struct mx3fb_data *mx3fb = platform_get_drvdata(dev);
1554        struct fb_info *fbi = mx3fb->fbi;
1555        struct mx3fb_info *mx3_fbi = fbi->par;
1556        struct dma_chan *chan;
1557
1558        chan = &mx3_fbi->idmac_channel->dma_chan;
1559        release_fbi(fbi);
1560
1561        dma_release_channel(chan);
1562        dmaengine_put();
1563
1564        iounmap(mx3fb->reg_base);
1565        kfree(mx3fb);
1566        return 0;
1567}
1568
1569static struct platform_driver mx3fb_driver = {
1570        .driver = {
1571                .name = MX3FB_NAME,
1572                .owner = THIS_MODULE,
1573        },
1574        .probe = mx3fb_probe,
1575        .remove = mx3fb_remove,
1576        .suspend = mx3fb_suspend,
1577        .resume = mx3fb_resume,
1578};
1579
1580/*
1581 * Parse user specified options (`video=mx3fb:')
1582 * example:
1583 *      video=mx3fb:bpp=16
1584 */
1585static int __init mx3fb_setup(void)
1586{
1587#ifndef MODULE
1588        char *opt, *options = NULL;
1589
1590        if (fb_get_options("mx3fb", &options))
1591                return -ENODEV;
1592
1593        if (!options || !*options)
1594                return 0;
1595
1596        while ((opt = strsep(&options, ",")) != NULL) {
1597                if (!*opt)
1598                        continue;
1599                if (!strncmp(opt, "bpp=", 4))
1600                        default_bpp = simple_strtoul(opt + 4, NULL, 0);
1601                else
1602                        fb_mode = opt;
1603        }
1604#endif
1605
1606        return 0;
1607}
1608
1609static int __init mx3fb_init(void)
1610{
1611        int ret = mx3fb_setup();
1612
1613        if (ret < 0)
1614                return ret;
1615
1616        ret = platform_driver_register(&mx3fb_driver);
1617        return ret;
1618}
1619
1620static void __exit mx3fb_exit(void)
1621{
1622        platform_driver_unregister(&mx3fb_driver);
1623}
1624
1625module_init(mx3fb_init);
1626module_exit(mx3fb_exit);
1627
1628MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1629MODULE_DESCRIPTION("MX3 framebuffer driver");
1630MODULE_ALIAS("platform:" MX3FB_NAME);
1631MODULE_LICENSE("GPL v2");
1632
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.