linux/drivers/spi/spi-s3c64xx.c
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   1/*
   2 * Copyright (C) 2009 Samsung Electronics Ltd.
   3 *      Jaswinder Singh <jassi.brar@samsung.com>
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 */
  19
  20#include <linux/init.h>
  21#include <linux/module.h>
  22#include <linux/workqueue.h>
  23#include <linux/interrupt.h>
  24#include <linux/delay.h>
  25#include <linux/clk.h>
  26#include <linux/dma-mapping.h>
  27#include <linux/platform_device.h>
  28#include <linux/pm_runtime.h>
  29#include <linux/spi/spi.h>
  30#include <linux/gpio.h>
  31#include <linux/of.h>
  32#include <linux/of_gpio.h>
  33
  34#include <mach/dma.h>
  35#include <linux/platform_data/spi-s3c64xx.h>
  36
  37#define MAX_SPI_PORTS           3
  38
  39/* Registers and bit-fields */
  40
  41#define S3C64XX_SPI_CH_CFG              0x00
  42#define S3C64XX_SPI_CLK_CFG             0x04
  43#define S3C64XX_SPI_MODE_CFG    0x08
  44#define S3C64XX_SPI_SLAVE_SEL   0x0C
  45#define S3C64XX_SPI_INT_EN              0x10
  46#define S3C64XX_SPI_STATUS              0x14
  47#define S3C64XX_SPI_TX_DATA             0x18
  48#define S3C64XX_SPI_RX_DATA             0x1C
  49#define S3C64XX_SPI_PACKET_CNT  0x20
  50#define S3C64XX_SPI_PENDING_CLR 0x24
  51#define S3C64XX_SPI_SWAP_CFG    0x28
  52#define S3C64XX_SPI_FB_CLK              0x2C
  53
  54#define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  55#define S3C64XX_SPI_CH_SW_RST           (1<<5)
  56#define S3C64XX_SPI_CH_SLAVE            (1<<4)
  57#define S3C64XX_SPI_CPOL_L              (1<<3)
  58#define S3C64XX_SPI_CPHA_B              (1<<2)
  59#define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  60#define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  61
  62#define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  63#define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  64#define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  65#define S3C64XX_SPI_PSR_MASK            0xff
  66
  67#define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  68#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  69#define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  70#define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  71#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  72#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  73#define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  74#define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  75#define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  76#define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  77#define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  78
  79#define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  80#define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  81
  82#define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  83#define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  84#define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  85#define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  86#define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  87#define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  88#define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  89
  90#define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  91#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  92#define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  93#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  94#define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  95#define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
  96
  97#define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
  98
  99#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
 100#define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 101#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 102#define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 103#define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 104
 105#define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 106#define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 107#define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 108#define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 109#define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 110#define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 111#define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 112#define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 113
 114#define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 115
 116#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 117#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 118                                (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 119#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 120#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 121                                        FIFO_LVL_MASK(i))
 122
 123#define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 124#define S3C64XX_SPI_TRAILCNT_OFF        19
 125
 126#define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 127
 128#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 129
 130#define RXBUSY    (1<<2)
 131#define TXBUSY    (1<<3)
 132
 133struct s3c64xx_spi_dma_data {
 134        unsigned                ch;
 135        enum dma_transfer_direction direction;
 136        enum dma_ch     dmach;
 137        struct property         *dma_prop;
 138};
 139
 140/**
 141 * struct s3c64xx_spi_info - SPI Controller hardware info
 142 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 143 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 144 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 145 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 146 * @clk_from_cmu: True, if the controller does not include a clock mux and
 147 *      prescaler unit.
 148 *
 149 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 150 * differ in some aspects such as the size of the fifo and spi bus clock
 151 * setup. Such differences are specified to the driver using this structure
 152 * which is provided as driver data to the driver.
 153 */
 154struct s3c64xx_spi_port_config {
 155        int     fifo_lvl_mask[MAX_SPI_PORTS];
 156        int     rx_lvl_offset;
 157        int     tx_st_done;
 158        bool    high_speed;
 159        bool    clk_from_cmu;
 160};
 161
 162/**
 163 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 164 * @clk: Pointer to the spi clock.
 165 * @src_clk: Pointer to the clock used to generate SPI signals.
 166 * @master: Pointer to the SPI Protocol master.
 167 * @cntrlr_info: Platform specific data for the controller this driver manages.
 168 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 169 * @queue: To log SPI xfer requests.
 170 * @lock: Controller specific lock.
 171 * @state: Set of FLAGS to indicate status.
 172 * @rx_dmach: Controller's DMA channel for Rx.
 173 * @tx_dmach: Controller's DMA channel for Tx.
 174 * @sfr_start: BUS address of SPI controller regs.
 175 * @regs: Pointer to ioremap'ed controller registers.
 176 * @irq: interrupt
 177 * @xfer_completion: To indicate completion of xfer task.
 178 * @cur_mode: Stores the active configuration of the controller.
 179 * @cur_bpw: Stores the active bits per word settings.
 180 * @cur_speed: Stores the active xfer clock speed.
 181 */
 182struct s3c64xx_spi_driver_data {
 183        void __iomem                    *regs;
 184        struct clk                      *clk;
 185        struct clk                      *src_clk;
 186        struct platform_device          *pdev;
 187        struct spi_master               *master;
 188        struct s3c64xx_spi_info  *cntrlr_info;
 189        struct spi_device               *tgl_spi;
 190        struct list_head                queue;
 191        spinlock_t                      lock;
 192        unsigned long                   sfr_start;
 193        struct completion               xfer_completion;
 194        unsigned                        state;
 195        unsigned                        cur_mode, cur_bpw;
 196        unsigned                        cur_speed;
 197        struct s3c64xx_spi_dma_data     rx_dma;
 198        struct s3c64xx_spi_dma_data     tx_dma;
 199        struct samsung_dma_ops          *ops;
 200        struct s3c64xx_spi_port_config  *port_conf;
 201        unsigned int                    port_id;
 202        unsigned long                   gpios[4];
 203};
 204
 205static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
 206        .name = "samsung-spi-dma",
 207};
 208
 209static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 210{
 211        void __iomem *regs = sdd->regs;
 212        unsigned long loops;
 213        u32 val;
 214
 215        writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 216
 217        val = readl(regs + S3C64XX_SPI_CH_CFG);
 218        val |= S3C64XX_SPI_CH_SW_RST;
 219        val &= ~S3C64XX_SPI_CH_HS_EN;
 220        writel(val, regs + S3C64XX_SPI_CH_CFG);
 221
 222        /* Flush TxFIFO*/
 223        loops = msecs_to_loops(1);
 224        do {
 225                val = readl(regs + S3C64XX_SPI_STATUS);
 226        } while (TX_FIFO_LVL(val, sdd) && loops--);
 227
 228        if (loops == 0)
 229                dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 230
 231        /* Flush RxFIFO*/
 232        loops = msecs_to_loops(1);
 233        do {
 234                val = readl(regs + S3C64XX_SPI_STATUS);
 235                if (RX_FIFO_LVL(val, sdd))
 236                        readl(regs + S3C64XX_SPI_RX_DATA);
 237                else
 238                        break;
 239        } while (loops--);
 240
 241        if (loops == 0)
 242                dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 243
 244        val = readl(regs + S3C64XX_SPI_CH_CFG);
 245        val &= ~S3C64XX_SPI_CH_SW_RST;
 246        writel(val, regs + S3C64XX_SPI_CH_CFG);
 247
 248        val = readl(regs + S3C64XX_SPI_MODE_CFG);
 249        val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 250        writel(val, regs + S3C64XX_SPI_MODE_CFG);
 251
 252        val = readl(regs + S3C64XX_SPI_CH_CFG);
 253        val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 254        writel(val, regs + S3C64XX_SPI_CH_CFG);
 255}
 256
 257static void s3c64xx_spi_dmacb(void *data)
 258{
 259        struct s3c64xx_spi_driver_data *sdd;
 260        struct s3c64xx_spi_dma_data *dma = data;
 261        unsigned long flags;
 262
 263        if (dma->direction == DMA_DEV_TO_MEM)
 264                sdd = container_of(data,
 265                        struct s3c64xx_spi_driver_data, rx_dma);
 266        else
 267                sdd = container_of(data,
 268                        struct s3c64xx_spi_driver_data, tx_dma);
 269
 270        spin_lock_irqsave(&sdd->lock, flags);
 271
 272        if (dma->direction == DMA_DEV_TO_MEM) {
 273                sdd->state &= ~RXBUSY;
 274                if (!(sdd->state & TXBUSY))
 275                        complete(&sdd->xfer_completion);
 276        } else {
 277                sdd->state &= ~TXBUSY;
 278                if (!(sdd->state & RXBUSY))
 279                        complete(&sdd->xfer_completion);
 280        }
 281
 282        spin_unlock_irqrestore(&sdd->lock, flags);
 283}
 284
 285static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 286                                        unsigned len, dma_addr_t buf)
 287{
 288        struct s3c64xx_spi_driver_data *sdd;
 289        struct samsung_dma_prep info;
 290        struct samsung_dma_config config;
 291
 292        if (dma->direction == DMA_DEV_TO_MEM) {
 293                sdd = container_of((void *)dma,
 294                        struct s3c64xx_spi_driver_data, rx_dma);
 295                config.direction = sdd->rx_dma.direction;
 296                config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 297                config.width = sdd->cur_bpw / 8;
 298                sdd->ops->config(sdd->rx_dma.ch, &config);
 299        } else {
 300                sdd = container_of((void *)dma,
 301                        struct s3c64xx_spi_driver_data, tx_dma);
 302                config.direction =  sdd->tx_dma.direction;
 303                config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 304                config.width = sdd->cur_bpw / 8;
 305                sdd->ops->config(sdd->tx_dma.ch, &config);
 306        }
 307
 308        info.cap = DMA_SLAVE;
 309        info.len = len;
 310        info.fp = s3c64xx_spi_dmacb;
 311        info.fp_param = dma;
 312        info.direction = dma->direction;
 313        info.buf = buf;
 314
 315        sdd->ops->prepare(dma->ch, &info);
 316        sdd->ops->trigger(dma->ch);
 317}
 318
 319static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
 320{
 321        struct samsung_dma_req req;
 322
 323        sdd->ops = samsung_dma_get_ops();
 324
 325        req.cap = DMA_SLAVE;
 326        req.client = &s3c64xx_spi_dma_client;
 327
 328        req.dt_dmach_prop = sdd->rx_dma.dma_prop;
 329        sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &req);
 330        req.dt_dmach_prop = sdd->tx_dma.dma_prop;
 331        sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &req);
 332
 333        return 1;
 334}
 335
 336static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 337                                struct spi_device *spi,
 338                                struct spi_transfer *xfer, int dma_mode)
 339{
 340        void __iomem *regs = sdd->regs;
 341        u32 modecfg, chcfg;
 342
 343        modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 344        modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 345
 346        chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 347        chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 348
 349        if (dma_mode) {
 350                chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 351        } else {
 352                /* Always shift in data in FIFO, even if xfer is Tx only,
 353                 * this helps setting PCKT_CNT value for generating clocks
 354                 * as exactly needed.
 355                 */
 356                chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 357                writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 358                                        | S3C64XX_SPI_PACKET_CNT_EN,
 359                                        regs + S3C64XX_SPI_PACKET_CNT);
 360        }
 361
 362        if (xfer->tx_buf != NULL) {
 363                sdd->state |= TXBUSY;
 364                chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 365                if (dma_mode) {
 366                        modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 367                        prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
 368                } else {
 369                        switch (sdd->cur_bpw) {
 370                        case 32:
 371                                iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 372                                        xfer->tx_buf, xfer->len / 4);
 373                                break;
 374                        case 16:
 375                                iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 376                                        xfer->tx_buf, xfer->len / 2);
 377                                break;
 378                        default:
 379                                iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 380                                        xfer->tx_buf, xfer->len);
 381                                break;
 382                        }
 383                }
 384        }
 385
 386        if (xfer->rx_buf != NULL) {
 387                sdd->state |= RXBUSY;
 388
 389                if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 390                                        && !(sdd->cur_mode & SPI_CPHA))
 391                        chcfg |= S3C64XX_SPI_CH_HS_EN;
 392
 393                if (dma_mode) {
 394                        modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 395                        chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 396                        writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 397                                        | S3C64XX_SPI_PACKET_CNT_EN,
 398                                        regs + S3C64XX_SPI_PACKET_CNT);
 399                        prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
 400                }
 401        }
 402
 403        writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 404        writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 405}
 406
 407static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 408                                                struct spi_device *spi)
 409{
 410        struct s3c64xx_spi_csinfo *cs;
 411
 412        if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
 413                if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 414                        /* Deselect the last toggled device */
 415                        cs = sdd->tgl_spi->controller_data;
 416                        gpio_set_value(cs->line,
 417                                spi->mode & SPI_CS_HIGH ? 0 : 1);
 418                }
 419                sdd->tgl_spi = NULL;
 420        }
 421
 422        cs = spi->controller_data;
 423        gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
 424}
 425
 426static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 427                                struct spi_transfer *xfer, int dma_mode)
 428{
 429        void __iomem *regs = sdd->regs;
 430        unsigned long val;
 431        int ms;
 432
 433        /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 434        ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 435        ms += 10; /* some tolerance */
 436
 437        if (dma_mode) {
 438                val = msecs_to_jiffies(ms) + 10;
 439                val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 440        } else {
 441                u32 status;
 442                val = msecs_to_loops(ms);
 443                do {
 444                        status = readl(regs + S3C64XX_SPI_STATUS);
 445                } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 446        }
 447
 448        if (!val)
 449                return -EIO;
 450
 451        if (dma_mode) {
 452                u32 status;
 453
 454                /*
 455                 * DmaTx returns after simply writing data in the FIFO,
 456                 * w/o waiting for real transmission on the bus to finish.
 457                 * DmaRx returns only after Dma read data from FIFO which
 458                 * needs bus transmission to finish, so we don't worry if
 459                 * Xfer involved Rx(with or without Tx).
 460                 */
 461                if (xfer->rx_buf == NULL) {
 462                        val = msecs_to_loops(10);
 463                        status = readl(regs + S3C64XX_SPI_STATUS);
 464                        while ((TX_FIFO_LVL(status, sdd)
 465                                || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 466                                        && --val) {
 467                                cpu_relax();
 468                                status = readl(regs + S3C64XX_SPI_STATUS);
 469                        }
 470
 471                        if (!val)
 472                                return -EIO;
 473                }
 474        } else {
 475                /* If it was only Tx */
 476                if (xfer->rx_buf == NULL) {
 477                        sdd->state &= ~TXBUSY;
 478                        return 0;
 479                }
 480
 481                switch (sdd->cur_bpw) {
 482                case 32:
 483                        ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 484                                xfer->rx_buf, xfer->len / 4);
 485                        break;
 486                case 16:
 487                        ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 488                                xfer->rx_buf, xfer->len / 2);
 489                        break;
 490                default:
 491                        ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 492                                xfer->rx_buf, xfer->len);
 493                        break;
 494                }
 495                sdd->state &= ~RXBUSY;
 496        }
 497
 498        return 0;
 499}
 500
 501static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 502                                                struct spi_device *spi)
 503{
 504        struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 505
 506        if (sdd->tgl_spi == spi)
 507                sdd->tgl_spi = NULL;
 508
 509        gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
 510}
 511
 512static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 513{
 514        void __iomem *regs = sdd->regs;
 515        u32 val;
 516
 517        /* Disable Clock */
 518        if (sdd->port_conf->clk_from_cmu) {
 519                clk_disable(sdd->src_clk);
 520        } else {
 521                val = readl(regs + S3C64XX_SPI_CLK_CFG);
 522                val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 523                writel(val, regs + S3C64XX_SPI_CLK_CFG);
 524        }
 525
 526        /* Set Polarity and Phase */
 527        val = readl(regs + S3C64XX_SPI_CH_CFG);
 528        val &= ~(S3C64XX_SPI_CH_SLAVE |
 529                        S3C64XX_SPI_CPOL_L |
 530                        S3C64XX_SPI_CPHA_B);
 531
 532        if (sdd->cur_mode & SPI_CPOL)
 533                val |= S3C64XX_SPI_CPOL_L;
 534
 535        if (sdd->cur_mode & SPI_CPHA)
 536                val |= S3C64XX_SPI_CPHA_B;
 537
 538        writel(val, regs + S3C64XX_SPI_CH_CFG);
 539
 540        /* Set Channel & DMA Mode */
 541        val = readl(regs + S3C64XX_SPI_MODE_CFG);
 542        val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 543                        | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 544
 545        switch (sdd->cur_bpw) {
 546        case 32:
 547                val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 548                val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 549                break;
 550        case 16:
 551                val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 552                val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 553                break;
 554        default:
 555                val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 556                val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 557                break;
 558        }
 559
 560        writel(val, regs + S3C64XX_SPI_MODE_CFG);
 561
 562        if (sdd->port_conf->clk_from_cmu) {
 563                /* Configure Clock */
 564                /* There is half-multiplier before the SPI */
 565                clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 566                /* Enable Clock */
 567                clk_enable(sdd->src_clk);
 568        } else {
 569                /* Configure Clock */
 570                val = readl(regs + S3C64XX_SPI_CLK_CFG);
 571                val &= ~S3C64XX_SPI_PSR_MASK;
 572                val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 573                                & S3C64XX_SPI_PSR_MASK);
 574                writel(val, regs + S3C64XX_SPI_CLK_CFG);
 575
 576                /* Enable Clock */
 577                val = readl(regs + S3C64XX_SPI_CLK_CFG);
 578                val |= S3C64XX_SPI_ENCLK_ENABLE;
 579                writel(val, regs + S3C64XX_SPI_CLK_CFG);
 580        }
 581}
 582
 583#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 584
 585static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 586                                                struct spi_message *msg)
 587{
 588        struct device *dev = &sdd->pdev->dev;
 589        struct spi_transfer *xfer;
 590
 591        if (msg->is_dma_mapped)
 592                return 0;
 593
 594        /* First mark all xfer unmapped */
 595        list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 596                xfer->rx_dma = XFER_DMAADDR_INVALID;
 597                xfer->tx_dma = XFER_DMAADDR_INVALID;
 598        }
 599
 600        /* Map until end or first fail */
 601        list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 602
 603                if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 604                        continue;
 605
 606                if (xfer->tx_buf != NULL) {
 607                        xfer->tx_dma = dma_map_single(dev,
 608                                        (void *)xfer->tx_buf, xfer->len,
 609                                        DMA_TO_DEVICE);
 610                        if (dma_mapping_error(dev, xfer->tx_dma)) {
 611                                dev_err(dev, "dma_map_single Tx failed\n");
 612                                xfer->tx_dma = XFER_DMAADDR_INVALID;
 613                                return -ENOMEM;
 614                        }
 615                }
 616
 617                if (xfer->rx_buf != NULL) {
 618                        xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
 619                                                xfer->len, DMA_FROM_DEVICE);
 620                        if (dma_mapping_error(dev, xfer->rx_dma)) {
 621                                dev_err(dev, "dma_map_single Rx failed\n");
 622                                dma_unmap_single(dev, xfer->tx_dma,
 623                                                xfer->len, DMA_TO_DEVICE);
 624                                xfer->tx_dma = XFER_DMAADDR_INVALID;
 625                                xfer->rx_dma = XFER_DMAADDR_INVALID;
 626                                return -ENOMEM;
 627                        }
 628                }
 629        }
 630
 631        return 0;
 632}
 633
 634static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 635                                                struct spi_message *msg)
 636{
 637        struct device *dev = &sdd->pdev->dev;
 638        struct spi_transfer *xfer;
 639
 640        if (msg->is_dma_mapped)
 641                return;
 642
 643        list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 644
 645                if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 646                        continue;
 647
 648                if (xfer->rx_buf != NULL
 649                                && xfer->rx_dma != XFER_DMAADDR_INVALID)
 650                        dma_unmap_single(dev, xfer->rx_dma,
 651                                                xfer->len, DMA_FROM_DEVICE);
 652
 653                if (xfer->tx_buf != NULL
 654                                && xfer->tx_dma != XFER_DMAADDR_INVALID)
 655                        dma_unmap_single(dev, xfer->tx_dma,
 656                                                xfer->len, DMA_TO_DEVICE);
 657        }
 658}
 659
 660static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
 661                                            struct spi_message *msg)
 662{
 663        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 664        struct spi_device *spi = msg->spi;
 665        struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 666        struct spi_transfer *xfer;
 667        int status = 0, cs_toggle = 0;
 668        u32 speed;
 669        u8 bpw;
 670
 671        /* If Master's(controller) state differs from that needed by Slave */
 672        if (sdd->cur_speed != spi->max_speed_hz
 673                        || sdd->cur_mode != spi->mode
 674                        || sdd->cur_bpw != spi->bits_per_word) {
 675                sdd->cur_bpw = spi->bits_per_word;
 676                sdd->cur_speed = spi->max_speed_hz;
 677                sdd->cur_mode = spi->mode;
 678                s3c64xx_spi_config(sdd);
 679        }
 680
 681        /* Map all the transfers if needed */
 682        if (s3c64xx_spi_map_mssg(sdd, msg)) {
 683                dev_err(&spi->dev,
 684                        "Xfer: Unable to map message buffers!\n");
 685                status = -ENOMEM;
 686                goto out;
 687        }
 688
 689        /* Configure feedback delay */
 690        writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 691
 692        list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 693
 694                unsigned long flags;
 695                int use_dma;
 696
 697                INIT_COMPLETION(sdd->xfer_completion);
 698
 699                /* Only BPW and Speed may change across transfers */
 700                bpw = xfer->bits_per_word ? : spi->bits_per_word;
 701                speed = xfer->speed_hz ? : spi->max_speed_hz;
 702
 703                if (xfer->len % (bpw / 8)) {
 704                        dev_err(&spi->dev,
 705                                "Xfer length(%u) not a multiple of word size(%u)\n",
 706                                xfer->len, bpw / 8);
 707                        status = -EIO;
 708                        goto out;
 709                }
 710
 711                if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 712                        sdd->cur_bpw = bpw;
 713                        sdd->cur_speed = speed;
 714                        s3c64xx_spi_config(sdd);
 715                }
 716
 717                /* Polling method for xfers not bigger than FIFO capacity */
 718                if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 719                        use_dma = 0;
 720                else
 721                        use_dma = 1;
 722
 723                spin_lock_irqsave(&sdd->lock, flags);
 724
 725                /* Pending only which is to be done */
 726                sdd->state &= ~RXBUSY;
 727                sdd->state &= ~TXBUSY;
 728
 729                enable_datapath(sdd, spi, xfer, use_dma);
 730
 731                /* Slave Select */
 732                enable_cs(sdd, spi);
 733
 734                /* Start the signals */
 735                writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 736
 737                spin_unlock_irqrestore(&sdd->lock, flags);
 738
 739                status = wait_for_xfer(sdd, xfer, use_dma);
 740
 741                /* Quiese the signals */
 742                writel(S3C64XX_SPI_SLAVE_SIG_INACT,
 743                       sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 744
 745                if (status) {
 746                        dev_err(&spi->dev, "I/O Error: "
 747                                "rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 748                                xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 749                                (sdd->state & RXBUSY) ? 'f' : 'p',
 750                                (sdd->state & TXBUSY) ? 'f' : 'p',
 751                                xfer->len);
 752
 753                        if (use_dma) {
 754                                if (xfer->tx_buf != NULL
 755                                                && (sdd->state & TXBUSY))
 756                                        sdd->ops->stop(sdd->tx_dma.ch);
 757                                if (xfer->rx_buf != NULL
 758                                                && (sdd->state & RXBUSY))
 759                                        sdd->ops->stop(sdd->rx_dma.ch);
 760                        }
 761
 762                        goto out;
 763                }
 764
 765                if (xfer->delay_usecs)
 766                        udelay(xfer->delay_usecs);
 767
 768                if (xfer->cs_change) {
 769                        /* Hint that the next mssg is gonna be
 770                           for the same device */
 771                        if (list_is_last(&xfer->transfer_list,
 772                                                &msg->transfers))
 773                                cs_toggle = 1;
 774                        else
 775                                disable_cs(sdd, spi);
 776                }
 777
 778                msg->actual_length += xfer->len;
 779
 780                flush_fifo(sdd);
 781        }
 782
 783out:
 784        if (!cs_toggle || status)
 785                disable_cs(sdd, spi);
 786        else
 787                sdd->tgl_spi = spi;
 788
 789        s3c64xx_spi_unmap_mssg(sdd, msg);
 790
 791        msg->status = status;
 792
 793        spi_finalize_current_message(master);
 794
 795        return 0;
 796}
 797
 798static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 799{
 800        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 801
 802        /* Acquire DMA channels */
 803        while (!acquire_dma(sdd))
 804                msleep(10);
 805
 806        pm_runtime_get_sync(&sdd->pdev->dev);
 807
 808        return 0;
 809}
 810
 811static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 812{
 813        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 814
 815        /* Free DMA channels */
 816        sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
 817        sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
 818
 819        pm_runtime_put(&sdd->pdev->dev);
 820
 821        return 0;
 822}
 823
 824static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 825                                struct s3c64xx_spi_driver_data *sdd,
 826                                struct spi_device *spi)
 827{
 828        struct s3c64xx_spi_csinfo *cs;
 829        struct device_node *slave_np, *data_np = NULL;
 830        u32 fb_delay = 0;
 831
 832        slave_np = spi->dev.of_node;
 833        if (!slave_np) {
 834                dev_err(&spi->dev, "device node not found\n");
 835                return ERR_PTR(-EINVAL);
 836        }
 837
 838        data_np = of_get_child_by_name(slave_np, "controller-data");
 839        if (!data_np) {
 840                dev_err(&spi->dev, "child node 'controller-data' not found\n");
 841                return ERR_PTR(-EINVAL);
 842        }
 843
 844        cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 845        if (!cs) {
 846                dev_err(&spi->dev, "could not allocate memory for controller"
 847                                        " data\n");
 848                of_node_put(data_np);
 849                return ERR_PTR(-ENOMEM);
 850        }
 851
 852        cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
 853        if (!gpio_is_valid(cs->line)) {
 854                dev_err(&spi->dev, "chip select gpio is not specified or "
 855                                        "invalid\n");
 856                kfree(cs);
 857                of_node_put(data_np);
 858                return ERR_PTR(-EINVAL);
 859        }
 860
 861        of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
 862        cs->fb_delay = fb_delay;
 863        of_node_put(data_np);
 864        return cs;
 865}
 866
 867/*
 868 * Here we only check the validity of requested configuration
 869 * and save the configuration in a local data-structure.
 870 * The controller is actually configured only just before we
 871 * get a message to transfer.
 872 */
 873static int s3c64xx_spi_setup(struct spi_device *spi)
 874{
 875        struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 876        struct s3c64xx_spi_driver_data *sdd;
 877        struct s3c64xx_spi_info *sci;
 878        struct spi_message *msg;
 879        unsigned long flags;
 880        int err;
 881
 882        sdd = spi_master_get_devdata(spi->master);
 883        if (!cs && spi->dev.of_node) {
 884                cs = s3c64xx_get_slave_ctrldata(sdd, spi);
 885                spi->controller_data = cs;
 886        }
 887
 888        if (IS_ERR_OR_NULL(cs)) {
 889                dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 890                return -ENODEV;
 891        }
 892
 893        if (!spi_get_ctldata(spi)) {
 894                err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
 895                                       dev_name(&spi->dev));
 896                if (err) {
 897                        dev_err(&spi->dev,
 898                                "Failed to get /CS gpio [%d]: %d\n",
 899                                cs->line, err);
 900                        goto err_gpio_req;
 901                }
 902                spi_set_ctldata(spi, cs);
 903        }
 904
 905        sci = sdd->cntrlr_info;
 906
 907        spin_lock_irqsave(&sdd->lock, flags);
 908
 909        list_for_each_entry(msg, &sdd->queue, queue) {
 910                /* Is some mssg is already queued for this device */
 911                if (msg->spi == spi) {
 912                        dev_err(&spi->dev,
 913                                "setup: attempt while mssg in queue!\n");
 914                        spin_unlock_irqrestore(&sdd->lock, flags);
 915                        err = -EBUSY;
 916                        goto err_msgq;
 917                }
 918        }
 919
 920        spin_unlock_irqrestore(&sdd->lock, flags);
 921
 922        if (spi->bits_per_word != 8
 923                        && spi->bits_per_word != 16
 924                        && spi->bits_per_word != 32) {
 925                dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
 926                                                        spi->bits_per_word);
 927                err = -EINVAL;
 928                goto setup_exit;
 929        }
 930
 931        pm_runtime_get_sync(&sdd->pdev->dev);
 932
 933        /* Check if we can provide the requested rate */
 934        if (!sdd->port_conf->clk_from_cmu) {
 935                u32 psr, speed;
 936
 937                /* Max possible */
 938                speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 939
 940                if (spi->max_speed_hz > speed)
 941                        spi->max_speed_hz = speed;
 942
 943                psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 944                psr &= S3C64XX_SPI_PSR_MASK;
 945                if (psr == S3C64XX_SPI_PSR_MASK)
 946                        psr--;
 947
 948                speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 949                if (spi->max_speed_hz < speed) {
 950                        if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 951                                psr++;
 952                        } else {
 953                                err = -EINVAL;
 954                                goto setup_exit;
 955                        }
 956                }
 957
 958                speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 959                if (spi->max_speed_hz >= speed) {
 960                        spi->max_speed_hz = speed;
 961                } else {
 962                        err = -EINVAL;
 963                        goto setup_exit;
 964                }
 965        }
 966
 967        pm_runtime_put(&sdd->pdev->dev);
 968        disable_cs(sdd, spi);
 969        return 0;
 970
 971setup_exit:
 972        /* setup() returns with device de-selected */
 973        disable_cs(sdd, spi);
 974
 975err_msgq:
 976        gpio_free(cs->line);
 977        spi_set_ctldata(spi, NULL);
 978
 979err_gpio_req:
 980        if (spi->dev.of_node)
 981                kfree(cs);
 982
 983        return err;
 984}
 985
 986static void s3c64xx_spi_cleanup(struct spi_device *spi)
 987{
 988        struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
 989
 990        if (cs) {
 991                gpio_free(cs->line);
 992                if (spi->dev.of_node)
 993                        kfree(cs);
 994        }
 995        spi_set_ctldata(spi, NULL);
 996}
 997
 998static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 999{
1000        struct s3c64xx_spi_driver_data *sdd = data;
1001        struct spi_master *spi = sdd->master;
1002        unsigned int val;
1003
1004        val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR);
1005
1006        val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1007                S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1008                S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1009                S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1010
1011        writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1012
1013        if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR)
1014                dev_err(&spi->dev, "RX overrun\n");
1015        if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR)
1016                dev_err(&spi->dev, "RX underrun\n");
1017        if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR)
1018                dev_err(&spi->dev, "TX overrun\n");
1019        if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR)
1020                dev_err(&spi->dev, "TX underrun\n");
1021
1022        return IRQ_HANDLED;
1023}
1024
1025static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1026{
1027        struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1028        void __iomem *regs = sdd->regs;
1029        unsigned int val;
1030
1031        sdd->cur_speed = 0;
1032
1033        writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1034
1035        /* Disable Interrupts - we use Polling if not DMA mode */
1036        writel(0, regs + S3C64XX_SPI_INT_EN);
1037
1038        if (!sdd->port_conf->clk_from_cmu)
1039                writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1040                                regs + S3C64XX_SPI_CLK_CFG);
1041        writel(0, regs + S3C64XX_SPI_MODE_CFG);
1042        writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1043
1044        /* Clear any irq pending bits */
1045        writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
1046                                regs + S3C64XX_SPI_PENDING_CLR);
1047
1048        writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1049
1050        val = readl(regs + S3C64XX_SPI_MODE_CFG);
1051        val &= ~S3C64XX_SPI_MODE_4BURST;
1052        val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1053        val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1054        writel(val, regs + S3C64XX_SPI_MODE_CFG);
1055
1056        flush_fifo(sdd);
1057}
1058
1059static int __devinit s3c64xx_spi_get_dmares(
1060                        struct s3c64xx_spi_driver_data *sdd, bool tx)
1061{
1062        struct platform_device *pdev = sdd->pdev;
1063        struct s3c64xx_spi_dma_data *dma_data;
1064        struct property *prop;
1065        struct resource *res;
1066        char prop_name[15], *chan_str;
1067
1068        if (tx) {
1069                dma_data = &sdd->tx_dma;
1070                dma_data->direction = DMA_MEM_TO_DEV;
1071                chan_str = "tx";
1072        } else {
1073                dma_data = &sdd->rx_dma;
1074                dma_data->direction = DMA_DEV_TO_MEM;
1075                chan_str = "rx";
1076        }
1077
1078        if (!sdd->pdev->dev.of_node) {
1079                res = platform_get_resource(pdev, IORESOURCE_DMA, tx ? 0 : 1);
1080                if (!res) {
1081                        dev_err(&pdev->dev, "Unable to get SPI-%s dma "
1082                                        "resource\n", chan_str);
1083                        return -ENXIO;
1084                }
1085                dma_data->dmach = res->start;
1086                return 0;
1087        }
1088
1089        sprintf(prop_name, "%s-dma-channel", chan_str);
1090        prop = of_find_property(pdev->dev.of_node, prop_name, NULL);
1091        if (!prop) {
1092                dev_err(&pdev->dev, "%s dma channel property not specified\n",
1093                                        chan_str);
1094                return -ENXIO;
1095        }
1096
1097        dma_data->dmach = DMACH_DT_PROP;
1098        dma_data->dma_prop = prop;
1099        return 0;
1100}
1101
1102#ifdef CONFIG_OF
1103static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1104{
1105        struct device *dev = &sdd->pdev->dev;
1106        int idx, gpio, ret;
1107
1108        /* find gpios for mosi, miso and clock lines */
1109        for (idx = 0; idx < 3; idx++) {
1110                gpio = of_get_gpio(dev->of_node, idx);
1111                if (!gpio_is_valid(gpio)) {
1112                        dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio);
1113                        goto free_gpio;
1114                }
1115
1116                ret = gpio_request(gpio, "spi-bus");
1117                if (ret) {
1118                        dev_err(dev, "gpio [%d] request failed: %d\n",
1119                                gpio, ret);
1120                        goto free_gpio;
1121                }
1122        }
1123        return 0;
1124
1125free_gpio:
1126        while (--idx >= 0)
1127                gpio_free(sdd->gpios[idx]);
1128        return -EINVAL;
1129}
1130
1131static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1132{
1133        unsigned int idx;
1134        for (idx = 0; idx < 3; idx++)
1135                gpio_free(sdd->gpios[idx]);
1136}
1137
1138static struct __devinit s3c64xx_spi_info * s3c64xx_spi_parse_dt(
1139                                                struct device *dev)
1140{
1141        struct s3c64xx_spi_info *sci;
1142        u32 temp;
1143
1144        sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1145        if (!sci) {
1146                dev_err(dev, "memory allocation for spi_info failed\n");
1147                return ERR_PTR(-ENOMEM);
1148        }
1149
1150        if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1151                dev_warn(dev, "spi bus clock parent not specified, using "
1152                                "clock at index 0 as parent\n");
1153                sci->src_clk_nr = 0;
1154        } else {
1155                sci->src_clk_nr = temp;
1156        }
1157
1158        if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1159                dev_warn(dev, "number of chip select lines not specified, "
1160                                "assuming 1 chip select line\n");
1161                sci->num_cs = 1;
1162        } else {
1163                sci->num_cs = temp;
1164        }
1165
1166        return sci;
1167}
1168#else
1169static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1170{
1171        return dev->platform_data;
1172}
1173
1174static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1175{
1176        return -EINVAL;
1177}
1178
1179static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1180{
1181}
1182#endif
1183
1184static const struct of_device_id s3c64xx_spi_dt_match[];
1185
1186static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1187                                                struct platform_device *pdev)
1188{
1189#ifdef CONFIG_OF
1190        if (pdev->dev.of_node) {
1191                const struct of_device_id *match;
1192                match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1193                return (struct s3c64xx_spi_port_config *)match->data;
1194        }
1195#endif
1196        return (struct s3c64xx_spi_port_config *)
1197                         platform_get_device_id(pdev)->driver_data;
1198}
1199
1200static int __init s3c64xx_spi_probe(struct platform_device *pdev)
1201{
1202        struct resource *mem_res;
1203        struct s3c64xx_spi_driver_data *sdd;
1204        struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
1205        struct spi_master *master;
1206        int ret, irq;
1207        char clk_name[16];
1208
1209        if (!sci && pdev->dev.of_node) {
1210                sci = s3c64xx_spi_parse_dt(&pdev->dev);
1211                if (IS_ERR(sci))
1212                        return PTR_ERR(sci);
1213        }
1214
1215        if (!sci) {
1216                dev_err(&pdev->dev, "platform_data missing!\n");
1217                return -ENODEV;
1218        }
1219
1220        mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1221        if (mem_res == NULL) {
1222                dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1223                return -ENXIO;
1224        }
1225
1226        irq = platform_get_irq(pdev, 0);
1227        if (irq < 0) {
1228                dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1229                return irq;
1230        }
1231
1232        master = spi_alloc_master(&pdev->dev,
1233                                sizeof(struct s3c64xx_spi_driver_data));
1234        if (master == NULL) {
1235                dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1236                return -ENOMEM;
1237        }
1238
1239        platform_set_drvdata(pdev, master);
1240
1241        sdd = spi_master_get_devdata(master);
1242        sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1243        sdd->master = master;
1244        sdd->cntrlr_info = sci;
1245        sdd->pdev = pdev;
1246        sdd->sfr_start = mem_res->start;
1247        if (pdev->dev.of_node) {
1248                ret = of_alias_get_id(pdev->dev.of_node, "spi");
1249                if (ret < 0) {
1250                        dev_err(&pdev->dev, "failed to get alias id, "
1251                                                "errno %d\n", ret);
1252                        goto err0;
1253                }
1254                sdd->port_id = ret;
1255        } else {
1256                sdd->port_id = pdev->id;
1257        }
1258
1259        sdd->cur_bpw = 8;
1260
1261        ret = s3c64xx_spi_get_dmares(sdd, true);
1262        if (ret)
1263                goto err0;
1264
1265        ret = s3c64xx_spi_get_dmares(sdd, false);
1266        if (ret)
1267                goto err0;
1268
1269        master->dev.of_node = pdev->dev.of_node;
1270        master->bus_num = sdd->port_id;
1271        master->setup = s3c64xx_spi_setup;
1272        master->cleanup = s3c64xx_spi_cleanup;
1273        master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1274        master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1275        master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1276        master->num_chipselect = sci->num_cs;
1277        master->dma_alignment = 8;
1278        /* the spi->mode bits understood by this driver: */
1279        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1280
1281        sdd->regs = devm_request_and_ioremap(&pdev->dev, mem_res);
1282        if (sdd->regs == NULL) {
1283                dev_err(&pdev->dev, "Unable to remap IO\n");
1284                ret = -ENXIO;
1285                goto err1;
1286        }
1287
1288        if (!sci->cfg_gpio && pdev->dev.of_node) {
1289                if (s3c64xx_spi_parse_dt_gpio(sdd))
1290                        return -EBUSY;
1291        } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) {
1292                dev_err(&pdev->dev, "Unable to config gpio\n");
1293                ret = -EBUSY;
1294                goto err2;
1295        }
1296
1297        /* Setup clocks */
1298        sdd->clk = clk_get(&pdev->dev, "spi");
1299        if (IS_ERR(sdd->clk)) {
1300                dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1301                ret = PTR_ERR(sdd->clk);
1302                goto err3;
1303        }
1304
1305        if (clk_enable(sdd->clk)) {
1306                dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1307                ret = -EBUSY;
1308                goto err4;
1309        }
1310
1311        sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1312        sdd->src_clk = clk_get(&pdev->dev, clk_name);
1313        if (IS_ERR(sdd->src_clk)) {
1314                dev_err(&pdev->dev,
1315                        "Unable to acquire clock '%s'\n", clk_name);
1316                ret = PTR_ERR(sdd->src_clk);
1317                goto err5;
1318        }
1319
1320        if (clk_enable(sdd->src_clk)) {
1321                dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1322                ret = -EBUSY;
1323                goto err6;
1324        }
1325
1326        /* Setup Deufult Mode */
1327        s3c64xx_spi_hwinit(sdd, sdd->port_id);
1328
1329        spin_lock_init(&sdd->lock);
1330        init_completion(&sdd->xfer_completion);
1331        INIT_LIST_HEAD(&sdd->queue);
1332
1333        ret = request_irq(irq, s3c64xx_spi_irq, 0, "spi-s3c64xx", sdd);
1334        if (ret != 0) {
1335                dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1336                        irq, ret);
1337                goto err7;
1338        }
1339
1340        writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1341               S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1342               sdd->regs + S3C64XX_SPI_INT_EN);
1343
1344        if (spi_register_master(master)) {
1345                dev_err(&pdev->dev, "cannot register SPI master\n");
1346                ret = -EBUSY;
1347                goto err8;
1348        }
1349
1350        dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
1351                                        "with %d Slaves attached\n",
1352                                        sdd->port_id, master->num_chipselect);
1353        dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1354                                        mem_res->end, mem_res->start,
1355                                        sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1356
1357        pm_runtime_enable(&pdev->dev);
1358
1359        return 0;
1360
1361err8:
1362        free_irq(irq, sdd);
1363err7:
1364        clk_disable(sdd->src_clk);
1365err6:
1366        clk_put(sdd->src_clk);
1367err5:
1368        clk_disable(sdd->clk);
1369err4:
1370        clk_put(sdd->clk);
1371err3:
1372        if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1373                s3c64xx_spi_dt_gpio_free(sdd);
1374err2:
1375err1:
1376err0:
1377        platform_set_drvdata(pdev, NULL);
1378        spi_master_put(master);
1379
1380        return ret;
1381}
1382
1383static int s3c64xx_spi_remove(struct platform_device *pdev)
1384{
1385        struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1386        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1387
1388        pm_runtime_disable(&pdev->dev);
1389
1390        spi_unregister_master(master);
1391
1392        writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1393
1394        free_irq(platform_get_irq(pdev, 0), sdd);
1395
1396        clk_disable(sdd->src_clk);
1397        clk_put(sdd->src_clk);
1398
1399        clk_disable(sdd->clk);
1400        clk_put(sdd->clk);
1401
1402        if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1403                s3c64xx_spi_dt_gpio_free(sdd);
1404
1405        platform_set_drvdata(pdev, NULL);
1406        spi_master_put(master);
1407
1408        return 0;
1409}
1410
1411#ifdef CONFIG_PM
1412static int s3c64xx_spi_suspend(struct device *dev)
1413{
1414        struct spi_master *master = dev_get_drvdata(dev);
1415        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1416
1417        spi_master_suspend(master);
1418
1419        /* Disable the clock */
1420        clk_disable(sdd->src_clk);
1421        clk_disable(sdd->clk);
1422
1423        if (!sdd->cntrlr_info->cfg_gpio && dev->of_node)
1424                s3c64xx_spi_dt_gpio_free(sdd);
1425
1426        sdd->cur_speed = 0; /* Output Clock is stopped */
1427
1428        return 0;
1429}
1430
1431static int s3c64xx_spi_resume(struct device *dev)
1432{
1433        struct spi_master *master = dev_get_drvdata(dev);
1434        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1435        struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1436
1437        if (!sci->cfg_gpio && dev->of_node)
1438                s3c64xx_spi_parse_dt_gpio(sdd);
1439        else
1440                sci->cfg_gpio();
1441
1442        /* Enable the clock */
1443        clk_enable(sdd->src_clk);
1444        clk_enable(sdd->clk);
1445
1446        s3c64xx_spi_hwinit(sdd, sdd->port_id);
1447
1448        spi_master_resume(master);
1449
1450        return 0;
1451}
1452#endif /* CONFIG_PM */
1453
1454#ifdef CONFIG_PM_RUNTIME
1455static int s3c64xx_spi_runtime_suspend(struct device *dev)
1456{
1457        struct spi_master *master = dev_get_drvdata(dev);
1458        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1459
1460        clk_disable(sdd->clk);
1461        clk_disable(sdd->src_clk);
1462
1463        return 0;
1464}
1465
1466static int s3c64xx_spi_runtime_resume(struct device *dev)
1467{
1468        struct spi_master *master = dev_get_drvdata(dev);
1469        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1470
1471        clk_enable(sdd->src_clk);
1472        clk_enable(sdd->clk);
1473
1474        return 0;
1475}
1476#endif /* CONFIG_PM_RUNTIME */
1477
1478static const struct dev_pm_ops s3c64xx_spi_pm = {
1479        SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1480        SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1481                           s3c64xx_spi_runtime_resume, NULL)
1482};
1483
1484static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1485        .fifo_lvl_mask  = { 0x7f },
1486        .rx_lvl_offset  = 13,
1487        .tx_st_done     = 21,
1488        .high_speed     = true,
1489};
1490
1491static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1492        .fifo_lvl_mask  = { 0x7f, 0x7F },
1493        .rx_lvl_offset  = 13,
1494        .tx_st_done     = 21,
1495};
1496
1497static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1498        .fifo_lvl_mask  = { 0x1ff, 0x7F },
1499        .rx_lvl_offset  = 15,
1500        .tx_st_done     = 25,
1501};
1502
1503static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1504        .fifo_lvl_mask  = { 0x7f, 0x7F },
1505        .rx_lvl_offset  = 13,
1506        .tx_st_done     = 21,
1507        .high_speed     = true,
1508};
1509
1510static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1511        .fifo_lvl_mask  = { 0x1ff, 0x7F },
1512        .rx_lvl_offset  = 15,
1513        .tx_st_done     = 25,
1514        .high_speed     = true,
1515};
1516
1517static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1518        .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1519        .rx_lvl_offset  = 15,
1520        .tx_st_done     = 25,
1521        .high_speed     = true,
1522        .clk_from_cmu   = true,
1523};
1524
1525static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1526        {
1527                .name           = "s3c2443-spi",
1528                .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1529        }, {
1530                .name           = "s3c6410-spi",
1531                .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1532        }, {
1533                .name           = "s5p64x0-spi",
1534                .driver_data    = (kernel_ulong_t)&s5p64x0_spi_port_config,
1535        }, {
1536                .name           = "s5pc100-spi",
1537                .driver_data    = (kernel_ulong_t)&s5pc100_spi_port_config,
1538        }, {
1539                .name           = "s5pv210-spi",
1540                .driver_data    = (kernel_ulong_t)&s5pv210_spi_port_config,
1541        }, {
1542                .name           = "exynos4210-spi",
1543                .driver_data    = (kernel_ulong_t)&exynos4_spi_port_config,
1544        },
1545        { },
1546};
1547
1548#ifdef CONFIG_OF
1549static const struct of_device_id s3c64xx_spi_dt_match[] = {
1550        { .compatible = "samsung,exynos4210-spi",
1551                        .data = (void *)&exynos4_spi_port_config,
1552        },
1553        { },
1554};
1555MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1556#endif /* CONFIG_OF */
1557
1558static struct platform_driver s3c64xx_spi_driver = {
1559        .driver = {
1560                .name   = "s3c64xx-spi",
1561                .owner = THIS_MODULE,
1562                .pm = &s3c64xx_spi_pm,
1563                .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1564        },
1565        .remove = s3c64xx_spi_remove,
1566        .id_table = s3c64xx_spi_driver_ids,
1567};
1568MODULE_ALIAS("platform:s3c64xx-spi");
1569
1570static int __init s3c64xx_spi_init(void)
1571{
1572        return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1573}
1574subsys_initcall(s3c64xx_spi_init);
1575
1576static void __exit s3c64xx_spi_exit(void)
1577{
1578        platform_driver_unregister(&s3c64xx_spi_driver);
1579}
1580module_exit(s3c64xx_spi_exit);
1581
1582MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1583MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1584MODULE_LICENSE("GPL");
1585
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