linux/drivers/spi/spi-omap-100k.c
<<
>>
Prefs
   1/*
   2 * OMAP7xx SPI 100k controller driver
   3 * Author: Fabrice Crohas <fcrohas@gmail.com>
   4 * from original omap1_mcspi driver
   5 *
   6 * Copyright (C) 2005, 2006 Nokia Corporation
   7 * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   8 *              Juha Yrj�l� <juha.yrjola@nokia.com>
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License as published by
  12 * the Free Software Foundation; either version 2 of the License, or
  13 * (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23 *
  24 */
  25#include <linux/kernel.h>
  26#include <linux/init.h>
  27#include <linux/interrupt.h>
  28#include <linux/module.h>
  29#include <linux/device.h>
  30#include <linux/delay.h>
  31#include <linux/platform_device.h>
  32#include <linux/err.h>
  33#include <linux/clk.h>
  34#include <linux/io.h>
  35#include <linux/gpio.h>
  36#include <linux/slab.h>
  37
  38#include <linux/spi/spi.h>
  39
  40#define OMAP1_SPI100K_MAX_FREQ          48000000
  41
  42#define ICR_SPITAS      (OMAP7XX_ICR_BASE + 0x12)
  43
  44#define SPI_SETUP1      0x00
  45#define SPI_SETUP2      0x02
  46#define SPI_CTRL        0x04
  47#define SPI_STATUS      0x06
  48#define SPI_TX_LSB      0x08
  49#define SPI_TX_MSB      0x0a
  50#define SPI_RX_LSB      0x0c
  51#define SPI_RX_MSB      0x0e
  52
  53#define SPI_SETUP1_INT_READ_ENABLE      (1UL << 5)
  54#define SPI_SETUP1_INT_WRITE_ENABLE     (1UL << 4)
  55#define SPI_SETUP1_CLOCK_DIVISOR(x)     ((x) << 1)
  56#define SPI_SETUP1_CLOCK_ENABLE         (1UL << 0)
  57
  58#define SPI_SETUP2_ACTIVE_EDGE_FALLING  (0UL << 0)
  59#define SPI_SETUP2_ACTIVE_EDGE_RISING   (1UL << 0)
  60#define SPI_SETUP2_NEGATIVE_LEVEL       (0UL << 5)
  61#define SPI_SETUP2_POSITIVE_LEVEL       (1UL << 5)
  62#define SPI_SETUP2_LEVEL_TRIGGER        (0UL << 10)
  63#define SPI_SETUP2_EDGE_TRIGGER         (1UL << 10)
  64
  65#define SPI_CTRL_SEN(x)                 ((x) << 7)
  66#define SPI_CTRL_WORD_SIZE(x)           (((x) - 1) << 2)
  67#define SPI_CTRL_WR                     (1UL << 1)
  68#define SPI_CTRL_RD                     (1UL << 0)
  69
  70#define SPI_STATUS_WE                   (1UL << 1)
  71#define SPI_STATUS_RD                   (1UL << 0)
  72
  73#define WRITE 0
  74#define READ  1
  75
  76
  77/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
  78 * cache operations; better heuristics consider wordsize and bitrate.
  79 */
  80#define DMA_MIN_BYTES                   8
  81
  82#define SPI_RUNNING     0
  83#define SPI_SHUTDOWN    1
  84
  85struct omap1_spi100k {
  86        struct work_struct      work;
  87
  88        /* lock protects queue and registers */
  89        spinlock_t              lock;
  90        struct list_head        msg_queue;
  91        struct spi_master       *master;
  92        struct clk              *ick;
  93        struct clk              *fck;
  94
  95        /* Virtual base address of the controller */
  96        void __iomem            *base;
  97
  98        /* State of the SPI */
  99        unsigned int            state;
 100};
 101
 102struct omap1_spi100k_cs {
 103        void __iomem            *base;
 104        int                     word_len;
 105};
 106
 107static struct workqueue_struct *omap1_spi100k_wq;
 108
 109#define MOD_REG_BIT(val, mask, set) do { \
 110        if (set) \
 111                val |= mask; \
 112        else \
 113                val &= ~mask; \
 114} while (0)
 115
 116static void spi100k_enable_clock(struct spi_master *master)
 117{
 118        unsigned int val;
 119        struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 120
 121        /* enable SPI */
 122        val = readw(spi100k->base + SPI_SETUP1);
 123        val |= SPI_SETUP1_CLOCK_ENABLE;
 124        writew(val, spi100k->base + SPI_SETUP1);
 125}
 126
 127static void spi100k_disable_clock(struct spi_master *master)
 128{
 129        unsigned int val;
 130        struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 131
 132        /* disable SPI */
 133        val = readw(spi100k->base + SPI_SETUP1);
 134        val &= ~SPI_SETUP1_CLOCK_ENABLE;
 135        writew(val, spi100k->base + SPI_SETUP1);
 136}
 137
 138static void spi100k_write_data(struct spi_master *master, int len, int data)
 139{
 140        struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 141
 142        /* write 16-bit word, shifting 8-bit data if necessary */
 143        if (len <= 8) {
 144                data <<= 8;
 145                len = 16;
 146        }
 147
 148        spi100k_enable_clock(master);
 149        writew( data , spi100k->base + SPI_TX_MSB);
 150
 151        writew(SPI_CTRL_SEN(0) |
 152               SPI_CTRL_WORD_SIZE(len) |
 153               SPI_CTRL_WR,
 154               spi100k->base + SPI_CTRL);
 155
 156        /* Wait for bit ack send change */
 157        while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE);
 158        udelay(1000);
 159
 160        spi100k_disable_clock(master);
 161}
 162
 163static int spi100k_read_data(struct spi_master *master, int len)
 164{
 165        int dataH,dataL;
 166        struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 167
 168        /* Always do at least 16 bits */
 169        if (len <= 8)
 170                len = 16;
 171
 172        spi100k_enable_clock(master);
 173        writew(SPI_CTRL_SEN(0) |
 174               SPI_CTRL_WORD_SIZE(len) |
 175               SPI_CTRL_RD,
 176               spi100k->base + SPI_CTRL);
 177
 178        while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD);
 179        udelay(1000);
 180
 181        dataL = readw(spi100k->base + SPI_RX_LSB);
 182        dataH = readw(spi100k->base + SPI_RX_MSB);
 183        spi100k_disable_clock(master);
 184
 185        return dataL;
 186}
 187
 188static void spi100k_open(struct spi_master *master)
 189{
 190        /* get control of SPI */
 191        struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 192
 193        writew(SPI_SETUP1_INT_READ_ENABLE |
 194               SPI_SETUP1_INT_WRITE_ENABLE |
 195               SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
 196
 197        /* configure clock and interrupts */
 198        writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
 199               SPI_SETUP2_NEGATIVE_LEVEL |
 200               SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
 201}
 202
 203static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
 204{
 205        if (enable)
 206                writew(0x05fc, spi100k->base + SPI_CTRL);
 207        else
 208                writew(0x05fd, spi100k->base + SPI_CTRL);
 209}
 210
 211static unsigned
 212omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 213{
 214        struct omap1_spi100k    *spi100k;
 215        struct omap1_spi100k_cs *cs = spi->controller_state;
 216        unsigned int            count, c;
 217        int                     word_len;
 218
 219        spi100k = spi_master_get_devdata(spi->master);
 220        count = xfer->len;
 221        c = count;
 222        word_len = cs->word_len;
 223
 224        if (word_len <= 8) {
 225                u8              *rx;
 226                const u8        *tx;
 227
 228                rx = xfer->rx_buf;
 229                tx = xfer->tx_buf;
 230                do {
 231                        c-=1;
 232                        if (xfer->tx_buf != NULL)
 233                                spi100k_write_data(spi->master, word_len, *tx++);
 234                        if (xfer->rx_buf != NULL)
 235                                *rx++ = spi100k_read_data(spi->master, word_len);
 236                } while(c);
 237        } else if (word_len <= 16) {
 238                u16             *rx;
 239                const u16       *tx;
 240
 241                rx = xfer->rx_buf;
 242                tx = xfer->tx_buf;
 243                do {
 244                        c-=2;
 245                        if (xfer->tx_buf != NULL)
 246                                spi100k_write_data(spi->master,word_len, *tx++);
 247                        if (xfer->rx_buf != NULL)
 248                                *rx++ = spi100k_read_data(spi->master,word_len);
 249                } while(c);
 250        } else if (word_len <= 32) {
 251                u32             *rx;
 252                const u32       *tx;
 253
 254                rx = xfer->rx_buf;
 255                tx = xfer->tx_buf;
 256                do {
 257                        c-=4;
 258                        if (xfer->tx_buf != NULL)
 259                                spi100k_write_data(spi->master,word_len, *tx);
 260                        if (xfer->rx_buf != NULL)
 261                                *rx = spi100k_read_data(spi->master,word_len);
 262                } while(c);
 263        }
 264        return count - c;
 265}
 266
 267/* called only when no transfer is active to this device */
 268static int omap1_spi100k_setup_transfer(struct spi_device *spi,
 269                struct spi_transfer *t)
 270{
 271        struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
 272        struct omap1_spi100k_cs *cs = spi->controller_state;
 273        u8 word_len = spi->bits_per_word;
 274
 275        if (t != NULL && t->bits_per_word)
 276                word_len = t->bits_per_word;
 277        if (!word_len)
 278                word_len = 8;
 279
 280        if (spi->bits_per_word > 32)
 281                return -EINVAL;
 282        cs->word_len = word_len;
 283
 284        /* SPI init before transfer */
 285        writew(0x3e , spi100k->base + SPI_SETUP1);
 286        writew(0x00 , spi100k->base + SPI_STATUS);
 287        writew(0x3e , spi100k->base + SPI_CTRL);
 288
 289        return 0;
 290}
 291
 292/* the spi->mode bits understood by this driver: */
 293#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
 294
 295static int omap1_spi100k_setup(struct spi_device *spi)
 296{
 297        int                     ret;
 298        struct omap1_spi100k    *spi100k;
 299        struct omap1_spi100k_cs *cs = spi->controller_state;
 300
 301        if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 302                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 303                        spi->bits_per_word);
 304                 return -EINVAL;
 305        }
 306
 307        spi100k = spi_master_get_devdata(spi->master);
 308
 309        if (!cs) {
 310                cs = kzalloc(sizeof *cs, GFP_KERNEL);
 311                if (!cs)
 312                        return -ENOMEM;
 313                cs->base = spi100k->base + spi->chip_select * 0x14;
 314                spi->controller_state = cs;
 315        }
 316
 317        spi100k_open(spi->master);
 318
 319        clk_enable(spi100k->ick);
 320        clk_enable(spi100k->fck);
 321
 322        ret = omap1_spi100k_setup_transfer(spi, NULL);
 323
 324        clk_disable(spi100k->ick);
 325        clk_disable(spi100k->fck);
 326
 327        return ret;
 328}
 329
 330static void omap1_spi100k_work(struct work_struct *work)
 331{
 332        struct omap1_spi100k    *spi100k;
 333        int status = 0;
 334
 335        spi100k = container_of(work, struct omap1_spi100k, work);
 336        spin_lock_irq(&spi100k->lock);
 337
 338        clk_enable(spi100k->ick);
 339        clk_enable(spi100k->fck);
 340
 341        /* We only enable one channel at a time -- the one whose message is
 342         * at the head of the queue -- although this controller would gladly
 343         * arbitrate among multiple channels.  This corresponds to "single
 344         * channel" master mode.  As a side effect, we need to manage the
 345         * chipselect with the FORCE bit ... CS != channel enable.
 346         */
 347         while (!list_empty(&spi100k->msg_queue)) {
 348                struct spi_message              *m;
 349                struct spi_device               *spi;
 350                struct spi_transfer             *t = NULL;
 351                int                             cs_active = 0;
 352                struct omap1_spi100k_cs         *cs;
 353                int                             par_override = 0;
 354
 355                m = container_of(spi100k->msg_queue.next, struct spi_message,
 356                                 queue);
 357
 358                list_del_init(&m->queue);
 359                spin_unlock_irq(&spi100k->lock);
 360
 361                spi = m->spi;
 362                cs = spi->controller_state;
 363
 364                list_for_each_entry(t, &m->transfers, transfer_list) {
 365                        if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 366                                status = -EINVAL;
 367                                break;
 368                        }
 369                        if (par_override || t->speed_hz || t->bits_per_word) {
 370                                par_override = 1;
 371                                status = omap1_spi100k_setup_transfer(spi, t);
 372                                if (status < 0)
 373                                        break;
 374                                if (!t->speed_hz && !t->bits_per_word)
 375                                        par_override = 0;
 376                        }
 377
 378                        if (!cs_active) {
 379                                omap1_spi100k_force_cs(spi100k, 1);
 380                                cs_active = 1;
 381                        }
 382
 383                        if (t->len) {
 384                                unsigned count;
 385
 386                                count = omap1_spi100k_txrx_pio(spi, t);
 387                                m->actual_length += count;
 388
 389                                if (count != t->len) {
 390                                        status = -EIO;
 391                                        break;
 392                                }
 393                        }
 394
 395                        if (t->delay_usecs)
 396                                udelay(t->delay_usecs);
 397
 398                        /* ignore the "leave it on after last xfer" hint */
 399
 400                        if (t->cs_change) {
 401                                omap1_spi100k_force_cs(spi100k, 0);
 402                                cs_active = 0;
 403                        }
 404                }
 405
 406                /* Restore defaults if they were overriden */
 407                if (par_override) {
 408                        par_override = 0;
 409                        status = omap1_spi100k_setup_transfer(spi, NULL);
 410                }
 411
 412                if (cs_active)
 413                        omap1_spi100k_force_cs(spi100k, 0);
 414
 415                m->status = status;
 416                m->complete(m->context);
 417
 418                spin_lock_irq(&spi100k->lock);
 419        }
 420
 421        clk_disable(spi100k->ick);
 422        clk_disable(spi100k->fck);
 423        spin_unlock_irq(&spi100k->lock);
 424
 425        if (status < 0)
 426                printk(KERN_WARNING "spi transfer failed with %d\n", status);
 427}
 428
 429static int omap1_spi100k_transfer(struct spi_device *spi, struct spi_message *m)
 430{
 431        struct omap1_spi100k    *spi100k;
 432        unsigned long           flags;
 433        struct spi_transfer     *t;
 434
 435        m->actual_length = 0;
 436        m->status = -EINPROGRESS;
 437
 438        spi100k = spi_master_get_devdata(spi->master);
 439
 440        /* Don't accept new work if we're shutting down */
 441        if (spi100k->state == SPI_SHUTDOWN)
 442                return -ESHUTDOWN;
 443
 444        /* reject invalid messages and transfers */
 445        if (list_empty(&m->transfers) || !m->complete)
 446                return -EINVAL;
 447
 448        list_for_each_entry(t, &m->transfers, transfer_list) {
 449                const void      *tx_buf = t->tx_buf;
 450                void            *rx_buf = t->rx_buf;
 451                unsigned        len = t->len;
 452
 453                if (t->speed_hz > OMAP1_SPI100K_MAX_FREQ
 454                                || (len && !(rx_buf || tx_buf))
 455                                || (t->bits_per_word &&
 456                                        (  t->bits_per_word < 4
 457                                        || t->bits_per_word > 32))) {
 458                        dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
 459                                        t->speed_hz,
 460                                        len,
 461                                        tx_buf ? "tx" : "",
 462                                        rx_buf ? "rx" : "",
 463                                        t->bits_per_word);
 464                        return -EINVAL;
 465                }
 466
 467                if (t->speed_hz && t->speed_hz < OMAP1_SPI100K_MAX_FREQ/(1<<16)) {
 468                        dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
 469                                        t->speed_hz,
 470                                        OMAP1_SPI100K_MAX_FREQ/(1<<16));
 471                        return -EINVAL;
 472                }
 473
 474        }
 475
 476        spin_lock_irqsave(&spi100k->lock, flags);
 477        list_add_tail(&m->queue, &spi100k->msg_queue);
 478        queue_work(omap1_spi100k_wq, &spi100k->work);
 479        spin_unlock_irqrestore(&spi100k->lock, flags);
 480
 481        return 0;
 482}
 483
 484static int __init omap1_spi100k_reset(struct omap1_spi100k *spi100k)
 485{
 486        return 0;
 487}
 488
 489static int __devinit omap1_spi100k_probe(struct platform_device *pdev)
 490{
 491        struct spi_master       *master;
 492        struct omap1_spi100k    *spi100k;
 493        int                     status = 0;
 494
 495        if (!pdev->id)
 496                return -EINVAL;
 497
 498        master = spi_alloc_master(&pdev->dev, sizeof *spi100k);
 499        if (master == NULL) {
 500                dev_dbg(&pdev->dev, "master allocation failed\n");
 501                return -ENOMEM;
 502        }
 503
 504        if (pdev->id != -1)
 505               master->bus_num = pdev->id;
 506
 507        master->setup = omap1_spi100k_setup;
 508        master->transfer = omap1_spi100k_transfer;
 509        master->cleanup = NULL;
 510        master->num_chipselect = 2;
 511        master->mode_bits = MODEBITS;
 512
 513        dev_set_drvdata(&pdev->dev, master);
 514
 515        spi100k = spi_master_get_devdata(master);
 516        spi100k->master = master;
 517
 518        /*
 519         * The memory region base address is taken as the platform_data.
 520         * You should allocate this with ioremap() before initializing
 521         * the SPI.
 522         */
 523        spi100k->base = (void __iomem *) pdev->dev.platform_data;
 524
 525        INIT_WORK(&spi100k->work, omap1_spi100k_work);
 526
 527        spin_lock_init(&spi100k->lock);
 528        INIT_LIST_HEAD(&spi100k->msg_queue);
 529        spi100k->ick = clk_get(&pdev->dev, "ick");
 530        if (IS_ERR(spi100k->ick)) {
 531                dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
 532                status = PTR_ERR(spi100k->ick);
 533                goto err1;
 534        }
 535
 536        spi100k->fck = clk_get(&pdev->dev, "fck");
 537        if (IS_ERR(spi100k->fck)) {
 538                dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
 539                status = PTR_ERR(spi100k->fck);
 540                goto err2;
 541        }
 542
 543        if (omap1_spi100k_reset(spi100k) < 0)
 544                goto err3;
 545
 546        status = spi_register_master(master);
 547        if (status < 0)
 548                goto err3;
 549
 550        spi100k->state = SPI_RUNNING;
 551
 552        return status;
 553
 554err3:
 555        clk_put(spi100k->fck);
 556err2:
 557        clk_put(spi100k->ick);
 558err1:
 559        spi_master_put(master);
 560        return status;
 561}
 562
 563static int __exit omap1_spi100k_remove(struct platform_device *pdev)
 564{
 565        struct spi_master       *master;
 566        struct omap1_spi100k    *spi100k;
 567        struct resource         *r;
 568        unsigned                limit = 500;
 569        unsigned long           flags;
 570        int                     status = 0;
 571
 572        master = dev_get_drvdata(&pdev->dev);
 573        spi100k = spi_master_get_devdata(master);
 574
 575        spin_lock_irqsave(&spi100k->lock, flags);
 576
 577        spi100k->state = SPI_SHUTDOWN;
 578        while (!list_empty(&spi100k->msg_queue) && limit--) {
 579                spin_unlock_irqrestore(&spi100k->lock, flags);
 580                msleep(10);
 581                spin_lock_irqsave(&spi100k->lock, flags);
 582        }
 583
 584        if (!list_empty(&spi100k->msg_queue))
 585                status = -EBUSY;
 586
 587        spin_unlock_irqrestore(&spi100k->lock, flags);
 588
 589        if (status != 0)
 590                return status;
 591
 592        clk_put(spi100k->fck);
 593        clk_put(spi100k->ick);
 594
 595        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 596
 597        spi_unregister_master(master);
 598
 599        return 0;
 600}
 601
 602static struct platform_driver omap1_spi100k_driver = {
 603        .driver = {
 604                .name           = "omap1_spi100k",
 605                .owner          = THIS_MODULE,
 606        },
 607        .remove         = __exit_p(omap1_spi100k_remove),
 608};
 609
 610
 611static int __init omap1_spi100k_init(void)
 612{
 613        omap1_spi100k_wq = create_singlethread_workqueue(
 614                        omap1_spi100k_driver.driver.name);
 615
 616        if (omap1_spi100k_wq == NULL)
 617                return -1;
 618
 619        return platform_driver_probe(&omap1_spi100k_driver, omap1_spi100k_probe);
 620}
 621
 622static void __exit omap1_spi100k_exit(void)
 623{
 624        platform_driver_unregister(&omap1_spi100k_driver);
 625
 626        destroy_workqueue(omap1_spi100k_wq);
 627}
 628
 629module_init(omap1_spi100k_init);
 630module_exit(omap1_spi100k_exit);
 631
 632MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
 633MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
 634MODULE_LICENSE("GPL");
 635
 636
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.