linux/drivers/pinctrl/pinctrl-coh901.c
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   1/*
   2 * U300 GPIO module.
   3 *
   4 * Copyright (C) 2007-2012 ST-Ericsson AB
   5 * License terms: GNU General Public License (GPL) version 2
   6 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
   7 * Author: Linus Walleij <linus.walleij@linaro.org>
   8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
   9 */
  10#include <linux/module.h>
  11#include <linux/irq.h>
  12#include <linux/interrupt.h>
  13#include <linux/delay.h>
  14#include <linux/errno.h>
  15#include <linux/io.h>
  16#include <linux/clk.h>
  17#include <linux/err.h>
  18#include <linux/platform_device.h>
  19#include <linux/gpio.h>
  20#include <linux/list.h>
  21#include <linux/slab.h>
  22#include <linux/pinctrl/consumer.h>
  23#include <linux/pinctrl/pinconf-generic.h>
  24#include <linux/platform_data/pinctrl-coh901.h>
  25#include "pinctrl-coh901.h"
  26
  27#define U300_GPIO_PORT_STRIDE                           (0x30)
  28/*
  29 * Control Register 32bit (R/W)
  30 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
  31 * gives the number of GPIO pins.
  32 * bit 8-2  (mask 0x000001FC) contains the core version ID.
  33 */
  34#define U300_GPIO_CR                                    (0x00)
  35#define U300_GPIO_CR_SYNC_SEL_ENABLE                    (0x00000002UL)
  36#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE                 (0x00000001UL)
  37#define U300_GPIO_PXPDIR                                (0x04)
  38#define U300_GPIO_PXPDOR                                (0x08)
  39#define U300_GPIO_PXPCR                                 (0x0C)
  40#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK              (0x0000FFFFUL)
  41#define U300_GPIO_PXPCR_PIN_MODE_MASK                   (0x00000003UL)
  42#define U300_GPIO_PXPCR_PIN_MODE_SHIFT                  (0x00000002UL)
  43#define U300_GPIO_PXPCR_PIN_MODE_INPUT                  (0x00000000UL)
  44#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL       (0x00000001UL)
  45#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN      (0x00000002UL)
  46#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE     (0x00000003UL)
  47#define U300_GPIO_PXPER                                 (0x10)
  48#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK        (0x000000FFUL)
  49#define U300_GPIO_PXPER_PULL_UP_DISABLE                 (0x00000001UL)
  50#define U300_GPIO_PXIEV                                 (0x14)
  51#define U300_GPIO_PXIEN                                 (0x18)
  52#define U300_GPIO_PXIFR                                 (0x1C)
  53#define U300_GPIO_PXICR                                 (0x20)
  54#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK             (0x000000FFUL)
  55#define U300_GPIO_PXICR_IRQ_CONFIG_MASK                 (0x00000001UL)
  56#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE         (0x00000000UL)
  57#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE          (0x00000001UL)
  58
  59/* 8 bits per port, no version has more than 7 ports */
  60#define U300_GPIO_PINS_PER_PORT 8
  61#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
  62
  63struct u300_gpio {
  64        struct gpio_chip chip;
  65        struct list_head port_list;
  66        struct clk *clk;
  67        struct resource *memres;
  68        void __iomem *base;
  69        struct device *dev;
  70        int irq_base;
  71        u32 stride;
  72        /* Register offsets */
  73        u32 pcr;
  74        u32 dor;
  75        u32 dir;
  76        u32 per;
  77        u32 icr;
  78        u32 ien;
  79        u32 iev;
  80};
  81
  82struct u300_gpio_port {
  83        struct list_head node;
  84        struct u300_gpio *gpio;
  85        char name[8];
  86        int irq;
  87        int number;
  88        u8 toggle_edge_mode;
  89};
  90
  91/*
  92 * Macro to expand to read a specific register found in the "gpio"
  93 * struct. It requires the struct u300_gpio *gpio variable to exist in
  94 * its context. It calculates the port offset from the given pin
  95 * offset, muliplies by the port stride and adds the register offset
  96 * so it provides a pointer to the desired register.
  97 */
  98#define U300_PIN_REG(pin, reg) \
  99        (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
 100
 101/*
 102 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
 103 * register.
 104 */
 105#define U300_PIN_BIT(pin) \
 106        (1 << (pin & 0x07))
 107
 108struct u300_gpio_confdata {
 109        u16 bias_mode;
 110        bool output;
 111        int outval;
 112};
 113
 114/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
 115#define BS335_GPIO_NUM_PORTS 7
 116
 117#define U300_FLOATING_INPUT { \
 118        .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
 119        .output = false, \
 120}
 121
 122#define U300_PULL_UP_INPUT { \
 123        .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
 124        .output = false, \
 125}
 126
 127#define U300_OUTPUT_LOW { \
 128        .output = true, \
 129        .outval = 0, \
 130}
 131
 132#define U300_OUTPUT_HIGH { \
 133        .output = true, \
 134        .outval = 1, \
 135}
 136
 137/* Initial configuration */
 138static const struct __initconst u300_gpio_confdata
 139bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
 140        /* Port 0, pins 0-7 */
 141        {
 142                U300_FLOATING_INPUT,
 143                U300_OUTPUT_HIGH,
 144                U300_FLOATING_INPUT,
 145                U300_OUTPUT_LOW,
 146                U300_OUTPUT_LOW,
 147                U300_OUTPUT_LOW,
 148                U300_OUTPUT_LOW,
 149                U300_OUTPUT_LOW,
 150        },
 151        /* Port 1, pins 0-7 */
 152        {
 153                U300_OUTPUT_LOW,
 154                U300_OUTPUT_LOW,
 155                U300_OUTPUT_LOW,
 156                U300_PULL_UP_INPUT,
 157                U300_FLOATING_INPUT,
 158                U300_OUTPUT_HIGH,
 159                U300_OUTPUT_LOW,
 160                U300_OUTPUT_LOW,
 161        },
 162        /* Port 2, pins 0-7 */
 163        {
 164                U300_FLOATING_INPUT,
 165                U300_FLOATING_INPUT,
 166                U300_FLOATING_INPUT,
 167                U300_FLOATING_INPUT,
 168                U300_OUTPUT_LOW,
 169                U300_PULL_UP_INPUT,
 170                U300_OUTPUT_LOW,
 171                U300_PULL_UP_INPUT,
 172        },
 173        /* Port 3, pins 0-7 */
 174        {
 175                U300_PULL_UP_INPUT,
 176                U300_OUTPUT_LOW,
 177                U300_FLOATING_INPUT,
 178                U300_FLOATING_INPUT,
 179                U300_FLOATING_INPUT,
 180                U300_FLOATING_INPUT,
 181                U300_FLOATING_INPUT,
 182                U300_FLOATING_INPUT,
 183        },
 184        /* Port 4, pins 0-7 */
 185        {
 186                U300_FLOATING_INPUT,
 187                U300_FLOATING_INPUT,
 188                U300_FLOATING_INPUT,
 189                U300_FLOATING_INPUT,
 190                U300_FLOATING_INPUT,
 191                U300_FLOATING_INPUT,
 192                U300_FLOATING_INPUT,
 193                U300_FLOATING_INPUT,
 194        },
 195        /* Port 5, pins 0-7 */
 196        {
 197                U300_FLOATING_INPUT,
 198                U300_FLOATING_INPUT,
 199                U300_FLOATING_INPUT,
 200                U300_FLOATING_INPUT,
 201                U300_FLOATING_INPUT,
 202                U300_FLOATING_INPUT,
 203                U300_FLOATING_INPUT,
 204                U300_FLOATING_INPUT,
 205        },
 206        /* Port 6, pind 0-7 */
 207        {
 208                U300_FLOATING_INPUT,
 209                U300_FLOATING_INPUT,
 210                U300_FLOATING_INPUT,
 211                U300_FLOATING_INPUT,
 212                U300_FLOATING_INPUT,
 213                U300_FLOATING_INPUT,
 214                U300_FLOATING_INPUT,
 215                U300_FLOATING_INPUT,
 216        }
 217};
 218
 219/**
 220 * to_u300_gpio() - get the pointer to u300_gpio
 221 * @chip: the gpio chip member of the structure u300_gpio
 222 */
 223static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
 224{
 225        return container_of(chip, struct u300_gpio, chip);
 226}
 227
 228static int u300_gpio_request(struct gpio_chip *chip, unsigned offset)
 229{
 230        /*
 231         * Map back to global GPIO space and request muxing, the direction
 232         * parameter does not matter for this controller.
 233         */
 234        int gpio = chip->base + offset;
 235
 236        return pinctrl_request_gpio(gpio);
 237}
 238
 239static void u300_gpio_free(struct gpio_chip *chip, unsigned offset)
 240{
 241        int gpio = chip->base + offset;
 242
 243        pinctrl_free_gpio(gpio);
 244}
 245
 246static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
 247{
 248        struct u300_gpio *gpio = to_u300_gpio(chip);
 249
 250        return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
 251}
 252
 253static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 254{
 255        struct u300_gpio *gpio = to_u300_gpio(chip);
 256        unsigned long flags;
 257        u32 val;
 258
 259        local_irq_save(flags);
 260
 261        val = readl(U300_PIN_REG(offset, dor));
 262        if (value)
 263                writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
 264        else
 265                writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
 266
 267        local_irq_restore(flags);
 268}
 269
 270static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 271{
 272        struct u300_gpio *gpio = to_u300_gpio(chip);
 273        unsigned long flags;
 274        u32 val;
 275
 276        local_irq_save(flags);
 277        val = readl(U300_PIN_REG(offset, pcr));
 278        /* Mask out this pin, note 2 bits per setting */
 279        val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
 280        writel(val, U300_PIN_REG(offset, pcr));
 281        local_irq_restore(flags);
 282        return 0;
 283}
 284
 285static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 286                                      int value)
 287{
 288        struct u300_gpio *gpio = to_u300_gpio(chip);
 289        unsigned long flags;
 290        u32 oldmode;
 291        u32 val;
 292
 293        local_irq_save(flags);
 294        val = readl(U300_PIN_REG(offset, pcr));
 295        /*
 296         * Drive mode must be set by the special mode set function, set
 297         * push/pull mode by default if no mode has been selected.
 298         */
 299        oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
 300                         ((offset & 0x07) << 1));
 301        /* mode = 0 means input, else some mode is already set */
 302        if (oldmode == 0) {
 303                val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
 304                         ((offset & 0x07) << 1));
 305                val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
 306                        << ((offset & 0x07) << 1));
 307                writel(val, U300_PIN_REG(offset, pcr));
 308        }
 309        u300_gpio_set(chip, offset, value);
 310        local_irq_restore(flags);
 311        return 0;
 312}
 313
 314static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 315{
 316        struct u300_gpio *gpio = to_u300_gpio(chip);
 317        int retirq = gpio->irq_base + offset;
 318
 319        dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d\n", offset,
 320                retirq);
 321        return retirq;
 322}
 323
 324/* Returning -EINVAL means "supported but not available" */
 325int u300_gpio_config_get(struct gpio_chip *chip,
 326                         unsigned offset,
 327                         unsigned long *config)
 328{
 329        struct u300_gpio *gpio = to_u300_gpio(chip);
 330        enum pin_config_param param = (enum pin_config_param) *config;
 331        bool biasmode;
 332        u32 drmode;
 333
 334        /* One bit per pin, clamp to bool range */
 335        biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
 336
 337        /* Mask out the two bits for this pin and shift to bits 0,1 */
 338        drmode = readl(U300_PIN_REG(offset, pcr));
 339        drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
 340        drmode >>= ((offset & 0x07) << 1);
 341
 342        switch(param) {
 343        case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 344                *config = 0;
 345                if (biasmode)
 346                        return 0;
 347                else
 348                        return -EINVAL;
 349                break;
 350        case PIN_CONFIG_BIAS_PULL_UP:
 351                *config = 0;
 352                if (!biasmode)
 353                        return 0;
 354                else
 355                        return -EINVAL;
 356                break;
 357        case PIN_CONFIG_DRIVE_PUSH_PULL:
 358                *config = 0;
 359                if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
 360                        return 0;
 361                else
 362                        return -EINVAL;
 363                break;
 364        case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 365                *config = 0;
 366                if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
 367                        return 0;
 368                else
 369                        return -EINVAL;
 370                break;
 371        case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 372                *config = 0;
 373                if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
 374                        return 0;
 375                else
 376                        return -EINVAL;
 377                break;
 378        default:
 379                break;
 380        }
 381        return -ENOTSUPP;
 382}
 383
 384int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
 385                         enum pin_config_param param)
 386{
 387        struct u300_gpio *gpio = to_u300_gpio(chip);
 388        unsigned long flags;
 389        u32 val;
 390
 391        local_irq_save(flags);
 392        switch (param) {
 393        case PIN_CONFIG_BIAS_DISABLE:
 394        case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 395                val = readl(U300_PIN_REG(offset, per));
 396                writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
 397                break;
 398        case PIN_CONFIG_BIAS_PULL_UP:
 399                val = readl(U300_PIN_REG(offset, per));
 400                writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
 401                break;
 402        case PIN_CONFIG_DRIVE_PUSH_PULL:
 403                val = readl(U300_PIN_REG(offset, pcr));
 404                val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 405                         << ((offset & 0x07) << 1));
 406                val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
 407                        << ((offset & 0x07) << 1));
 408                writel(val, U300_PIN_REG(offset, pcr));
 409                break;
 410        case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 411                val = readl(U300_PIN_REG(offset, pcr));
 412                val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 413                         << ((offset & 0x07) << 1));
 414                val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
 415                        << ((offset & 0x07) << 1));
 416                writel(val, U300_PIN_REG(offset, pcr));
 417                break;
 418        case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 419                val = readl(U300_PIN_REG(offset, pcr));
 420                val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 421                         << ((offset & 0x07) << 1));
 422                val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
 423                        << ((offset & 0x07) << 1));
 424                writel(val, U300_PIN_REG(offset, pcr));
 425                break;
 426        default:
 427                local_irq_restore(flags);
 428                dev_err(gpio->dev, "illegal configuration requested\n");
 429                return -EINVAL;
 430        }
 431        local_irq_restore(flags);
 432        return 0;
 433}
 434
 435static struct gpio_chip u300_gpio_chip = {
 436        .label                  = "u300-gpio-chip",
 437        .owner                  = THIS_MODULE,
 438        .request                = u300_gpio_request,
 439        .free                   = u300_gpio_free,
 440        .get                    = u300_gpio_get,
 441        .set                    = u300_gpio_set,
 442        .direction_input        = u300_gpio_direction_input,
 443        .direction_output       = u300_gpio_direction_output,
 444        .to_irq                 = u300_gpio_to_irq,
 445};
 446
 447static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
 448{
 449        u32 val;
 450
 451        val = readl(U300_PIN_REG(offset, icr));
 452        /* Set mode depending on state */
 453        if (u300_gpio_get(&gpio->chip, offset)) {
 454                /* High now, let's trigger on falling edge next then */
 455                writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 456                dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
 457                        offset);
 458        } else {
 459                /* Low now, let's trigger on rising edge next then */
 460                writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 461                dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
 462                        offset);
 463        }
 464}
 465
 466static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
 467{
 468        struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
 469        struct u300_gpio *gpio = port->gpio;
 470        int offset = d->irq - gpio->irq_base;
 471        u32 val;
 472
 473        if ((trigger & IRQF_TRIGGER_RISING) &&
 474            (trigger & IRQF_TRIGGER_FALLING)) {
 475                /*
 476                 * The GPIO block can only trigger on falling OR rising edges,
 477                 * not both. So we need to toggle the mode whenever the pin
 478                 * goes from one state to the other with a special state flag
 479                 */
 480                dev_dbg(gpio->dev,
 481                        "trigger on both rising and falling edge on pin %d\n",
 482                        offset);
 483                port->toggle_edge_mode |= U300_PIN_BIT(offset);
 484                u300_toggle_trigger(gpio, offset);
 485        } else if (trigger & IRQF_TRIGGER_RISING) {
 486                dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
 487                        offset);
 488                val = readl(U300_PIN_REG(offset, icr));
 489                writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 490                port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
 491        } else if (trigger & IRQF_TRIGGER_FALLING) {
 492                dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
 493                        offset);
 494                val = readl(U300_PIN_REG(offset, icr));
 495                writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 496                port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
 497        }
 498
 499        return 0;
 500}
 501
 502static void u300_gpio_irq_enable(struct irq_data *d)
 503{
 504        struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
 505        struct u300_gpio *gpio = port->gpio;
 506        int offset = d->irq - gpio->irq_base;
 507        u32 val;
 508        unsigned long flags;
 509
 510        local_irq_save(flags);
 511        val = readl(U300_PIN_REG(offset, ien));
 512        writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
 513        local_irq_restore(flags);
 514}
 515
 516static void u300_gpio_irq_disable(struct irq_data *d)
 517{
 518        struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
 519        struct u300_gpio *gpio = port->gpio;
 520        int offset = d->irq - gpio->irq_base;
 521        u32 val;
 522        unsigned long flags;
 523
 524        local_irq_save(flags);
 525        val = readl(U300_PIN_REG(offset, ien));
 526        writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
 527        local_irq_restore(flags);
 528}
 529
 530static struct irq_chip u300_gpio_irqchip = {
 531        .name                   = "u300-gpio-irqchip",
 532        .irq_enable             = u300_gpio_irq_enable,
 533        .irq_disable            = u300_gpio_irq_disable,
 534        .irq_set_type           = u300_gpio_irq_type,
 535
 536};
 537
 538static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 539{
 540        struct u300_gpio_port *port = irq_get_handler_data(irq);
 541        struct u300_gpio *gpio = port->gpio;
 542        int pinoffset = port->number << 3; /* get the right stride */
 543        unsigned long val;
 544
 545        desc->irq_data.chip->irq_ack(&desc->irq_data);
 546        /* Read event register */
 547        val = readl(U300_PIN_REG(pinoffset, iev));
 548        /* Mask relevant bits */
 549        val &= 0xFFU; /* 8 bits per port */
 550        /* ACK IRQ (clear event) */
 551        writel(val, U300_PIN_REG(pinoffset, iev));
 552
 553        /* Call IRQ handler */
 554        if (val != 0) {
 555                int irqoffset;
 556
 557                for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
 558                        int pin_irq = gpio->irq_base + (port->number << 3)
 559                                + irqoffset;
 560                        int offset = pinoffset + irqoffset;
 561
 562                        dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
 563                                pin_irq, offset);
 564                        generic_handle_irq(pin_irq);
 565                        /*
 566                         * Triggering IRQ on both rising and falling edge
 567                         * needs mockery
 568                         */
 569                        if (port->toggle_edge_mode & U300_PIN_BIT(offset))
 570                                u300_toggle_trigger(gpio, offset);
 571                }
 572        }
 573
 574        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 575}
 576
 577static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
 578                                      int offset,
 579                                      const struct u300_gpio_confdata *conf)
 580{
 581        /* Set mode: input or output */
 582        if (conf->output) {
 583                u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
 584
 585                /* Deactivate bias mode for output */
 586                u300_gpio_config_set(&gpio->chip, offset,
 587                                     PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
 588
 589                /* Set drive mode for output */
 590                u300_gpio_config_set(&gpio->chip, offset,
 591                                     PIN_CONFIG_DRIVE_PUSH_PULL);
 592
 593                dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
 594                        offset, conf->outval);
 595        } else {
 596                u300_gpio_direction_input(&gpio->chip, offset);
 597
 598                /* Always set output low on input pins */
 599                u300_gpio_set(&gpio->chip, offset, 0);
 600
 601                /* Set bias mode for input */
 602                u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
 603
 604                dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
 605                        offset, conf->bias_mode);
 606        }
 607}
 608
 609static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
 610                                     struct u300_gpio_platform *plat)
 611{
 612        int i, j;
 613
 614        /* Write default config and values to all pins */
 615        for (i = 0; i < plat->ports; i++) {
 616                for (j = 0; j < 8; j++) {
 617                        const struct u300_gpio_confdata *conf;
 618                        int offset = (i*8) + j;
 619
 620                        conf = &bs335_gpio_config[i][j];
 621                        u300_gpio_init_pin(gpio, offset, conf);
 622                }
 623        }
 624}
 625
 626static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
 627{
 628        struct u300_gpio_port *port;
 629        struct list_head *p, *n;
 630
 631        list_for_each_safe(p, n, &gpio->port_list) {
 632                port = list_entry(p, struct u300_gpio_port, node);
 633                list_del(&port->node);
 634                kfree(port);
 635        }
 636}
 637
 638static int __init u300_gpio_probe(struct platform_device *pdev)
 639{
 640        struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
 641        struct u300_gpio *gpio;
 642        int err = 0;
 643        int portno;
 644        u32 val;
 645        u32 ifr;
 646        int i;
 647
 648        gpio = kzalloc(sizeof(struct u300_gpio), GFP_KERNEL);
 649        if (gpio == NULL) {
 650                dev_err(&pdev->dev, "failed to allocate memory\n");
 651                return -ENOMEM;
 652        }
 653
 654        gpio->chip = u300_gpio_chip;
 655        gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
 656        gpio->irq_base = plat->gpio_irq_base;
 657        gpio->chip.dev = &pdev->dev;
 658        gpio->chip.base = plat->gpio_base;
 659        gpio->dev = &pdev->dev;
 660
 661        /* Get GPIO clock */
 662        gpio->clk = clk_get(gpio->dev, NULL);
 663        if (IS_ERR(gpio->clk)) {
 664                err = PTR_ERR(gpio->clk);
 665                dev_err(gpio->dev, "could not get GPIO clock\n");
 666                goto err_no_clk;
 667        }
 668        err = clk_prepare_enable(gpio->clk);
 669        if (err) {
 670                dev_err(gpio->dev, "could not enable GPIO clock\n");
 671                goto err_no_clk_enable;
 672        }
 673
 674        gpio->memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 675        if (!gpio->memres) {
 676                dev_err(gpio->dev, "could not get GPIO memory resource\n");
 677                err = -ENODEV;
 678                goto err_no_resource;
 679        }
 680
 681        if (!request_mem_region(gpio->memres->start,
 682                                resource_size(gpio->memres),
 683                                "GPIO Controller")) {
 684                err = -ENODEV;
 685                goto err_no_ioregion;
 686        }
 687
 688        gpio->base = ioremap(gpio->memres->start, resource_size(gpio->memres));
 689        if (!gpio->base) {
 690                err = -ENOMEM;
 691                goto err_no_ioremap;
 692        }
 693
 694        dev_info(gpio->dev,
 695                 "initializing GPIO Controller COH 901 571/3\n");
 696        gpio->stride = U300_GPIO_PORT_STRIDE;
 697        gpio->pcr = U300_GPIO_PXPCR;
 698        gpio->dor = U300_GPIO_PXPDOR;
 699        gpio->dir = U300_GPIO_PXPDIR;
 700        gpio->per = U300_GPIO_PXPER;
 701        gpio->icr = U300_GPIO_PXICR;
 702        gpio->ien = U300_GPIO_PXIEN;
 703        gpio->iev = U300_GPIO_PXIEV;
 704        ifr = U300_GPIO_PXIFR;
 705
 706        val = readl(gpio->base + U300_GPIO_CR);
 707        dev_info(gpio->dev, "COH901571/3 block version: %d, " \
 708                 "number of cores: %d totalling %d pins\n",
 709                 ((val & 0x000001FC) >> 2),
 710                 ((val & 0x0000FE00) >> 9),
 711                 ((val & 0x0000FE00) >> 9) * 8);
 712        writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
 713               gpio->base + U300_GPIO_CR);
 714        u300_gpio_init_coh901571(gpio, plat);
 715
 716        /* Add each port with its IRQ separately */
 717        INIT_LIST_HEAD(&gpio->port_list);
 718        for (portno = 0 ; portno < plat->ports; portno++) {
 719                struct u300_gpio_port *port =
 720                        kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
 721
 722                if (!port) {
 723                        dev_err(gpio->dev, "out of memory\n");
 724                        err = -ENOMEM;
 725                        goto err_no_port;
 726                }
 727
 728                snprintf(port->name, 8, "gpio%d", portno);
 729                port->number = portno;
 730                port->gpio = gpio;
 731
 732                port->irq = platform_get_irq_byname(pdev,
 733                                                    port->name);
 734
 735                dev_dbg(gpio->dev, "register IRQ %d for %s\n", port->irq,
 736                        port->name);
 737
 738                irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
 739                irq_set_handler_data(port->irq, port);
 740
 741                /* For each GPIO pin set the unique IRQ handler */
 742                for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
 743                        int irqno = gpio->irq_base + (portno << 3) + i;
 744
 745                        dev_dbg(gpio->dev, "handler for IRQ %d on %s\n",
 746                                irqno, port->name);
 747                        irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
 748                                                 handle_simple_irq);
 749                        set_irq_flags(irqno, IRQF_VALID);
 750                        irq_set_chip_data(irqno, port);
 751                }
 752
 753                /* Turns off irq force (test register) for this port */
 754                writel(0x0, gpio->base + portno * gpio->stride + ifr);
 755
 756                list_add_tail(&port->node, &gpio->port_list);
 757        }
 758        dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
 759
 760        err = gpiochip_add(&gpio->chip);
 761        if (err) {
 762                dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
 763                goto err_no_chip;
 764        }
 765
 766        /* Spawn pin controller device as child of the GPIO, pass gpio chip */
 767        plat->pinctrl_device->dev.platform_data = &gpio->chip;
 768        err = platform_device_register(plat->pinctrl_device);
 769        if (err)
 770                goto err_no_pinctrl;
 771
 772        platform_set_drvdata(pdev, gpio);
 773
 774        return 0;
 775
 776err_no_pinctrl:
 777        err = gpiochip_remove(&gpio->chip);
 778err_no_chip:
 779err_no_port:
 780        u300_gpio_free_ports(gpio);
 781        iounmap(gpio->base);
 782err_no_ioremap:
 783        release_mem_region(gpio->memres->start, resource_size(gpio->memres));
 784err_no_ioregion:
 785err_no_resource:
 786        clk_disable_unprepare(gpio->clk);
 787err_no_clk_enable:
 788        clk_put(gpio->clk);
 789err_no_clk:
 790        kfree(gpio);
 791        dev_info(&pdev->dev, "module ERROR:%d\n", err);
 792        return err;
 793}
 794
 795static int __exit u300_gpio_remove(struct platform_device *pdev)
 796{
 797        struct u300_gpio *gpio = platform_get_drvdata(pdev);
 798        int err;
 799
 800        /* Turn off the GPIO block */
 801        writel(0x00000000U, gpio->base + U300_GPIO_CR);
 802
 803        err = gpiochip_remove(&gpio->chip);
 804        if (err < 0) {
 805                dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
 806                return err;
 807        }
 808        u300_gpio_free_ports(gpio);
 809        iounmap(gpio->base);
 810        release_mem_region(gpio->memres->start,
 811                           resource_size(gpio->memres));
 812        clk_disable_unprepare(gpio->clk);
 813        clk_put(gpio->clk);
 814        platform_set_drvdata(pdev, NULL);
 815        kfree(gpio);
 816        return 0;
 817}
 818
 819static struct platform_driver u300_gpio_driver = {
 820        .driver         = {
 821                .name   = "u300-gpio",
 822        },
 823        .remove         = __exit_p(u300_gpio_remove),
 824};
 825
 826static int __init u300_gpio_init(void)
 827{
 828        return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
 829}
 830
 831static void __exit u300_gpio_exit(void)
 832{
 833        platform_driver_unregister(&u300_gpio_driver);
 834}
 835
 836arch_initcall(u300_gpio_init);
 837module_exit(u300_gpio_exit);
 838
 839MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
 840MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
 841MODULE_LICENSE("GPL");
 842
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