linux/drivers/ide/scc_pata.c
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   1/*
   2 * Support for IDE interfaces on Celleb platform
   3 *
   4 * (C) Copyright 2006 TOSHIBA CORPORATION
   5 *
   6 * This code is based on drivers/ide/pci/siimage.c:
   7 * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   8 * Copyright (C) 2003           Red Hat
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License as published by
  12 * the Free Software Foundation; either version 2 of the License, or
  13 * (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License along
  21 * with this program; if not, write to the Free Software Foundation, Inc.,
  22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  23 */
  24
  25#include <linux/types.h>
  26#include <linux/module.h>
  27#include <linux/pci.h>
  28#include <linux/delay.h>
  29#include <linux/ide.h>
  30#include <linux/init.h>
  31
  32#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA            0x01b4
  33
  34#define SCC_PATA_NAME           "scc IDE"
  35
  36#define TDVHSEL_MASTER          0x00000001
  37#define TDVHSEL_SLAVE           0x00000004
  38
  39#define MODE_JCUSFEN            0x00000080
  40
  41#define CCKCTRL_ATARESET        0x00040000
  42#define CCKCTRL_BUFCNT          0x00020000
  43#define CCKCTRL_CRST            0x00010000
  44#define CCKCTRL_OCLKEN          0x00000100
  45#define CCKCTRL_ATACLKOEN       0x00000002
  46#define CCKCTRL_LCLKEN          0x00000001
  47
  48#define QCHCD_IOS_SS            0x00000001
  49
  50#define QCHSD_STPDIAG           0x00020000
  51
  52#define INTMASK_MSK             0xD1000012
  53#define INTSTS_SERROR           0x80000000
  54#define INTSTS_PRERR            0x40000000
  55#define INTSTS_RERR             0x10000000
  56#define INTSTS_ICERR            0x01000000
  57#define INTSTS_BMSINT           0x00000010
  58#define INTSTS_BMHE             0x00000008
  59#define INTSTS_IOIRQS           0x00000004
  60#define INTSTS_INTRQ            0x00000002
  61#define INTSTS_ACTEINT          0x00000001
  62
  63#define ECMODE_VALUE 0x01
  64
  65static struct scc_ports {
  66        unsigned long ctl, dma;
  67        struct ide_host *host;  /* for removing port from system */
  68} scc_ports[MAX_HWIFS];
  69
  70/* PIO transfer mode  table */
  71/* JCHST */
  72static unsigned long JCHSTtbl[2][7] = {
  73        {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00},   /* 100MHz */
  74        {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00}    /* 133MHz */
  75};
  76
  77/* JCHHT */
  78static unsigned long JCHHTtbl[2][7] = {
  79        {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00},   /* 100MHz */
  80        {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00}    /* 133MHz */
  81};
  82
  83/* JCHCT */
  84static unsigned long JCHCTtbl[2][7] = {
  85        {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00},   /* 100MHz */
  86        {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00}    /* 133MHz */
  87};
  88
  89
  90/* DMA transfer mode  table */
  91/* JCHDCTM/JCHDCTS */
  92static unsigned long JCHDCTxtbl[2][7] = {
  93        {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00},   /* 100MHz */
  94        {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00}    /* 133MHz */
  95};
  96
  97/* JCSTWTM/JCSTWTS  */
  98static unsigned long JCSTWTxtbl[2][7] = {
  99        {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00},   /* 100MHz */
 100        {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 101};
 102
 103/* JCTSS */
 104static unsigned long JCTSStbl[2][7] = {
 105        {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00},   /* 100MHz */
 106        {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05}    /* 133MHz */
 107};
 108
 109/* JCENVT */
 110static unsigned long JCENVTtbl[2][7] = {
 111        {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00},   /* 100MHz */
 112        {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 113};
 114
 115/* JCACTSELS/JCACTSELM */
 116static unsigned long JCACTSELtbl[2][7] = {
 117        {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00},   /* 100MHz */
 118        {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}    /* 133MHz */
 119};
 120
 121
 122static u8 scc_ide_inb(unsigned long port)
 123{
 124        u32 data = in_be32((void*)port);
 125        return (u8)data;
 126}
 127
 128static void scc_exec_command(ide_hwif_t *hwif, u8 cmd)
 129{
 130        out_be32((void *)hwif->io_ports.command_addr, cmd);
 131        eieio();
 132        in_be32((void *)(hwif->dma_base + 0x01c));
 133        eieio();
 134}
 135
 136static u8 scc_read_status(ide_hwif_t *hwif)
 137{
 138        return (u8)in_be32((void *)hwif->io_ports.status_addr);
 139}
 140
 141static u8 scc_read_altstatus(ide_hwif_t *hwif)
 142{
 143        return (u8)in_be32((void *)hwif->io_ports.ctl_addr);
 144}
 145
 146static u8 scc_dma_sff_read_status(ide_hwif_t *hwif)
 147{
 148        return (u8)in_be32((void *)(hwif->dma_base + 4));
 149}
 150
 151static void scc_write_devctl(ide_hwif_t *hwif, u8 ctl)
 152{
 153        out_be32((void *)hwif->io_ports.ctl_addr, ctl);
 154        eieio();
 155        in_be32((void *)(hwif->dma_base + 0x01c));
 156        eieio();
 157}
 158
 159static void scc_ide_insw(unsigned long port, void *addr, u32 count)
 160{
 161        u16 *ptr = (u16 *)addr;
 162        while (count--) {
 163                *ptr++ = le16_to_cpu(in_be32((void*)port));
 164        }
 165}
 166
 167static void scc_ide_insl(unsigned long port, void *addr, u32 count)
 168{
 169        u16 *ptr = (u16 *)addr;
 170        while (count--) {
 171                *ptr++ = le16_to_cpu(in_be32((void*)port));
 172                *ptr++ = le16_to_cpu(in_be32((void*)port));
 173        }
 174}
 175
 176static void scc_ide_outb(u8 addr, unsigned long port)
 177{
 178        out_be32((void*)port, addr);
 179}
 180
 181static void
 182scc_ide_outsw(unsigned long port, void *addr, u32 count)
 183{
 184        u16 *ptr = (u16 *)addr;
 185        while (count--) {
 186                out_be32((void*)port, cpu_to_le16(*ptr++));
 187        }
 188}
 189
 190static void
 191scc_ide_outsl(unsigned long port, void *addr, u32 count)
 192{
 193        u16 *ptr = (u16 *)addr;
 194        while (count--) {
 195                out_be32((void*)port, cpu_to_le16(*ptr++));
 196                out_be32((void*)port, cpu_to_le16(*ptr++));
 197        }
 198}
 199
 200/**
 201 *      scc_set_pio_mode        -       set host controller for PIO mode
 202 *      @hwif: port
 203 *      @drive: drive
 204 *
 205 *      Load the timing settings for this device mode into the
 206 *      controller.
 207 */
 208
 209static void scc_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 210{
 211        struct scc_ports *ports = ide_get_hwifdata(hwif);
 212        unsigned long ctl_base = ports->ctl;
 213        unsigned long cckctrl_port = ctl_base + 0xff0;
 214        unsigned long piosht_port = ctl_base + 0x000;
 215        unsigned long pioct_port = ctl_base + 0x004;
 216        unsigned long reg;
 217        int offset;
 218        const u8 pio = drive->pio_mode - XFER_PIO_0;
 219
 220        reg = in_be32((void __iomem *)cckctrl_port);
 221        if (reg & CCKCTRL_ATACLKOEN) {
 222                offset = 1; /* 133MHz */
 223        } else {
 224                offset = 0; /* 100MHz */
 225        }
 226        reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
 227        out_be32((void __iomem *)piosht_port, reg);
 228        reg = JCHCTtbl[offset][pio];
 229        out_be32((void __iomem *)pioct_port, reg);
 230}
 231
 232/**
 233 *      scc_set_dma_mode        -       set host controller for DMA mode
 234 *      @hwif: port
 235 *      @drive: drive
 236 *
 237 *      Load the timing settings for this device mode into the
 238 *      controller.
 239 */
 240
 241static void scc_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 242{
 243        struct scc_ports *ports = ide_get_hwifdata(hwif);
 244        unsigned long ctl_base = ports->ctl;
 245        unsigned long cckctrl_port = ctl_base + 0xff0;
 246        unsigned long mdmact_port = ctl_base + 0x008;
 247        unsigned long mcrcst_port = ctl_base + 0x00c;
 248        unsigned long sdmact_port = ctl_base + 0x010;
 249        unsigned long scrcst_port = ctl_base + 0x014;
 250        unsigned long udenvt_port = ctl_base + 0x018;
 251        unsigned long tdvhsel_port   = ctl_base + 0x020;
 252        int is_slave = drive->dn & 1;
 253        int offset, idx;
 254        unsigned long reg;
 255        unsigned long jcactsel;
 256        const u8 speed = drive->dma_mode;
 257
 258        reg = in_be32((void __iomem *)cckctrl_port);
 259        if (reg & CCKCTRL_ATACLKOEN) {
 260                offset = 1; /* 133MHz */
 261        } else {
 262                offset = 0; /* 100MHz */
 263        }
 264
 265        idx = speed - XFER_UDMA_0;
 266
 267        jcactsel = JCACTSELtbl[offset][idx];
 268        if (is_slave) {
 269                out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
 270                out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
 271                jcactsel = jcactsel << 2;
 272                out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
 273        } else {
 274                out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
 275                out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
 276                out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
 277        }
 278        reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
 279        out_be32((void __iomem *)udenvt_port, reg);
 280}
 281
 282static void scc_dma_host_set(ide_drive_t *drive, int on)
 283{
 284        ide_hwif_t *hwif = drive->hwif;
 285        u8 unit = drive->dn & 1;
 286        u8 dma_stat = scc_dma_sff_read_status(hwif);
 287
 288        if (on)
 289                dma_stat |= (1 << (5 + unit));
 290        else
 291                dma_stat &= ~(1 << (5 + unit));
 292
 293        scc_ide_outb(dma_stat, hwif->dma_base + 4);
 294}
 295
 296/**
 297 *      scc_dma_setup   -       begin a DMA phase
 298 *      @drive: target device
 299 *      @cmd: command
 300 *
 301 *      Build an IDE DMA PRD (IDE speak for scatter gather table)
 302 *      and then set up the DMA transfer registers.
 303 *
 304 *      Returns 0 on success. If a PIO fallback is required then 1
 305 *      is returned.
 306 */
 307
 308static int scc_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
 309{
 310        ide_hwif_t *hwif = drive->hwif;
 311        u32 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
 312        u8 dma_stat;
 313
 314        /* fall back to pio! */
 315        if (ide_build_dmatable(drive, cmd) == 0)
 316                return 1;
 317
 318        /* PRD table */
 319        out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma);
 320
 321        /* specify r/w */
 322        out_be32((void __iomem *)hwif->dma_base, rw);
 323
 324        /* read DMA status for INTR & ERROR flags */
 325        dma_stat = scc_dma_sff_read_status(hwif);
 326
 327        /* clear INTR & ERROR flags */
 328        out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6);
 329
 330        return 0;
 331}
 332
 333static void scc_dma_start(ide_drive_t *drive)
 334{
 335        ide_hwif_t *hwif = drive->hwif;
 336        u8 dma_cmd = scc_ide_inb(hwif->dma_base);
 337
 338        /* start DMA */
 339        scc_ide_outb(dma_cmd | 1, hwif->dma_base);
 340}
 341
 342static int __scc_dma_end(ide_drive_t *drive)
 343{
 344        ide_hwif_t *hwif = drive->hwif;
 345        u8 dma_stat, dma_cmd;
 346
 347        /* get DMA command mode */
 348        dma_cmd = scc_ide_inb(hwif->dma_base);
 349        /* stop DMA */
 350        scc_ide_outb(dma_cmd & ~1, hwif->dma_base);
 351        /* get DMA status */
 352        dma_stat = scc_dma_sff_read_status(hwif);
 353        /* clear the INTR & ERROR bits */
 354        scc_ide_outb(dma_stat | 6, hwif->dma_base + 4);
 355        /* verify good DMA status */
 356        return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
 357}
 358
 359/**
 360 *      scc_dma_end     -       Stop DMA
 361 *      @drive: IDE drive
 362 *
 363 *      Check and clear INT Status register.
 364 *      Then call __scc_dma_end().
 365 */
 366
 367static int scc_dma_end(ide_drive_t *drive)
 368{
 369        ide_hwif_t *hwif = drive->hwif;
 370        void __iomem *dma_base = (void __iomem *)hwif->dma_base;
 371        unsigned long intsts_port = hwif->dma_base + 0x014;
 372        u32 reg;
 373        int dma_stat, data_loss = 0;
 374        static int retry = 0;
 375
 376        /* errata A308 workaround: Step5 (check data loss) */
 377        /* We don't check non ide_disk because it is limited to UDMA4 */
 378        if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr)
 379              & ATA_ERR) &&
 380            drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
 381                reg = in_be32((void __iomem *)intsts_port);
 382                if (!(reg & INTSTS_ACTEINT)) {
 383                        printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
 384                               drive->name);
 385                        data_loss = 1;
 386                        if (retry++) {
 387                                struct request *rq = hwif->rq;
 388                                ide_drive_t *drive;
 389                                int i;
 390
 391                                /* ERROR_RESET and drive->crc_count are needed
 392                                 * to reduce DMA transfer mode in retry process.
 393                                 */
 394                                if (rq)
 395                                        rq->errors |= ERROR_RESET;
 396
 397                                ide_port_for_each_dev(i, drive, hwif)
 398                                        drive->crc_count++;
 399                        }
 400                }
 401        }
 402
 403        while (1) {
 404                reg = in_be32((void __iomem *)intsts_port);
 405
 406                if (reg & INTSTS_SERROR) {
 407                        printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
 408                        out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
 409
 410                        out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
 411                        continue;
 412                }
 413
 414                if (reg & INTSTS_PRERR) {
 415                        u32 maea0, maec0;
 416                        unsigned long ctl_base = hwif->config_data;
 417
 418                        maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
 419                        maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
 420
 421                        printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
 422
 423                        out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
 424
 425                        out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
 426                        continue;
 427                }
 428
 429                if (reg & INTSTS_RERR) {
 430                        printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
 431                        out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
 432
 433                        out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
 434                        continue;
 435                }
 436
 437                if (reg & INTSTS_ICERR) {
 438                        out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
 439
 440                        printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
 441                        out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
 442                        continue;
 443                }
 444
 445                if (reg & INTSTS_BMSINT) {
 446                        printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
 447                        out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
 448
 449                        ide_do_reset(drive);
 450                        continue;
 451                }
 452
 453                if (reg & INTSTS_BMHE) {
 454                        out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
 455                        continue;
 456                }
 457
 458                if (reg & INTSTS_ACTEINT) {
 459                        out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
 460                        continue;
 461                }
 462
 463                if (reg & INTSTS_IOIRQS) {
 464                        out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
 465                        continue;
 466                }
 467                break;
 468        }
 469
 470        dma_stat = __scc_dma_end(drive);
 471        if (data_loss)
 472                dma_stat |= 2; /* emulate DMA error (to retry command) */
 473        return dma_stat;
 474}
 475
 476/* returns 1 if dma irq issued, 0 otherwise */
 477static int scc_dma_test_irq(ide_drive_t *drive)
 478{
 479        ide_hwif_t *hwif = drive->hwif;
 480        u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
 481
 482        /* SCC errata A252,A308 workaround: Step4 */
 483        if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr)
 484             & ATA_ERR) &&
 485            (int_stat & INTSTS_INTRQ))
 486                return 1;
 487
 488        /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
 489        if (int_stat & INTSTS_IOIRQS)
 490                return 1;
 491
 492        return 0;
 493}
 494
 495static u8 scc_udma_filter(ide_drive_t *drive)
 496{
 497        ide_hwif_t *hwif = drive->hwif;
 498        u8 mask = hwif->ultra_mask;
 499
 500        /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
 501        if ((drive->media != ide_disk) && (mask & 0xE0)) {
 502                printk(KERN_INFO "%s: limit %s to UDMA4\n",
 503                       SCC_PATA_NAME, drive->name);
 504                mask = ATA_UDMA4;
 505        }
 506
 507        return mask;
 508}
 509
 510/**
 511 *      setup_mmio_scc  -       map CTRL/BMID region
 512 *      @dev: PCI device we are configuring
 513 *      @name: device name
 514 *
 515 */
 516
 517static int setup_mmio_scc (struct pci_dev *dev, const char *name)
 518{
 519        void __iomem *ctl_addr;
 520        void __iomem *dma_addr;
 521        int i, ret;
 522
 523        for (i = 0; i < MAX_HWIFS; i++) {
 524                if (scc_ports[i].ctl == 0)
 525                        break;
 526        }
 527        if (i >= MAX_HWIFS)
 528                return -ENOMEM;
 529
 530        ret = pci_request_selected_regions(dev, (1 << 2) - 1, name);
 531        if (ret < 0) {
 532                printk(KERN_ERR "%s: can't reserve resources\n", name);
 533                return ret;
 534        }
 535
 536        ctl_addr = pci_ioremap_bar(dev, 0);
 537        if (!ctl_addr)
 538                goto fail_0;
 539
 540        dma_addr = pci_ioremap_bar(dev, 1);
 541        if (!dma_addr)
 542                goto fail_1;
 543
 544        pci_set_master(dev);
 545        scc_ports[i].ctl = (unsigned long)ctl_addr;
 546        scc_ports[i].dma = (unsigned long)dma_addr;
 547        pci_set_drvdata(dev, (void *) &scc_ports[i]);
 548
 549        return 1;
 550
 551 fail_1:
 552        iounmap(ctl_addr);
 553 fail_0:
 554        return -ENOMEM;
 555}
 556
 557static int scc_ide_setup_pci_device(struct pci_dev *dev,
 558                                    const struct ide_port_info *d)
 559{
 560        struct scc_ports *ports = pci_get_drvdata(dev);
 561        struct ide_host *host;
 562        struct ide_hw hw, *hws[] = { &hw };
 563        int i, rc;
 564
 565        memset(&hw, 0, sizeof(hw));
 566        for (i = 0; i <= 8; i++)
 567                hw.io_ports_array[i] = ports->dma + 0x20 + i * 4;
 568        hw.irq = dev->irq;
 569        hw.dev = &dev->dev;
 570
 571        rc = ide_host_add(d, hws, 1, &host);
 572        if (rc)
 573                return rc;
 574
 575        ports->host = host;
 576
 577        return 0;
 578}
 579
 580/**
 581 *      init_setup_scc  -       set up an SCC PATA Controller
 582 *      @dev: PCI device
 583 *      @d: IDE port info
 584 *
 585 *      Perform the initial set up for this device.
 586 */
 587
 588static int __devinit init_setup_scc(struct pci_dev *dev,
 589                                    const struct ide_port_info *d)
 590{
 591        unsigned long ctl_base;
 592        unsigned long dma_base;
 593        unsigned long cckctrl_port;
 594        unsigned long intmask_port;
 595        unsigned long mode_port;
 596        unsigned long ecmode_port;
 597        u32 reg = 0;
 598        struct scc_ports *ports;
 599        int rc;
 600
 601        rc = pci_enable_device(dev);
 602        if (rc)
 603                goto end;
 604
 605        rc = setup_mmio_scc(dev, d->name);
 606        if (rc < 0)
 607                goto end;
 608
 609        ports = pci_get_drvdata(dev);
 610        ctl_base = ports->ctl;
 611        dma_base = ports->dma;
 612        cckctrl_port = ctl_base + 0xff0;
 613        intmask_port = dma_base + 0x010;
 614        mode_port = ctl_base + 0x024;
 615        ecmode_port = ctl_base + 0xf00;
 616
 617        /* controller initialization */
 618        reg = 0;
 619        out_be32((void*)cckctrl_port, reg);
 620        reg |= CCKCTRL_ATACLKOEN;
 621        out_be32((void*)cckctrl_port, reg);
 622        reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
 623        out_be32((void*)cckctrl_port, reg);
 624        reg |= CCKCTRL_CRST;
 625        out_be32((void*)cckctrl_port, reg);
 626
 627        for (;;) {
 628                reg = in_be32((void*)cckctrl_port);
 629                if (reg & CCKCTRL_CRST)
 630                        break;
 631                udelay(5000);
 632        }
 633
 634        reg |= CCKCTRL_ATARESET;
 635        out_be32((void*)cckctrl_port, reg);
 636
 637        out_be32((void*)ecmode_port, ECMODE_VALUE);
 638        out_be32((void*)mode_port, MODE_JCUSFEN);
 639        out_be32((void*)intmask_port, INTMASK_MSK);
 640
 641        rc = scc_ide_setup_pci_device(dev, d);
 642
 643 end:
 644        return rc;
 645}
 646
 647static void scc_tf_load(ide_drive_t *drive, struct ide_taskfile *tf, u8 valid)
 648{
 649        struct ide_io_ports *io_ports = &drive->hwif->io_ports;
 650
 651        if (valid & IDE_VALID_FEATURE)
 652                scc_ide_outb(tf->feature, io_ports->feature_addr);
 653        if (valid & IDE_VALID_NSECT)
 654                scc_ide_outb(tf->nsect, io_ports->nsect_addr);
 655        if (valid & IDE_VALID_LBAL)
 656                scc_ide_outb(tf->lbal, io_ports->lbal_addr);
 657        if (valid & IDE_VALID_LBAM)
 658                scc_ide_outb(tf->lbam, io_ports->lbam_addr);
 659        if (valid & IDE_VALID_LBAH)
 660                scc_ide_outb(tf->lbah, io_ports->lbah_addr);
 661        if (valid & IDE_VALID_DEVICE)
 662                scc_ide_outb(tf->device, io_ports->device_addr);
 663}
 664
 665static void scc_tf_read(ide_drive_t *drive, struct ide_taskfile *tf, u8 valid)
 666{
 667        struct ide_io_ports *io_ports = &drive->hwif->io_ports;
 668
 669        if (valid & IDE_VALID_ERROR)
 670                tf->error  = scc_ide_inb(io_ports->feature_addr);
 671        if (valid & IDE_VALID_NSECT)
 672                tf->nsect  = scc_ide_inb(io_ports->nsect_addr);
 673        if (valid & IDE_VALID_LBAL)
 674                tf->lbal   = scc_ide_inb(io_ports->lbal_addr);
 675        if (valid & IDE_VALID_LBAM)
 676                tf->lbam   = scc_ide_inb(io_ports->lbam_addr);
 677        if (valid & IDE_VALID_LBAH)
 678                tf->lbah   = scc_ide_inb(io_ports->lbah_addr);
 679        if (valid & IDE_VALID_DEVICE)
 680                tf->device = scc_ide_inb(io_ports->device_addr);
 681}
 682
 683static void scc_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
 684                           void *buf, unsigned int len)
 685{
 686        unsigned long data_addr = drive->hwif->io_ports.data_addr;
 687
 688        len++;
 689
 690        if (drive->io_32bit) {
 691                scc_ide_insl(data_addr, buf, len / 4);
 692
 693                if ((len & 3) >= 2)
 694                        scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1);
 695        } else
 696                scc_ide_insw(data_addr, buf, len / 2);
 697}
 698
 699static void scc_output_data(ide_drive_t *drive,  struct ide_cmd *cmd,
 700                            void *buf, unsigned int len)
 701{
 702        unsigned long data_addr = drive->hwif->io_ports.data_addr;
 703
 704        len++;
 705
 706        if (drive->io_32bit) {
 707                scc_ide_outsl(data_addr, buf, len / 4);
 708
 709                if ((len & 3) >= 2)
 710                        scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1);
 711        } else
 712                scc_ide_outsw(data_addr, buf, len / 2);
 713}
 714
 715/**
 716 *      init_mmio_iops_scc      -       set up the iops for MMIO
 717 *      @hwif: interface to set up
 718 *
 719 */
 720
 721static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
 722{
 723        struct pci_dev *dev = to_pci_dev(hwif->dev);
 724        struct scc_ports *ports = pci_get_drvdata(dev);
 725        unsigned long dma_base = ports->dma;
 726
 727        ide_set_hwifdata(hwif, ports);
 728
 729        hwif->dma_base = dma_base;
 730        hwif->config_data = ports->ctl;
 731}
 732
 733/**
 734 *      init_iops_scc   -       set up iops
 735 *      @hwif: interface to set up
 736 *
 737 *      Do the basic setup for the SCC hardware interface
 738 *      and then do the MMIO setup.
 739 */
 740
 741static void __devinit init_iops_scc(ide_hwif_t *hwif)
 742{
 743        struct pci_dev *dev = to_pci_dev(hwif->dev);
 744
 745        hwif->hwif_data = NULL;
 746        if (pci_get_drvdata(dev) == NULL)
 747                return;
 748        init_mmio_iops_scc(hwif);
 749}
 750
 751static int __devinit scc_init_dma(ide_hwif_t *hwif,
 752                                  const struct ide_port_info *d)
 753{
 754        return ide_allocate_dma_engine(hwif);
 755}
 756
 757static u8 scc_cable_detect(ide_hwif_t *hwif)
 758{
 759        return ATA_CBL_PATA80;
 760}
 761
 762/**
 763 *      init_hwif_scc   -       set up hwif
 764 *      @hwif: interface to set up
 765 *
 766 *      We do the basic set up of the interface structure. The SCC
 767 *      requires several custom handlers so we override the default
 768 *      ide DMA handlers appropriately.
 769 */
 770
 771static void __devinit init_hwif_scc(ide_hwif_t *hwif)
 772{
 773        /* PTERADD */
 774        out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
 775
 776        if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
 777                hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
 778        else
 779                hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
 780}
 781
 782static const struct ide_tp_ops scc_tp_ops = {
 783        .exec_command           = scc_exec_command,
 784        .read_status            = scc_read_status,
 785        .read_altstatus         = scc_read_altstatus,
 786        .write_devctl           = scc_write_devctl,
 787
 788        .dev_select             = ide_dev_select,
 789        .tf_load                = scc_tf_load,
 790        .tf_read                = scc_tf_read,
 791
 792        .input_data             = scc_input_data,
 793        .output_data            = scc_output_data,
 794};
 795
 796static const struct ide_port_ops scc_port_ops = {
 797        .set_pio_mode           = scc_set_pio_mode,
 798        .set_dma_mode           = scc_set_dma_mode,
 799        .udma_filter            = scc_udma_filter,
 800        .cable_detect           = scc_cable_detect,
 801};
 802
 803static const struct ide_dma_ops scc_dma_ops = {
 804        .dma_host_set           = scc_dma_host_set,
 805        .dma_setup              = scc_dma_setup,
 806        .dma_start              = scc_dma_start,
 807        .dma_end                = scc_dma_end,
 808        .dma_test_irq           = scc_dma_test_irq,
 809        .dma_lost_irq           = ide_dma_lost_irq,
 810        .dma_timer_expiry       = ide_dma_sff_timer_expiry,
 811        .dma_sff_read_status    = scc_dma_sff_read_status,
 812};
 813
 814static const struct ide_port_info scc_chipset __devinitconst = {
 815        .name           = "sccIDE",
 816        .init_iops      = init_iops_scc,
 817        .init_dma       = scc_init_dma,
 818        .init_hwif      = init_hwif_scc,
 819        .tp_ops         = &scc_tp_ops,
 820        .port_ops       = &scc_port_ops,
 821        .dma_ops        = &scc_dma_ops,
 822        .host_flags     = IDE_HFLAG_SINGLE,
 823        .irq_flags      = IRQF_SHARED,
 824        .pio_mask       = ATA_PIO4,
 825        .chipset        = ide_pci,
 826};
 827
 828/**
 829 *      scc_init_one    -       pci layer discovery entry
 830 *      @dev: PCI device
 831 *      @id: ident table entry
 832 *
 833 *      Called by the PCI code when it finds an SCC PATA controller.
 834 *      We then use the IDE PCI generic helper to do most of the work.
 835 */
 836
 837static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 838{
 839        return init_setup_scc(dev, &scc_chipset);
 840}
 841
 842/**
 843 *      scc_remove      -       pci layer remove entry
 844 *      @dev: PCI device
 845 *
 846 *      Called by the PCI code when it removes an SCC PATA controller.
 847 */
 848
 849static void __devexit scc_remove(struct pci_dev *dev)
 850{
 851        struct scc_ports *ports = pci_get_drvdata(dev);
 852        struct ide_host *host = ports->host;
 853
 854        ide_host_remove(host);
 855
 856        iounmap((void*)ports->dma);
 857        iounmap((void*)ports->ctl);
 858        pci_release_selected_regions(dev, (1 << 2) - 1);
 859        memset(ports, 0, sizeof(*ports));
 860}
 861
 862static const struct pci_device_id scc_pci_tbl[] = {
 863        { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
 864        { 0, },
 865};
 866MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
 867
 868static struct pci_driver scc_pci_driver = {
 869        .name = "SCC IDE",
 870        .id_table = scc_pci_tbl,
 871        .probe = scc_init_one,
 872        .remove = __devexit_p(scc_remove),
 873};
 874
 875static int __init scc_ide_init(void)
 876{
 877        return ide_pci_register_driver(&scc_pci_driver);
 878}
 879
 880static void __exit scc_ide_exit(void)
 881{
 882        pci_unregister_driver(&scc_pci_driver);
 883}
 884
 885module_init(scc_ide_init);
 886module_exit(scc_ide_exit);
 887
 888MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
 889MODULE_LICENSE("GPL");
 890
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