linux/drivers/ata/sata_sil24.c
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   1/*
   2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
   3 *
   4 * Copyright 2005  Tejun Heo
   5 *
   6 * Based on preview driver from Silicon Image.
   7 *
   8 * This program is free software; you can redistribute it and/or modify it
   9 * under the terms of the GNU General Public License as published by the
  10 * Free Software Foundation; either version 2, or (at your option) any
  11 * later version.
  12 *
  13 * This program is distributed in the hope that it will be useful, but
  14 * WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 * General Public License for more details.
  17 *
  18 */
  19
  20#include <linux/kernel.h>
  21#include <linux/module.h>
  22#include <linux/gfp.h>
  23#include <linux/pci.h>
  24#include <linux/blkdev.h>
  25#include <linux/delay.h>
  26#include <linux/interrupt.h>
  27#include <linux/dma-mapping.h>
  28#include <linux/device.h>
  29#include <scsi/scsi_host.h>
  30#include <scsi/scsi_cmnd.h>
  31#include <linux/libata.h>
  32
  33#define DRV_NAME        "sata_sil24"
  34#define DRV_VERSION     "1.1"
  35
  36/*
  37 * Port request block (PRB) 32 bytes
  38 */
  39struct sil24_prb {
  40        __le16  ctrl;
  41        __le16  prot;
  42        __le32  rx_cnt;
  43        u8      fis[6 * 4];
  44};
  45
  46/*
  47 * Scatter gather entry (SGE) 16 bytes
  48 */
  49struct sil24_sge {
  50        __le64  addr;
  51        __le32  cnt;
  52        __le32  flags;
  53};
  54
  55
  56enum {
  57        SIL24_HOST_BAR          = 0,
  58        SIL24_PORT_BAR          = 2,
  59
  60        /* sil24 fetches in chunks of 64bytes.  The first block
  61         * contains the PRB and two SGEs.  From the second block, it's
  62         * consisted of four SGEs and called SGT.  Calculate the
  63         * number of SGTs that fit into one page.
  64         */
  65        SIL24_PRB_SZ            = sizeof(struct sil24_prb)
  66                                  + 2 * sizeof(struct sil24_sge),
  67        SIL24_MAX_SGT           = (PAGE_SIZE - SIL24_PRB_SZ)
  68                                  / (4 * sizeof(struct sil24_sge)),
  69
  70        /* This will give us one unused SGEs for ATA.  This extra SGE
  71         * will be used to store CDB for ATAPI devices.
  72         */
  73        SIL24_MAX_SGE           = 4 * SIL24_MAX_SGT + 1,
  74
  75        /*
  76         * Global controller registers (128 bytes @ BAR0)
  77         */
  78                /* 32 bit regs */
  79        HOST_SLOT_STAT          = 0x00, /* 32 bit slot stat * 4 */
  80        HOST_CTRL               = 0x40,
  81        HOST_IRQ_STAT           = 0x44,
  82        HOST_PHY_CFG            = 0x48,
  83        HOST_BIST_CTRL          = 0x50,
  84        HOST_BIST_PTRN          = 0x54,
  85        HOST_BIST_STAT          = 0x58,
  86        HOST_MEM_BIST_STAT      = 0x5c,
  87        HOST_FLASH_CMD          = 0x70,
  88                /* 8 bit regs */
  89        HOST_FLASH_DATA         = 0x74,
  90        HOST_TRANSITION_DETECT  = 0x75,
  91        HOST_GPIO_CTRL          = 0x76,
  92        HOST_I2C_ADDR           = 0x78, /* 32 bit */
  93        HOST_I2C_DATA           = 0x7c,
  94        HOST_I2C_XFER_CNT       = 0x7e,
  95        HOST_I2C_CTRL           = 0x7f,
  96
  97        /* HOST_SLOT_STAT bits */
  98        HOST_SSTAT_ATTN         = (1 << 31),
  99
 100        /* HOST_CTRL bits */
 101        HOST_CTRL_M66EN         = (1 << 16), /* M66EN PCI bus signal */
 102        HOST_CTRL_TRDY          = (1 << 17), /* latched PCI TRDY */
 103        HOST_CTRL_STOP          = (1 << 18), /* latched PCI STOP */
 104        HOST_CTRL_DEVSEL        = (1 << 19), /* latched PCI DEVSEL */
 105        HOST_CTRL_REQ64         = (1 << 20), /* latched PCI REQ64 */
 106        HOST_CTRL_GLOBAL_RST    = (1 << 31), /* global reset */
 107
 108        /*
 109         * Port registers
 110         * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
 111         */
 112        PORT_REGS_SIZE          = 0x2000,
 113
 114        PORT_LRAM               = 0x0000, /* 31 LRAM slots and PMP regs */
 115        PORT_LRAM_SLOT_SZ       = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
 116
 117        PORT_PMP                = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
 118        PORT_PMP_STATUS         = 0x0000, /* port device status offset */
 119        PORT_PMP_QACTIVE        = 0x0004, /* port device QActive offset */
 120        PORT_PMP_SIZE           = 0x0008, /* 8 bytes per PMP */
 121
 122                /* 32 bit regs */
 123        PORT_CTRL_STAT          = 0x1000, /* write: ctrl-set, read: stat */
 124        PORT_CTRL_CLR           = 0x1004, /* write: ctrl-clear */
 125        PORT_IRQ_STAT           = 0x1008, /* high: status, low: interrupt */
 126        PORT_IRQ_ENABLE_SET     = 0x1010, /* write: enable-set */
 127        PORT_IRQ_ENABLE_CLR     = 0x1014, /* write: enable-clear */
 128        PORT_ACTIVATE_UPPER_ADDR= 0x101c,
 129        PORT_EXEC_FIFO          = 0x1020, /* command execution fifo */
 130        PORT_CMD_ERR            = 0x1024, /* command error number */
 131        PORT_FIS_CFG            = 0x1028,
 132        PORT_FIFO_THRES         = 0x102c,
 133                /* 16 bit regs */
 134        PORT_DECODE_ERR_CNT     = 0x1040,
 135        PORT_DECODE_ERR_THRESH  = 0x1042,
 136        PORT_CRC_ERR_CNT        = 0x1044,
 137        PORT_CRC_ERR_THRESH     = 0x1046,
 138        PORT_HSHK_ERR_CNT       = 0x1048,
 139        PORT_HSHK_ERR_THRESH    = 0x104a,
 140                /* 32 bit regs */
 141        PORT_PHY_CFG            = 0x1050,
 142        PORT_SLOT_STAT          = 0x1800,
 143        PORT_CMD_ACTIVATE       = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
 144        PORT_CONTEXT            = 0x1e04,
 145        PORT_EXEC_DIAG          = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
 146        PORT_PSD_DIAG           = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
 147        PORT_SCONTROL           = 0x1f00,
 148        PORT_SSTATUS            = 0x1f04,
 149        PORT_SERROR             = 0x1f08,
 150        PORT_SACTIVE            = 0x1f0c,
 151
 152        /* PORT_CTRL_STAT bits */
 153        PORT_CS_PORT_RST        = (1 << 0), /* port reset */
 154        PORT_CS_DEV_RST         = (1 << 1), /* device reset */
 155        PORT_CS_INIT            = (1 << 2), /* port initialize */
 156        PORT_CS_IRQ_WOC         = (1 << 3), /* interrupt write one to clear */
 157        PORT_CS_CDB16           = (1 << 5), /* 0=12b cdb, 1=16b cdb */
 158        PORT_CS_PMP_RESUME      = (1 << 6), /* PMP resume */
 159        PORT_CS_32BIT_ACTV      = (1 << 10), /* 32-bit activation */
 160        PORT_CS_PMP_EN          = (1 << 13), /* port multiplier enable */
 161        PORT_CS_RDY             = (1 << 31), /* port ready to accept commands */
 162
 163        /* PORT_IRQ_STAT/ENABLE_SET/CLR */
 164        /* bits[11:0] are masked */
 165        PORT_IRQ_COMPLETE       = (1 << 0), /* command(s) completed */
 166        PORT_IRQ_ERROR          = (1 << 1), /* command execution error */
 167        PORT_IRQ_PORTRDY_CHG    = (1 << 2), /* port ready change */
 168        PORT_IRQ_PWR_CHG        = (1 << 3), /* power management change */
 169        PORT_IRQ_PHYRDY_CHG     = (1 << 4), /* PHY ready change */
 170        PORT_IRQ_COMWAKE        = (1 << 5), /* COMWAKE received */
 171        PORT_IRQ_UNK_FIS        = (1 << 6), /* unknown FIS received */
 172        PORT_IRQ_DEV_XCHG       = (1 << 7), /* device exchanged */
 173        PORT_IRQ_8B10B          = (1 << 8), /* 8b/10b decode error threshold */
 174        PORT_IRQ_CRC            = (1 << 9), /* CRC error threshold */
 175        PORT_IRQ_HANDSHAKE      = (1 << 10), /* handshake error threshold */
 176        PORT_IRQ_SDB_NOTIFY     = (1 << 11), /* SDB notify received */
 177
 178        DEF_PORT_IRQ            = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
 179                                  PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
 180                                  PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
 181
 182        /* bits[27:16] are unmasked (raw) */
 183        PORT_IRQ_RAW_SHIFT      = 16,
 184        PORT_IRQ_MASKED_MASK    = 0x7ff,
 185        PORT_IRQ_RAW_MASK       = (0x7ff << PORT_IRQ_RAW_SHIFT),
 186
 187        /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
 188        PORT_IRQ_STEER_SHIFT    = 30,
 189        PORT_IRQ_STEER_MASK     = (3 << PORT_IRQ_STEER_SHIFT),
 190
 191        /* PORT_CMD_ERR constants */
 192        PORT_CERR_DEV           = 1, /* Error bit in D2H Register FIS */
 193        PORT_CERR_SDB           = 2, /* Error bit in SDB FIS */
 194        PORT_CERR_DATA          = 3, /* Error in data FIS not detected by dev */
 195        PORT_CERR_SEND          = 4, /* Initial cmd FIS transmission failure */
 196        PORT_CERR_INCONSISTENT  = 5, /* Protocol mismatch */
 197        PORT_CERR_DIRECTION     = 6, /* Data direction mismatch */
 198        PORT_CERR_UNDERRUN      = 7, /* Ran out of SGEs while writing */
 199        PORT_CERR_OVERRUN       = 8, /* Ran out of SGEs while reading */
 200        PORT_CERR_PKT_PROT      = 11, /* DIR invalid in 1st PIO setup of ATAPI */
 201        PORT_CERR_SGT_BOUNDARY  = 16, /* PLD ecode 00 - SGT not on qword boundary */
 202        PORT_CERR_SGT_TGTABRT   = 17, /* PLD ecode 01 - target abort */
 203        PORT_CERR_SGT_MSTABRT   = 18, /* PLD ecode 10 - master abort */
 204        PORT_CERR_SGT_PCIPERR   = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
 205        PORT_CERR_CMD_BOUNDARY  = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
 206        PORT_CERR_CMD_TGTABRT   = 25, /* ctrl[15:13] 010 - target abort */
 207        PORT_CERR_CMD_MSTABRT   = 26, /* ctrl[15:13] 100 - master abort */
 208        PORT_CERR_CMD_PCIPERR   = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
 209        PORT_CERR_XFR_UNDEF     = 32, /* PSD ecode 00 - undefined */
 210        PORT_CERR_XFR_TGTABRT   = 33, /* PSD ecode 01 - target abort */
 211        PORT_CERR_XFR_MSTABRT   = 34, /* PSD ecode 10 - master abort */
 212        PORT_CERR_XFR_PCIPERR   = 35, /* PSD ecode 11 - PCI prity err during transfer */
 213        PORT_CERR_SENDSERVICE   = 36, /* FIS received while sending service */
 214
 215        /* bits of PRB control field */
 216        PRB_CTRL_PROTOCOL       = (1 << 0), /* override def. ATA protocol */
 217        PRB_CTRL_PACKET_READ    = (1 << 4), /* PACKET cmd read */
 218        PRB_CTRL_PACKET_WRITE   = (1 << 5), /* PACKET cmd write */
 219        PRB_CTRL_NIEN           = (1 << 6), /* Mask completion irq */
 220        PRB_CTRL_SRST           = (1 << 7), /* Soft reset request (ign BSY?) */
 221
 222        /* PRB protocol field */
 223        PRB_PROT_PACKET         = (1 << 0),
 224        PRB_PROT_TCQ            = (1 << 1),
 225        PRB_PROT_NCQ            = (1 << 2),
 226        PRB_PROT_READ           = (1 << 3),
 227        PRB_PROT_WRITE          = (1 << 4),
 228        PRB_PROT_TRANSPARENT    = (1 << 5),
 229
 230        /*
 231         * Other constants
 232         */
 233        SGE_TRM                 = (1 << 31), /* Last SGE in chain */
 234        SGE_LNK                 = (1 << 30), /* linked list
 235                                                Points to SGT, not SGE */
 236        SGE_DRD                 = (1 << 29), /* discard data read (/dev/null)
 237                                                data address ignored */
 238
 239        SIL24_MAX_CMDS          = 31,
 240
 241        /* board id */
 242        BID_SIL3124             = 0,
 243        BID_SIL3132             = 1,
 244        BID_SIL3131             = 2,
 245
 246        /* host flags */
 247        SIL24_COMMON_FLAGS      = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
 248                                  ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
 249                                  ATA_FLAG_AN | ATA_FLAG_PMP,
 250        SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
 251
 252        IRQ_STAT_4PORTS         = 0xf,
 253};
 254
 255struct sil24_ata_block {
 256        struct sil24_prb prb;
 257        struct sil24_sge sge[SIL24_MAX_SGE];
 258};
 259
 260struct sil24_atapi_block {
 261        struct sil24_prb prb;
 262        u8 cdb[16];
 263        struct sil24_sge sge[SIL24_MAX_SGE];
 264};
 265
 266union sil24_cmd_block {
 267        struct sil24_ata_block ata;
 268        struct sil24_atapi_block atapi;
 269};
 270
 271static const struct sil24_cerr_info {
 272        unsigned int err_mask, action;
 273        const char *desc;
 274} sil24_cerr_db[] = {
 275        [0]                     = { AC_ERR_DEV, 0,
 276                                    "device error" },
 277        [PORT_CERR_DEV]         = { AC_ERR_DEV, 0,
 278                                    "device error via D2H FIS" },
 279        [PORT_CERR_SDB]         = { AC_ERR_DEV, 0,
 280                                    "device error via SDB FIS" },
 281        [PORT_CERR_DATA]        = { AC_ERR_ATA_BUS, ATA_EH_RESET,
 282                                    "error in data FIS" },
 283        [PORT_CERR_SEND]        = { AC_ERR_ATA_BUS, ATA_EH_RESET,
 284                                    "failed to transmit command FIS" },
 285        [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
 286                                     "protocol mismatch" },
 287        [PORT_CERR_DIRECTION]   = { AC_ERR_HSM, ATA_EH_RESET,
 288                                    "data directon mismatch" },
 289        [PORT_CERR_UNDERRUN]    = { AC_ERR_HSM, ATA_EH_RESET,
 290                                    "ran out of SGEs while writing" },
 291        [PORT_CERR_OVERRUN]     = { AC_ERR_HSM, ATA_EH_RESET,
 292                                    "ran out of SGEs while reading" },
 293        [PORT_CERR_PKT_PROT]    = { AC_ERR_HSM, ATA_EH_RESET,
 294                                    "invalid data directon for ATAPI CDB" },
 295        [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
 296                                     "SGT not on qword boundary" },
 297        [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
 298                                    "PCI target abort while fetching SGT" },
 299        [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
 300                                    "PCI master abort while fetching SGT" },
 301        [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
 302                                    "PCI parity error while fetching SGT" },
 303        [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
 304                                     "PRB not on qword boundary" },
 305        [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
 306                                    "PCI target abort while fetching PRB" },
 307        [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
 308                                    "PCI master abort while fetching PRB" },
 309        [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
 310                                    "PCI parity error while fetching PRB" },
 311        [PORT_CERR_XFR_UNDEF]   = { AC_ERR_HOST_BUS, ATA_EH_RESET,
 312                                    "undefined error while transferring data" },
 313        [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
 314                                    "PCI target abort while transferring data" },
 315        [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
 316                                    "PCI master abort while transferring data" },
 317        [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
 318                                    "PCI parity error while transferring data" },
 319        [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
 320                                    "FIS received while sending service FIS" },
 321};
 322
 323/*
 324 * ap->private_data
 325 *
 326 * The preview driver always returned 0 for status.  We emulate it
 327 * here from the previous interrupt.
 328 */
 329struct sil24_port_priv {
 330        union sil24_cmd_block *cmd_block;       /* 32 cmd blocks */
 331        dma_addr_t cmd_block_dma;               /* DMA base addr for them */
 332        int do_port_rst;
 333};
 334
 335static void sil24_dev_config(struct ata_device *dev);
 336static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val);
 337static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val);
 338static int sil24_qc_defer(struct ata_queued_cmd *qc);
 339static void sil24_qc_prep(struct ata_queued_cmd *qc);
 340static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
 341static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
 342static void sil24_pmp_attach(struct ata_port *ap);
 343static void sil24_pmp_detach(struct ata_port *ap);
 344static void sil24_freeze(struct ata_port *ap);
 345static void sil24_thaw(struct ata_port *ap);
 346static int sil24_softreset(struct ata_link *link, unsigned int *class,
 347                           unsigned long deadline);
 348static int sil24_hardreset(struct ata_link *link, unsigned int *class,
 349                           unsigned long deadline);
 350static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
 351                               unsigned long deadline);
 352static void sil24_error_handler(struct ata_port *ap);
 353static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
 354static int sil24_port_start(struct ata_port *ap);
 355static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
 356#ifdef CONFIG_PM
 357static int sil24_pci_device_resume(struct pci_dev *pdev);
 358static int sil24_port_resume(struct ata_port *ap);
 359#endif
 360
 361static const struct pci_device_id sil24_pci_tbl[] = {
 362        { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
 363        { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
 364        { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
 365        { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
 366        { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 },
 367        { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
 368        { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
 369
 370        { } /* terminate list */
 371};
 372
 373static struct pci_driver sil24_pci_driver = {
 374        .name                   = DRV_NAME,
 375        .id_table               = sil24_pci_tbl,
 376        .probe                  = sil24_init_one,
 377        .remove                 = ata_pci_remove_one,
 378#ifdef CONFIG_PM
 379        .suspend                = ata_pci_device_suspend,
 380        .resume                 = sil24_pci_device_resume,
 381#endif
 382};
 383
 384static struct scsi_host_template sil24_sht = {
 385        ATA_NCQ_SHT(DRV_NAME),
 386        .can_queue              = SIL24_MAX_CMDS,
 387        .sg_tablesize           = SIL24_MAX_SGE,
 388        .dma_boundary           = ATA_DMA_BOUNDARY,
 389};
 390
 391static struct ata_port_operations sil24_ops = {
 392        .inherits               = &sata_pmp_port_ops,
 393
 394        .qc_defer               = sil24_qc_defer,
 395        .qc_prep                = sil24_qc_prep,
 396        .qc_issue               = sil24_qc_issue,
 397        .qc_fill_rtf            = sil24_qc_fill_rtf,
 398
 399        .freeze                 = sil24_freeze,
 400        .thaw                   = sil24_thaw,
 401        .softreset              = sil24_softreset,
 402        .hardreset              = sil24_hardreset,
 403        .pmp_softreset          = sil24_softreset,
 404        .pmp_hardreset          = sil24_pmp_hardreset,
 405        .error_handler          = sil24_error_handler,
 406        .post_internal_cmd      = sil24_post_internal_cmd,
 407        .dev_config             = sil24_dev_config,
 408
 409        .scr_read               = sil24_scr_read,
 410        .scr_write              = sil24_scr_write,
 411        .pmp_attach             = sil24_pmp_attach,
 412        .pmp_detach             = sil24_pmp_detach,
 413
 414        .port_start             = sil24_port_start,
 415#ifdef CONFIG_PM
 416        .port_resume            = sil24_port_resume,
 417#endif
 418};
 419
 420static bool sata_sil24_msi;    /* Disable MSI */
 421module_param_named(msi, sata_sil24_msi, bool, S_IRUGO);
 422MODULE_PARM_DESC(msi, "Enable MSI (Default: false)");
 423
 424/*
 425 * Use bits 30-31 of port_flags to encode available port numbers.
 426 * Current maxium is 4.
 427 */
 428#define SIL24_NPORTS2FLAG(nports)       ((((unsigned)(nports) - 1) & 0x3) << 30)
 429#define SIL24_FLAG2NPORTS(flag)         ((((flag) >> 30) & 0x3) + 1)
 430
 431static const struct ata_port_info sil24_port_info[] = {
 432        /* sil_3124 */
 433        {
 434                .flags          = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
 435                                  SIL24_FLAG_PCIX_IRQ_WOC,
 436                .pio_mask       = ATA_PIO4,
 437                .mwdma_mask     = ATA_MWDMA2,
 438                .udma_mask      = ATA_UDMA5,
 439                .port_ops       = &sil24_ops,
 440        },
 441        /* sil_3132 */
 442        {
 443                .flags          = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
 444                .pio_mask       = ATA_PIO4,
 445                .mwdma_mask     = ATA_MWDMA2,
 446                .udma_mask      = ATA_UDMA5,
 447                .port_ops       = &sil24_ops,
 448        },
 449        /* sil_3131/sil_3531 */
 450        {
 451                .flags          = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
 452                .pio_mask       = ATA_PIO4,
 453                .mwdma_mask     = ATA_MWDMA2,
 454                .udma_mask      = ATA_UDMA5,
 455                .port_ops       = &sil24_ops,
 456        },
 457};
 458
 459static int sil24_tag(int tag)
 460{
 461        if (unlikely(ata_tag_internal(tag)))
 462                return 0;
 463        return tag;
 464}
 465
 466static unsigned long sil24_port_offset(struct ata_port *ap)
 467{
 468        return ap->port_no * PORT_REGS_SIZE;
 469}
 470
 471static void __iomem *sil24_port_base(struct ata_port *ap)
 472{
 473        return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap);
 474}
 475
 476static void sil24_dev_config(struct ata_device *dev)
 477{
 478        void __iomem *port = sil24_port_base(dev->link->ap);
 479
 480        if (dev->cdb_len == 16)
 481                writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
 482        else
 483                writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
 484}
 485
 486static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
 487{
 488        void __iomem *port = sil24_port_base(ap);
 489        struct sil24_prb __iomem *prb;
 490        u8 fis[6 * 4];
 491
 492        prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
 493        memcpy_fromio(fis, prb->fis, sizeof(fis));
 494        ata_tf_from_fis(fis, tf);
 495}
 496
 497static int sil24_scr_map[] = {
 498        [SCR_CONTROL]   = 0,
 499        [SCR_STATUS]    = 1,
 500        [SCR_ERROR]     = 2,
 501        [SCR_ACTIVE]    = 3,
 502};
 503
 504static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
 505{
 506        void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
 507
 508        if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
 509                void __iomem *addr;
 510                addr = scr_addr + sil24_scr_map[sc_reg] * 4;
 511                *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
 512                return 0;
 513        }
 514        return -EINVAL;
 515}
 516
 517static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
 518{
 519        void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
 520
 521        if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
 522                void __iomem *addr;
 523                addr = scr_addr + sil24_scr_map[sc_reg] * 4;
 524                writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
 525                return 0;
 526        }
 527        return -EINVAL;
 528}
 529
 530static void sil24_config_port(struct ata_port *ap)
 531{
 532        void __iomem *port = sil24_port_base(ap);
 533
 534        /* configure IRQ WoC */
 535        if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
 536                writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
 537        else
 538                writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
 539
 540        /* zero error counters. */
 541        writew(0x8000, port + PORT_DECODE_ERR_THRESH);
 542        writew(0x8000, port + PORT_CRC_ERR_THRESH);
 543        writew(0x8000, port + PORT_HSHK_ERR_THRESH);
 544        writew(0x0000, port + PORT_DECODE_ERR_CNT);
 545        writew(0x0000, port + PORT_CRC_ERR_CNT);
 546        writew(0x0000, port + PORT_HSHK_ERR_CNT);
 547
 548        /* always use 64bit activation */
 549        writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
 550
 551        /* clear port multiplier enable and resume bits */
 552        writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
 553}
 554
 555static void sil24_config_pmp(struct ata_port *ap, int attached)
 556{
 557        void __iomem *port = sil24_port_base(ap);
 558
 559        if (attached)
 560                writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
 561        else
 562                writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
 563}
 564
 565static void sil24_clear_pmp(struct ata_port *ap)
 566{
 567        void __iomem *port = sil24_port_base(ap);
 568        int i;
 569
 570        writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
 571
 572        for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
 573                void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
 574
 575                writel(0, pmp_base + PORT_PMP_STATUS);
 576                writel(0, pmp_base + PORT_PMP_QACTIVE);
 577        }
 578}
 579
 580static int sil24_init_port(struct ata_port *ap)
 581{
 582        void __iomem *port = sil24_port_base(ap);
 583        struct sil24_port_priv *pp = ap->private_data;
 584        u32 tmp;
 585
 586        /* clear PMP error status */
 587        if (sata_pmp_attached(ap))
 588                sil24_clear_pmp(ap);
 589
 590        writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
 591        ata_wait_register(ap, port + PORT_CTRL_STAT,
 592                          PORT_CS_INIT, PORT_CS_INIT, 10, 100);
 593        tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
 594                                PORT_CS_RDY, 0, 10, 100);
 595
 596        if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
 597                pp->do_port_rst = 1;
 598                ap->link.eh_context.i.action |= ATA_EH_RESET;
 599                return -EIO;
 600        }
 601
 602        return 0;
 603}
 604
 605static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
 606                                 const struct ata_taskfile *tf,
 607                                 int is_cmd, u32 ctrl,
 608                                 unsigned long timeout_msec)
 609{
 610        void __iomem *port = sil24_port_base(ap);
 611        struct sil24_port_priv *pp = ap->private_data;
 612        struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
 613        dma_addr_t paddr = pp->cmd_block_dma;
 614        u32 irq_enabled, irq_mask, irq_stat;
 615        int rc;
 616
 617        prb->ctrl = cpu_to_le16(ctrl);
 618        ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
 619
 620        /* temporarily plug completion and error interrupts */
 621        irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
 622        writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
 623
 624        /*
 625         * The barrier is required to ensure that writes to cmd_block reach
 626         * the memory before the write to PORT_CMD_ACTIVATE.
 627         */
 628        wmb();
 629        writel((u32)paddr, port + PORT_CMD_ACTIVATE);
 630        writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
 631
 632        irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
 633        irq_stat = ata_wait_register(ap, port + PORT_IRQ_STAT, irq_mask, 0x0,
 634                                     10, timeout_msec);
 635
 636        writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
 637        irq_stat >>= PORT_IRQ_RAW_SHIFT;
 638
 639        if (irq_stat & PORT_IRQ_COMPLETE)
 640                rc = 0;
 641        else {
 642                /* force port into known state */
 643                sil24_init_port(ap);
 644
 645                if (irq_stat & PORT_IRQ_ERROR)
 646                        rc = -EIO;
 647                else
 648                        rc = -EBUSY;
 649        }
 650
 651        /* restore IRQ enabled */
 652        writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
 653
 654        return rc;
 655}
 656
 657static int sil24_softreset(struct ata_link *link, unsigned int *class,
 658                           unsigned long deadline)
 659{
 660        struct ata_port *ap = link->ap;
 661        int pmp = sata_srst_pmp(link);
 662        unsigned long timeout_msec = 0;
 663        struct ata_taskfile tf;
 664        const char *reason;
 665        int rc;
 666
 667        DPRINTK("ENTER\n");
 668
 669        /* put the port into known state */
 670        if (sil24_init_port(ap)) {
 671                reason = "port not ready";
 672                goto err;
 673        }
 674
 675        /* do SRST */
 676        if (time_after(deadline, jiffies))
 677                timeout_msec = jiffies_to_msecs(deadline - jiffies);
 678
 679        ata_tf_init(link->device, &tf); /* doesn't really matter */
 680        rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
 681                                   timeout_msec);
 682        if (rc == -EBUSY) {
 683                reason = "timeout";
 684                goto err;
 685        } else if (rc) {
 686                reason = "SRST command error";
 687                goto err;
 688        }
 689
 690        sil24_read_tf(ap, 0, &tf);
 691        *class = ata_dev_classify(&tf);
 692
 693        DPRINTK("EXIT, class=%u\n", *class);
 694        return 0;
 695
 696 err:
 697        ata_link_err(link, "softreset failed (%s)\n", reason);
 698        return -EIO;
 699}
 700
 701static int sil24_hardreset(struct ata_link *link, unsigned int *class,
 702                           unsigned long deadline)
 703{
 704        struct ata_port *ap = link->ap;
 705        void __iomem *port = sil24_port_base(ap);
 706        struct sil24_port_priv *pp = ap->private_data;
 707        int did_port_rst = 0;
 708        const char *reason;
 709        int tout_msec, rc;
 710        u32 tmp;
 711
 712 retry:
 713        /* Sometimes, DEV_RST is not enough to recover the controller.
 714         * This happens often after PM DMA CS errata.
 715         */
 716        if (pp->do_port_rst) {
 717                ata_port_warn(ap,
 718                              "controller in dubious state, performing PORT_RST\n");
 719
 720                writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
 721                ata_msleep(ap, 10);
 722                writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
 723                ata_wait_register(ap, port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
 724                                  10, 5000);
 725
 726                /* restore port configuration */
 727                sil24_config_port(ap);
 728                sil24_config_pmp(ap, ap->nr_pmp_links);
 729
 730                pp->do_port_rst = 0;
 731                did_port_rst = 1;
 732        }
 733
 734        /* sil24 does the right thing(tm) without any protection */
 735        sata_set_spd(link);
 736
 737        tout_msec = 100;
 738        if (ata_link_online(link))
 739                tout_msec = 5000;
 740
 741        writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
 742        tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
 743                                PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
 744                                tout_msec);
 745
 746        /* SStatus oscillates between zero and valid status after
 747         * DEV_RST, debounce it.
 748         */
 749        rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
 750        if (rc) {
 751                reason = "PHY debouncing failed";
 752                goto err;
 753        }
 754
 755        if (tmp & PORT_CS_DEV_RST) {
 756                if (ata_link_offline(link))
 757                        return 0;
 758                reason = "link not ready";
 759                goto err;
 760        }
 761
 762        /* Sil24 doesn't store signature FIS after hardreset, so we
 763         * can't wait for BSY to clear.  Some devices take a long time
 764         * to get ready and those devices will choke if we don't wait
 765         * for BSY clearance here.  Tell libata to perform follow-up
 766         * softreset.
 767         */
 768        return -EAGAIN;
 769
 770 err:
 771        if (!did_port_rst) {
 772                pp->do_port_rst = 1;
 773                goto retry;
 774        }
 775
 776        ata_link_err(link, "hardreset failed (%s)\n", reason);
 777        return -EIO;
 778}
 779
 780static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
 781                                 struct sil24_sge *sge)
 782{
 783        struct scatterlist *sg;
 784        struct sil24_sge *last_sge = NULL;
 785        unsigned int si;
 786
 787        for_each_sg(qc->sg, sg, qc->n_elem, si) {
 788                sge->addr = cpu_to_le64(sg_dma_address(sg));
 789                sge->cnt = cpu_to_le32(sg_dma_len(sg));
 790                sge->flags = 0;
 791
 792                last_sge = sge;
 793                sge++;
 794        }
 795
 796        last_sge->flags = cpu_to_le32(SGE_TRM);
 797}
 798
 799static int sil24_qc_defer(struct ata_queued_cmd *qc)
 800{
 801        struct ata_link *link = qc->dev->link;
 802        struct ata_port *ap = link->ap;
 803        u8 prot = qc->tf.protocol;
 804
 805        /*
 806         * There is a bug in the chip:
 807         * Port LRAM Causes the PRB/SGT Data to be Corrupted
 808         * If the host issues a read request for LRAM and SActive registers
 809         * while active commands are available in the port, PRB/SGT data in
 810         * the LRAM can become corrupted. This issue applies only when
 811         * reading from, but not writing to, the LRAM.
 812         *
 813         * Therefore, reading LRAM when there is no particular error [and
 814         * other commands may be outstanding] is prohibited.
 815         *
 816         * To avoid this bug there are two situations where a command must run
 817         * exclusive of any other commands on the port:
 818         *
 819         * - ATAPI commands which check the sense data
 820         * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
 821         *   set.
 822         *
 823         */
 824        int is_excl = (ata_is_atapi(prot) ||
 825                       (qc->flags & ATA_QCFLAG_RESULT_TF));
 826
 827        if (unlikely(ap->excl_link)) {
 828                if (link == ap->excl_link) {
 829                        if (ap->nr_active_links)
 830                                return ATA_DEFER_PORT;
 831                        qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
 832                } else
 833                        return ATA_DEFER_PORT;
 834        } else if (unlikely(is_excl)) {
 835                ap->excl_link = link;
 836                if (ap->nr_active_links)
 837                        return ATA_DEFER_PORT;
 838                qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
 839        }
 840
 841        return ata_std_qc_defer(qc);
 842}
 843
 844static void sil24_qc_prep(struct ata_queued_cmd *qc)
 845{
 846        struct ata_port *ap = qc->ap;
 847        struct sil24_port_priv *pp = ap->private_data;
 848        union sil24_cmd_block *cb;
 849        struct sil24_prb *prb;
 850        struct sil24_sge *sge;
 851        u16 ctrl = 0;
 852
 853        cb = &pp->cmd_block[sil24_tag(qc->tag)];
 854
 855        if (!ata_is_atapi(qc->tf.protocol)) {
 856                prb = &cb->ata.prb;
 857                sge = cb->ata.sge;
 858                if (ata_is_data(qc->tf.protocol)) {
 859                        u16 prot = 0;
 860                        ctrl = PRB_CTRL_PROTOCOL;
 861                        if (ata_is_ncq(qc->tf.protocol))
 862                                prot |= PRB_PROT_NCQ;
 863                        if (qc->tf.flags & ATA_TFLAG_WRITE)
 864                                prot |= PRB_PROT_WRITE;
 865                        else
 866                                prot |= PRB_PROT_READ;
 867                        prb->prot = cpu_to_le16(prot);
 868                }
 869        } else {
 870                prb = &cb->atapi.prb;
 871                sge = cb->atapi.sge;
 872                memset(cb->atapi.cdb, 0, sizeof(cb->atapi.cdb));
 873                memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
 874
 875                if (ata_is_data(qc->tf.protocol)) {
 876                        if (qc->tf.flags & ATA_TFLAG_WRITE)
 877                                ctrl = PRB_CTRL_PACKET_WRITE;
 878                        else
 879                                ctrl = PRB_CTRL_PACKET_READ;
 880                }
 881        }
 882
 883        prb->ctrl = cpu_to_le16(ctrl);
 884        ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
 885
 886        if (qc->flags & ATA_QCFLAG_DMAMAP)
 887                sil24_fill_sg(qc, sge);
 888}
 889
 890static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
 891{
 892        struct ata_port *ap = qc->ap;
 893        struct sil24_port_priv *pp = ap->private_data;
 894        void __iomem *port = sil24_port_base(ap);
 895        unsigned int tag = sil24_tag(qc->tag);
 896        dma_addr_t paddr;
 897        void __iomem *activate;
 898
 899        paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
 900        activate = port + PORT_CMD_ACTIVATE + tag * 8;
 901
 902        /*
 903         * The barrier is required to ensure that writes to cmd_block reach
 904         * the memory before the write to PORT_CMD_ACTIVATE.
 905         */
 906        wmb();
 907        writel((u32)paddr, activate);
 908        writel((u64)paddr >> 32, activate + 4);
 909
 910        return 0;
 911}
 912
 913static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
 914{
 915        sil24_read_tf(qc->ap, qc->tag, &qc->result_tf);
 916        return true;
 917}
 918
 919static void sil24_pmp_attach(struct ata_port *ap)
 920{
 921        u32 *gscr = ap->link.device->gscr;
 922
 923        sil24_config_pmp(ap, 1);
 924        sil24_init_port(ap);
 925
 926        if (sata_pmp_gscr_vendor(gscr) == 0x11ab &&
 927            sata_pmp_gscr_devid(gscr) == 0x4140) {
 928                ata_port_info(ap,
 929                        "disabling NCQ support due to sil24-mv4140 quirk\n");
 930                ap->flags &= ~ATA_FLAG_NCQ;
 931        }
 932}
 933
 934static void sil24_pmp_detach(struct ata_port *ap)
 935{
 936        sil24_init_port(ap);
 937        sil24_config_pmp(ap, 0);
 938
 939        ap->flags |= ATA_FLAG_NCQ;
 940}
 941
 942static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
 943                               unsigned long deadline)
 944{
 945        int rc;
 946
 947        rc = sil24_init_port(link->ap);
 948        if (rc) {
 949                ata_link_err(link, "hardreset failed (port not ready)\n");
 950                return rc;
 951        }
 952
 953        return sata_std_hardreset(link, class, deadline);
 954}
 955
 956static void sil24_freeze(struct ata_port *ap)
 957{
 958        void __iomem *port = sil24_port_base(ap);
 959
 960        /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
 961         * PORT_IRQ_ENABLE instead.
 962         */
 963        writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
 964}
 965
 966static void sil24_thaw(struct ata_port *ap)
 967{
 968        void __iomem *port = sil24_port_base(ap);
 969        u32 tmp;
 970
 971        /* clear IRQ */
 972        tmp = readl(port + PORT_IRQ_STAT);
 973        writel(tmp, port + PORT_IRQ_STAT);
 974
 975        /* turn IRQ back on */
 976        writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
 977}
 978
 979static void sil24_error_intr(struct ata_port *ap)
 980{
 981        void __iomem *port = sil24_port_base(ap);
 982        struct sil24_port_priv *pp = ap->private_data;
 983        struct ata_queued_cmd *qc = NULL;
 984        struct ata_link *link;
 985        struct ata_eh_info *ehi;
 986        int abort = 0, freeze = 0;
 987        u32 irq_stat;
 988
 989        /* on error, we need to clear IRQ explicitly */
 990        irq_stat = readl(port + PORT_IRQ_STAT);
 991        writel(irq_stat, port + PORT_IRQ_STAT);
 992
 993        /* first, analyze and record host port events */
 994        link = &ap->link;
 995        ehi = &link->eh_info;
 996        ata_ehi_clear_desc(ehi);
 997
 998        ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
 999
1000        if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
1001                ata_ehi_push_desc(ehi, "SDB notify");
1002                sata_async_notification(ap);
1003        }
1004
1005        if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
1006                ata_ehi_hotplugged(ehi);
1007                ata_ehi_push_desc(ehi, "%s",
1008                                  irq_stat & PORT_IRQ_PHYRDY_CHG ?
1009                                  "PHY RDY changed" : "device exchanged");
1010                freeze = 1;
1011        }
1012
1013        if (irq_stat & PORT_IRQ_UNK_FIS) {
1014                ehi->err_mask |= AC_ERR_HSM;
1015                ehi->action |= ATA_EH_RESET;
1016                ata_ehi_push_desc(ehi, "unknown FIS");
1017                freeze = 1;
1018        }
1019
1020        /* deal with command error */
1021        if (irq_stat & PORT_IRQ_ERROR) {
1022                const struct sil24_cerr_info *ci = NULL;
1023                unsigned int err_mask = 0, action = 0;
1024                u32 context, cerr;
1025                int pmp;
1026
1027                abort = 1;
1028
1029                /* DMA Context Switch Failure in Port Multiplier Mode
1030                 * errata.  If we have active commands to 3 or more
1031                 * devices, any error condition on active devices can
1032                 * corrupt DMA context switching.
1033                 */
1034                if (ap->nr_active_links >= 3) {
1035                        ehi->err_mask |= AC_ERR_OTHER;
1036                        ehi->action |= ATA_EH_RESET;
1037                        ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1038                        pp->do_port_rst = 1;
1039                        freeze = 1;
1040                }
1041
1042                /* find out the offending link and qc */
1043                if (sata_pmp_attached(ap)) {
1044                        context = readl(port + PORT_CONTEXT);
1045                        pmp = (context >> 5) & 0xf;
1046
1047                        if (pmp < ap->nr_pmp_links) {
1048                                link = &ap->pmp_link[pmp];
1049                                ehi = &link->eh_info;
1050                                qc = ata_qc_from_tag(ap, link->active_tag);
1051
1052                                ata_ehi_clear_desc(ehi);
1053                                ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1054                                                  irq_stat);
1055                        } else {
1056                                err_mask |= AC_ERR_HSM;
1057                                action |= ATA_EH_RESET;
1058                                freeze = 1;
1059                        }
1060                } else
1061                        qc = ata_qc_from_tag(ap, link->active_tag);
1062
1063                /* analyze CMD_ERR */
1064                cerr = readl(port + PORT_CMD_ERR);
1065                if (cerr < ARRAY_SIZE(sil24_cerr_db))
1066                        ci = &sil24_cerr_db[cerr];
1067
1068                if (ci && ci->desc) {
1069                        err_mask |= ci->err_mask;
1070                        action |= ci->action;
1071                        if (action & ATA_EH_RESET)
1072                                freeze = 1;
1073                        ata_ehi_push_desc(ehi, "%s", ci->desc);
1074                } else {
1075                        err_mask |= AC_ERR_OTHER;
1076                        action |= ATA_EH_RESET;
1077                        freeze = 1;
1078                        ata_ehi_push_desc(ehi, "unknown command error %d",
1079                                          cerr);
1080                }
1081
1082                /* record error info */
1083                if (qc)
1084                        qc->err_mask |= err_mask;
1085                else
1086                        ehi->err_mask |= err_mask;
1087
1088                ehi->action |= action;
1089
1090                /* if PMP, resume */
1091                if (sata_pmp_attached(ap))
1092                        writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1093        }
1094
1095        /* freeze or abort */
1096        if (freeze)
1097                ata_port_freeze(ap);
1098        else if (abort) {
1099                if (qc)
1100                        ata_link_abort(qc->dev->link);
1101                else
1102                        ata_port_abort(ap);
1103        }
1104}
1105
1106static inline void sil24_host_intr(struct ata_port *ap)
1107{
1108        void __iomem *port = sil24_port_base(ap);
1109        u32 slot_stat, qc_active;
1110        int rc;
1111
1112        /* If PCIX_IRQ_WOC, there's an inherent race window between
1113         * clearing IRQ pending status and reading PORT_SLOT_STAT
1114         * which may cause spurious interrupts afterwards.  This is
1115         * unavoidable and much better than losing interrupts which
1116         * happens if IRQ pending is cleared after reading
1117         * PORT_SLOT_STAT.
1118         */
1119        if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1120                writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1121
1122        slot_stat = readl(port + PORT_SLOT_STAT);
1123
1124        if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1125                sil24_error_intr(ap);
1126                return;
1127        }
1128
1129        qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1130        rc = ata_qc_complete_multiple(ap, qc_active);
1131        if (rc > 0)
1132                return;
1133        if (rc < 0) {
1134                struct ata_eh_info *ehi = &ap->link.eh_info;
1135                ehi->err_mask |= AC_ERR_HSM;
1136                ehi->action |= ATA_EH_RESET;
1137                ata_port_freeze(ap);
1138                return;
1139        }
1140
1141        /* spurious interrupts are expected if PCIX_IRQ_WOC */
1142        if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1143                ata_port_info(ap,
1144                        "spurious interrupt (slot_stat 0x%x active_tag %d sactive 0x%x)\n",
1145                        slot_stat, ap->link.active_tag, ap->link.sactive);
1146}
1147
1148static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1149{
1150        struct ata_host *host = dev_instance;
1151        void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1152        unsigned handled = 0;
1153        u32 status;
1154        int i;
1155
1156        status = readl(host_base + HOST_IRQ_STAT);
1157
1158        if (status == 0xffffffff) {
1159                printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1160                       "PCI fault or device removal?\n");
1161                goto out;
1162        }
1163
1164        if (!(status & IRQ_STAT_4PORTS))
1165                goto out;
1166
1167        spin_lock(&host->lock);
1168
1169        for (i = 0; i < host->n_ports; i++)
1170                if (status & (1 << i)) {
1171                        sil24_host_intr(host->ports[i]);
1172                        handled++;
1173                }
1174
1175        spin_unlock(&host->lock);
1176 out:
1177        return IRQ_RETVAL(handled);
1178}
1179
1180static void sil24_error_handler(struct ata_port *ap)
1181{
1182        struct sil24_port_priv *pp = ap->private_data;
1183
1184        if (sil24_init_port(ap))
1185                ata_eh_freeze_port(ap);
1186
1187        sata_pmp_error_handler(ap);
1188
1189        pp->do_port_rst = 0;
1190}
1191
1192static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1193{
1194        struct ata_port *ap = qc->ap;
1195
1196        /* make DMA engine forget about the failed command */
1197        if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1198                ata_eh_freeze_port(ap);
1199}
1200
1201static int sil24_port_start(struct ata_port *ap)
1202{
1203        struct device *dev = ap->host->dev;
1204        struct sil24_port_priv *pp;
1205        union sil24_cmd_block *cb;
1206        size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1207        dma_addr_t cb_dma;
1208
1209        pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1210        if (!pp)
1211                return -ENOMEM;
1212
1213        cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1214        if (!cb)
1215                return -ENOMEM;
1216        memset(cb, 0, cb_size);
1217
1218        pp->cmd_block = cb;
1219        pp->cmd_block_dma = cb_dma;
1220
1221        ap->private_data = pp;
1222
1223        ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1224        ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port");
1225
1226        return 0;
1227}
1228
1229static void sil24_init_controller(struct ata_host *host)
1230{
1231        void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1232        u32 tmp;
1233        int i;
1234
1235        /* GPIO off */
1236        writel(0, host_base + HOST_FLASH_CMD);
1237
1238        /* clear global reset & mask interrupts during initialization */
1239        writel(0, host_base + HOST_CTRL);
1240
1241        /* init ports */
1242        for (i = 0; i < host->n_ports; i++) {
1243                struct ata_port *ap = host->ports[i];
1244                void __iomem *port = sil24_port_base(ap);
1245
1246
1247                /* Initial PHY setting */
1248                writel(0x20c, port + PORT_PHY_CFG);
1249
1250                /* Clear port RST */
1251                tmp = readl(port + PORT_CTRL_STAT);
1252                if (tmp & PORT_CS_PORT_RST) {
1253                        writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1254                        tmp = ata_wait_register(NULL, port + PORT_CTRL_STAT,
1255                                                PORT_CS_PORT_RST,
1256                                                PORT_CS_PORT_RST, 10, 100);
1257                        if (tmp & PORT_CS_PORT_RST)
1258                                dev_err(host->dev,
1259                                        "failed to clear port RST\n");
1260                }
1261
1262                /* configure port */
1263                sil24_config_port(ap);
1264        }
1265
1266        /* Turn on interrupts */
1267        writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1268}
1269
1270static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1271{
1272        extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
1273        struct ata_port_info pi = sil24_port_info[ent->driver_data];
1274        const struct ata_port_info *ppi[] = { &pi, NULL };
1275        void __iomem * const *iomap;
1276        struct ata_host *host;
1277        int rc;
1278        u32 tmp;
1279
1280        /* cause link error if sil24_cmd_block is sized wrongly */
1281        if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1282                __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1283
1284        ata_print_version_once(&pdev->dev, DRV_VERSION);
1285
1286        /* acquire resources */
1287        rc = pcim_enable_device(pdev);
1288        if (rc)
1289                return rc;
1290
1291        rc = pcim_iomap_regions(pdev,
1292                                (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1293                                DRV_NAME);
1294        if (rc)
1295                return rc;
1296        iomap = pcim_iomap_table(pdev);
1297
1298        /* apply workaround for completion IRQ loss on PCI-X errata */
1299        if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1300                tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1301                if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1302                        dev_info(&pdev->dev,
1303                                 "Applying completion IRQ loss on PCI-X errata fix\n");
1304                else
1305                        pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1306        }
1307
1308        /* allocate and fill host */
1309        host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1310                                    SIL24_FLAG2NPORTS(ppi[0]->flags));
1311        if (!host)
1312                return -ENOMEM;
1313        host->iomap = iomap;
1314
1315        /* configure and activate the device */
1316        if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1317                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1318                if (rc) {
1319                        rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1320                        if (rc) {
1321                                dev_err(&pdev->dev,
1322                                        "64-bit DMA enable failed\n");
1323                                return rc;
1324                        }
1325                }
1326        } else {
1327                rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1328                if (rc) {
1329                        dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1330                        return rc;
1331                }
1332                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1333                if (rc) {
1334                        dev_err(&pdev->dev,
1335                                "32-bit consistent DMA enable failed\n");
1336                        return rc;
1337                }
1338        }
1339
1340        /* Set max read request size to 4096.  This slightly increases
1341         * write throughput for pci-e variants.
1342         */
1343        pcie_set_readrq(pdev, 4096);
1344
1345        sil24_init_controller(host);
1346
1347        if (sata_sil24_msi && !pci_enable_msi(pdev)) {
1348                dev_info(&pdev->dev, "Using MSI\n");
1349                pci_intx(pdev, 0);
1350        }
1351
1352        pci_set_master(pdev);
1353        return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1354                                 &sil24_sht);
1355}
1356
1357#ifdef CONFIG_PM
1358static int sil24_pci_device_resume(struct pci_dev *pdev)
1359{
1360        struct ata_host *host = dev_get_drvdata(&pdev->dev);
1361        void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1362        int rc;
1363
1364        rc = ata_pci_device_do_resume(pdev);
1365        if (rc)
1366                return rc;
1367
1368        if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1369                writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1370
1371        sil24_init_controller(host);
1372
1373        ata_host_resume(host);
1374
1375        return 0;
1376}
1377
1378static int sil24_port_resume(struct ata_port *ap)
1379{
1380        sil24_config_pmp(ap, ap->nr_pmp_links);
1381        return 0;
1382}
1383#endif
1384
1385module_pci_driver(sil24_pci_driver);
1386
1387MODULE_AUTHOR("Tejun Heo");
1388MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1389MODULE_LICENSE("GPL");
1390MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1391
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