linux/drivers/ata/pdc_adma.c
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v v13/a>3spa	 class="comment">/*3/spa	  v v23/a>3spa	 class="comment"> *  pdc_adma.c - Pacific Digital Corpora8.13v v33/a>3spa	 class="comment"> *3/spa	  v v43/a>3spa	 class="comment"> *  Maintained by:  Mark Lord <mlord@pobox.com>3/spa	  v v53/a>3spa	 class="comment"> *3/spa	  v v63/a>3spa	 class="comment"> *  Copyright 2005 Mark Lord3/spa	  v v73/a>3spa	 class="comment"> *3/spa	  v v83/a>3spa	 class="comment"> *  This program is free software; you ca	 redistribute it and/or modify3/spa	  v v93/a>3spa	 class="comment"> *  it under the terms of the GNU General Public License as published by3/spa	  v 3.18a>3spa	 class="comment"> *  the Free Software Founda8.13; either vers.13<2, or (at your .13"
	)3/spa	  v 113/a>3spa	 class="comment"> *  any later vers.13.3/spa	  v 123/a>3spa	 class="comment"> *3/spa	  v 133/a>3spa	 class="comment"> *  This program is distributed in the hope that it will be useful,3/spa	  v 143/a>3spa	 class="comment"> *  but WITHOUT ANY WARRANTY; without even the implied warranty of3/spa	  v 153/a>3spa	 class="comment"> *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the3/spa	  v 163/a>3spa	 class="comment"> *  GNU General Public License for more details.3/spa	  v 173/a>3spa	 class="comment"> *3/spa	  v 183/a>3spa	 class="comment"> *  You should have received a copy of the GNU General Public License3/spa	  v 193/a>3spa	 class="comment"> *  along with this program; see the file COPYING.  If not, write to3/spa	  v 2.18a>3spa	 class="comment"> *  the Free Software Founda8.13, 675 Mass Ave, Cambridge, MA 02139, USA.3/spa	  v 213/a>3spa	 class="comment"> *3/spa	  v 223/a>3spa	 class="comment"> *3/spa	  v 233/a>3spa	 class="comment"> *  libata documenta8.13v 243/a>3spa	 class="comment"> *  as Documenta8.13/DocBook/libata.*3/spa	  v 253/a>3spa	 class="comment"> *3/spa	  v 263/a>3spa	 class="comment"> *3/spa	  v 273/a>3spa	 class="comment"> *  Supports ATA disks in single-packetv 283/a>3spa	 class="comment"> *  Uses PIO for everything else.3/spa	  v 293/a>3spa	 class="comment"> *3/spa	  v 3.18a>3spa	 class="comment"> *  TODO:  Usev 313/a>3spa	 class="comment"> *  This requires careful attent.13v 323/a>3spa	 class="comment"> *3/spa	  v 333/a>3spa	 class="comment"> */3/spa	  v 343/a> v 353/a>#include <linux/kernel.h3/a>> v 363/a>#include <linux/module.h3/a>> v 373/a>#include <linux/gfp.h3/a>> v 383/a>#include <linux/pci.h3/a>> v 393/a>#include <linux/init.h3/a>> v 403/a>#include <linux/blkdev.h3/a>> v 413/a>#include <linux/delay.h3/a>> v 423/a>#include <linux/interrupt.h3/a>> v 433/a>#include <linux/device.h3/a>> v 443/a>#include <scsi/scsi_host.h3/a>> v 453/a>#include <linux/libata.h3/a>> v 463/a> v 473/a>#definev3a href="+code=DRV_NAME" class="sref">DRV_NAME3/a>        3spa	 class="string">"pdc_adma"3/spa	  v 483/a>#definev3a href="+code=DRV_VERSION" class="sref">DRV_VERSION3/a>     3spa	 class="string">"1.0"3/spa	  v 493/a> v 5.18a>3spa	 class="comment">/* macrov 513/a>#definev3a href="+code=ADMA_ATA_REGS" class="sref">ADMA_ATA_REGS3/a>(3a href="+code=base" class="sref">base3/a>,v3a href="+code=port_no" class="sref">port_no3/a>)    ((3a href="+code=base" class="sref">base3/a>) + ((3a href="+code=port_no" class="sref">port_no3/a>) * 0x40)) v 523/a> v 533/a>3spa	 class="comment">/* macrov 543/a>#definev3a href="+code=ADMA_REGS" class="sref">ADMA_REGS3/a>(3a href="+code=base" class="sref">base3/a>,v3a href="+code=port_no" class="sref">port_no3/a>)        ((3a href="+code=base" class="sref">base3/a>) + 0x80 + ((3a href="+code=port_no" class="sref">port_no3/a>) * 0x20)) v 553/a> v 563/a>3spa	 class="comment">/* macrov 573/a>#definev3a href="+code=ADMA_PORT_REGS" class="sref">ADMA_PORT_REGS3/a>(3a href="+code=ap" class="sref">ap3/a>) \ v 583/a>        3a href="+code=ADMA_REGS" class="sref">ADMA_REGS3/a>((3a href="+code=ap" class="sref">ap3/a>)->3a href="+code=host" class="sref">host3/a>->3a href="+code=iomap" class="sref">iomap3/a>[3a href="+code=ADMA_MMIO_BAR" class="sref">ADMA_MMIO_BAR3/a>],v3a href="+code=ap" class="sref">ap3/a>->3a href="+code=port_no" class="sref">port_no3/a>) v 593/a> v 6.18a>enum { v 613/a>        3a href="+code=ADMA_MMIO_BAR" class="sref">ADMA_MMIO_BAR3/a>           = 4, v 623/a> v 633/a>        3a href="+code=ADMA_PORTS" class="sref">ADMA_PORTS3/a>              = 2, v 643/a>        3a href="+code=ADMA_CPB_BYTES" class="sref">ADMA_CPB_BYTES3/a>          = 40, v 653/a>        3a href="+code=ADMA_PRD_BYTES" class="sref">ADMA_PRD_BYTES3/a>          = 3a href="+code=LIBATA_MAX_PRD" class="sref">LIBATA_MAX_PRD3/a> * 16, v 663/a>        3a href="+code=ADMA_PKT_BYTES" class="sref">ADMA_PKT_BYTES3/a>          = 3a href="+code=ADMA_CPB_BYTES" class="sref">ADMA_CPB_BYTES3/a> + 3a href="+code=ADMA_PRD_BYTES" class="sref">ADMA_PRD_BYTES3/a>, v 673/a> v 683/a>        3a href="+code=ADMA_DMA_BOUNDARY" class="sref">ADMA_DMA_BOUNDARY3/a>       = 0xffffffff, v 693/a> v 703/a>        3spa	 class="comment">/* global register offsets */3/spa	  v 713/a>        3a href="+code=ADMA_MODE_LOCK" class="sref">ADMA_MODE_LOCK3/a>          = 0x00c7, v 723/a> v 733/a>        3spa	 class="comment">/* per-channel register offsets */3/spa	  v 743/a>        3a href="+code=ADMA_CONTROL" class="sref">ADMA_CONTROL3/a>            = 0x0000, 3spa	 class="comment">/* ADMA control */3/spa	  v 753/a>        3a href="+code=ADMA_STATUS" class="sref">ADMA_STATUS3/a>             = 0x0002, 3spa	 class="comment">/* ADMA status */3/spa	  v 763/a>        3a href="+code=ADMA_CPB_COUNT" class="sref">ADMA_CPB_COUNT3/a>          = 0x0004, 3spa	 class="comment">/* CPB count */3/spa	  v 773/a>        3a href="+code=ADMA_CPB_CURRENT" class="sref">ADMA_CPB_CURRENT3/a>        = 0x000c, 3spa	 class="comment">/* current CPB address */3/spa	  v 783/a>        3a href="+code=ADMA_CPB_NEXT" class="sref">ADMA_CPB_NEXT3/a>           = 0x000c, 3spa	 class="comment">/* next CPB address */3/spa	  v 793/a>        3a href="+code=ADMA_CPB_LOOKUP" class="sref">ADMA_CPB_LOOKUP3/a>         = 0x0010, 3spa	 class="comment">/* CPB lookup table */3/spa	  v 803/a>        3a href="+code=ADMA_FIFO_IN" class="sref">ADMA_FIFO_IN3/a>            = 0x0014, 3spa	 class="comment">/* input FIFO threshold */3/spa	  v 813/a>        3a href="+code=ADMA_FIFO_OUT" class="sref">ADMA_FIFO_OUT3/a>           = 0x0016, 3spa	 class="comment">/* output FIFO threshold */3/spa	  v 823/a> v 833/a>        3spa	 class="comment">/* ADMA_CONTROL register bits */3/spa	  v 843/a>        3a href="+code=aNIEN" class="sref">aNIEN3/a>                   = (1 << 8), 3spa	 class="comment">/* irq mask: 1==masked */3/spa	  v 853/a>        3a href="+code=aGO" class="sref">aGO3/a>                     = (1 << 7), 3spa	 class="comment">/* packetv 863/a>        3a href="+code=aRSTADM" class="sref">aRSTADM3/a>                 = (1 << 5), 3spa	 class="comment">/* ADMA logic reset */3/spa	  v 873/a>        3a href="+code=aPIOMD4" class="sref">aPIOMD43/a>                 = 0x0003,   3spa	 class="comment">/* PIO mode 4 */3/spa	  v 883/a> v 893/a>        3spa	 class="comment">/* ADMA_STATUS register bits */3/spa	  v 903/a>        3a href="+code=aPSD" class="sref">aPSD3/a>                    = (1 << 6), v 913/a>        3a href="+code=aUIRQ" class="sref">aUIRQ3/a>                   = (1 << 4), v 923/a>        3a href="+code=aPERR" class="sref">aPERR3/a>                   = (1 << 0), v 933/a> v 943/a>        3spa	 class="comment">/* CPB bits */3/spa	  v 953/a>        3a href="+code=cDONE" class="sref">cDONE3/a>                   = (1 << 0), v 963/a>        3a href="+code=cATERR" class="sref">cATERR3/a>                  = (1 << 3), v 973/a> v 983/a>        3a href="+code=cVLD" class="sref">cVLD3/a>                    = (1 << 0), v 993/a>        3a href="+code=cDAT" class="sref">cDAT3/a>                    = (1 << 2), v1003/a>        3a href="+code=cIEN" class="sref">cIEN3/a>                    = (1 << 3), v1013/a> v1023/a>        3spa	 class="comment">/* PRD bits */3/spa	  v1033/a>        3a href="+code=pORD" class="sref">pORD3/a>                    = (1 << 4), v1043/a>        3a href="+code=pDIRO" class="sref">pDIRO3/a>                   = (1 << 5), v1053/a>        3a href="+code=pEND" class="sref">pEND3/a>                    = (1 << 7), v1063/a> v1073/a>        3spa	 class="comment">/* ATA register flags */3/spa	  v1083/a>        3a href="+code=rIGN" class="sref">rIGN3/a>                    = (1 << 5), v1093/a>        3a href="+code=rEND" class="sref">rEND3/a>                    = (1 << 7), v13.18a> v1113/a>        3spa	 class="comment">/* ATA register addresses */3/spa	  v1123/a>        3a href="+code=ADMA_REGS_CONTROL" class="sref">ADMA_REGS_CONTROL3/a>       = 0x0e, v1133/a>        3a href="+code=ADMA_REGS_SECTOR_COUNT" class="sref">ADMA_REGS_SECTOR_COUNT3/a>  = 0x12, v1143/a>        3a href="+code=ADMA_REGS_LBA_LOW" class="sref">ADMA_REGS_LBA_LOW3/a>       = 0x13, v1153/a>        3a href="+code=ADMA_REGS_LBA_MID" class="sref">ADMA_REGS_LBA_MID3/a>       = 0x14, v1163/a>        3a href="+code=ADMA_REGS_LBA_HIGH" class="sref">ADMA_REGS_LBA_HIGH3/a>      = 0x15, v1173/a>        3a href="+code=ADMA_REGS_DEVICE" class="sref">ADMA_REGS_DEVICE3/a>        = 0x16, v1183/a>        3a href="+code=ADMA_REGS_COMMAND" class="sref">ADMA_REGS_COMMAND3/a>       = 0x17, v1193/a> v1203/a>        3spa	 class="comment">/* PCI device IDs */3/spa	  v1213/a>        3a href="+code=board_1841_idx" class="sref">board_1841_idx3/a>          = 0,    3spa	 class="comment">/* ADMA 2-port controller */3/spa	  v1223/a>}; v1233/a> v1243/a>typidef enum { 3a href="+code=adma_state_idle" class="sref">adma_state_idle3/a>,v3a href="+code=adma_state_pkt" class="sref">adma_state_pkt3/a>,v3a href="+code=adma_state_mmio" class="sref">adma_state_mmio3/a> }v3a href="+code=adma_state_t" class="sref">adma_state_t3/a>; v1253/a> v1263/a>structv3a href="+code=adma_port_priv" class="sref">adma_port_priv3/a> { v1273/a>        3a href="+code=u8" class="sref">u83/a>                      *3a href="+code=pkt" class="sref">pkt3/a>; v1283/a>        3a href="+code=dma_addr_t" class="sref">dma_addr_t3/a>              3a href="+code=pkt_dma" class="sref">pkt_dma3/a>; v1293/a>        3a href="+code=adma_state_t" class="sref">adma_state_t3/a>            3a href="+code=state" class="sref">state3/a>; v13.18a>}; v1313/a> v1323/a>static intv3a href="+code=adma_ata_init_one" class="sref">adma_ata_init_one3/a>(structv3a href="+code=pci_dev" class="sref">pci_dev3/a> *3a href="+code=pdev" class="sref">pdev3/a>, v1333/a>                                const structv3a href="+code=pci_device_id" class="sref">pci_device_id3/a> *3a href="+code=ent" class="sref">ent3/a>); v1343/a>static intv3a href="+code=adma_port_start" class="sref">adma_port_start3/a>(structv3a href="+code=ata_port" class="sref">ata_port3/a> *3a href="+code=ap" class="sref">ap3/a>); v1353/a>static voidv3a href="+code=adma_port_stop" class="sref">adma_port_stop3/a>(structv3a href="+code=ata_port" class="sref">ata_port3/a> *3a href="+code=ap" class="sref">ap3/a>); v1363/a>static voidv3a href="+code=adma_qc_prep" class="sref">adma_qc_prep3/a>(structv3a href="+code=ata_queued_cmd" class="sref">ata_queued_cmd3/a> *3a href="+code=qc" class="sref">qc3/a>); v1373/a>static unsigned intv3a href="+code=adma_qc_issue" class="sref">adma_qc_issue3/a>(structv3a href="+code=ata_queued_cmd" class="sref">ata_queued_cmd3/a> *3a href="+code=qc" class="sref">qc3/a>); v1383/a>static intv3a href="+code=adma_check_atapi_dma" class="sref">adma_check_atapi_dma3/a>(structv3a href="+code=ata_queued_cmd" class="sref">ata_queued_cmd3/a> *3a href="+code=qc" class="sref">qc3/a>); v1393/a>static voidv3a href="+code=adma_freeze" class="sref">adma_freeze3/a>(structv3a href="+code=ata_port" class="sref">ata_port3/a> *3a href="+code=ap" class="sref">ap3/a>); v1403/a>static voidv3a href="+code=adma_thaw" class="sref">adma_thaw3/a>(structv3a href="+code=ata_port" class="sref">ata_port3/a> *3a href="+code=ap" class="sref">ap3/a>); v1413/a>static intv3a href="+code=adma_prereset" class="sref">adma_prereset3/a>(structv3a href="+code=ata_link" class="sref">ata_link3/a> *3a href="+code=link" class="sref">link3/a>, unsigned long 3a href="+code=deadline" class="sref">deadline3/a>); v1423/a> v1433/a>static structv3a href="+code=scsi_host_template" class="sref">scsi_host_template3/a> 3a href="+code=adma_ata_sht" class="sref">adma_ata_sht3/a> = { v1443/a>        3a href="+code=ATA_BASE_SHT" class="sref">ATA_BASE_SHT3/a>(3a href="+code=DRV_NAME" class="sref">DRV_NAME3/a>), v1453/a>        .3a href="+code=sg_tablesize" class="sref">sg_tablesize3/a>           = 3a href="+code=LIBATA_MAX_PRD" class="sref">LIBATA_MAX_PRD3/a>, v1463/a>        .3a href="+code=dma_boundary" class="sref">dma_boundary3/a>           = 3a href="+code=ADMA_DMA_BOUNDARY" class="sref">ADMA_DMA_BOUNDARY3/a>, v1473/a>}; v1483/a> v1493/a>static structv3a href="+code=ata_port_opera8.13s" class="sref">ata_port_opera8.13s3/a> 3a href="+code=adma_ata_ops" class="sref">adma_ata_ops3/a> = { v1503/a>        .3a href="+code=inherits" class="sref">inherits3/a>               = &3a href="+code=ata_sff_port_ops" class="sref">ata_sff_port_ops3/a>, v1513/a> v1523/a>        .3a href="+code=lost_interrupt" class="sref">lost_interrupt3/a>         = 3a href="+code=ATA_OP_NULL" class="sref">ATA_OP_NULL3/a>, v1533/a> v1543/a>        .3a href="+code=check_atapi_dma" class="sref">check_atapi_dma3/a>        = 3a href="+code=adma_check_atapi_dma" class="sref">adma_check_atapi_dma3/a>, v1553/a>        .3a href="+code=qc_prep" class="sref">qc_prep3/a>                = 3a href="+code=adma_qc_prep" class="sref">adma_qc_prep3/a>, v1563/a>        .3a href="+code=qc_issue" class="sref">qc_issue3/a>               = 3a href="+code=adma_qc_issue" class="sref">adma_qc_issue3/a>, v1573/a> v1583/a>        .3a href="+code=freeze" class="sref">freeze3/a>                 = 3a href="+code=adma_freeze" class="sref">adma_freeze3/a>, v1593/a>        .3a href="+code=thaw" class="sref">thaw3/a>                   = 3a href="+code=adma_thaw" class="sref">adma_thaw3/a>, v1603/a>        .3a href="+code=prereset" class="sref">prereset3/a>               = 3a href="+code=adma_prereset" class="sref">adma_prereset3/a>, v1613/a> v1623/a>        .3a href="+code=port_start" class="sref">port_start3/a>             = 3a href="+code=adma_port_start" class="sref">adma_port_start3/a>, v1633/a>        .3a href="+code=port_stop" class="sref">port_stop3/a>              = 3a href="+code=adma_port_stop" class="sref">adma_port_stop3/a>, v1643/a>}; v1653/a> v1663/a>static structv3a href="+code=ata_port_info" class="sref">ata_port_info3/a> 3a href="+code=adma_port_info" class="sref">adma_port_info3/a>[] = { v1673/a>        3spa	 class="comment">/* board_1841_idx */3/spa	  v1683/a>        { v1693/a>                .3a href="+code=flags" class="sref">flags3/a>          = 3a href="+code=ATA_FLAG_SLAVE_POSS" class="sref">ATA_FLAG_SLAVE_POSS3/a> | 3a href="+code=ATA_FLAG_PIO_POLLING" class="sref">ATA_FLAG_PIO_POLLING3/a>, v1703/a>                .3a href="+code=pio_mask" class="sref">pio_mask3/a>       = 3a href="+code=ATA_PIO4_ONLY" class="sref">ATA_PIO4_ONLY3/a>, v1713/a>                .3a href="+code=udma_mask" class="sref">udma_mask3/a>      = 3a href="+code=ATA_UDMA4" class="sref">ATA_UDMA43/a>, v1723/a>                .3a href="+code=port_ops" class="sref">port_ops3/a>       = &3a href="+code=adma_ata_ops" class="sref">adma_ata_ops3/a>, v1733/a>        }, v1743/a>}; v1753/a> v1763/a>static const structv3a href="+code=pci_device_id" class="sref">pci_device_id3/a> 3a href="+code=adma_ata_pci_tbl" class="sref">adma_ata_pci_tbl3/a>[] = { v1773/a>        { 3a href="+code=PCI_VDEVICE" class="sref">PCI_VDEVICE3/a>(3a href="+code=PDC" class="sref">PDC3/a>, unsigned lo0x3/spa	  1/* CPB lo1okup table */3/spa	  v1763/a>stati.c#L1structv3a href="+code=pci_device_i.c#L1nL176">v1763/a>e=pci_device_i.c#L1.13s3/a> 3a href="+code=adma_ata_ops" classss="line"1 namionL82">v 823/a>  nL176">v1763/a>/a> onL159">v1593/a>        .3a href="+code=ode=ATA_BASE_SHT" class="sref">ATA_o0x3/spa	  v145ass="line" namiod">v145v1603/a>        .3a href="+code=prereset"_device_id" class="sref">pci_device_id3/a> 3a o0x3/spa	  v1593/a>       href="+code=prereset"_dev="line" namionL132">v1323/a>static intv3a hro0x3/spa	  v13remov 58">v1583/a>        .3a href="+code=freice_id3remov ne" namionL132">v132ice_id3remov ne" a hro0x3/spa	  adma_ataogic reset */3/spa	  /* 1PIO mode 4 */3/spa	  v 883/a> v1383/a>static intv3a href="+code=adma_check_atapi_dma" class="sref">adma_check_atapi_dma3/a>(structv3a href="+code=ata_queued_cmd" class="srs/ata/pdc_adma.c#L88" idonL88" cla1TATUS reg1ister bits */3/spa	   3a href="+code=adma_ata_ops" class         1   = (1 << 6), boanot ye.c#27" cl   = (1 << 8), 3spa	 class="comment">/* 1         1   = (1 << 4), /* 1 s="line"1   = (1 << 0), v 933/a> static voidv3a href="+code=adma_thaw" class="sref">adma_thaw3/a>(structv3a href="+code=ata_port" clas/ata/pdc_adma.c#L93" idonL93" cla1sine" nami* CPB bits */3/spa	   3a href="+code=adma_ata_ops" class "line" na   = (1 << 0), van.13s3/a"+code=dma_boundary"7" class="line" namionL57">v 573/a>#definev3a href="+code=ADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class="         1   = (1 << 3), v 973/a>          = 0x0010, 3spa	 class="comment">1         1   = (1 << 0),  *ass="sref">thaw3t"> *afinev3a href="+code=AonL87" class="line" namionL87">v code=ATA_FLAG_SLAdonL84" class="line" namionL84code=ATA_FLAG_SLAdonL86" class="line" namionL86">vI_VDEVICE3/a>(3a "linne" namionL154">van.13s33a href="+code=ADMA_CP4" class="line" namionL74">v 743/a>   sa/pdc_adma.c#L147" idonL147" class=2         2 = (1 << 2), v17nclufinev2sa/pdc_adma.c#L147" idonL147" class=2 ridge, MA = (1 << 3),  *ass="sref">thaw3t"> *afinev3a href="+code=AonL87" class="line" namionL87">vI_VDEVICE3/a>(3a "linne" namionL154">van.13s33a href="+code=ADMA_CP4" class="line" namionL74">v 743/a>   sa/pdc_adma.c#L147" idonL147" class=2 a	 class=mionL101">v1013/a> v17nclufinev2sa/pdc_adma.c#L147" idonL147" class=2 a	 class=PRD bits */3/spa	  /* 2         2 = (1 << 4), static voidv3a href="+code=adma_thaw" class="sref">adma_thaw3/a>(structv3a href="+code=ata_port" clas/ata/pdc_adma.c#L93" idonL93" cla2         2 = (1 << 7), v1063/a> v1263/a>structvne3/a>(structv3a ass="line" namionp.13s3/a"+code=dma_bounADMA_MMIO_BAR" class="sref">ADMA_MMIO_BAR3/a>st293/dma_ass="line" namiprst293/dma_s="sa/pdc_adma.c#L147" idonL147" class=2 gle-packeer flags */3/spa	  van.13s3/a"+code=dma_boundary"7" class="line" namionL57">v 573/a>#definev3a href="+code=ADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=2         2 = (1 << 5),   /clea18a>3s23/a>    ionL120">v1203/a>        3spa	 class="comment2="line" n2mionL110">v13.18a>  *bss="sref">thaw3t"> *bfinev3a href="+code=f">uonL84" class="line"f">uonL87">vI_VDEVICE3/a>(3a ADMA_MMIO_BAR" class="sref">ADMA_MMIO_BAR3/io8">vass="line" namioo8">vs="sdma.c#L154" idonLtl_8">vass="line" namiLtl_8">vss="sa/pdc_adma.c#L147" idonL147" class=2register 2ddresses */3/spa	      tic inSTATUSfinev3a href="+code=ADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=2GS_CONTRO23/a>       = 0x0e,   = 0x12,  *"lineenglinonL120">v1203/a>        3spa	 class="comment2=        23/a>       = 0x13, st3a href="+code=ADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=2G        23/a>       = 0x14,       = 0x15,      "o 0x100onL120">v1203/a>        3spa	 class="comment2=gle-packe/a>        = 0x16,  *ass="sref">thaw3t"> *afinev0x100I_VDEVICE3/a>(3a "linne" namionL154">van.13s33a href="+code=ADMA_CP0" class="line" namionL80">v 803/a>   sa/pdc_adma.c#L147" idonL147" class=2G        23/a>       = 0x17, v1193/a> onL120">v1203/a>        3spa	 class="comment2>/* PCI d2vice IDs */3/spa	   *" class="sref">pt"> *"finevt3a href="+code=umionL131">v171">v1vers/a)e3/a>(structv3a ass="line" namionp.13sref">ADMA_MMIO_BAR3/adr_t" class="sref">dma_addr_t3/aI_VDEVICE3/a>(3a "linne" namionL154">van.13s33a href="+code=ADMA_CP4" class="line" namionL78">v 783/a>     sa/pdc_adma.c#L147" idonL147" class=2 2-port c2ntroller */3/spa	  v1223/a>};      "o 0x100onL120">v1203/a>        3spa	 class="comment2="line" n2mionL123">v1233/a>  *ass="sref">thaw3t"> *afinev0x100I_VDEVICE3/a>(3a "linne" namionL154">van.13s33a href="+code=ADMA_CP0" class="line" namionL81">v 813/a>     sa/pdc_adma.c#L147" idonL147" class=2         2>adma_state_t3/a>; v1253/a>           = 0x0004, 3spa	 class="co2="sref">a2ma_port_priv3/a> {  *ass="sref">thaw3t"> *afinev1I_VDEVICE3/a>(3a "linne" namionL154">van.13s33a href="+code=ADMA_CP4" class="line" namionL76">v 763/a>       sa/pdc_adma.c#L147" idonL147" class=2 gle-packess="sref">pkt3/a>; pkt_dma3/a>; ADMA_STATUS3/a>             = 0x0002, 3spa	 class="comm2ate" clas2="sref">state3/a>; thaw3readb/a>st3a href="+code="linne" namionL154">van.13s33a href="+code=ADMA_CP5" class="line" namionL75">v 753/a> sa/pdc_adma.c#L147" idonL147" class=2line" nam2onL130">v13.18a>}; /* 2="line" n2mionL131">v1313/a> pdev3/a>, l  g_43/ak" class="sref"0" cle3/a>l  g_43/a/a>static voidv3a href="+code=adma_thaw" class="sref">adma_thaw3/a>(structv3a href="+code=ata_port" clas/ata/pdc_adma.c#L93" idonL93" cla2=ent" cla2s="sref">ent3/a>); ap3/a>); van.13s3/a"+code=dma_boundary"7" class="line" namionL57">v 573/a>#definev3a href="+code=ADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=2de=ap" cl2ss="sref">ap3/a>); qc3/a>);  *ass="sref">thaw3t"> *afinev3a href="+code=AonL87" class="line" namionL87">vI_VDEVICE3/a>(3a "linne" namionL154">van.13s33a href="+code=ADMA_CP4" class="line" namionL74">v 743/a>   sa/pdc_adma.c#L147" idonL147" class=2de=qc" cl2ss="sref">qc3/a>); thaw3readb/a>st3a href="+code="linne" namionL154">van.13s33a href="+code=ADMA_CP5" class="line" namionL75">v 753/a> saata/pdc_adma.c#L89" idonL89" clflush3/a>             = 0x0002, 3spa	 class="comm2a" class=2ss="sref">qc3/a>); /* 2de=ap" cl2ss="sref">ap3/a>); ap3/a>); v1393/a>static voidv3a href="+code=adma_freeze" class="sref">adma_freeze3/a>(structv3a href="+code=ata_port" clata/pdc_adma.c#L110" idonL110" clas2d"line" n2ef">deadline3/a>); v1423/a> van.13s3/a"+code=dma_boundary"7" class="line" namionL57">v 573/a>#definev3a href="+code=ADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=2="sref">a2ma_ata_sht3/a> = { DRV_NAME3/a>),   /clea18a>3s23/a>    ionL120">v1203/a>        3spa	 class="comment2s="sref">2IBATA_MAX_PRD3/a>,  *bss="sref">thaw3t"> *bfinev3a href="+code=f">uonL84" class="line"f">uonL87">vI_VDEVICE3/a>(3a ADMA_MMIO_BAR" class="sref">ADMA_MMIO_BAR3/io8">vass="line" namioo8">vs="sdma.c#L154" idonLtl_8">vass="line" namiLtl_8">vss="sa/pdc_adma.c#L147" idonL147" clasnt2se=qc" cl2_DMA_BOUNDARY3/a>,     tic inSTATUSfinev3a href="+code=ADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=2line" nam2onL147">v1473/a>}; v1483/a>          = 0x0010, 3spa	 class="comment">2="sref">a2ma_ata_ops3/a> = {  *ass="sref">thaw3t"> *afinev3a href="+code=AonL87" class="line" namionL87">v code=ATA_FLAG_SLAdonL84" class="line" namionL84code=ATA_FLAG_SLAdonL86" class="line" namionL86">vI_VDEVICE3/a>(3a "linne" namionL154">van.13s33a href="+code=ADMA_CP4" class="line" namionL74">v 743/a>   sa/pdc_adma.c#L147" idonL147" class=2"sref">at2_sff_port_ops3/a>, v17nclufinev2sa/pdc_adma.c#L147" idonL147" class=2="line" n2mionL151">v1513/a>  *ass="sref">thaw3t"> *afinev3a href="+code=AonL87" class="line" namionL87">v code=ATA_FLAG_SLAdonL84" class="line" namionL8I_VDEVICE3/a>(3a "linne" namionL154">van.13s33a href="+code=ADMA_CP4" class="line" namionL74">v 743/a>   sa/pdc_adma.c#L147" idonL147" class=2""line" n2">ATA_OP_NULL3/a>, v17nclufinev2sa/pdc_adma.c#L147" idonL147" class=2="sref">a2mionL153">v1533/a> /* 2f">adma_c2eck_atapi_dma3/a>, v1403/a>static voidv3a href="+code=adma_thaw" class="sref">adma_thaw3/a>(structv3a href="+code=ata_port" clata/pdc_adma.c#L125" idonL125" clas2ae=qc" cl2adma_qc_issue3/a>, v1573/a> st3a href="+code=ADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=2lass="sre2">adma_freeze3/a>, /* 2 class="s2ef">adma_thaw3/a>, , v1413/a>static intv3a href="+code=adma_prereset" class="sref">adma_prereset3/a>(structv3a href="+code=ata_link" class="sref">ata_link3/a> *3a href="+code=link" class="sref">link3/a>, unta/pdc_adma.c#L110" idonL110" clas2s"line" n2mionL161">v1613/a> a2ma_port_start3/a>, adma_thaw3/a>(structv3a href="+code=ata_port" cl3/a"+code=dma_bounref="+code=ata_link" class=ref">ADMA_MMIO_BAR3/ref="+code=ata_port" cla/pdc_adma.c#L147" idonL147" class=2s="sref">2dma_port_stop3/a>, v1263/a>structvne3/a>(structv3a ass="line" namionp.13s3/a"+code=dma_bounADMA_MMIO_BAR" class="sref">ADMA_MMIO_BAR3/a>st293/dma_ass="line" namiprst293/dma_s="sa/pdc_adma.c#L147" idonL147" class=2line" nam2onL164">v1643/a>}; v1653/a> ADMA_MMIO_BAR3/ate_t" class="sref">adma_stat ! href="+code=prereset"="line" namionL124">v1243/a>typidef enum { 3)dc_adma.c#L89" idonL89" clhealthy paranoia/a>         = 0x0010, 3spa	 class="comment">2ef">adma_2ort_info3/a>[] = { ADMA_MMIO_BAR3/ate_t" class="sref">adma_stat  href="+code=prereset"="linekt" class="sref">adma_state_pkt3/a>,v3a/pdc_adma.c#L147" idonL147" class=2l"line" n21841_idx */3/spa	  st3a href="+code=ADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=2amionL1682>v1683/a>        { ATA_FL2G_PIO_POLLING3/a>,        lass="li/a>st3a href="+code=ref="+code=ata_link" class="s/a> *3a href="+code=link" class="sref">link3/a>, una/pdc_adma.c#L147" idonL147" class=2ss="sref"2ATA_PIO4_ONLY3/a>, /* 2 class="s2ef">ATA_UDMA43/a>, v139ill_sgic intv3a href="+code=adma_prerlass="sref">adma_check_atapi_dma3/a>(structv3a href="+code=ata_queued_cmd" class="srs/ata/pdc_adma.c#L88" idonL88" cla2mionL173"2v1733/a>        }, v1743/a>}; acatterlis ructv3a href="+code=asgine" namionL139sgic ia/pdc_adma.c#L147" idonL147" class=2s"line" n2mionL175">v1753/a> adma_thaw3/a>(structv3a href="+code=ata_port" cl3/a"+code=dma_bounta_queued_cmd" class="sref">ADMA_MMIO_BAR3/ref="+code=ata_port" cla/pdc_adma.c#L147" idonL147" class=2">adma_at2_pci_tbl3/a>[] = { v1263/a>structvne3/a>(structv3a ass="line" namionp.13s3/a"+code=dma_bounADMA_MMIO_BAR" class="sref">ADMA_MMIO_BAR3/a>st293/dma_ass="line" namiprst293/dma_s="sa/pdc_adma.c#L147" idonL147" class=2""line" n2= (structv3abuf127" class="linbuf.13s3/a"+code=dma_boun ass="line" namionp.13sref">ADMA_MMIO_BAR3/adrss="line" namione3/a>,v33/a>(structv3a hrast_buf127" class="linrast_buf.13s3/a"+code=dma_bounlass="sref">lost_in3/a>    a/pdc_adma.c#L147" idonL147" class=2"mionL1682PB address */3/spa	  ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonass="line" namionL169">v1693/a   .3   .3a href="+code=uTSS3/aWRITE4" class="line"f">uTSS3/aWRITE { 3)d?a"+code=dma_boun L104" class="line" namionL104: 0na/pdc_adma.c#L147" idonL147" class=2nput FIFO2 threshold */3/spa	  v 823/a> st3a href="+code=ta_queued_cmd" class="sref">ADMA_MMIO_BAR3/sgine" namionL139sgic i"s/a> *3a href="+sgine" namionL139sgic i"s/a> *3a href="+ta_queued_cmd" class="sref">ADMA_MMIO_BAR3/n_elemf="+code=ata_pon_elemic i"s/a> *3a href="+siass="line" namisi    )a> 3a href="+code=adma_ata_ops" clas2NTROL reg2ister bits */3/spa	  v171">v1vers/a_adma.c#L126" idon>vass="line" nami8">vss="a/pdc_adma.c#L147" idonL147" class=2tine" nam2 1==masked */3/spa	  v171">v1vers/a_adma.c#L126" idlenne" namionL154"lenss="a/pdc_adma.c#L147" idonL147" class=2t"line" n2Go!") */3/spa	  adma_at2ogic reset */3/spa	  vass="line" nami8">vss="3/a(dma.c#L100" idoumionL131">v171">v1vers/a)e3/a>(structv3asgddr__ionL111ine" namionL139sgddr__ionL111/a>st3a href="+code=sgine" namionL139sgic ina/pdc_adma.c#L147" idonL147" class=2n"line" n2PIO mode 4 */3/spa	  v1273/a*t3a href="+code=__lemionL131">v171">v__lemiructvn)t3a href="+code=buf127" class="linbuf.13s33a href="+code=ADiass="line" namio.13s)3/a"+code=dma_bouncpu_to_lemionL131">v171">vcpu_to_lemi/a>st3a href="+code=An>vass="line" nami8">vss="na/pdc_adma.c#L147" idonL147" class=2nmionL1682 namionL88">v 883/a> st3a href="+code=sgine" namionL139sgic in ef">ef"> 3a/pdc_adma.c#L147" idonL147" class=2Tput FIFO2   = (1 << 4), v171">v__lemiructvn)t3a href="+code=buf127" class="linbuf.13s33a href="+code=ADiass="line" namio.13s)3/a"+code=dma_bouncpu_to_lemionL131">v171">vcpu_to_lemi/a>st3a href="+code=lenne" namionL154"lenss="na/pdc_adma.c#L147" idonL147" class=2 s="line"2   = (1 << 0), v 933/a> adma_at2   = (1 << 3), ADMA_MMIO_BAR3/href="+code=pci_de" classref">ADMA_MMIO_BAR3/h13/ao/ak" class="sref"h13/ao/a693/a   .3 0xfa/pdc_adma.c#L147" idonL147" class=2T"line" n2 namionL97">v 973/a> v1273/adma.c#L108" idobuf127" class="linbuf.13s[.c#L141" idonL1iass="line" namio.13s++]3/a0aatac_adma.c#L89" idonL89" clpPKLW/a>         = 0x0010, 3spa	 class="comment">2         2   = (1 << 0), /* 3         3 = (1 << 2), v171">v__lemiructvn)t3a href="+code=buf127" class="linbuf.13s33a href="+code=ADiass="line" namio.13s)3/ta/pdc_adma.c#L110" idonL110" clas3 2idge, M3   = (1 << 4), v171">vcpu_to_lemi/a>st3a href="+code= ass="line" namionp.13sref">ADMA_MMIO_BAR3/adr_t" class="sref">dma_addr_t3/a33a href="+code=ADiass="line" namio.13s33a4na/pdc_adma.c#L147" idonL147" class=3 a	 class3PRD bits */3/spa	  st3_adma.c#L89"string">"PRD[%u]3/a(0x%lX"sre%X)\n"(1 <"s/a> *3a href="+iass="line" namio.13s/4o0x3/spa	  ata_link)e3/a>(structv3aAn>vass="line" nami8">vss=""s/a> *3a href="+lenne" namionL154"lenss="na/pdc_adma.c#L147" idonL147" class=3="line" n3mionL106">v1063/a> /* 3 gle-pack3er flags */3/spa	  vlikelu/a>st3a href="+code=last_buf127" class="linrast_buf.13s)rs/ata/pdc_adma.c#L88" idonL88" cla3         3 = (1 << 7), v13.18a>        = 0x0e, /* 3GS_SECTOR3COUNT3/a>  = 0x12,        = 0x13, qc_prep3/a>             ntv3a href="+code=adma_prerlass="sref">adma_check_atapi_dma3/a>(structv3a href="+code=ata_queued_cmd" class="srs/ata/pdc_adma.c#L88" idonL88" cla3G        33/a>       = 0x14,       = 0x15, v1263/a>structvne3/a>(structv3a ass="line" namionp.13s3/a"+code=dma_bounta_queued_cmd" class="sref">ADMA_MMIO_BAR3/ref="+code=ata_port" clref">ADMA_MMIO_BAR3/a>st293/dma_ass="line" namiprst293/dma_s="sa/pdc_adma.c#L147" idonL147" class=3=gle-pack3/a>        = 0x16, (structv3abuf127" class="linbuf.13s3/a"+code=dma_boun ass="line" namionp.13sref">ADMA_MMIO_BAR3/adrss="line" namione3/a>,a/pdc_adma.c#L147" idonL147" class=3=        33/a>       = 0x17, v171">v1vers/a_adma.c#L126" idadr_t" class="sref">dma_addr_t3/a3/a(dma.c#L100" idoumionL131">v171">v1vers/a)e3/a>(structv3a ass="line" namionp.13sref">ADMA_MMIO_BAR3/adr_t" class="sref">dma_addr_t3/aa/pdc_adma.c#L147" idonL147" class=3="line" n3mionL119">v1193/a> st3_adma.c#L89"string">"ENTER\n"(1 <na/pdc_adma.c#L147" idonL147" class=3line" nam3onL122">v1223/a>}; v1233/a> l  g_43/ak" class="sref"0" cle3/a>l  g_43/a/a>st"+code=dma_bounta_queued_cmd" class="sref">ADMA_MMIO_BAR3/ref="+code=ata_port" clna/pdc_adma.c#L147" idonL147" class=3l        3>adma_state_t3/a>; ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonprotoco" class="sref">pprotoco"rs/at! href="+code=prerio_maROT_DMA class="sref">pio_maROT_DMAs="srs/ata/pdc_adma.c#L88" idonL88" cla3="line" n3mionL125">v1253/a>  { pkt3/a>; v1 = (1 << 8), 3spa	 class="comment">/* 3a" class=3sref">pkt_dma3/a>; /* 3ate" clas3="sref">state3/a>; v13.18a>}; /* 3a2-port c3mionL131">v1313/a> pdev3/a>, v171">v__lemiructvn)t3a href="+code=buf127" class="linbuf.13s+ href="+code=ADiass="line" namio.13s)3/a"+code=dma_bouncpu_to_lemionL131">v171">vcpu_to_lemi/a>st3a href="+code=adr_t" class="sref">dma_addr_t3/asaata/pdc_adma.c#L89" idonL89" clcNass== (1 << 8), 3spa	 class="comment">/* 3a"line" n3s="sref">ent3/a>); /* 3a        3ss="sref">ap3/a>); /* 3a"line" n3ss="sref">ap3/a>); qc3/a>); /* 3agle-pack3ss="sref">qc3/a>); /* 3a" class=3ss="sref">qc3/a>); /* 3de=ap" cl3ss="sref">ap3/a>); /* 3dine" nam3ss="sref">ap3/a>); deadline3/a>); s; must be a multiple of 4 = (1 << 8), 3spa	 class="comment">/* 3ddev" cla3mionL142">v1423/a> ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonic conf="+code=pci_de" ccononL8a/pdc_adma.c#L147" idonL147" class=3="sref">a3ma_ata_sht3/a> = { >#de_class="line" namionL1L74">>#de_class=onL8a/pdc_adma.c#L147" idonL147" class=3=        3ef">DRV_NAME3/a>), ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonass="line" namionL169">v1693/a   .3   .3a href="+code=uTSS3/aLBA4L127" class="linde=uTSS3/aLBA4L.13s)ra> 3a href="+code=adma_ata_ops" clas3s="sref">3IBATA_MAX_PRD3/a>, ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonhob_nsecrss="line" namiohob_nsecronL8a/pdc_adma.c#L147" idonL147" class=3=e=qc" cl3_DMA_BOUNDARY3/a>, >#de_SECTORclass="line" namionL76">v >#de_SECTORclass=onL8a/pdc_adma.c#L147" idonL147" class=3=gle-pack3onL147">v1473/a>}; v1273/adma.c#L108" idobuf127" class="linbuf.13s[.c#L141" idonL1iass="line" namio.13s++]3/a"+code=dma_bounta_queued_cmd" class="sref">ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonhob_lba" class="sref">phob_lba"onL8a/pdc_adma.c#L147" idonL147" class=3=" class=3mionL148">v1483/a> >#de_LBA_LOW"line" namionL76">v >#de_LBA_LOWonL8a/pdc_adma.c#L147" idonL147" class=3="sref">a3ma_ata_ops3/a> = { ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonhob_lbamf="+code=ata_pohob_lbamonL8a/pdc_adma.c#L147" idonL147" class=3=ine" nam3_sff_port_ops3/a>, >#de_LBA_MI03" class="line"L74">>#de_LBA_MI0onL8a/pdc_adma.c#L147" idonL147" class=3="line" n3mionL151">v1513/a> ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonhob_lbahf="+code=ata_pohob_lbahonL8a/pdc_adma.c#L147" idonL147" class=3=dev" cla3">ATA_OP_NULL3/a>, >#de_LBA_HIGH3" class="line"L74">>#de_LBA_HIGHonL8a/pdc_adma.c#L147" idonL147" class=3="sref">a3mionL153">v1533/a> /* 3f">adma_c3eck_atapi_dma3/a>, ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonnsecrss="line" namionsecronL8a/pdc_adma.c#L147" idonL147" class=3ass="sref3>adma_qc_prep3/a>, >#de_SECTORclass="line" namionL76">v >#de_SECTORclass=onL8a/pdc_adma.c#L147" idonL147" class=3ae=qc" cl3adma_qc_issue3/a>, ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonlba" class="sref">plba"onL8a/pdc_adma.c#L147" idonL147" class=3="line" n3mionL157">v1573/a> >#de_LBA_LOW"line" namionL76">v >#de_LBA_LOWonL8a/pdc_adma.c#L147" idonL147" class=3=" class=3">adma_freeze3/a>, ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonlbamf="+code=ata_polbamonL8a/pdc_adma.c#L147" idonL147" class=3 class="s3ef">adma_thaw3/a>, >#de_LBA_MI03" class="line"L74">>#de_LBA_MI0onL8a/pdc_adma.c#L147" idonL147" class=3ss="sref"3adma_prereset3/a>, ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonlbahf="+code=ata_polbahonL8a/pdc_adma.c#L147" idonL147" class=3s"line" n3mionL161">v1613/a> >#de_LBA_HIGH3" class="line"L74">>#de_LBA_HIGHonL8a/pdc_adma.c#L147" idonL147" class=3="sref">a3ma_port_start3/a>, 3dma_port_stop3/a>, >#de_4" class="line" namionL74">>#de_4" clasonL8a/pdc_adma.c#L147" idonL147" class=3=">adma_c3onL164">v1643/a>}; v1653/a> [] = { ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idondonLanf">adma_check_at54" idoonL8a/pdc_adma.c#L147" idonL147" class=3=a_freeze3a_2ort_info3/a>[] = { >#de_4"MMAN03" class="line"L74">>#de_4"MMAN0rs/at|a"+code=dma_bounrEN03" class="line"rEN0 { 3a/pdc_adma.c#L147" idonL147" class=3amionL1683>v1683/a>        { ATA_FL3G_PIO_POLLING3/a>, ef"> 3) - 2;/ata/pdpdc_a/pdc_adma.c#L1._adma.c#L89" idonL89" clcLEN = (1 << 8), 3spa	 class="comment">/* 3ss="sref"3ATA_PIO4_ONLY3/a>, v171">v__lemiructvn)t3a href="+code=buf127" class="linbuf.13s+8)3/a"+code=dma_bouncpu_to_lemionL131">v171">vcpu_to_lemi/a>st3a href="+code=adr_t" class="sref">dma_addr_t3/a33a href="+code=ADiass="line" namio.13s);_ad_adma.c#L89" idonL89" clcPRD = (1 << 8), 3spa	 class="comment">/* 3s"line" n3ef">ATA_UDMA43/a>, v139ill_sgic in"+code=dma_bounta_queued_cmd" class="sna/pdc_adma.c#L147" idonL147" class=3mionL173"3v1733/a>        }, thaw3tmbfinev);_ad_adma.c#L89" idonL89" clflush3PRDs ido a_ae"o memory = (1 << 8), 3spa	 class="comment">/* 3s">adma_c3onL174">v1743/a>}; /* 3sss="sref3mionL175">v1753/a> /* 3se=qc" cl3_pci_tbl3/a>[] = { v1273/aadma.c#L141" idonL1jss="sref">thaw3j nam"s/a> *3a href="+lenne" namionL154"lenss="3/a0a/pdc_adma.c#L147" idonL147" class=3"mionL1683PB address */3/spa	   *3a href="+obuf127" class="linobuf.13s[2048]a/pdc_adma.c#L147" idonL147" class=3/* CPB lo3okup table */3/spa	  thaw3j nam3/a0aa"+code=dma_bounjss="sref">thaw3j nam3<aa"+code=dma_bouniass="line" namio.13sa ++ href="+code=ADjss="sref">thaw3j namra> 3a href="+code=adma_ata_ops" clas3nput FIFO3 threshold */3/spa	  "%02x "(1 <"s/a> *3a href="+buf127" class="linbuf.13s[.c#L141" idonL1jss="sref">thaw3j nam]na/pdc_adma.c#L147" idonL147" class=3tput FIFO3 threshold */3/spa	  thaw3j nam3&  .3 7)3/= 7)3> 3a href="+code=adma_ata_ops" clas3nss="sref3 namionL82">v 823/a> "%s\n"(1 <"s/a> *3a href="+obuf127" class="linobuf.13sna/pdc_adma.c#L147" idonL147" class=3tionL173"3ister bits */3/spa	  /* 3t"line" n3Go!") */3/spa	  /* 3te=qc" cl3ogic reset */3/spa	  /* 3t"line" n3PIO mode 4 */3/spa	  v1273/ata/pdc_adma.c#L144" idopradm="+code=ata_linkpradm=ic in"_adma.c#L89"string">"%s\n"(1 <"s/a> *3a href="+obuf127" class="linobuf.13sna/pdc_adma.c#L147" idonL147" class=3tmionL1683 namionL88">v 883/a> /* 3TATUS reg3ister bits */3/spa	  /* 3Tput FIFO3   = (1 << 6), /* 3Tput FIFO3   = (1 << 4), adma_check_atapi_dma3/a>(structv3a href="+code=ata_queued_cmd" class="srs/ata/pdc_adma.c#L88" idonL88" cla3TTROL reg3 namionL93">v 933/a>  3a href="+code=adma_ata_ops" clas3sine" nam3* CPB bits */3/spa	  adma_thaw3/a>(structv3a href="+code=ata_port" cl3/a"+code=dma_bounta_queued_cmd" class="sref">ADMA_MMIO_BAR3/ref="+code=ata_port" cla/pdc_adma.c#L147" idonL147" class=3T"line" n3   = (1 << 0), van.13s3/a"+code=dma_boundary"7" class="line" namionL57">v 573/a>#definev3a href="+code=ADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=3T>adma_at3   = (1 << 3), v 973/a> st3_adma.c#L89"string">"ENTER, ap %p\n"(1 <"s/a> *3a href="+ADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=3TmionL1683   = (1 << 0), /* 4 ridge, M4 = (1 << 3),  *ass="sref">thaw3t"> *afinev3a href="+code=AonL87" class="line" namionL87">v code=ATA_FLAG_SLAdG4" class="line" dG4 nam"s/a> *3a href="+"linne" namionL154">van.13s33a href="+code=ADMA_CP4" class="line" namionL74">v 743/a>   sa/pdc_adma.c#L147" idonL147" class=4 2idge, M4   = (1 << 4), /* 4 a	 class4PRD bits */3/spa	       issuak" class="sref"0" cl   issuaic intv3a href="+code=adma_prerlass="sref">adma_check_atapi_dma3/a>(structv3a href="+code=ata_queued_cmd" class="srs/ata/pdc_adma.c#L88" idonL88" cla4         4 = (1 << 5), v1263/a>structvne3/a>(structv3a ass="line" namionp.13s3/a"+code=dma_bounta_queued_cmd" class="sref">ADMA_MMIO_BAR3/ref="+code=ata_port" clref">ADMA_MMIO_BAR3/a>st293/dma_ass="line" namiprst293/dma_s="sa/3a href="+code=adma_ata_ops" clas4 7       4   = (1 << 3), ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonprotoco" class="sref">pprotoco"rs/a)3> 3a href="+code=adma_ata_ops" clas4         4 = (1 << 5), pio_maROT_DMAs="s: 3a href="+code=adma_ata_ops" clas4         4 = (1 << 7), ADMA_MMIO_BAR3/ate_t" class="sref">adma_stat  href="+code=prereset"="lineadrss="line" namioeset"="lineadrs="sa/3a href="+code=adma_ata_ops" clas4="line" n4mionL110">v13.18a>        = 0x0e,   = 0x12, pio_PImaROT_DMAs="s: 3a href="+code=adma_ata_ops" clas4         43/a>       = 0x13, pBUGfinev); 3a href="+code=adma_ata_ops" clas4         43/a>       = 0x14,       = 0x15,         = 0x16,        = 0x17, v1193/a> /* 4="line" n4vice IDs */3/spa	  ADMA_MMIO_BAR3/ate_t" class="sref">adma_stat  href="+code=prereset"="linekt" class="sref">adma_state_pkt3/a>,v3a/pdc_adma.c#L147" idonL147" class=4line" nam4onL122">v1223/a>}; v1233/a> /* 4=        4>adma_state_t3/a>; v1253/a>   37"readrss="line" namioeset"37"readric intv3a href="+code=adma_prerhos " class="sref">prerhos ructvne3/a>(structv3ahos " class="sref">hos ructrs/ata/pdc_adma.c#L88" idonL88" cla4lS_LBA_HI4ma_port_priv3/a> { pkt3/a>; adma_check_atvandlefss="3/a0"s/a> *3a href="+1263/n class="sref">ad1263/n >,v3a/pdc_adma.c#L147" idonL147" class=4l        4sref">pkt_dma3/a>; state3/a>; ad1263/n >,v33/a0aa"+code=dma_boun1263/n class="sref">ad1263/n >,v33<aa"+code=dma_bounhos " class="sref">hos ructref">ADMA_MMIO_BAR3/n_1263"line" namionL16n_1263".13sa ++ href="+code=AD1263/n class="sref">ad1263/n >,v3)3> 3a href="+code=adma_ata_ops" clas4line" nam4onL130">v13.18a>}; adma_thaw3/a>(structv3a href="+code=ata_port" cl3/a"+code=dma_bounhos " class="sref">hos ructref">ADMA_MMIO_BAR3/1263"line" namionL161263".13s[.c#L141" idonL11263/n class="sref">ad1263/n >,v3]a/pdc_adma.c#L147" idonL147" class=4a2-port c4mionL131">v1313/a> v1263/a>structvne3/a>(structv3a ass="line" namionp.13sa/pdc_adma.c#L147" idonL147" class=4aine" nam4s="sref">pdev3/a>, adma_check_atapi_dma3/a>(structv3a href="+code=ata_queued_cmd" class="sa/pdc_adma.c#L147" idonL147" class=4a"line" n4s="sref">ent3/a>); van.13s3/a"+code=dma_boundary"7" class="line" namionL57">v 573/a>#definev3a href="+code=ADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=4a        4ss="sref">ap3/a>); thaw3readbfinev3a href="+code="linne" namionL154">van.13s33a href="+code=ADMA_CPSTATU="line" namionL57">v STATU=ss="sa/pdc_adma.c#L147" idonL147" class=4a"line" n4ss="sref">ap3/a>); qc3/a>); qc3/a>); v1273/ata/pdc_acontinuea/pdc_adma.c#L147" idonL147" class=4a        4ss="sref">qc3/a>); adma_check_atvandlefss="3/a1a/pdc_adma.c#L147" idonL147" class=4de=ap" cl4ss="sref">ap3/a>); ve3/a>l  g_43/ak" class="sref"0" cle3/a>l  g_43/a/a>st"+code=dma_bounADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=4dine" nam4ss="sref">ap3/a>); ADMA_MMIO_BAR3/a>st293/dma_ass="line" namiprst293/dma_s="sa/pdc_adma.c#L147" idonL147" class=4d"line" n4ef">deadline3/a>); ADMA_MMIO_BAR3/ate_t" class="sref">adma_stat ! href="+code=prereset"="lineadrss="line" namioeset"="lineadrs="srs/ata/pdc_adma.c#L88" idonL88" cla4ddev" cla4mionL142">v1423/a> a4ma_ata_sht3/a> = { st"+code=dma_bounADMA_PORT_REGS" class=""s/a> *3a href="+ADMA_PORT_REGS" class="ref">ADMA_MMIO_BAR3//a>="+code=ata_link/a>=s="sdma.c#L154" idonactL14_tagine" namionL139"ctL14_tagss="sa/pdc_adma.c#L147" idonL147" class=4d        4ef">DRV_NAME3/a>), ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonass="line" namionL169">v1693/a   .3   .3a href="+code=uTSS3/aPOLLING class="sref">pde=uTSS3/aPOLLINGss="s)ra> 3a href="+code=adma_ata_ops" clas4s="sref">4IBATA_MAX_PRD3/a>, , ADMA_MMIO_BAR3/err_mas="+code=ata_linkerr_mas=.13s3|/a"+code=dma_boundC_ERR_HOST_BU="line" namionL57C_ERR_HOST_BU=s="sa/pdc_adma.c#L147" idonL147" class=4dgle-pack4onL147">v1473/a>}; v1273/aaaaaaaaaelse1af tt3a href="+code=ta/pu1ine" namionL139sa/pu1.13s3   .3 v3a href="+code=AoS03" class="line"AoS0.13s3|   .3a href="+coaUIRQ3" class="line"AUIRQss="s)r/pdc_adma.c#L147" idonL147" class=4d        4mionL148">v1483/a> ADMA_MMIO_BAR3/err_mas="+code=ata_linkerr_mas=.13s3|/a"+code=dma_boundC_ERR_OTHER class="line" ndC_ERR_OTHERs="sa/pdc_adma.c#L147" idonL147" class=4="sref">a4ma_ata_ops3/a> = { , ADMA_MMIO_BAR3/adrss="line" namione3/a>,[0]3   .3   .3a href="+cocATERR class="line" ncATERRs="srs/ata/pdc_adma.c#L88" idonL88" cla4="line" n4mionL151">v1513/a> ADMA_MMIO_BAR3/err_mas="+code=ata_linkerr_mas=.13s3|/a"+code=dma_boundC_ERR_DEV class="line" ndC_ERR_DEVs="sa/pdc_adma.c#L147" idonL147" class=4=dev" cla4">ATA_OP_NULL3/a>, ADMA_MMIO_BAR3/adrss="line" namione3/a>,[0]3! href="+code=prercDONE class="line" ncDONEs="srs/ata/pdc_adma.c#L88" idonL88" cla4="sref">a4mionL153">v1533/a> ADMA_MMIO_BAR3/err_mas="+code=ata_linkerr_mas=.13s3|/a"+code=dma_boundC_ERR_OTHER class="line" ndC_ERR_OTHERs="sa/pdc_adma.c#L147" idonL147" class=4=        4eck_atapi_dma3/a>, ADMA_MMIO_BAR3/err_mas="+code=ata_linkerr_mas=.13srs/ata/pdc_adma.c#L88" idonL88" cla4=e=qc" cl4adma_qc_issue3/a>, "tcl   comple_tic in"+code=dma_bounta_queued_cmd" class="sna/pdc_adma.c#L147" idonL147" class=4="line" n4mionL157">v1573/a> v1273/aaaaaaaaaelse1> 3a href="+code=adma_ata_ops" clas4=" class=4">adma_freeze3/a>, admrereh_inf _thaw3/a>(structv3a hehiass="line" namiehis="s3/a   .3/a> *3a href="+ADMA_PORT_REGS" class="ref">ADMA_MMIO_BAR3//a>="+code=ata_link/a>=s="sdma.c#L154" idoneh_inf class="sref">adeh_inf _thaa/pdc_adma.c#L147" idonL147" class=4 class="s4ef">adma_thaw3/a>, , v1613/a> "7">v-sa/pu1sre%02X"(1 <"s/a> *3a href="+ta/pu1ine" namionL139sa/pu1.13sna/pdc_adma.c#L147" idonL147" class=4sdev" cla4ma_port_start3/a>, a4dma_port_stop3/a>, "ne3[0]3re%02X"(1 <"s/a> *3a href="+ ass="line" namionp.13sref">ADMA_MMIO_BAR3/adrss="line" namione3/a>,[0]na/pdc_adma.c#L147" idonL147" class=4s        4onL164">v1643/a>}; v1653/a> ADMA_MMIO_BAR3/3/err_mas="+code=ata_linkerr_mas=.13=ma.c#L147" idonL147" class=4=dev" cla4">ATA_OP_NULL3/a>,cla4=e=qc" cl4adma_qc_issue3/a>, [] = { adma/abma_/a>st"+code=dma_bounADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=4=a_freeze4a_2ort_info3/a>[] = { v1273/aaaaaaaaaaaaaaaaaelse/pdc_adma.c#L147" idonL147" class=4=" class=4>v1683/a>        { "tcl1263/freezt/a>st"+code=dma_bounADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=4f">ATA_FL4G_PIO_POLLING3/a>, /* 4ss="sref"4ATA_PIO4_ONLY3/a>, /* 4s"line" n4ef">ATA_UDMA43/a>, /* 4sdev" cla4>adma_ata_ops3/a>, adma_check_atvandlefss="a/pdc_adma.c#L147" idonL147" class=4f"sref">a4v1733/a>        }, /* 4s">adma_c4onL174">v1743/a>}; v1753/a>   37"rekt" class="sref">adma_st37"rekt" /a>sttv3a href="+code=adma_prerhos " class="sref">prerhos ructvne3/a>(structv3ahos " class="sref">hos ructrs/ata/pdc_adma.c#L88" idonL88" cla4se=qc" cl4_pci_tbl3/a>[] = { adma_check_atvandlefss="3/a0"s/a> *3a href="+1263/n class="sref">ad1263/n >,v3a/pdc_adma.c#L147" idonL147" class=4"mionL1684PB address */3/spa	  ad1263/n >,v33/a0aa"+code=dma_boun1263/n class="sref">ad1263/n >,v33<aa"+code=dma_bounhos " class="sref">hos ructref">ADMA_MMIO_BAR3/n_1263"line" namionL16n_1263".13sa ++ href="+code=AD1263/n class="sref">ad1263/n >,v3)3> 3a href="+code=adma_ata_ops" clas4nput FIFO4 threshold */3/spa	  adma_thaw3/a>(structv3a href="+code=ata_port" cl3/a"+code=dma_bounhos " class="sref">hos ructref">ADMA_MMIO_BAR3/1263"line" namionL161263".13s[.c#L141" idonL11263/n class="sref">ad1263/n >,v3]a/pdc_adma.c#L147adma_ata_ops" clas4n"line" n4 threshold */3/spa	  v1263/a>structvne3/a>(structv3a ass="line" namionp.13s3/a"+code=dma_bounADMA_MMIO_BAR" class="sref">ADMA_MMIO_BAR3/a>st293/dma_ass="line" namiprst293/dma_s="sa/pdc_adma.c#L147" idonL147" class=4nss="sref4 namionL82">v 823/a> adma_check_atapi_dma3/a>(structv3a href="+code=ata_queued_cmd" class="sa/pdc_adma.c#L147" idonL147" class=4tionL173"4ister bits */3/spa	  adma_c4 1==masked */3/spa	  ADMA_MMIO_BAR3/ate_t" class="sref">adma_stat ! href="+code=prereset"="linekt" class="sref">adma_state_pkt3/a>,v3rs/ata/pdc_adma.c#L88" idonL88" cla4t"line" n4Go!") */3/spa	  st"+code=dma_bounADMA_PORT_REGS" class=""s/a> *3a href="+ADMA_PORT_REGS" class="ref">ADMA_MMIO_BAR3//a>="+code=ata_link/a>=s="sdma.c#L154" idonactL14_tagine" namionL139"ctL14_tagss="sa/pdc_adma.c#L147" idonL147" class=4t"line" n4PIO mode 4 */3/spa	  v1273/aaf t3a href="+code=ta_queued_cmd" class="s3&  .3&  .3 (!t3a href="+code=ta_queued_cmd" class="sref">ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonass="line" namionL169">v1693/a   .3   .3a href="+code=uTSS3/aPOLLING class="sref">pde=uTSS3/aPOLLINGss="s)ra> 3a href="+code=adma_ata_ops" clas4tmionL1684 namionL88">v 883/a> /* 4Tput FIFO4   = (1 << 6), st"+code=dma_bounADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=4Tput FIFO4   = (1 << 4), pde=uBUSYss="s)/pdc_adma.c#L147" idonL147" class=4Tss="sref4   = (1 << 0), v 933/a> st3_adma.c#L89"string">"ido%u: protoco" %d (dev_ta/p3re%X)\n"(1 <"/pdc_adma.c#L147" idonL147" class=4T">adma_c4* CPB bits */3/spa	  ADMA_MMIO_BAR3/a>snt_if">adma_check_ata>snt_ifss=""s/a> *3a href="+ta_queued_cmd" class="sref">ADMA_MMIO_BAR3/tf127" class="lintfs="sdma.c#L154" idonprotoco" class="sref">pprotoco"rs/a"s/a> *3a href="+ta/pu1ine" namionL139sa/pu1.13sna/pdc_adma.c#L147" idonL147" class=4T"line" n4   = (1 << 0), adma_at4   = (1 << 3), /* 4T"line" n4 namionL97">v 973/a> v1273/ata/pdc_adma.c#L144" idopass="line" namionp.13sref">ADMA_MMIO_BAR3/ate_t" class="sref">adma_stat  href="+code=prereset"="lineidlak" class="sref"0" cl="lineidlas="sa/pdc_adma.c#L147" idonL147" class=4TmionL1684   = (1 << 0), ADMA_MMIO_BAR3/err_mas="+code=ata_linkerr_mas=.13s3|/a"+code=dma_bounac_err_mas="+code=ata_linkac_err_mas=/a>st"+code=dma_bounta/pu1ine" namionL139sa/pu1.13sna/pdc_adma.c#L147" idonL147" class=5         5 = (1 << 2), ADMA_MMIO_BAR3/err_mas="+code=ata_linkerr_mas=.13srs/ata/pdc_adma.c#L88" idonL88" cla5 ridge, M5 = (1 << 3), "tcl   comple_tic in"+code=dma_bounta_queued_cmd" class="sna/pdc_adma.c#L147" idonL147" class=5 2idge, M5   = (1 << 4), admrereh_inf _thaw3/a>(structv3a hehiass="line" namiehis="s3/a   .3/a> *3a href="+ADMA_PORT_REGS" class="ref">ADMA_MMIO_BAR3//a>="+code=ata_link/a>=s="sdma.c#L154" idoneh_inf class="sref">adeh_inf _thaa/pdc_adma.+code=adma_ata_ops" clas5 4	 class5PnamionL93">v 933/a> "sa/pu1sre%02X"(1 <"s/a> *3a href="+ta/pu1ine" namionL139sa/pu1.13sna/pdc_adma.c#L147" idonL147" class=5         5 = (1 << 7), ADMA_MMIO_BAR3/3/err_mas="+code=ata_linkerr_mas=.13=ma.c#L147" idonL147" class=4=dev" cla4">ATA_OP_NULL3/a>,cla4=e=qc" cl4adma_qc_issue3/a>, v1273/aaaaaaaaaaaaaaaaadma.c#L1  .3a href="+coAtcl1263/abma_thaw" class="sref">adma/abma_/a>st"+code=dma_bounADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=5         5 = (1 << 5), "tcl1263/freezt/a>st"+code=dma_bounADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=5="line" n5mionL110">v13.18a> /* 5register 5ddresses */3/spa	  adma_check_atvandlefss="3/a1a/pdc_adma.c#L147" idonL147" class=5=a	 class53/a>       = 0x0e, /* 5r4	 class5COUNT3/a>  = 0x12, /* 5r        53/a>       = 0x13, adma_check_atvandlefss="a/pdc_adma.c#L147" idonL147" class=5         53/a>       = 0x14, /* 5r7       5H3/a>      = 0x15,         = 0x16, adma_st37"r/a>st37" idonL137" classirqthaw" class="srirqs="soaadma.3/a>(structv3a hdev_inta/nct" class="sref">dev_inta/nct/a>,cla4=e=qc" cl4adma_qc_issue3/a>,        = 0x17, v1193/a> prerhos ructvne3/a>(structv3ahos " class="sref">hos ruct  href="+code=prerdev_inta/nct" class="sref">dev_inta/nct/a>,a/pdc_adma.c#L147" idonL147" class=5="line" n5vice IDs */3/spa	  adma_check_atvandlefss="3/a0a/pdc_adma.c#L147" idonL147" class=5=egister 5ntroller */3/spa	  v1223/a>}; st3_adma.c#L89"string">"ENTER\n"(1 <sa/pdc_adma.c#L147" idonL147" class=5="line" n5mionL123">v1233/a> adma_state_t3/a>; hos ructref">ADMA_MMIO_BAR3/locas="+code=ata_liloca/a>ssa/pdc_adma.c#L147" idonL147" class=5=        5mionL125">v1253/a> adma_check_atvandlefss="3  href="+code=prereset"37"readrss="line" namioeset"37"readric in/a> *3a href="+hos " class="sref">hos ruct)3|   .3a href="+coaa>  37"rekt" class="sref">adma_st37"rekt" /a>st/a> *3a href="+hos " class="sref">hos ruct)a/pdc_adma.c#L147" idonL147" class=5=7       5ma_port_priv3/a> { hos ructref">ADMA_MMIO_BAR3/locas="+code=ata_liloca/a>ssa/pdc_adma.c#L147" idonL147" class=5=gle-pack5ss="sref">pkt3/a>; pkt_dma3/a>; st3_adma.c#L89"string">"EXIT\n"(1 <sa/pdc_adma.c#L147" idonL147" class=5ate" clas5="sref">state3/a>; v13.18a>}; st/a> *3a href="+handlef">adma_check_atvandlefss="sa/pdc_adma.c#L147" idonL147" class=5aegister 5mionL131">v1313/a> /* 5aine" nam5s="sref">pdev3/a>, ent3/a>); sttv3a href="+code=adma_prerio1263"line" namionL16prerio1263"ructvne3/a>(structv3adma_thaw" class="srdma_/a>s,aadma.c#L140" idonL14__iomemf="+code=ata_po__iomem_thaw3/a>(structv3a hbast" class="sref">bast/a>,cla4=e=qc" cl4adma_qc_issue3/a>, ap3/a>); ap3/a>); ADMA_MMIO_BAR3/cmdopsdrclass="sref">adcmdopsdrrs/ata/pdc_adm= 3a href="+code=adma_ata_ops" clas5a7       5ss="sref">qc3/a>); ADMA_MMIO_BAR3/dma_opsdrclass="sref">addma_opsdrrs/ata/pdc_ad href="+code=prerbast" class="sref">bast/a>, + 0x000a/pdc_adma.c#L147" idonL147" class=5agle-pack5ss="sref">qc3/a>); ADMA_MMIO_BAR3/erroropsdrclass="sref">aderroropsdrrs/ata/pdc_a= 3a href="+code=adma_ata_ops" clas5a        5ss="sref">qc3/a>); ADMA_MMIO_BAR3/fea v3eopsdrclass="sref">adfea v3eopsdrrs/ata/pdc href="+code=prerbast" class="sref">bast/a>, + 0x004a/pdc_adma.c#L147" idonL147" class=5de=ap" cl5ss="sref">ap3/a>); ADMA_MMIO_BAR3/nsectopsdrclass="sref">adnsectopsdrrs/ata/pdc_a=href="+code=prerbast" class="sref">bast/a>, + 0x008a/pdc_adma.c#L147" idonL147" class=5dine" nam5ss="sref">ap3/a>); ADMA_MMIO_BAR3/lbalopsdrclass="sref">adlbalopsdrrs/ata/pdc_ad href="+code=prerbast" class="sref">bast/a>, + 0x00ca/pdc_adma.c#L147" idonL147" class=5degister 5ef">deadline3/a>); ADMA_MMIO_BAR3/lbamopsdrclass="sref">adlbamopsdrrs/ata/pdc_ad href="+code=prerbast" class="sref">bast/a>, + 0x010a/pdc_adma.c#L147" idonL147" class=5ddev" cla5mionL142">v1423/a> ADMA_MMIO_BAR3/lbahopsdrclass="sref">adlbahopsdrrs/ata/pdc_ad href="+code=prerbast" class="sref">bast/a>, + 0x014a/pdc_adma.c#L147" idonL147" class=5d"line" n5ma_ata_sht3/a> = { ADMA_MMIO_BAR3/deviceopsdrclass="sref">addeviceopsdrrs/ata/pdc_ href="+code=prerbast" class="sref">bast/a>, + 0x018a/pdc_adma.c#L147" idonL147" class=5d        5ef">DRV_NAME3/a>), ADMA_MMIO_BAR3/sa/pu1opsdrclass="sref">adsa/pu1opsdrrs/ata/pdc_ /pdc_adma.c#L147" idonL147" class=5d"line" n5IBATA_MAX_PRD3/a>, ADMA_MMIO_BAR3/commandopsdrclass="sref">adcommandopsdrrs/ata/pdc href="+code=prerbast" class="sref">bast/a>, + 0x01ca/pdc_adma.c#L147" idonL147" class=5d7       5_DMA_BOUNDARY3/a>, ADMA_MMIO_BAR3/altsa/pu1opsdrclass="sref">adaltsa/pu1opsdrrs/ata/p /pdc_adma.c#L147" idonL147" class=5dgle-pack5onL147">v1473/a>}; ADMA_MMIO_BAR3/ctlopsdrclass="sref">adctlopsdrrs/ata/pdc_adm=href="+code=prerbast" class="sref">bast/a>, + 0x038a/pdc_adma.c#L147" idonL147" class=5d        5mionL148">v1483/a> /* 5="sref">a5ma_ata_ops3/a> = { ,   1263/atea_thaw" class="sre" clp263/atea_/a>sttv3a href="+code=adma_prerdma_thaw" class="sref">adma_thaw3/a>(structv3a href="+code=ata_port" clcla4=e=qc" cl4adma_qc_issue3/a>, v1513/a> ATA_OP_NULL3/a>, addevice_thaw3/a>(structv3a hdevclass="sref">addevruct  href="+code=prerADMA_PORT_REGS" class="ref">ADMA_MMIO_BAR3/hos " class="sref">hos ructref">ADMA_MMIO_BAR3/devclass="sref">addevructa/pdc_adma.c#L147" idonL147" class=5="sref">a5mionL153">v1533/a> v1263/a>structvne3/a>(structv3a ass="line" namionp.13sa/pdc_adma.c#L147" idonL147" class=5=        5eck_atapi_dma3/a>, ve3/a>l  g_43/ak" class="sref"0" cle3/a>l  g_43/a/a>st"+code=dma_bounADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=5=e=qc" cl5adma_qc_issue3/a>, st"+code=dma_boundevclass="sref">addevruct, sizeof(ne3/a>(structv3a ass="line" namionp.13s)"s/a> *3a href="+GFP_KERNEss="line" namionGFP_KERNEsss="sa/pdc_adma.c#L147" idonL147" class=5=gle-pack5mionL157">v1573/a> , adma_freeze3/a>, adma_thaw3/a>, ADMA_MMIO_BAR3/adrss="line" namione3/a>,3/a"+code=dma_boundmamoplloa_cohernL89lass="sref">addmamoplloa_cohernL8/a>st"+code=dma_boundevclass="sref">addevruct, "+code=dma_boun7">v 5KT_BYTE="line" namionL57">v 5KT_BYTE=ruct,    .3/a> *3a href="+dass="line" namionp.13sref">ADMA_MMIO_BAR3/adr_dmass="line" namione3_dmaruct,/pdc_adma.c#L147" idonL147" class=5 ine" nam5adma_prereset3/a>, v1613/a> ADMA_MMIO_BAR3/adrss="line" namione3/a>,cla4=e=qc" cl4adma_qc_issue3/a>, , a5dma_port_stop3/a>, /* 5s        5onL164">v1643/a>}; ADMA_MMIO_BAR3/adr_dmass="line" namione3_dmaruct3   .3 7) ! h0ra> 3a href="+code=adma_ata_ops" clas5=ss="sref5mionL165">v1653/a> snta/a>st"+code=dma_bounKERN_ERR class="line" nKERN_ERRivers3_adma.c#L89"string">"bad alignonL8afor ppref">ne3_dma: %08x\n"(1 <"/pdc_adma.c#L147" idonL147" class=5se=qc" cl5ort_info3/a>[] = { vine" nu3ers/a)3a href="+code= ass="line" namionp.13sref">ADMA_MMIO_BAR3/adr_dmass="line" namione3_dmaructsa/pdc_adma.c#L147" idonL147" class=5sgle-pack5a_2ort_info3/a>[] = { v1273/a v v3/d-adma.c#L126" idENOMEMss="line" namioENOMEM.13sa/pdc_adma.c#L147" idonL147" class=5         5>v1683/a>        { /* 5f">ATA_FL5G_PIO_POLLING3/a>, st"+code=dma_boun ass="line" namionp.13sref">ADMA_MMIO_BAR3/adrss="line" namione3/a>,,a0"s/a> *3a href="+7">v 5KT_BYTE="line" namionL57">v 5KT_BYTE=ructsa/pdc_adma.c#L147" idonL147" class=5ss="sref"5ATA_PIO4_ONLY3/a>, ADMA_MMIO_BAR3/a>st293/dma_ass="line" namiprst293/dma_s="s3/a"+code=dma_boun ass="line" namionp.13sa/pdc_adma.c#L147" idonL147" class=5s"line" n5ef">ATA_UDMA43/a>, st"+code=dma_bounADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=5sdev" cla5>adma_ata_ops3/a>, a5v1733/a>        }, /* 5s">adma_c5onL174">v1743/a>}; v1753/a> sttv3a href="+code=adma_prerdma_thaw" class="sref">adma_thaw3/a>(structv3a href="+code=ata_port" clcla4=e=qc" cl4adma_qc_issue3/a>, [] = { st"+code=dma_bounADMA_PORT_REGS" class="sa/pdc_adma.c#L147" idonL147" class=5s        5PB address */3/spa	  /* 5/* CPB lo5okup table */3/spa	  sttv3a href="+code=adma_prerhos " class="sref">prerhos ructvne3/a>(structv3ahos " class="sref">hos ruct,aadma.c#L137" idonL137" classchip_if">adma_check_atchip_if" clcla4=e=qc" cl4adma_qc_issue3/a>,  3a href="+code=adma_ata_ops" clas5nss="sref5 namionL82">v 823/a> ad1263/n >,v3a/pdc_adma.c#L147" idonL147" class=5tionL173"5ister bits */3/spa	  adma_c5 1==masked */3/spa	  /* 5t"line" n5Go!") */3/spa	  thaw3writeb/a>st7"s/a> *3a href="+hos " class="sref">hos ructref">ADMA_MMIO_BAR3/iomADMA_PORT_REGS" ciomADruct[.c#L141" idonL17">v MMIO_BAR class="line" nd">v MMIO_BARruct]33a href="+code=ADMA_CPMODE_LOCKass="line" namiMA_CPMODE_LOCKss="sa/pdc_adma.c#L147" idonL147" class=5te=qc" cl5ogic reset */3/spa	  /* 5t        5 namionL88">v 883/a> ad1263/n >,v33/a0aa"+code=dma_boun1263/n class="sref">ad1263/n >,v33<aa"+code=dma_boun7">v 573/="line" namionL57">v 573/=s="sa ++ href="+code=AD1263/n class="sref">ad1263/n >,v3)< 8), 3spa	 class="comment">/* 5TATUS reg5ister bits */3/spa	  st"+code=dma_bounhos " class="sref">hos ructref">ADMA_MMIO_BAR3/1263"line" namionL161263".13s[.c#L141" idonL11263/n class="sref">ad1263/n >,v3]sa/pdc_adma.c#L147" idonL147" class=5Tput FIFO5   = (1 << 6), /* 5Tput FIFO5   = (1 << 4),   serla>  r_ma"line" namionL16pa>  serla>  r_ma"/a>sttv3a href="+code=adma_pci_devclass="sref">adpci_devructvne3/a>(structv3a devclass="sref">adpdevruct, adma.c#L140" idonL14__iomemf="+code=ata_po__iomem_thaw3/a>(structv3a hkt" _bast" class="sref">kt" _bast>,v3)< 8), 3spa	 class="comment">/* 5TionL173"5 namionL93">v 933/a>  3a href="+code=adma_ata_ops" clas5T">adma_c5* CPB bits */3/spa	  adma_at5   = (1 << 3),   r_maclass="sref">adpci_serla>  r_ma/a>st"+code=dma_boun devclass="sref">adpdevruct, "+code=dma_boun">v BIT_MASKass="line" namiD>v BIT_MASK/a>st32)sa/pdc_adma.c#L147" idonL147" class=5T"line" n5 namionL97">v 973/a> addev_err/a>st   .3/a> *3a href="+ddevclass="sref">adpdevructref">ADMA_MMIO_BAR3/devclass="sref">addevructoaa_adma.c#L89"string">"32-bit A_C enable failed\n"(1 <sa/pdc_adma.c#L147" idonL147" class=6         6 = (1 << 2), /* 6 2idge, M6   = (1 << 4),   r_maclass="sref">adpci_serlcodmastnL8la>  r_ma/a>st"+code=dma_boun devclass="sref">adpdevruct, "+code=dma_boun">v BIT_MASKass="line" namiD>v BIT_MASK/a>st32)sa/pdc_adma.c#L147" idonL147" class=6 a	 class6PRD bits */3/spa	  v 933/a> addev_err/a>st   .3/a> *3a href="+ddevclass="sref">adpdevructref">ADMA_MMIO_BAR3/devclass="sref">addevructoaa_adma.c#L89"string">"32-bit codmastnL8 A_C enable failed\n"(1 <sa/pdc_adma.c#L147" idonL147" class=6 5	 class6P CPB bits */3/spa	  /* 6 7	 class6P  = (1 << 3), /* 6 9le-pack6e  = (1 << 0),   prerinitloink" class="sref"0" clprerinitloin/a>sttv3a href="+code=adma_pci_devclass="sref">adpci_devructvne3/a>(structv3a devclass="sref">adpdevruct,ta/pdc_adma.c#L119" idonL119" clas6 ridge, M6mionL110">v13.18a> adma_check_ataci_deviceoifructvne3/a>(structv3anL89lass="sref">adnL8/a>s)< 8), 3spa	 class="comment">/* 6register 6ddresses */3/spa	         = 0x0e, adboardoifxs="s3/a(adma.c#L137") idonL137" classnL89lass="sref">adnL8/a>sref">ADMA_MMIO_BAR3/dcode=/dma_ass="line" namidcode=/dma_s="sa/pdc_adma.c#L147" idonL147" class=6r4	 class6COUNT3/a>  = 0x12, admrer1263/inf ructvne3/a>(structv3a piass="line" nami pi.13s[]3/a{a   .3/a> *3a href="+A" clp263/inf class="sref">adm" clp263/inf .13s[.c#L141" idonL1boardoifx9lass="sref">adboardoifxs="s], "+code=dma_bounNULss="line" namionNULsructv}a/pdc_adma.c#L147" idonL147" class=6r5	 class63/a>       = 0x13, prerhos ructvne3/a>(structv3ahos " class="sref">hos ructa/pdc_adma.c#L147" idonL147" class=6r6	 class63/a>       = 0x14, kt" _bast>,v3a/pdc_adma.c#L147" idonL147" class=6r7	 class6H3/a>      = 0x15,  *3a href="+1263/n class="sref">ad1263/n >,v3a/pdc_adma.c#L147" idonL147" class=6=gle-pack6/a>        = 0x16,        = 0x17, snt_147"ionloiceclass="sref">admrer1>snt_147"ionloice/a>st   .3/a> *3a href="+ddevclass="sref">adpdevructref">ADMA_MMIO_BAR3/devclass="sref">addevructoaa+code=dma_boun"RV_VERSIONass="line" namiDRV_VERSIONss="sa/pdc_adma.c#L147" idonL147" class=6="line" n6mionL119">v1193/a> /* 6=egister 6ntroller */3/spa	  hos ruct  href="+code=prerprerhos oplloa_pinf class="sref">admrerhos oplloa_pinf /a>st   .3/a> *3a href="+ddevclass="sref">adpdevructref">ADMA_MMIO_BAR3/devclass="sref">addevructoaa+code=dma_boun piass="line" nami pi.13s"s/a> *3a href="+7">v 573/="line" namionL57">v 573/=s="ssa/pdc_adma.c#L147" idonL147" class=6=a	 class6onL122">v1223/a>}; hos ructrs/ata/pdc_adma.c#L88" idonL88" cla6="line" n6mionL123">v1233/a> adma_state_t3/a>; v1253/a> /* 6=7	 class6ma_port_priv3/a> { ad cim_enable_device/a>st"+code=dma_boun devclass="sref">adpdevructsa/pdc_adma.c#L147" idonL147" class=6=gle-pack6ss="sref">pkt3/a>; pkt_dma3/a>; state3/a>; v13.18a>}; adpdevruct, 4)3   .3   .3a href="+coIORESOURCE_MEMss="line" namioIORESOURCE_MEMs="sra= h0rta/pdc_adma.c#L110" idonL110" clas6legister 6mionL131">v1313/a> ATENOss=s="sa/pdc_adma.c#L147" idonL147" class=6aa	 class6s="sref">pdev3/a>, ent3/a>); st"+code=dma_boun devclass="sref">adpdevruct, 13<a<aa"+code=dma_boun7">v MMIO_BAR class="line" nd">v MMIO_BARructoaa+code=dma_boun"RV_NAMEass="line" namiDRV_NAMEructsa/pdc_adma.c#L147" idonL147" class=6a        6ss="sref">ap3/a>); ap3/a>); qc3/a>); hos ructref">ADMA_MMIO_BAR3/iomADMA_PORT_REGS" ciomADruct3/a"+code=dma_boun cim_iomADltableline" namionL16 cim_iomADltable/a>st"+code=dma_boun devclass="sref">adpdevructsa/pdc_adma.c#L147" idonL147" class=6agle-pack6ss="sref">qc3/a>); kt" _bast>,v33/a"+code=dma_bounhos " class="sref">hos ructref">ADMA_MMIO_BAR3/iomADMA_PORT_REGS" ciomADruct[.c#L141" idonL17">v MMIO_BAR class="line" nd">v MMIO_BARruct]a/pdc_adma.c#L147" idonL147" class=6a        6ss="sref">qc3/a>); ap3/a>);   serla>  r_ma"line" namionL16pa>  serla>  r_ma"/a>st"+code=dma_boun devclass="sref">adpdevruct, "+code=dma_bounkt" _bast" class="sref">kt" _bast>,v3)a/pdc_adma.c#L147" idonL147" class=6dine" nam6ss="sref">ap3/a>); deadline3/a>); v1423/a>  = { ad1263/n >,v33/a0aa"+code=dma_boun1263/n class="sref">ad1263/n >,v33<aa"+code=dma_boun7">v 573/="line" namionL57">v 573/=s="sa ++ href="+code=AD1263/n class="sref">ad1263/n >,v3)a> 3a href="+code=adma_ata_ops" clas6d        6ef">DRV_NAME3/a>), adma_thaw3/a>(structv3a href="+code=ata_port" cl3/a"+code=dma_bounhos " class="sref">hos ructref">ADMA_MMIO_BAR3/1263"line" namionL161263".13s[.c#L141" idonL11263/n class="sref">ad1263/n >,v3]a/pdc_adma.c#L147adma_ata_ops" clas6d"line" n6IBATA_MAX_PRD3/a>, 1263/bast" cl3/a"+code=dma_boun7">v de=uREG="line" namionL57">v de=uREG=/a>st"+code=dma_bounkt" _bast" class="sref">kt" _bast>,v3"s/a> *3a href="+1263/n class="sref">ad1263/n >,v3)a/pdc_adma.c#L147" idonL147" class=6d7	 class6_DMA_BOUNDARY3/a>, 1263/bast" cl3- "+code=dma_bounkt" _bast" class="sref">kt" _bast>,v3a/pdc_adma.c#L147" idonL147" class=6dgle-pack6onL147">v1473/a>}; v1483/a> st   .3/a> *3a href="+ADMA_PORT_REGS" class="ref">ADMA_MMIO_BAR3/iopsdrclass="sref">adiopsdr>,v3"s/a> *3a href="+1263/bast" class="sref">1263/bast" cl)a/pdc_adma.c#L147" idonL147" class=6="sref">a6ma_ata_ops3/a> = { , st"+code=dma_bounADMA_PORT_REGS" class=""s/a> *3a href="+7">v MMIO_BAR class="line" nd">v MMIO_BARructoa-1oaa_adma.c#L89"string">"kt" "(1 <sa/pdc_adma.c#L147" idonL147" class=6="line" n6mionL151">v1513/a> st"+code=dma_bounADMA_PORT_REGS" class=""s/a> *3a href="+7">v MMIO_BAR class="line" nd">v MMIO_BARructoaidonL137" classoffserss="line" namiooffserructoaa_adma.c#L89"string">"1263"(1 <sa/pdc_adma.c#L147" idonL147" class=6=dev" cla6">ATA_OP_NULL3/a>, /* 6="sref">a6mionL153">v1533/a> , /* 6ass="sref6>adma_qc_prep3/a>, vhos _initk" class="sref"0" clhos _init/a>st"+code=dma_bounhos " class="sref">hos ructoaidonL137" classboardoifx9lass="sref">adboardoifxs="ssa/pdc_adma.c#L147" idonL147" class=6=7	 class6adma_qc_issue3/a>, v1573/a> st"+code=dma_boun devclass="sref">adpdevructsa/pdc_adma.c#L147" idonL147" class=6=        6">adma_freeze3/a>, admrerhos opctst293/a>st"+code=dma_bounhos " class="sref">hos ructoaidonL137" classddevclass="sref">adpdevructref">ADMA_MMIO_BAR3/irqthaw" class="srirqs="soadma.c#L116" ido26">v37"rclass="sref">adma_st37"r/a>soadma.c#L116" idoIRQF_SHAREDss="line" namioIRQF_SHARED/a>so/pdc_adma.c#L147" idonL147" class=6 class="s6ef">adma_thaw3/a>, , /* 6s"line" n6mionL161">v1613/a> , kodule_aci_d.c#L1/a>st"+code=dma_bounA" cl0   aci_d.c#L1" class="sref">A" cl0   aci_d.c#L1ruct)a/pdc_adma.c#L147" idonL147" class=6 "sref">a6dma_port_stop3/a>, v1643/a>}; st"_adma.c#L89"string">"Mark Lord"(1 <sa/pdc_adma.c#L147" idonL147" class=6=ss="sref6mionL165">v1653/a> st"_adma.c#L89"string">"Pacific Digital Cor126atLon MA_C low-level c#L147"(1 <sa/pdc_adma.c#L147" idonL147" class=6=7	 class6ort_info3/a>[] = { st"_adma.c#L89"string">"GPL"(1 <sa/pdc_adma.c#L147" idonL147" class=6=gle-pack6a_2ort_info3/a>[] = { st"+code=dma_boun ciass="line" nami ci.13s"s/a> *3a href="+A" cl0   aci_tbl" class="sref">A" cl0   aci_tblruct)a/pdc_adma.c#L147" idonL147" class=6         6>v1683/a>        { st"+code=dma_boun"RV_VERSIONass="line" namiDRV_VERSIONss="sa/pdc_adma.c#L147" idonL147" class=6f">ATA_FL6G_PIO_POLLING3/a>, lxr@NG3ux.no.13s.
lxr.NG3ux.no kindly hos ed by pdc_adma.http://www.redpill-NG3pro.no">Redpill LG3pro A=ruct, provider_of LG3uxdcodmulting and operatLons services since 1995.