LXR linux/drivers/ata/ahci.c

   1/*
   2 *  ahci.c - AHCI SATA support
   3 *
   4 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5 *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6 *                  on emails.
   7 *
   8 *  Copyright 2004-2005 Red Hat, Inc.
   9 *
  10 *
  11 *  This program is free software; you can redistribute it and/or modify
  12 *  it under the terms of the GNU General Public License as published by
  13 *  the Free Software Foundation; either version 2, or (at your option)
  14 *  any later version.
  15 *
  16 *  This program is distributed in the hope that it will be useful,
  17 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 *  GNU General Public License for more details.
  20 *
  21 *  You should have received a copy of the GNU General Public License
  22 *  along with this program; see the file COPYING.  If not, write to
  23 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24 *
  25 *
  26 * libata documentation is available via 'make {ps|pdf}docs',
  27 * as Documentation/DocBook/libata.*
  28 *
  29 * AHCI hardware documentation:
  30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  32 *
  33 */
  34
  35#include <linux/kernel.h>
  36#include <linux/module.h>
  37#include <linux/pci.h>
  38#include <linux/init.h>
  39#include <linux/blkdev.h>
  40#include <linux/delay.h>
  41#include <linux/interrupt.h>
  42#include <linux/dma-mapping.h>
  43#include <linux/device.h>
  44#include <linux/dmi.h>
  45#include <linux/gfp.h>
  46#include <scsi/scsi_host.h>
  47#include <scsi/scsi_cmnd.h>
  48#include <linux/libata.h>
  49#include "ahci.h"
  50
  51#define DRV_NAME        "ahci"
  52#define DRV_VERSION     "3.0"
  53
  54enum {
  55        AHCI_PCI_BAR_STA2X11    = 0,
  56        AHCI_PCI_BAR_STANDARD   = 5,
  57};
  58
  59enum board_ids {
  60        /* board IDs by feature in alphabetical order */
  61        board_ahci,
  62        board_ahci_ign_iferr,
  63        board_ahci_nosntf,
  64        board_ahci_yes_fbs,
  65
  66        /* board IDs for specific chipsets in alphabetical order */
  67        board_ahci_mcp65,
  68        board_ahci_mcp77,
  69        board_ahci_mcp89,
  70        board_ahci_mv,
  71        board_ahci_sb600,
  72        board_ahci_sb700,       /* for SB700 and SB800 */
  73        board_ahci_vt8251,
  74
  75        /* aliases */
  76        board_ahci_mcp_linux    = board_ahci_mcp65,
  77        board_ahci_mcp67        = board_ahci_mcp65,
  78        board_ahci_mcp73        = board_ahci_mcp65,
  79        board_ahci_mcp79        = board_ahci_mcp77,
  80};
  81
  82static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  83static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  84                                 unsigned long deadline);
  85static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  86                                unsigned long deadline);
  87#ifdef CONFIG_PM
  88static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
  89static int ahci_pci_device_resume(struct pci_dev *pdev);
  90#endif
  91
  92static struct scsi_host_template ahci_sht = {
  93        AHCI_SHT("ahci"),
  94};
  95
  96static struct ata_port_operations ahci_vt8251_ops = {
  97        .inherits               = &ahci_ops,
  98        .hardreset              = ahci_vt8251_hardreset,
  99};
 100
 101static struct ata_port_operations ahci_p5wdh_ops = {
 102        .inherits               = &ahci_ops,
 103        .hardreset              = ahci_p5wdh_hardreset,
 104};
 105
 106static const struct ata_port_info ahci_port_info[] = {
 107        /* by features */
 108        [board_ahci] = {
 109                .flags          = AHCI_FLAG_COMMON,
 110                .pio_mask       = ATA_PIO4,
 111                .udma_mask      = ATA_UDMA6,
 112                .port_ops       = &ahci_ops,
 113        },
 114        [board_ahci_ign_iferr] = {
 115                AHCI_HFLAGS     (AHCI_HFLAG_IGN_IRQ_IF_ERR),
 116                .flags          = AHCI_FLAG_COMMON,
 117                .pio_mask       = ATA_PIO4,
 118                .udma_mask      = ATA_UDMA6,
 119                .port_ops       = &ahci_ops,
 120        },
 121        [board_ahci_nosntf] = {
 122                AHCI_HFLAGS     (AHCI_HFLAG_NO_SNTF),
 123                .flags          = AHCI_FLAG_COMMON,
 124                .pio_mask       = ATA_PIO4,
 125                .udma_mask      = ATA_UDMA6,
 126                .port_ops       = &ahci_ops,
 127        },
 128        [board_ahci_yes_fbs] = {
 129                AHCI_HFLAGS     (AHCI_HFLAG_YES_FBS),
 130                .flags          = AHCI_FLAG_COMMON,
 131                .pio_mask       = ATA_PIO4,
 132                .udma_mask      = ATA_UDMA6,
 133                .port_ops       = &ahci_ops,
 134        },
 135        /* by chipsets */
 136        [board_ahci_mcp65] = {
 137                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
 138                                 AHCI_HFLAG_YES_NCQ),
 139                .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
 140                .pio_mask       = ATA_PIO4,
 141                .udma_mask      = ATA_UDMA6,
 142                .port_ops       = &ahci_ops,
 143        },
 144        [board_ahci_mcp77] = {
 145                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
 146                .flags          = AHCI_FLAG_COMMON,
 147                .pio_mask       = ATA_PIO4,
 148                .udma_mask      = ATA_UDMA6,
 149                .port_ops       = &ahci_ops,
 150        },
 151        [board_ahci_mcp89] = {
 152                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA),
 153                .flags          = AHCI_FLAG_COMMON,
 154                .pio_mask       = ATA_PIO4,
 155                .udma_mask      = ATA_UDMA6,
 156                .port_ops       = &ahci_ops,
 157        },
 158        [board_ahci_mv] = {
 159                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
 160                                 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
 161                .flags          = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
 162                .pio_mask       = ATA_PIO4,
 163                .udma_mask      = ATA_UDMA6,
 164                .port_ops       = &ahci_ops,
 165        },
 166        [board_ahci_sb600] = {
 167                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL |
 168                                 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
 169                                 AHCI_HFLAG_32BIT_ONLY),
 170                .flags          = AHCI_FLAG_COMMON,
 171                .pio_mask       = ATA_PIO4,
 172                .udma_mask      = ATA_UDMA6,
 173                .port_ops       = &ahci_pmp_retry_srst_ops,
 174        },
 175        [board_ahci_sb700] = {  /* for SB700 and SB800 */
 176                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL),
 177                .flags          = AHCI_FLAG_COMMON,
 178                .pio_mask       = ATA_PIO4,
 179                .udma_mask      = ATA_UDMA6,
 180                .port_ops       = &ahci_pmp_retry_srst_ops,
 181        },
 182        [board_ahci_vt8251] = {
 183                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
 184                .flags          = AHCI_FLAG_COMMON,
 185                .pio_mask       = ATA_PIO4,
 186                .udma_mask      = ATA_UDMA6,
 187                .port_ops       = &ahci_vt8251_ops,
 188        },
 189};
 190
 191static const struct pci_device_id ahci_pci_tbl[] = {
 192        /* Intel */
 193        { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
 194        { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
 195        { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
 196        { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
 197        { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
 198        { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
 199        { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
 200        { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
 201        { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
 202        { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
 203        { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
 204        { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
 205        { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
 206        { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
 207        { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
 208        { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
 209        { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
 210        { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
 211        { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
 212        { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
 213        { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
 214        { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
 215        { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
 216        { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
 217        { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
 218        { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
 219        { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
 220        { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
 221        { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
 222        { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
 223        { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
 224        { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
 225        { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
 226        { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
 227        { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
 228        { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
 229        { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
 230        { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
 231        { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
 232        { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
 233        { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
 234        { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
 235        { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
 236        { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
 237        { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
 238        { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
 239        { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
 240        { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
 241        { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
 242        { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
 243        { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
 244        { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
 245        { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
 246        { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
 247        { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
 248        { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
 249        { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
 250        { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
 251        { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
 252        { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
 253        { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
 254        { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
 255        { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
 256        { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
 257        { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
 258        { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
 259        { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
 260        { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
 261        { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
 262        { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
 263        { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
 264        { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
 265        { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
 266        { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
 267
 268        /* JMicron 360/1/3/5/6, match class to avoid IDE function */
 269        { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 270          PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
 271        /* JMicron 362B and 362C have an AHCI function with IDE class code */
 272        { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
 273        { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
 274
 275        /* ATI */
 276        { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
 277        { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
 278        { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
 279        { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
 280        { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
 281        { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
 282        { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
 283
 284        /* AMD */
 285        { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
 286        /* AMD is using RAID class only for ahci controllers */
 287        { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 288          PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
 289
 290        /* VIA */
 291        { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
 292        { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
 293
 294        /* NVIDIA */
 295        { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },      /* MCP65 */
 296        { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },      /* MCP65 */
 297        { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },      /* MCP65 */
 298        { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },      /* MCP65 */
 299        { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },      /* MCP65 */
 300        { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },      /* MCP65 */
 301        { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },      /* MCP65 */
 302        { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },      /* MCP65 */
 303        { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },      /* MCP67 */
 304        { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },      /* MCP67 */
 305        { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },      /* MCP67 */
 306        { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },      /* MCP67 */
 307        { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },      /* MCP67 */
 308        { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },      /* MCP67 */
 309        { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },      /* MCP67 */
 310        { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },      /* MCP67 */
 311        { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },      /* MCP67 */
 312        { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },      /* MCP67 */
 313        { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },      /* MCP67 */
 314        { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },      /* MCP67 */
 315        { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },  /* Linux ID */
 316        { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },  /* Linux ID */
 317        { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },  /* Linux ID */
 318        { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },  /* Linux ID */
 319        { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },  /* Linux ID */
 320        { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },  /* Linux ID */
 321        { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },  /* Linux ID */
 322        { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },  /* Linux ID */
 323        { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },  /* Linux ID */
 324        { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },  /* Linux ID */
 325        { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },  /* Linux ID */
 326        { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },  /* Linux ID */
 327        { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },  /* Linux ID */
 328        { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },  /* Linux ID */
 329        { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },  /* Linux ID */
 330        { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },  /* Linux ID */
 331        { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },      /* MCP73 */
 332        { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },      /* MCP73 */
 333        { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },      /* MCP73 */
 334        { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },      /* MCP73 */
 335        { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },      /* MCP73 */
 336        { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },      /* MCP73 */
 337        { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },      /* MCP73 */
 338        { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },      /* MCP73 */
 339        { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },      /* MCP73 */
 340        { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },      /* MCP73 */
 341        { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },      /* MCP73 */
 342        { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },      /* MCP73 */
 343        { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },      /* MCP77 */
 344        { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },      /* MCP77 */
 345        { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },      /* MCP77 */
 346        { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },      /* MCP77 */
 347        { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },      /* MCP77 */
 348        { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },      /* MCP77 */
 349        { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },      /* MCP77 */
 350        { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },      /* MCP77 */
 351        { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },      /* MCP77 */
 352        { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },      /* MCP77 */
 353        { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },      /* MCP77 */
 354        { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },      /* MCP77 */
 355        { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },      /* MCP79 */
 356        { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },      /* MCP79 */
 357        { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },      /* MCP79 */
 358        { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },      /* MCP79 */
 359        { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },      /* MCP79 */
 360        { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },      /* MCP79 */
 361        { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },      /* MCP79 */
 362        { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },      /* MCP79 */
 363        { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },      /* MCP79 */
 364        { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },      /* MCP79 */
 365        { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },      /* MCP79 */
 366        { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },      /* MCP79 */
 367        { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },      /* MCP89 */
 368        { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },      /* MCP89 */
 369        { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },      /* MCP89 */
 370        { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },      /* MCP89 */
 371        { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },      /* MCP89 */
 372        { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },      /* MCP89 */
 373        { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },      /* MCP89 */
 374        { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },      /* MCP89 */
 375        { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },      /* MCP89 */
 376        { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },      /* MCP89 */
 377        { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },      /* MCP89 */
 378        { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },      /* MCP89 */
 379
 380        /* SiS */
 381        { PCI_VDEVICE(SI, 0x1184), board_ahci },                /* SiS 966 */
 382        { PCI_VDEVICE(SI, 0x1185), board_ahci },                /* SiS 968 */
 383        { PCI_VDEVICE(SI, 0x0186), board_ahci },                /* SiS 968 */
 384
 385        /* ST Microelectronics */
 386        { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },           /* ST ConneXt */
 387
 388        /* Marvell */
 389        { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
 390        { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },        /* 6121 */
 391        { PCI_DEVICE(0x1b4b, 0x9123),
 392          .class = PCI_CLASS_STORAGE_SATA_AHCI,
 393          .class_mask = 0xffffff,
 394          .driver_data = board_ahci_yes_fbs },                  /* 88se9128 */
 395        { PCI_DEVICE(0x1b4b, 0x9125),
 396          .driver_data = board_ahci_yes_fbs },                  /* 88se9125 */
 397        { PCI_DEVICE(0x1b4b, 0x917a),
 398          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
 399        { PCI_DEVICE(0x1b4b, 0x9192),
 400          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 on some Gigabyte */
 401        { PCI_DEVICE(0x1b4b, 0x91a3),
 402          .driver_data = board_ahci_yes_fbs },
 403
 404        /* Promise */
 405        { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },   /* PDC42819 */
 406
 407        /* Asmedia */
 408        { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },   /* ASM1060 */
 409        { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },   /* ASM1060 */
 410        { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },   /* ASM1061 */
 411        { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },   /* ASM1062 */
 412
 413        /* Generic, PCI class code for AHCI */
 414        { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 415          PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
 416
 417        { }     /* terminate list */
 418};
 419
 420
 421static struct pci_driver ahci_pci_driver = {
 422        .name                   = DRV_NAME,
 423        .id_table               = ahci_pci_tbl,
 424        .probe                  = ahci_init_one,
 425        .remove                 = ata_pci_remove_one,
 426#ifdef CONFIG_PM
 427        .suspend                = ahci_pci_device_suspend,
 428        .resume                 = ahci_pci_device_resume,
 429#endif
 430};
 431
 432#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
 433static int marvell_enable;
 434#else
 435static int marvell_enable = 1;
 436#endif
 437module_param(marvell_enable, int, 0644);
 438MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
 439
 440
 441static void ahci_pci_save_initial_config(struct pci_dev *pdev,
 442                                         struct ahci_host_priv *hpriv)
 443{
 444        unsigned int force_port_map = 0;
 445        unsigned int mask_port_map = 0;
 446
 447        if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
 448                dev_info(&pdev->dev, "JMB361 has only one port\n");
 449                force_port_map = 1;
 450        }
 451
 452        /*
 453         * Temporary Marvell 6145 hack: PATA port presence
 454         * is asserted through the standard AHCI port
 455         * presence register, as bit 4 (counting from 0)
 456         */
 457        if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 458                if (pdev->device == 0x6121)
 459                        mask_port_map = 0x3;
 460                else
 461                        mask_port_map = 0xf;
 462                dev_info(&pdev->dev,
 463                          "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
 464        }
 465
 466        ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
 467                                 mask_port_map);
 468}
 469
 470static int ahci_pci_reset_controller(struct ata_host *host)
 471{
 472        struct pci_dev *pdev = to_pci_dev(host->dev);
 473
 474        ahci_reset_controller(host);
 475
 476        if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 477                struct ahci_host_priv *hpriv = host->private_data;
 478                u16 tmp16;
 479
 480                /* configure PCS */
 481                pci_read_config_word(pdev, 0x92, &tmp16);
 482                if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
 483                        tmp16 |= hpriv->port_map;
 484                        pci_write_config_word(pdev, 0x92, tmp16);
 485                }
 486        }
 487
 488        return 0;
 489}
 490
 491static void ahci_pci_init_controller(struct ata_host *host)
 492{
 493        struct ahci_host_priv *hpriv = host->private_data;
 494        struct pci_dev *pdev = to_pci_dev(host->dev);
 495        void __iomem *port_mmio;
 496        u32 tmp;
 497        int mv;
 498
 499        if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 500                if (pdev->device == 0x6121)
 501                        mv = 2;
 502                else
 503                        mv = 4;
 504                port_mmio = __ahci_port_base(host, mv);
 505
 506                writel(0, port_mmio + PORT_IRQ_MASK);
 507
 508                /* clear port IRQ */
 509                tmp = readl(port_mmio + PORT_IRQ_STAT);
 510                VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
 511                if (tmp)
 512                        writel(tmp, port_mmio + PORT_IRQ_STAT);
 513        }
 514
 515        ahci_init_controller(host);
 516}
 517
 518static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 519                                 unsigned long deadline)
 520{
 521        struct ata_port *ap = link->ap;
 522        bool online;
 523        int rc;
 524
 525        DPRINTK("ENTER\n");
 526
 527        ahci_stop_engine(ap);
 528
 529        rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 530                                 deadline, &online, NULL);
 531
 532        ahci_start_engine(ap);
 533
 534        DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 535
 536        /* vt8251 doesn't clear BSY on signature FIS reception,
 537         * request follow-up softreset.
 538         */
 539        return online ? -EAGAIN : rc;
 540}
 541
 542static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 543                                unsigned long deadline)
 544{
 545        struct ata_port *ap = link->ap;
 546        struct ahci_port_priv *pp = ap->private_data;
 547        u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 548        struct ata_taskfile tf;
 549        bool online;
 550        int rc;
 551
 552        ahci_stop_engine(ap);
 553
 554        /* clear D2H reception area to properly wait for D2H FIS */
 555        ata_tf_init(link->device, &tf);
 556        tf.command = 0x80;
 557        ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 558
 559        rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 560                                 deadline, &online, NULL);
 561
 562        ahci_start_engine(ap);
 563
 564        /* The pseudo configuration device on SIMG4726 attached to
 565         * ASUS P5W-DH Deluxe doesn't send signature FIS after
 566         * hardreset if no device is attached to the first downstream
 567         * port && the pseudo device locks up on SRST w/ PMP==0.  To
 568         * work around this, wait for !BSY only briefly.  If BSY isn't
 569         * cleared, perform CLO and proceed to IDENTIFY (achieved by
 570         * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
 571         *
 572         * Wait for two seconds.  Devices attached to downstream port
 573         * which can't process the following IDENTIFY after this will
 574         * have to be reset again.  For most cases, this should
 575         * suffice while making probing snappish enough.
 576         */
 577        if (online) {
 578                rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
 579                                          ahci_check_ready);
 580                if (rc)
 581                        ahci_kick_engine(ap);
 582        }
 583        return rc;
 584}
 585
 586#ifdef CONFIG_PM
 587static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 588{
 589        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 590        struct ahci_host_priv *hpriv = host->private_data;
 591        void __iomem *mmio = hpriv->mmio;
 592        u32 ctl;
 593
 594        if (mesg.event & PM_EVENT_SUSPEND &&
 595            hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
 596                dev_err(&pdev->dev,
 597                        "BIOS update required for suspend/resume\n");
 598                return -EIO;
 599        }
 600
 601        if (mesg.event & PM_EVENT_SLEEP) {
 602                /* AHCI spec rev1.1 section 8.3.3:
 603                 * Software must disable interrupts prior to requesting a
 604                 * transition of the HBA to D3 state.
 605                 */
 606                ctl = readl(mmio + HOST_CTL);
 607                ctl &= ~HOST_IRQ_EN;
 608                writel(ctl, mmio + HOST_CTL);
 609                readl(mmio + HOST_CTL); /* flush */
 610        }
 611
 612        return ata_pci_device_suspend(pdev, mesg);
 613}
 614
 615static int ahci_pci_device_resume(struct pci_dev *pdev)
 616{
 617        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 618        int rc;
 619
 620        rc = ata_pci_device_do_resume(pdev);
 621        if (rc)
 622                return rc;
 623
 624        if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
 625                rc = ahci_pci_reset_controller(host);
 626                if (rc)
 627                        return rc;
 628
 629                ahci_pci_init_controller(host);
 630        }
 631
 632        ata_host_resume(host);
 633
 634        return 0;
 635}
 636#endif
 637
 638static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 639{
 640        int rc;
 641
 642        /*
 643         * If the device fixup already set the dma_mask to some non-standard
 644         * value, don't extend it here. This happens on STA2X11, for example.
 645         */
 646        if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
 647                return 0;
 648
 649        if (using_dac &&
 650            !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
 651                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 652                if (rc) {
 653                        rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 654                        if (rc) {
 655                                dev_err(&pdev->dev,
 656                                        "64-bit DMA enable failed\n");
 657                                return rc;
 658                        }
 659                }
 660        } else {
 661                rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 662                if (rc) {
 663                        dev_err(&pdev->dev, "32-bit DMA enable failed\n");
 664                        return rc;
 665                }
 666                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 667                if (rc) {
 668                        dev_err(&pdev->dev,
 669                                "32-bit consistent DMA enable failed\n");
 670                        return rc;
 671                }
 672        }
 673        return 0;
 674}
 675
 676static void ahci_pci_print_info(struct ata_host *host)
 677{
 678        struct pci_dev *pdev = to_pci_dev(host->dev);
 679        u16 cc;
 680        const char *scc_s;
 681
 682        pci_read_config_word(pdev, 0x0a, &cc);
 683        if (cc == PCI_CLASS_STORAGE_IDE)
 684                scc_s = "IDE";
 685        else if (cc == PCI_CLASS_STORAGE_SATA)
 686                scc_s = "SATA";
 687        else if (cc == PCI_CLASS_STORAGE_RAID)
 688                scc_s = "RAID";
 689        else
 690                scc_s = "unknown";
 691
 692        ahci_print_info(host, scc_s);
 693}
 694
 695/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
 696 * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
 697 * support PMP and the 4726 either directly exports the device
 698 * attached to the first downstream port or acts as a hardware storage
 699 * controller and emulate a single ATA device (can be RAID 0/1 or some
 700 * other configuration).
 701 *
 702 * When there's no device attached to the first downstream port of the
 703 * 4726, "Config Disk" appears, which is a pseudo ATA device to
 704 * configure the 4726.  However, ATA emulation of the device is very
 705 * lame.  It doesn't send signature D2H Reg FIS after the initial
 706 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
 707 *
 708 * The following function works around the problem by always using
 709 * hardreset on the port and not depending on receiving signature FIS
 710 * afterward.  If signature FIS isn't received soon, ATA class is
 711 * assumed without follow-up softreset.
 712 */
 713static void ahci_p5wdh_workaround(struct ata_host *host)
 714{
 715        static struct dmi_system_id sysids[] = {
 716                {
 717                        .ident = "P5W DH Deluxe",
 718                        .matches = {
 719                                DMI_MATCH(DMI_SYS_VENDOR,
 720                                          "ASUSTEK COMPUTER INC"),
 721                                DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
 722                        },
 723                },
 724                { }
 725        };
 726        struct pci_dev *pdev = to_pci_dev(host->dev);
 727
 728        if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
 729            dmi_check_system(sysids)) {
 730                struct ata_port *ap = host->ports[1];
 731
 732                dev_info(&pdev->dev,
 733                         "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
 734
 735                ap->ops = &ahci_p5wdh_ops;
 736                ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
 737        }
 738}
 739
 740/* only some SB600 ahci controllers can do 64bit DMA */
 741static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
 742{
 743        static const struct dmi_system_id sysids[] = {
 744                /*
 745                 * The oldest version known to be broken is 0901 and
 746                 * working is 1501 which was released on 2007-10-26.
 747                 * Enable 64bit DMA on 1501 and anything newer.
 748                 *
 749                 * Please read bko#9412 for more info.
 750                 */
 751                {
 752                        .ident = "ASUS M2A-VM",
 753                        .matches = {
 754                                DMI_MATCH(DMI_BOARD_VENDOR,
 755                                          "ASUSTeK Computer INC."),
 756                                DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
 757                        },
 758                        .driver_data = "20071026",      /* yyyymmdd */
 759                },
 760                /*
 761                 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
 762                 * support 64bit DMA.
 763                 *
 764                 * BIOS versions earlier than 1.5 had the Manufacturer DMI
 765                 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
 766                 * This spelling mistake was fixed in BIOS version 1.5, so
 767                 * 1.5 and later have the Manufacturer as
 768                 * "MICRO-STAR INTERNATIONAL CO.,LTD".
 769                 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
 770                 *
 771                 * BIOS versions earlier than 1.9 had a Board Product Name
 772                 * DMI field of "MS-7376". This was changed to be
 773                 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
 774                 * match on DMI_BOARD_NAME of "MS-7376".
 775                 */
 776                {
 777                        .ident = "MSI K9A2 Platinum",
 778                        .matches = {
 779                                DMI_MATCH(DMI_BOARD_VENDOR,
 780                                          "MICRO-STAR INTER"),
 781                                DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
 782                        },
 783                },
 784                /*
 785                 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
 786                 * 64bit DMA.
 787                 *
 788                 * This board also had the typo mentioned above in the
 789                 * Manufacturer DMI field (fixed in BIOS version 1.5), so
 790                 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
 791                 */
 792                {
 793                        .ident = "MSI K9AGM2",
 794                        .matches = {
 795                                DMI_MATCH(DMI_BOARD_VENDOR,
 796                                          "MICRO-STAR INTER"),
 797                                DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
 798                        },
 799                },
 800                /*
 801                 * All BIOS versions for the Asus M3A support 64bit DMA.
 802                 * (all release versions from 0301 to 1206 were tested)
 803                 */
 804                {
 805                        .ident = "ASUS M3A",
 806                        .matches = {
 807                                DMI_MATCH(DMI_BOARD_VENDOR,
 808                                          "ASUSTeK Computer INC."),
 809                                DMI_MATCH(DMI_BOARD_NAME, "M3A"),
 810                        },
 811                },
 812                { }
 813        };
 814        const struct dmi_system_id *match;
 815        int year, month, date;
 816        char buf[9];
 817
 818        match = dmi_first_match(sysids);
 819        if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
 820            !match)
 821                return false;
 822
 823        if (!match->driver_data)
 824                goto enable_64bit;
 825
 826        dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
 827        snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
 828
 829        if (strcmp(buf, match->driver_data) >= 0)
 830                goto enable_64bit;
 831        else {
 832                dev_warn(&pdev->dev,
 833                         "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
 834                         match->ident);
 835                return false;
 836        }
 837
 838enable_64bit:
 839        dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
 840        return true;
 841}
 842
 843static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
 844{
 845        static const struct dmi_system_id broken_systems[] = {
 846                {
 847                        .ident = "HP Compaq nx6310",
 848                        .matches = {
 849                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 850                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
 851                        },
 852                        /* PCI slot number of the controller */
 853                        .driver_data = (void *)0x1FUL,
 854                },
 855                {
 856                        .ident = "HP Compaq 6720s",
 857                        .matches = {
 858                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 859                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
 860                        },
 861                        /* PCI slot number of the controller */
 862                        .driver_data = (void *)0x1FUL,
 863                },
 864
 865                { }     /* terminate list */
 866        };
 867        const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
 868
 869        if (dmi) {
 870                unsigned long slot = (unsigned long)dmi->driver_data;
 871                /* apply the quirk only to on-board controllers */
 872                return slot == PCI_SLOT(pdev->devfn);
 873        }
 874
 875        return false;
 876}
 877
 878static bool ahci_broken_suspend(struct pci_dev *pdev)
 879{
 880        static const struct dmi_system_id sysids[] = {
 881                /*
 882                 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
 883                 * to the harddisk doesn't become online after
 884                 * resuming from STR.  Warn and fail suspend.
 885                 *
 886                 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
 887                 *
 888                 * Use dates instead of versions to match as HP is
 889                 * apparently recycling both product and version
 890                 * strings.
 891                 *
 892                 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
 893                 */
 894                {
 895                        .ident = "dv4",
 896                        .matches = {
 897                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 898                                DMI_MATCH(DMI_PRODUCT_NAME,
 899                                          "HP Pavilion dv4 Notebook PC"),
 900                        },
 901                        .driver_data = "20090105",      /* F.30 */
 902                },
 903                {
 904                        .ident = "dv5",
 905                        .matches = {
 906                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 907                                DMI_MATCH(DMI_PRODUCT_NAME,
 908                                          "HP Pavilion dv5 Notebook PC"),
 909                        },
 910                        .driver_data = "20090506",      /* F.16 */
 911                },
 912                {
 913                        .ident = "dv6",
 914                        .matches = {
 915                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 916                                DMI_MATCH(DMI_PRODUCT_NAME,
 917                                          "HP Pavilion dv6 Notebook PC"),
 918                        },
 919                        .driver_data = "20090423",      /* F.21 */
 920                },
 921                {
 922                        .ident = "HDX18",
 923                        .matches = {
 924                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 925                                DMI_MATCH(DMI_PRODUCT_NAME,
 926                                          "HP HDX18 Notebook PC"),
 927                        },
 928                        .driver_data = "20090430",      /* F.23 */
 929                },
 930                /*
 931                 * Acer eMachines G725 has the same problem.  BIOS
 932                 * V1.03 is known to be broken.  V3.04 is known to
 933                 * work.  Between, there are V1.06, V2.06 and V3.03
 934                 * that we don't have much idea about.  For now,
 935                 * blacklist anything older than V3.04.
 936                 *
 937                 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
 938                 */
 939                {
 940                        .ident = "G725",
 941                        .matches = {
 942                                DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
 943                                DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
 944                        },
 945                        .driver_data = "20091216",      /* V3.04 */
 946                },
 947                { }     /* terminate list */
 948        };
 949        const struct dmi_system_id *dmi = dmi_first_match(sysids);
 950        int year, month, date;
 951        char buf[9];
 952
 953        if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
 954                return false;
 955
 956        dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
 957        snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
 958
 959        return strcmp(buf, dmi->driver_data) < 0;
 960}
 961
 962static bool ahci_broken_online(struct pci_dev *pdev)
 963{
 964#define ENCODE_BUSDEVFN(bus, slot, func)                        \
 965        (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
 966        static const struct dmi_system_id sysids[] = {
 967                /*
 968                 * There are several gigabyte boards which use
 969                 * SIMG5723s configured as hardware RAID.  Certain
 970                 * 5723 firmware revisions shipped there keep the link
 971                 * online but fail to answer properly to SRST or
 972                 * IDENTIFY when no device is attached downstream
 973                 * causing libata to retry quite a few times leading
 974                 * to excessive detection delay.
 975                 *
 976                 * As these firmwares respond to the second reset try
 977                 * with invalid device signature, considering unknown
 978                 * sig as offline works around the problem acceptably.
 979                 */
 980                {
 981                        .ident = "EP45-DQ6",
 982                        .matches = {
 983                                DMI_MATCH(DMI_BOARD_VENDOR,
 984                                          "Gigabyte Technology Co., Ltd."),
 985                                DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
 986                        },
 987                        .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
 988                },
 989                {
 990                        .ident = "EP45-DS5",
 991                        .matches = {
 992                                DMI_MATCH(DMI_BOARD_VENDOR,
 993                                          "Gigabyte Technology Co., Ltd."),
 994                                DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
 995                        },
 996                        .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
 997                },
 998                { }     /* terminate list */
 999        };
1000#undef ENCODE_BUSDEVFN

1001        const struct dmi_system_id *dmi = dmi_first_match(sysids);
1002        unsigned int val;
1003
1004        if (!dmi)
1005                return false;
1006
1007        val = (unsigned long)dmi->driver_data;
1008
1009        return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1010}
1011
1012#ifdef CONFIG_ATA_ACPI
1013static void ahci_gtf_filter_workaround(struct ata_host *host)
1014{
1015        static const struct dmi_system_id sysids[] = {
1016                /*
1017                 * Aspire 3810T issues a bunch of SATA enable commands
1018                 * via _GTF including an invalid one and one which is
1019                 * rejected by the device.  Among the successful ones
1020                 * is FPDMA non-zero offset enable which when enabled
1021                 * only on the drive side leads to NCQ command
1022                 * failures.  Filter it out.
1023                 */
1024                {
1025                        .ident = "Aspire 3810T",
1026                        .matches = {
1027                                DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1028                                DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1029                        },
1030                        .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1031                },
1032                { }
1033        };
1034        const struct dmi_system_id *dmi = dmi_first_match(sysids);
1035        unsigned int filter;
1036        int i;
1037
1038        if (!dmi)
1039                return;
1040
1041        filter = (unsigned long)dmi->driver_data;
1042        dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1043                 filter, dmi->ident);
1044
1045        for (i = 0; i < host->n_ports; i++) {
1046                struct ata_port *ap = host->ports[i];
1047                struct ata_link *link;
1048                struct ata_device *dev;
1049
1050                ata_for_each_link(link, ap, EDGE)
1051                        ata_for_each_dev(dev, link, ALL)
1052                                dev->gtf_filter |= filter;
1053        }
1054}
1055#else
1056static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1057{}
1058#endif
1059
1060static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1061{
1062        unsigned int board_id = ent->driver_data;
1063        struct ata_port_info pi = ahci_port_info[board_id];
1064        const struct ata_port_info *ppi[] = { &pi, NULL };
1065        struct device *dev = &pdev->dev;
1066        struct ahci_host_priv *hpriv;
1067        struct ata_host *host;
1068        int n_ports, i, rc;
1069        int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1070
1071        VPRINTK("ENTER\n");
1072
1073        WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1074
1075        ata_print_version_once(&pdev->dev, DRV_VERSION);
1076
1077        /* The AHCI driver can only drive the SATA ports, the PATA driver
1078           can drive them all so if both drivers are selected make sure
1079           AHCI stays out of the way */
1080        if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1081                return -ENODEV;
1082
1083        /*
1084         * For some reason, MCP89 on MacBook 7,1 doesn't work with
1085         * ahci, use ata_generic instead.
1086         */
1087        if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1088            pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1089            pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1090            pdev->subsystem_device == 0xcb89)
1091                return -ENODEV;
1092
1093        /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1094         * At the moment, we can only use the AHCI mode. Let the users know
1095         * that for SAS drives they're out of luck.
1096         */
1097        if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1098                dev_info(&pdev->dev,
1099                         "PDC42819 can only drive SATA devices with this driver\n");
1100
1101        /* The Connext uses non-standard BAR */
1102        if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1103                ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1104
1105        /* acquire resources */
1106        rc = pcim_enable_device(pdev);
1107        if (rc)
1108                return rc;
1109
1110        /* AHCI controllers often implement SFF compatible interface.
1111         * Grab all PCI BARs just in case.
1112         */
1113        rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1114        if (rc == -EBUSY)
1115                pcim_pin_device(pdev);
1116        if (rc)
1117                return rc;
1118
1119        if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1120            (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1121                u8 map;
1122
1123                /* ICH6s share the same PCI ID for both piix and ahci
1124                 * modes.  Enabling ahci mode while MAP indicates
1125                 * combined mode is a bad idea.  Yield to ata_piix.
1126                 */
1127                pci_read_config_byte(pdev, ICH_MAP, &map);
1128                if (map & 0x3) {
1129                        dev_info(&pdev->dev,
1130                                 "controller is in combined mode, can't enable AHCI mode\n");
1131                        return -ENODEV;
1132                }
1133        }
1134
1135        hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1136        if (!hpriv)
1137                return -ENOMEM;
1138        hpriv->flags |= (unsigned long)pi.private_data;
1139
1140        /* MCP65 revision A1 and A2 can't do MSI */
1141        if (board_id == board_ahci_mcp65 &&
1142            (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1143                hpriv->flags |= AHCI_HFLAG_NO_MSI;
1144
1145        /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1146        if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1147                hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1148
1149        /* only some SB600s can do 64bit DMA */
1150        if (ahci_sb600_enable_64bit(pdev))
1151                hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1152
1153        if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1154                pci_intx(pdev, 1);
1155
1156        hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1157
1158        /* save initial config */
1159        ahci_pci_save_initial_config(pdev, hpriv);
1160
1161        /* prepare host */
1162        if (hpriv->cap & HOST_CAP_NCQ) {
1163                pi.flags |= ATA_FLAG_NCQ;
1164                /*
1165                 * Auto-activate optimization is supposed to be
1166                 * supported on all AHCI controllers indicating NCQ
1167                 * capability, but it seems to be broken on some
1168                 * chipsets including NVIDIAs.
1169                 */
1170                if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1171                        pi.flags |= ATA_FLAG_FPDMA_AA;
1172        }
1173
1174        if (hpriv->cap & HOST_CAP_PMP)
1175                pi.flags |= ATA_FLAG_PMP;
1176
1177        ahci_set_em_messages(hpriv, &pi);
1178
1179        if (ahci_broken_system_poweroff(pdev)) {
1180                pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1181                dev_info(&pdev->dev,
1182                        "quirky BIOS, skipping spindown on poweroff\n");
1183        }
1184
1185        if (ahci_broken_suspend(pdev)) {
1186                hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1187                dev_warn(&pdev->dev,
1188                         "BIOS update required for suspend/resume\n");
1189        }
1190
1191        if (ahci_broken_online(pdev)) {
1192                hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1193                dev_info(&pdev->dev,
1194                         "online status unreliable, applying workaround\n");
1195        }
1196
1197        /* CAP.NP sometimes indicate the index of the last enabled
1198         * port, at other times, that of the last possible port, so
1199         * determining the maximum port number requires looking at
1200         * both CAP.NP and port_map.
1201         */
1202        n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1203
1204        host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1205        if (!host)
1206                return -ENOMEM;
1207        host->private_data = hpriv;
1208
1209        if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1210                host->flags |= ATA_HOST_PARALLEL_SCAN;
1211        else
1212                printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1213
1214        if (pi.flags & ATA_FLAG_EM)
1215                ahci_reset_em(host);
1216
1217        for (i = 0; i < host->n_ports; i++) {
1218                struct ata_port *ap = host->ports[i];
1219
1220                ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1221                ata_port_pbar_desc(ap, ahci_pci_bar,
1222                                   0x100 + ap->port_no * 0x80, "port");
1223
1224                /* set enclosure management message type */
1225                if (ap->flags & ATA_FLAG_EM)
1226                        ap->em_message_type = hpriv->em_msg_type;
1227
1228
1229                /* disabled/not-implemented port */
1230                if (!(hpriv->port_map & (1 << i)))
1231                        ap->ops = &ata_dummy_port_ops;
1232        }
1233
1234        /* apply workaround for ASUS P5W DH Deluxe mainboard */
1235        ahci_p5wdh_workaround(host);
1236
1237        /* apply gtf filter quirk */
1238        ahci_gtf_filter_workaround(host);
1239
1240        /* initialize adapter */
1241        rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1242        if (rc)
1243                return rc;
1244
1245        rc = ahci_pci_reset_controller(host);
1246        if (rc)
1247                return rc;
1248
1249        ahci_pci_init_controller(host);
1250        ahci_pci_print_info(host);
1251
1252        pci_set_master(pdev);
1253        return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1254                                 &ahci_sht);
1255}
1256
1257module_pci_driver(ahci_pci_driver);
1258
1259MODULE_AUTHOR("Jeff Garzik");
1260MODULE_DESCRIPTION("AHCI SATA low-level driver");
1261MODULE_LICENSE("GPL");
1262MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1263MODULE_VERSION(DRV_VERSION);
1264