linux/arch/arm/Kconfig
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   1config ARM
   2        bool
   3        default y
   4        select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5        select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6        select ARCH_HAVE_CUSTOM_GPIO_H
   7        select ARCH_WANT_IPC_PARSE_VERSION
   8        select CPU_PM if (SUSPEND || CPU_IDLE)
   9        select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
  10        select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  11        select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  12        select GENERIC_IRQ_PROBE
  13        select GENERIC_IRQ_SHOW
  14        select GENERIC_KERNEL_THREAD
  15        select GENERIC_KERNEL_EXECVE
  16        select GENERIC_PCI_IOMAP
  17        select GENERIC_SMP_IDLE_THREAD
  18        select GENERIC_STRNCPY_FROM_USER
  19        select GENERIC_STRNLEN_USER
  20        select HARDIRQS_SW_RESEND
  21        select HAVE_AOUT
  22        select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  23        select HAVE_ARCH_KGDB
  24        select HAVE_ARCH_TRACEHOOK
  25        select HAVE_BPF_JIT
  26        select HAVE_C_RECORDMCOUNT
  27        select HAVE_DEBUG_KMEMLEAK
  28        select HAVE_DMA_API_DEBUG
  29        select HAVE_DMA_ATTRS
  30        select HAVE_DMA_CONTIGUOUS if MMU
  31        select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  32        select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  33        select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  34        select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  35        select HAVE_GENERIC_DMA_COHERENT
  36        select HAVE_GENERIC_HARDIRQS
  37        select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  38        select HAVE_IDE if PCI || ISA || PCMCIA
  39        select HAVE_IRQ_WORK
  40        select HAVE_KERNEL_GZIP
  41        select HAVE_KERNEL_LZMA
  42        select HAVE_KERNEL_LZO
  43        select HAVE_KERNEL_XZ
  44        select HAVE_KPROBES if !XIP_KERNEL
  45        select HAVE_KRETPROBES if (HAVE_KPROBES)
  46        select HAVE_MEMBLOCK
  47        select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  48        select HAVE_PERF_EVENTS
  49        select HAVE_REGS_AND_STACK_ACCESS_API
  50        select HAVE_SYSCALL_TRACEPOINTS
  51        select HAVE_UID16
  52        select KTIME_SCALAR
  53        select PERF_USE_VMALLOC
  54        select RTC_LIB
  55        select SYS_SUPPORTS_APM_EMULATION
  56        select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  57        select MODULES_USE_ELF_REL
  58        help
  59          The ARM series is a line of low-power-consumption RISC chip designs
  60          licensed by ARM Ltd and targeted at embedded applications and
  61          handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  62          manufactured, but legacy ARM-based PC hardware remains popular in
  63          Europe.  There is an ARM Linux project with a web page at
  64          <http://www.arm.linux.org.uk/>.
  65
  66config ARM_HAS_SG_CHAIN
  67        bool
  68
  69config NEED_SG_DMA_LENGTH
  70        bool
  71
  72config ARM_DMA_USE_IOMMU
  73        bool
  74        select ARM_HAS_SG_CHAIN
  75        select NEED_SG_DMA_LENGTH
  76
  77config HAVE_PWM
  78        bool
  79
  80config MIGHT_HAVE_PCI
  81        bool
  82
  83config SYS_SUPPORTS_APM_EMULATION
  84        bool
  85
  86config GENERIC_GPIO
  87        bool
  88
  89config HAVE_TCM
  90        bool
  91        select GENERIC_ALLOCATOR
  92
  93config HAVE_PROC_CPU
  94        bool
  95
  96config NO_IOPORT
  97        bool
  98
  99config EISA
 100        bool
 101        ---help---
 102          The Extended Industry Standard Architecture (EISA) bus was
 103          developed as an open alternative to the IBM MicroChannel bus.
 104
 105          The EISA bus provided some of the features of the IBM MicroChannel
 106          bus while maintaining backward compatibility with cards made for
 107          the older ISA bus.  The EISA bus saw limited use between 1988 and
 108          1995 when it was made obsolete by the PCI bus.
 109
 110          Say Y here if you are building a kernel for an EISA-based machine.
 111
 112          Otherwise, say N.
 113
 114config SBUS
 115        bool
 116
 117config STACKTRACE_SUPPORT
 118        bool
 119        default y
 120
 121config HAVE_LATENCYTOP_SUPPORT
 122        bool
 123        depends on !SMP
 124        default y
 125
 126config LOCKDEP_SUPPORT
 127        bool
 128        default y
 129
 130config TRACE_IRQFLAGS_SUPPORT
 131        bool
 132        default y
 133
 134config RWSEM_GENERIC_SPINLOCK
 135        bool
 136        default y
 137
 138config RWSEM_XCHGADD_ALGORITHM
 139        bool
 140
 141config ARCH_HAS_ILOG2_U32
 142        bool
 143
 144config ARCH_HAS_ILOG2_U64
 145        bool
 146
 147config ARCH_HAS_CPUFREQ
 148        bool
 149        help
 150          Internal node to signify that the ARCH has CPUFREQ support
 151          and that the relevant menu configurations are displayed for
 152          it.
 153
 154config GENERIC_HWEIGHT
 155        bool
 156        default y
 157
 158config GENERIC_CALIBRATE_DELAY
 159        bool
 160        default y
 161
 162config ARCH_MAY_HAVE_PC_FDC
 163        bool
 164
 165config ZONE_DMA
 166        bool
 167
 168config NEED_DMA_MAP_STATE
 169       def_bool y
 170
 171config ARCH_HAS_DMA_SET_COHERENT_MASK
 172        bool
 173
 174config GENERIC_ISA_DMA
 175        bool
 176
 177config FIQ
 178        bool
 179
 180config NEED_RET_TO_USER
 181        bool
 182
 183config ARCH_MTD_XIP
 184        bool
 185
 186config VECTORS_BASE
 187        hex
 188        default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 189        default DRAM_BASE if REMAP_VECTORS_TO_RAM
 190        default 0x00000000
 191        help
 192          The base address of exception vectors.
 193
 194config ARM_PATCH_PHYS_VIRT
 195        bool "Patch physical to virtual translations at runtime" if EMBEDDED
 196        default y
 197        depends on !XIP_KERNEL && MMU
 198        depends on !ARCH_REALVIEW || !SPARSEMEM
 199        help
 200          Patch phys-to-virt and virt-to-phys translation functions at
 201          boot and module load time according to the position of the
 202          kernel in system memory.
 203
 204          This can only be used with non-XIP MMU kernels where the base
 205          of physical memory is at a 16MB boundary.
 206
 207          Only disable this option if you know that you do not require
 208          this feature (eg, building a kernel for a single machine) and
 209          you need to shrink the kernel to the minimal size.
 210
 211config NEED_MACH_GPIO_H
 212        bool
 213        help
 214          Select this when mach/gpio.h is required to provide special
 215          definitions for this platform. The need for mach/gpio.h should
 216          be avoided when possible.
 217
 218config NEED_MACH_IO_H
 219        bool
 220        help
 221          Select this when mach/io.h is required to provide special
 222          definitions for this platform.  The need for mach/io.h should
 223          be avoided when possible.
 224
 225config NEED_MACH_MEMORY_H
 226        bool
 227        help
 228          Select this when mach/memory.h is required to provide special
 229          definitions for this platform.  The need for mach/memory.h should
 230          be avoided when possible.
 231
 232config PHYS_OFFSET
 233        hex "Physical address of main memory" if MMU
 234        depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 235        default DRAM_BASE if !MMU
 236        help
 237          Please provide the physical address corresponding to the
 238          location of main memory in your system.
 239
 240config GENERIC_BUG
 241        def_bool y
 242        depends on BUG
 243
 244source "init/Kconfig"
 245
 246source "kernel/Kconfig.freezer"
 247
 248menu "System Type"
 249
 250config MMU
 251        bool "MMU-based Paged Memory Management Support"
 252        default y
 253        help
 254          Select if you want MMU-based virtualised addressing space
 255          support by paged memory management. If unsure, say 'Y'.
 256
 257#
 258# The "ARM system type" choice list is ordered alphabetically by option
 259# text.  Please add new entries in the option alphabetic order.
 260#
 261choice
 262        prompt "ARM system type"
 263        default ARCH_MULTIPLATFORM
 264
 265config ARCH_MULTIPLATFORM
 266        bool "Allow multiple platforms to be selected"
 267        depends on MMU
 268        select ARM_PATCH_PHYS_VIRT
 269        select AUTO_ZRELADDR
 270        select COMMON_CLK
 271        select MULTI_IRQ_HANDLER
 272        select SPARSE_IRQ
 273        select USE_OF
 274
 275config ARCH_INTEGRATOR
 276        bool "ARM Ltd. Integrator family"
 277        select ARCH_HAS_CPUFREQ
 278        select ARM_AMBA
 279        select COMMON_CLK
 280        select COMMON_CLK_VERSATILE
 281        select GENERIC_CLOCKEVENTS
 282        select HAVE_TCM
 283        select ICST
 284        select MULTI_IRQ_HANDLER
 285        select NEED_MACH_MEMORY_H
 286        select PLAT_VERSATILE
 287        select PLAT_VERSATILE_FPGA_IRQ
 288        select SPARSE_IRQ
 289        help
 290          Support for ARM's Integrator platform.
 291
 292config ARCH_REALVIEW
 293        bool "ARM Ltd. RealView family"
 294        select ARCH_WANT_OPTIONAL_GPIOLIB
 295        select ARM_AMBA
 296        select ARM_TIMER_SP804
 297        select COMMON_CLK
 298        select COMMON_CLK_VERSATILE
 299        select GENERIC_CLOCKEVENTS
 300        select GPIO_PL061 if GPIOLIB
 301        select ICST
 302        select NEED_MACH_MEMORY_H
 303        select PLAT_VERSATILE
 304        select PLAT_VERSATILE_CLCD
 305        help
 306          This enables support for ARM Ltd RealView boards.
 307
 308config ARCH_VERSATILE
 309        bool "ARM Ltd. Versatile family"
 310        select ARCH_WANT_OPTIONAL_GPIOLIB
 311        select ARM_AMBA
 312        select ARM_TIMER_SP804
 313        select ARM_VIC
 314        select CLKDEV_LOOKUP
 315        select GENERIC_CLOCKEVENTS
 316        select HAVE_MACH_CLKDEV
 317        select ICST
 318        select PLAT_VERSATILE
 319        select PLAT_VERSATILE_CLCD
 320        select PLAT_VERSATILE_CLOCK
 321        select PLAT_VERSATILE_FPGA_IRQ
 322        help
 323          This enables support for ARM Ltd Versatile board.
 324
 325config ARCH_AT91
 326        bool "Atmel AT91"
 327        select ARCH_REQUIRE_GPIOLIB
 328        select CLKDEV_LOOKUP
 329        select HAVE_CLK
 330        select IRQ_DOMAIN
 331        select NEED_MACH_GPIO_H
 332        select NEED_MACH_IO_H if PCCARD
 333        help
 334          This enables support for systems based on Atmel
 335          AT91RM9200 and AT91SAM9* processors.
 336
 337config ARCH_BCM2835
 338        bool "Broadcom BCM2835 family"
 339        select ARCH_WANT_OPTIONAL_GPIOLIB
 340        select ARM_AMBA
 341        select ARM_ERRATA_411920
 342        select ARM_TIMER_SP804
 343        select CLKDEV_LOOKUP
 344        select COMMON_CLK
 345        select CPU_V6
 346        select GENERIC_CLOCKEVENTS
 347        select MULTI_IRQ_HANDLER
 348        select SPARSE_IRQ
 349        select USE_OF
 350        help
 351          This enables support for the Broadcom BCM2835 SoC. This SoC is
 352          use in the Raspberry Pi, and Roku 2 devices.
 353
 354config ARCH_CNS3XXX
 355        bool "Cavium Networks CNS3XXX family"
 356        select ARM_GIC
 357        select CPU_V6K
 358        select GENERIC_CLOCKEVENTS
 359        select MIGHT_HAVE_CACHE_L2X0
 360        select MIGHT_HAVE_PCI
 361        select PCI_DOMAINS if PCI
 362        help
 363          Support for Cavium Networks CNS3XXX platform.
 364
 365config ARCH_CLPS711X
 366        bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 367        select ARCH_USES_GETTIMEOFFSET
 368        select CLKDEV_LOOKUP
 369        select COMMON_CLK
 370        select CPU_ARM720T
 371        select NEED_MACH_MEMORY_H
 372        help
 373          Support for Cirrus Logic 711x/721x/731x based boards.
 374
 375config ARCH_GEMINI
 376        bool "Cortina Systems Gemini"
 377        select ARCH_REQUIRE_GPIOLIB
 378        select ARCH_USES_GETTIMEOFFSET
 379        select CPU_FA526
 380        help
 381          Support for the Cortina Systems Gemini family SoCs
 382
 383config ARCH_SIRF
 384        bool "CSR SiRF"
 385        select ARCH_REQUIRE_GPIOLIB
 386        select COMMON_CLK
 387        select GENERIC_CLOCKEVENTS
 388        select GENERIC_IRQ_CHIP
 389        select MIGHT_HAVE_CACHE_L2X0
 390        select NO_IOPORT
 391        select PINCTRL
 392        select PINCTRL_SIRF
 393        select USE_OF
 394        help
 395          Support for CSR SiRFprimaII/Marco/Polo platforms
 396
 397config ARCH_EBSA110
 398        bool "EBSA-110"
 399        select ARCH_USES_GETTIMEOFFSET
 400        select CPU_SA110
 401        select ISA
 402        select NEED_MACH_IO_H
 403        select NEED_MACH_MEMORY_H
 404        select NO_IOPORT
 405        help
 406          This is an evaluation board for the StrongARM processor available
 407          from Digital. It has limited hardware on-board, including an
 408          Ethernet interface, two PCMCIA sockets, two serial ports and a
 409          parallel port.
 410
 411config ARCH_EP93XX
 412        bool "EP93xx-based"
 413        select ARCH_HAS_HOLES_MEMORYMODEL
 414        select ARCH_REQUIRE_GPIOLIB
 415        select ARCH_USES_GETTIMEOFFSET
 416        select ARM_AMBA
 417        select ARM_VIC
 418        select CLKDEV_LOOKUP
 419        select CPU_ARM920T
 420        select NEED_MACH_MEMORY_H
 421        help
 422          This enables support for the Cirrus EP93xx series of CPUs.
 423
 424config ARCH_FOOTBRIDGE
 425        bool "FootBridge"
 426        select CPU_SA110
 427        select FOOTBRIDGE
 428        select GENERIC_CLOCKEVENTS
 429        select HAVE_IDE
 430        select NEED_MACH_IO_H if !MMU
 431        select NEED_MACH_MEMORY_H
 432        help
 433          Support for systems based on the DC21285 companion chip
 434          ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 435
 436config ARCH_MXC
 437        bool "Freescale MXC/iMX-based"
 438        select ARCH_REQUIRE_GPIOLIB
 439        select CLKDEV_LOOKUP
 440        select CLKSRC_MMIO
 441        select GENERIC_CLOCKEVENTS
 442        select GENERIC_IRQ_CHIP
 443        select MULTI_IRQ_HANDLER
 444        select SPARSE_IRQ
 445        select USE_OF
 446        help
 447          Support for Freescale MXC/iMX-based family of processors
 448
 449config ARCH_MXS
 450        bool "Freescale MXS-based"
 451        select ARCH_REQUIRE_GPIOLIB
 452        select CLKDEV_LOOKUP
 453        select CLKSRC_MMIO
 454        select COMMON_CLK
 455        select GENERIC_CLOCKEVENTS
 456        select HAVE_CLK_PREPARE
 457        select MULTI_IRQ_HANDLER
 458        select PINCTRL
 459        select SPARSE_IRQ
 460        select USE_OF
 461        help
 462          Support for Freescale MXS-based family of processors
 463
 464config ARCH_NETX
 465        bool "Hilscher NetX based"
 466        select ARM_VIC
 467        select CLKSRC_MMIO
 468        select CPU_ARM926T
 469        select GENERIC_CLOCKEVENTS
 470        help
 471          This enables support for systems based on the Hilscher NetX Soc
 472
 473config ARCH_H720X
 474        bool "Hynix HMS720x-based"
 475        select ARCH_USES_GETTIMEOFFSET
 476        select CPU_ARM720T
 477        select ISA_DMA_API
 478        help
 479          This enables support for systems based on the Hynix HMS720x
 480
 481config ARCH_IOP13XX
 482        bool "IOP13xx-based"
 483        depends on MMU
 484        select ARCH_SUPPORTS_MSI
 485        select CPU_XSC3
 486        select NEED_MACH_MEMORY_H
 487        select NEED_RET_TO_USER
 488        select PCI
 489        select PLAT_IOP
 490        select VMSPLIT_1G
 491        help
 492          Support for Intel's IOP13XX (XScale) family of processors.
 493
 494config ARCH_IOP32X
 495        bool "IOP32x-based"
 496        depends on MMU
 497        select ARCH_REQUIRE_GPIOLIB
 498        select CPU_XSCALE
 499        select NEED_MACH_GPIO_H
 500        select NEED_RET_TO_USER
 501        select PCI
 502        select PLAT_IOP
 503        help
 504          Support for Intel's 80219 and IOP32X (XScale) family of
 505          processors.
 506
 507config ARCH_IOP33X
 508        bool "IOP33x-based"
 509        depends on MMU
 510        select ARCH_REQUIRE_GPIOLIB
 511        select CPU_XSCALE
 512        select NEED_MACH_GPIO_H
 513        select NEED_RET_TO_USER
 514        select PCI
 515        select PLAT_IOP
 516        help
 517          Support for Intel's IOP33X (XScale) family of processors.
 518
 519config ARCH_IXP4XX
 520        bool "IXP4xx-based"
 521        depends on MMU
 522        select ARCH_HAS_DMA_SET_COHERENT_MASK
 523        select ARCH_REQUIRE_GPIOLIB
 524        select CLKSRC_MMIO
 525        select CPU_XSCALE
 526        select DMABOUNCE if PCI
 527        select GENERIC_CLOCKEVENTS
 528        select MIGHT_HAVE_PCI
 529        select NEED_MACH_IO_H
 530        help
 531          Support for Intel's IXP4XX (XScale) family of processors.
 532
 533config ARCH_DOVE
 534        bool "Marvell Dove"
 535        select ARCH_REQUIRE_GPIOLIB
 536        select CPU_V7
 537        select GENERIC_CLOCKEVENTS
 538        select MIGHT_HAVE_PCI
 539        select PLAT_ORION_LEGACY
 540        select USB_ARCH_HAS_EHCI
 541        help
 542          Support for the Marvell Dove SoC 88AP510
 543
 544config ARCH_KIRKWOOD
 545        bool "Marvell Kirkwood"
 546        select ARCH_REQUIRE_GPIOLIB
 547        select CPU_FEROCEON
 548        select GENERIC_CLOCKEVENTS
 549        select PCI
 550        select PCI_QUIRKS
 551        select PLAT_ORION_LEGACY
 552        help
 553          Support for the following Marvell Kirkwood series SoCs:
 554          88F6180, 88F6192 and 88F6281.
 555
 556config ARCH_MV78XX0
 557        bool "Marvell MV78xx0"
 558        select ARCH_REQUIRE_GPIOLIB
 559        select CPU_FEROCEON
 560        select GENERIC_CLOCKEVENTS
 561        select PCI
 562        select PLAT_ORION_LEGACY
 563        help
 564          Support for the following Marvell MV78xx0 series SoCs:
 565          MV781x0, MV782x0.
 566
 567config ARCH_ORION5X
 568        bool "Marvell Orion"
 569        depends on MMU
 570        select ARCH_REQUIRE_GPIOLIB
 571        select CPU_FEROCEON
 572        select GENERIC_CLOCKEVENTS
 573        select PCI
 574        select PLAT_ORION_LEGACY
 575        help
 576          Support for the following Marvell Orion 5x series SoCs:
 577          Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 578          Orion-2 (5281), Orion-1-90 (6183).
 579
 580config ARCH_MMP
 581        bool "Marvell PXA168/910/MMP2"
 582        depends on MMU
 583        select ARCH_REQUIRE_GPIOLIB
 584        select CLKDEV_LOOKUP
 585        select GENERIC_ALLOCATOR
 586        select GENERIC_CLOCKEVENTS
 587        select GPIO_PXA
 588        select IRQ_DOMAIN
 589        select NEED_MACH_GPIO_H
 590        select PLAT_PXA
 591        select SPARSE_IRQ
 592        help
 593          Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 594
 595config ARCH_KS8695
 596        bool "Micrel/Kendin KS8695"
 597        select ARCH_REQUIRE_GPIOLIB
 598        select CLKSRC_MMIO
 599        select CPU_ARM922T
 600        select GENERIC_CLOCKEVENTS
 601        select NEED_MACH_MEMORY_H
 602        help
 603          Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 604          System-on-Chip devices.
 605
 606config ARCH_W90X900
 607        bool "Nuvoton W90X900 CPU"
 608        select ARCH_REQUIRE_GPIOLIB
 609        select CLKDEV_LOOKUP
 610        select CLKSRC_MMIO
 611        select CPU_ARM926T
 612        select GENERIC_CLOCKEVENTS
 613        help
 614          Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 615          At present, the w90x900 has been renamed nuc900, regarding
 616          the ARM series product line, you can login the following
 617          link address to know more.
 618
 619          <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 620                ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 621
 622config ARCH_LPC32XX
 623        bool "NXP LPC32XX"
 624        select ARCH_REQUIRE_GPIOLIB
 625        select ARM_AMBA
 626        select CLKDEV_LOOKUP
 627        select CLKSRC_MMIO
 628        select CPU_ARM926T
 629        select GENERIC_CLOCKEVENTS
 630        select HAVE_IDE
 631        select HAVE_PWM
 632        select USB_ARCH_HAS_OHCI
 633        select USE_OF
 634        help
 635          Support for the NXP LPC32XX family of processors
 636
 637config ARCH_TEGRA
 638        bool "NVIDIA Tegra"
 639        select ARCH_HAS_CPUFREQ
 640        select CLKDEV_LOOKUP
 641        select CLKSRC_MMIO
 642        select COMMON_CLK
 643        select GENERIC_CLOCKEVENTS
 644        select GENERIC_GPIO
 645        select HAVE_CLK
 646        select HAVE_SMP
 647        select MIGHT_HAVE_CACHE_L2X0
 648        select USE_OF
 649        help
 650          This enables support for NVIDIA Tegra based systems (Tegra APX,
 651          Tegra 6xx and Tegra 2 series).
 652
 653config ARCH_PXA
 654        bool "PXA2xx/PXA3xx-based"
 655        depends on MMU
 656        select ARCH_HAS_CPUFREQ
 657        select ARCH_MTD_XIP
 658        select ARCH_REQUIRE_GPIOLIB
 659        select ARM_CPU_SUSPEND if PM
 660        select AUTO_ZRELADDR
 661        select CLKDEV_LOOKUP
 662        select CLKSRC_MMIO
 663        select GENERIC_CLOCKEVENTS
 664        select GPIO_PXA
 665        select HAVE_IDE
 666        select MULTI_IRQ_HANDLER
 667        select NEED_MACH_GPIO_H
 668        select PLAT_PXA
 669        select SPARSE_IRQ
 670        help
 671          Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 672
 673config ARCH_MSM
 674        bool "Qualcomm MSM"
 675        select ARCH_REQUIRE_GPIOLIB
 676        select CLKDEV_LOOKUP
 677        select GENERIC_CLOCKEVENTS
 678        select HAVE_CLK
 679        help
 680          Support for Qualcomm MSM/QSD based systems.  This runs on the
 681          apps processor of the MSM/QSD and depends on a shared memory
 682          interface to the modem processor which runs the baseband
 683          stack and controls some vital subsystems
 684          (clock and power control, etc).
 685
 686config ARCH_SHMOBILE
 687        bool "Renesas SH-Mobile / R-Mobile"
 688        select CLKDEV_LOOKUP
 689        select GENERIC_CLOCKEVENTS
 690        select HAVE_CLK
 691        select HAVE_MACH_CLKDEV
 692        select HAVE_SMP
 693        select MIGHT_HAVE_CACHE_L2X0
 694        select MULTI_IRQ_HANDLER
 695        select NEED_MACH_MEMORY_H
 696        select NO_IOPORT
 697        select PM_GENERIC_DOMAINS if PM
 698        select SPARSE_IRQ
 699        help
 700          Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 701
 702config ARCH_RPC
 703        bool "RiscPC"
 704        select ARCH_ACORN
 705        select ARCH_MAY_HAVE_PC_FDC
 706        select ARCH_SPARSEMEM_ENABLE
 707        select ARCH_USES_GETTIMEOFFSET
 708        select FIQ
 709        select HAVE_IDE
 710        select HAVE_PATA_PLATFORM
 711        select ISA_DMA_API
 712        select NEED_MACH_IO_H
 713        select NEED_MACH_MEMORY_H
 714        select NO_IOPORT
 715        help
 716          On the Acorn Risc-PC, Linux can support the internal IDE disk and
 717          CD-ROM interface, serial and parallel port, and the floppy drive.
 718
 719config ARCH_SA1100
 720        bool "SA1100-based"
 721        select ARCH_HAS_CPUFREQ
 722        select ARCH_MTD_XIP
 723        select ARCH_REQUIRE_GPIOLIB
 724        select ARCH_SPARSEMEM_ENABLE
 725        select CLKDEV_LOOKUP
 726        select CLKSRC_MMIO
 727        select CPU_FREQ
 728        select CPU_SA1100
 729        select GENERIC_CLOCKEVENTS
 730        select HAVE_IDE
 731        select ISA
 732        select NEED_MACH_GPIO_H
 733        select NEED_MACH_MEMORY_H
 734        select SPARSE_IRQ
 735        help
 736          Support for StrongARM 11x0 based boards.
 737
 738config ARCH_S3C24XX
 739        bool "Samsung S3C24XX SoCs"
 740        select ARCH_HAS_CPUFREQ
 741        select ARCH_USES_GETTIMEOFFSET
 742        select CLKDEV_LOOKUP
 743        select GENERIC_GPIO
 744        select HAVE_CLK
 745        select HAVE_S3C2410_I2C if I2C
 746        select HAVE_S3C2410_WATCHDOG if WATCHDOG
 747        select HAVE_S3C_RTC if RTC_CLASS
 748        select NEED_MACH_GPIO_H
 749        select NEED_MACH_IO_H
 750        help
 751          Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 752          and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 753          (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 754          Samsung SMDK2410 development board (and derivatives).
 755
 756config ARCH_S3C64XX
 757        bool "Samsung S3C64XX"
 758        select ARCH_HAS_CPUFREQ
 759        select ARCH_REQUIRE_GPIOLIB
 760        select ARCH_USES_GETTIMEOFFSET
 761        select ARM_VIC
 762        select CLKDEV_LOOKUP
 763        select CPU_V6
 764        select HAVE_CLK
 765        select HAVE_S3C2410_I2C if I2C
 766        select HAVE_S3C2410_WATCHDOG if WATCHDOG
 767        select HAVE_TCM
 768        select NEED_MACH_GPIO_H
 769        select NO_IOPORT
 770        select PLAT_SAMSUNG
 771        select S3C_DEV_NAND
 772        select S3C_GPIO_TRACK
 773        select SAMSUNG_CLKSRC
 774        select SAMSUNG_GPIOLIB_4BIT
 775        select SAMSUNG_IRQ_VIC_TIMER
 776        select USB_ARCH_HAS_OHCI
 777        help
 778          Samsung S3C64XX series based systems
 779
 780config ARCH_S5P64X0
 781        bool "Samsung S5P6440 S5P6450"
 782        select CLKDEV_LOOKUP
 783        select CLKSRC_MMIO
 784        select CPU_V6
 785        select GENERIC_CLOCKEVENTS
 786        select GENERIC_GPIO
 787        select HAVE_CLK
 788        select HAVE_S3C2410_I2C if I2C
 789        select HAVE_S3C2410_WATCHDOG if WATCHDOG
 790        select HAVE_S3C_RTC if RTC_CLASS
 791        select NEED_MACH_GPIO_H
 792        help
 793          Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 794          SMDK6450.
 795
 796config ARCH_S5PC100
 797        bool "Samsung S5PC100"
 798        select ARCH_USES_GETTIMEOFFSET
 799        select CLKDEV_LOOKUP
 800        select CPU_V7
 801        select GENERIC_GPIO
 802        select HAVE_CLK
 803        select HAVE_S3C2410_I2C if I2C
 804        select HAVE_S3C2410_WATCHDOG if WATCHDOG
 805        select HAVE_S3C_RTC if RTC_CLASS
 806        select NEED_MACH_GPIO_H
 807        help
 808          Samsung S5PC100 series based systems
 809
 810config ARCH_S5PV210
 811        bool "Samsung S5PV210/S5PC110"
 812        select ARCH_HAS_CPUFREQ
 813        select ARCH_HAS_HOLES_MEMORYMODEL
 814        select ARCH_SPARSEMEM_ENABLE
 815        select CLKDEV_LOOKUP
 816        select CLKSRC_MMIO
 817        select CPU_V7
 818        select GENERIC_CLOCKEVENTS
 819        select GENERIC_GPIO
 820        select HAVE_CLK
 821        select HAVE_S3C2410_I2C if I2C
 822        select HAVE_S3C2410_WATCHDOG if WATCHDOG
 823        select HAVE_S3C_RTC if RTC_CLASS
 824        select NEED_MACH_GPIO_H
 825        select NEED_MACH_MEMORY_H
 826        help
 827          Samsung S5PV210/S5PC110 series based systems
 828
 829config ARCH_EXYNOS
 830        bool "Samsung EXYNOS"
 831        select ARCH_HAS_CPUFREQ
 832        select ARCH_HAS_HOLES_MEMORYMODEL
 833        select ARCH_SPARSEMEM_ENABLE
 834        select CLKDEV_LOOKUP
 835        select CPU_V7
 836        select GENERIC_CLOCKEVENTS
 837        select GENERIC_GPIO
 838        select HAVE_CLK
 839        select HAVE_S3C2410_I2C if I2C
 840        select HAVE_S3C2410_WATCHDOG if WATCHDOG
 841        select HAVE_S3C_RTC if RTC_CLASS
 842        select NEED_MACH_GPIO_H
 843        select NEED_MACH_MEMORY_H
 844        help
 845          Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 846
 847config ARCH_SHARK
 848        bool "Shark"
 849        select ARCH_USES_GETTIMEOFFSET
 850        select CPU_SA110
 851        select ISA
 852        select ISA_DMA
 853        select NEED_MACH_MEMORY_H
 854        select PCI
 855        select ZONE_DMA
 856        help
 857          Support for the StrongARM based Digital DNARD machine, also known
 858          as "Shark" (<http://www.shark-linux.de/shark.html>).
 859
 860config ARCH_U300
 861        bool "ST-Ericsson U300 Series"
 862        depends on MMU
 863        select ARCH_REQUIRE_GPIOLIB
 864        select ARM_AMBA
 865        select ARM_PATCH_PHYS_VIRT
 866        select ARM_VIC
 867        select CLKDEV_LOOKUP
 868        select CLKSRC_MMIO
 869        select COMMON_CLK
 870        select CPU_ARM926T
 871        select GENERIC_CLOCKEVENTS
 872        select GENERIC_GPIO
 873        select HAVE_TCM
 874        select SPARSE_IRQ
 875        help
 876          Support for ST-Ericsson U300 series mobile platforms.
 877
 878config ARCH_U8500
 879        bool "ST-Ericsson U8500 Series"
 880        depends on MMU
 881        select ARCH_HAS_CPUFREQ
 882        select ARCH_REQUIRE_GPIOLIB
 883        select ARM_AMBA
 884        select CLKDEV_LOOKUP
 885        select CPU_V7
 886        select GENERIC_CLOCKEVENTS
 887        select HAVE_SMP
 888        select MIGHT_HAVE_CACHE_L2X0
 889        help
 890          Support for ST-Ericsson's Ux500 architecture
 891
 892config ARCH_NOMADIK
 893        bool "STMicroelectronics Nomadik"
 894        select ARCH_REQUIRE_GPIOLIB
 895        select ARM_AMBA
 896        select ARM_VIC
 897        select COMMON_CLK
 898        select CPU_ARM926T
 899        select GENERIC_CLOCKEVENTS
 900        select MIGHT_HAVE_CACHE_L2X0
 901        select PINCTRL
 902        select PINCTRL_STN8815
 903        help
 904          Support for the Nomadik platform by ST-Ericsson
 905
 906config PLAT_SPEAR
 907        bool "ST SPEAr"
 908        select ARCH_REQUIRE_GPIOLIB
 909        select ARM_AMBA
 910        select CLKDEV_LOOKUP
 911        select CLKSRC_MMIO
 912        select COMMON_CLK
 913        select GENERIC_CLOCKEVENTS
 914        select HAVE_CLK
 915        help
 916          Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 917
 918config ARCH_DAVINCI
 919        bool "TI DaVinci"
 920        select ARCH_HAS_HOLES_MEMORYMODEL
 921        select ARCH_REQUIRE_GPIOLIB
 922        select CLKDEV_LOOKUP
 923        select GENERIC_ALLOCATOR
 924        select GENERIC_CLOCKEVENTS
 925        select GENERIC_IRQ_CHIP
 926        select HAVE_IDE
 927        select NEED_MACH_GPIO_H
 928        select ZONE_DMA
 929        help
 930          Support for TI's DaVinci platform.
 931
 932config ARCH_OMAP
 933        bool "TI OMAP"
 934        depends on MMU
 935        select ARCH_HAS_CPUFREQ
 936        select ARCH_HAS_HOLES_MEMORYMODEL
 937        select ARCH_REQUIRE_GPIOLIB
 938        select CLKSRC_MMIO
 939        select GENERIC_CLOCKEVENTS
 940        select HAVE_CLK
 941        select NEED_MACH_GPIO_H
 942        help
 943          Support for TI's OMAP platform (OMAP1/2/3/4).
 944
 945config ARCH_VT8500
 946        bool "VIA/WonderMedia 85xx"
 947        select ARCH_HAS_CPUFREQ
 948        select ARCH_REQUIRE_GPIOLIB
 949        select CLKDEV_LOOKUP
 950        select COMMON_CLK
 951        select CPU_ARM926T
 952        select GENERIC_CLOCKEVENTS
 953        select GENERIC_GPIO
 954        select HAVE_CLK
 955        select USE_OF
 956        help
 957          Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 958
 959config ARCH_ZYNQ
 960        bool "Xilinx Zynq ARM Cortex A9 Platform"
 961        select ARM_AMBA
 962        select ARM_GIC
 963        select CLKDEV_LOOKUP
 964        select CPU_V7
 965        select GENERIC_CLOCKEVENTS
 966        select ICST
 967        select MIGHT_HAVE_CACHE_L2X0
 968        select USE_OF
 969        help
 970          Support for Xilinx Zynq ARM Cortex A9 Platform
 971endchoice
 972
 973menu "Multiple platform selection"
 974        depends on ARCH_MULTIPLATFORM
 975
 976comment "CPU Core family selection"
 977
 978config ARCH_MULTI_V4
 979        bool "ARMv4 based platforms (FA526, StrongARM)"
 980        depends on !ARCH_MULTI_V6_V7
 981        select ARCH_MULTI_V4_V5
 982
 983config ARCH_MULTI_V4T
 984        bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 985        depends on !ARCH_MULTI_V6_V7
 986        select ARCH_MULTI_V4_V5
 987
 988config ARCH_MULTI_V5
 989        bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 990        depends on !ARCH_MULTI_V6_V7
 991        select ARCH_MULTI_V4_V5
 992
 993config ARCH_MULTI_V4_V5
 994        bool
 995
 996config ARCH_MULTI_V6
 997        bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
 998        select ARCH_MULTI_V6_V7
 999        select CPU_V6
1000
1001config ARCH_MULTI_V7
1002        bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1003        default y
1004        select ARCH_MULTI_V6_V7
1005        select ARCH_VEXPRESS
1006        select CPU_V7
1007
1008config ARCH_MULTI_V6_V7
1009        bool
1010
1011config ARCH_MULTI_CPU_AUTO
1012        def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1013        select ARCH_MULTI_V5
1014
1015endmenu
1016
1017#
1018# This is sorted alphabetically by mach-* pathname.  However, plat-*
1019# Kconfigs may be included either alphabetically (according to the
1020# plat- suffix) or along side the corresponding mach-* source.
1021#
1022source "arch/arm/mach-mvebu/Kconfig"
1023
1024source "arch/arm/mach-at91/Kconfig"
1025
1026source "arch/arm/mach-clps711x/Kconfig"
1027
1028source "arch/arm/mach-cns3xxx/Kconfig"
1029
1030source "arch/arm/mach-davinci/Kconfig"
1031
1032source "arch/arm/mach-dove/Kconfig"
1033
1034source "arch/arm/mach-ep93xx/Kconfig"
1035
1036source "arch/arm/mach-footbridge/Kconfig"
1037
1038source "arch/arm/mach-gemini/Kconfig"
1039
1040source "arch/arm/mach-h720x/Kconfig"
1041
1042source "arch/arm/mach-highbank/Kconfig"
1043
1044source "arch/arm/mach-integrator/Kconfig"
1045
1046source "arch/arm/mach-iop32x/Kconfig"
1047
1048source "arch/arm/mach-iop33x/Kconfig"
1049
1050source "arch/arm/mach-iop13xx/Kconfig"
1051
1052source "arch/arm/mach-ixp4xx/Kconfig"
1053
1054source "arch/arm/mach-kirkwood/Kconfig"
1055
1056source "arch/arm/mach-ks8695/Kconfig"
1057
1058source "arch/arm/mach-msm/Kconfig"
1059
1060source "arch/arm/mach-mv78xx0/Kconfig"
1061
1062source "arch/arm/plat-mxc/Kconfig"
1063
1064source "arch/arm/mach-mxs/Kconfig"
1065
1066source "arch/arm/mach-netx/Kconfig"
1067
1068source "arch/arm/mach-nomadik/Kconfig"
1069source "arch/arm/plat-nomadik/Kconfig"
1070
1071source "arch/arm/plat-omap/Kconfig"
1072
1073source "arch/arm/mach-omap1/Kconfig"
1074
1075source "arch/arm/mach-omap2/Kconfig"
1076
1077source "arch/arm/mach-orion5x/Kconfig"
1078
1079source "arch/arm/mach-picoxcell/Kconfig"
1080
1081source "arch/arm/mach-pxa/Kconfig"
1082source "arch/arm/plat-pxa/Kconfig"
1083
1084source "arch/arm/mach-mmp/Kconfig"
1085
1086source "arch/arm/mach-realview/Kconfig"
1087
1088source "arch/arm/mach-sa1100/Kconfig"
1089
1090source "arch/arm/plat-samsung/Kconfig"
1091source "arch/arm/plat-s3c24xx/Kconfig"
1092
1093source "arch/arm/mach-socfpga/Kconfig"
1094
1095source "arch/arm/plat-spear/Kconfig"
1096
1097source "arch/arm/mach-s3c24xx/Kconfig"
1098if ARCH_S3C24XX
1099source "arch/arm/mach-s3c2412/Kconfig"
1100source "arch/arm/mach-s3c2440/Kconfig"
1101endif
1102
1103if ARCH_S3C64XX
1104source "arch/arm/mach-s3c64xx/Kconfig"
1105endif
1106
1107source "arch/arm/mach-s5p64x0/Kconfig"
1108
1109source "arch/arm/mach-s5pc100/Kconfig"
1110
1111source "arch/arm/mach-s5pv210/Kconfig"
1112
1113source "arch/arm/mach-exynos/Kconfig"
1114
1115source "arch/arm/mach-shmobile/Kconfig"
1116
1117source "arch/arm/mach-prima2/Kconfig"
1118
1119source "arch/arm/mach-tegra/Kconfig"
1120
1121source "arch/arm/mach-u300/Kconfig"
1122
1123source "arch/arm/mach-ux500/Kconfig"
1124
1125source "arch/arm/mach-versatile/Kconfig"
1126
1127source "arch/arm/mach-vexpress/Kconfig"
1128source "arch/arm/plat-versatile/Kconfig"
1129
1130source "arch/arm/mach-w90x900/Kconfig"
1131
1132# Definitions to make life easier
1133config ARCH_ACORN
1134        bool
1135
1136config PLAT_IOP
1137        bool
1138        select GENERIC_CLOCKEVENTS
1139
1140config PLAT_ORION
1141        bool
1142        select CLKSRC_MMIO
1143        select COMMON_CLK
1144        select GENERIC_IRQ_CHIP
1145        select IRQ_DOMAIN
1146
1147config PLAT_ORION_LEGACY
1148        bool
1149        select PLAT_ORION
1150
1151config PLAT_PXA
1152        bool
1153
1154config PLAT_VERSATILE
1155        bool
1156
1157config ARM_TIMER_SP804
1158        bool
1159        select CLKSRC_MMIO
1160        select HAVE_SCHED_CLOCK
1161
1162source arch/arm/mm/Kconfig
1163
1164config ARM_NR_BANKS
1165        int
1166        default 16 if ARCH_EP93XX
1167        default 8
1168
1169config IWMMXT
1170        bool "Enable iWMMXt support"
1171        depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1172        default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1173        help
1174          Enable support for iWMMXt context switching at run time if
1175          running on a CPU that supports it.
1176
1177config XSCALE_PMU
1178        bool
1179        depends on CPU_XSCALE
1180        default y
1181
1182config MULTI_IRQ_HANDLER
1183        bool
1184        help
1185          Allow each machine to specify it's own IRQ handler at run time.
1186
1187if !MMU
1188source "arch/arm/Kconfig-nommu"
1189endif
1190
1191config ARM_ERRATA_326103
1192        bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1193        depends on CPU_V6
1194        help
1195          Executing a SWP instruction to read-only memory does not set bit 11
1196          of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1197          treat the access as a read, preventing a COW from occurring and
1198          causing the faulting task to livelock.
1199
1200config ARM_ERRATA_411920
1201        bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1202        depends on CPU_V6 || CPU_V6K
1203        help
1204          Invalidation of the Instruction Cache operation can
1205          fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1206          It does not affect the MPCore. This option enables the ARM Ltd.
1207          recommended workaround.
1208
1209config ARM_ERRATA_430973
1210        bool "ARM errata: Stale prediction on replaced interworking branch"
1211        depends on CPU_V7
1212        help
1213          This option enables the workaround for the 430973 Cortex-A8
1214          (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1215          interworking branch is replaced with another code sequence at the
1216          same virtual address, whether due to self-modifying code or virtual
1217          to physical address re-mapping, Cortex-A8 does not recover from the
1218          stale interworking branch prediction. This results in Cortex-A8
1219          executing the new code sequence in the incorrect ARM or Thumb state.
1220          The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1221          and also flushes the branch target cache at every context switch.
1222          Note that setting specific bits in the ACTLR register may not be
1223          available in non-secure mode.
1224
1225config ARM_ERRATA_458693
1226        bool "ARM errata: Processor deadlock when a false hazard is created"
1227        depends on CPU_V7
1228        help
1229          This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1230          erratum. For very specific sequences of memory operations, it is
1231          possible for a hazard condition intended for a cache line to instead
1232          be incorrectly associated with a different cache line. This false
1233          hazard might then cause a processor deadlock. The workaround enables
1234          the L1 caching of the NEON accesses and disables the PLD instruction
1235          in the ACTLR register. Note that setting specific bits in the ACTLR
1236          register may not be available in non-secure mode.
1237
1238config ARM_ERRATA_460075
1239        bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1240        depends on CPU_V7
1241        help
1242          This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1243          erratum. Any asynchronous access to the L2 cache may encounter a
1244          situation in which recent store transactions to the L2 cache are lost
1245          and overwritten with stale memory contents from external memory. The
1246          workaround disables the write-allocate mode for the L2 cache via the
1247          ACTLR register. Note that setting specific bits in the ACTLR register
1248          may not be available in non-secure mode.
1249
1250config ARM_ERRATA_742230
1251        bool "ARM errata: DMB operation may be faulty"
1252        depends on CPU_V7 && SMP
1253        help
1254          This option enables the workaround for the 742230 Cortex-A9
1255          (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1256          between two write operations may not ensure the correct visibility
1257          ordering of the two writes. This workaround sets a specific bit in
1258          the diagnostic register of the Cortex-A9 which causes the DMB
1259          instruction to behave as a DSB, ensuring the correct behaviour of
1260          the two writes.
1261
1262config ARM_ERRATA_742231
1263        bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1264        depends on CPU_V7 && SMP
1265        help
1266          This option enables the workaround for the 742231 Cortex-A9
1267          (r2p0..r2p2) erratum. Under certain conditions, specific to the
1268          Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1269          accessing some data located in the same cache line, may get corrupted
1270          data due to bad handling of the address hazard when the line gets
1271          replaced from one of the CPUs at the same time as another CPU is
1272          accessing it. This workaround sets specific bits in the diagnostic
1273          register of the Cortex-A9 which reduces the linefill issuing
1274          capabilities of the processor.
1275
1276config PL310_ERRATA_588369
1277        bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1278        depends on CACHE_L2X0
1279        help
1280           The PL310 L2 cache controller implements three types of Clean &
1281           Invalidate maintenance operations: by Physical Address
1282           (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1283           They are architecturally defined to behave as the execution of a
1284           clean operation followed immediately by an invalidate operation,
1285           both performing to the same memory location. This functionality
1286           is not correctly implemented in PL310 as clean lines are not
1287           invalidated as a result of these operations.
1288
1289config ARM_ERRATA_720789
1290        bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1291        depends on CPU_V7
1292        help
1293          This option enables the workaround for the 720789 Cortex-A9 (prior to
1294          r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1295          broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1296          As a consequence of this erratum, some TLB entries which should be
1297          invalidated are not, resulting in an incoherency in the system page
1298          tables. The workaround changes the TLB flushing routines to invalidate
1299          entries regardless of the ASID.
1300
1301config PL310_ERRATA_727915
1302        bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1303        depends on CACHE_L2X0
1304        help
1305          PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1306          operation (offset 0x7FC). This operation runs in background so that
1307          PL310 can handle normal accesses while it is in progress. Under very
1308          rare circumstances, due to this erratum, write data can be lost when
1309          PL310 treats a cacheable write transaction during a Clean &
1310          Invalidate by Way operation.
1311
1312config ARM_ERRATA_743622
1313        bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1314        depends on CPU_V7
1315        help
1316          This option enables the workaround for the 743622 Cortex-A9
1317          (r2p*) erratum. Under very rare conditions, a faulty
1318          optimisation in the Cortex-A9 Store Buffer may lead to data
1319          corruption. This workaround sets a specific bit in the diagnostic
1320          register of the Cortex-A9 which disables the Store Buffer
1321          optimisation, preventing the defect from occurring. This has no
1322          visible impact on the overall performance or power consumption of the
1323          processor.
1324
1325config ARM_ERRATA_751472
1326        bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1327        depends on CPU_V7
1328        help
1329          This option enables the workaround for the 751472 Cortex-A9 (prior
1330          to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1331          completion of a following broadcasted operation if the second
1332          operation is received by a CPU before the ICIALLUIS has completed,
1333          potentially leading to corrupted entries in the cache or TLB.
1334
1335config PL310_ERRATA_753970
1336        bool "PL310 errata: cache sync operation may be faulty"
1337        depends on CACHE_PL310
1338        help
1339          This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1340
1341          Under some condition the effect of cache sync operation on
1342          the store buffer still remains when the operation completes.
1343          This means that the store buffer is always asked to drain and
1344          this prevents it from merging any further writes. The workaround
1345          is to replace the normal offset of cache sync operation (0x730)
1346          by another offset targeting an unmapped PL310 register 0x740.
1347          This has the same effect as the cache sync operation: store buffer
1348          drain and waiting for all buffers empty.
1349
1350config ARM_ERRATA_754322
1351        bool "ARM errata: possible faulty MMU translations following an ASID switch"
1352        depends on CPU_V7
1353        help
1354          This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1355          r3p*) erratum. A speculative memory access may cause a page table walk
1356          which starts prior to an ASID switch but completes afterwards. This
1357          can populate the micro-TLB with a stale entry which may be hit with
1358          the new ASID. This workaround places two dsb instructions in the mm
1359          switching code so that no page table walks can cross the ASID switch.
1360
1361config ARM_ERRATA_754327
1362        bool "ARM errata: no automatic Store Buffer drain"
1363        depends on CPU_V7 && SMP
1364        help
1365          This option enables the workaround for the 754327 Cortex-A9 (prior to
1366          r2p0) erratum. The Store Buffer does not have any automatic draining
1367          mechanism and therefore a livelock may occur if an external agent
1368          continuously polls a memory location waiting to observe an update.
1369          This workaround defines cpu_relax() as smp_mb(), preventing correctly
1370          written polling loops from denying visibility of updates to memory.
1371
1372config ARM_ERRATA_364296
1373        bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1374        depends on CPU_V6 && !SMP
1375        help
1376          This options enables the workaround for the 364296 ARM1136
1377          r0p2 erratum (possible cache data corruption with
1378          hit-under-miss enabled). It sets the undocumented bit 31 in
1379          the auxiliary control register and the FI bit in the control
1380          register, thus disabling hit-under-miss without putting the
1381          processor into full low interrupt latency mode. ARM11MPCore
1382          is not affected.
1383
1384config ARM_ERRATA_764369
1385        bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1386        depends on CPU_V7 && SMP
1387        help
1388          This option enables the workaround for erratum 764369
1389          affecting Cortex-A9 MPCore with two or more processors (all
1390          current revisions). Under certain timing circumstances, a data
1391          cache line maintenance operation by MVA targeting an Inner
1392          Shareable memory region may fail to proceed up to either the
1393          Point of Coherency or to the Point of Unification of the
1394          system. This workaround adds a DSB instruction before the
1395          relevant cache maintenance functions and sets a specific bit
1396          in the diagnostic control register of the SCU.
1397
1398config PL310_ERRATA_769419
1399        bool "PL310 errata: no automatic Store Buffer drain"
1400        depends on CACHE_L2X0
1401        help
1402          On revisions of the PL310 prior to r3p2, the Store Buffer does
1403          not automatically drain. This can cause normal, non-cacheable
1404          writes to be retained when the memory system is idle, leading
1405          to suboptimal I/O performance for drivers using coherent DMA.
1406          This option adds a write barrier to the cpu_idle loop so that,
1407          on systems with an outer cache, the store buffer is drained
1408          explicitly.
1409
1410config ARM_ERRATA_775420
1411       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1412       depends on CPU_V7
1413       help
1414         This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1415         r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1416         operation aborts with MMU exception, it might cause the processor
1417         to deadlock. This workaround puts DSB before executing ISB if
1418         an abort may occur on cache maintenance.
1419
1420endmenu
1421
1422source "arch/arm/common/Kconfig"
1423
1424menu "Bus support"
1425
1426config ARM_AMBA
1427        bool
1428
1429config ISA
1430        bool
1431        help
1432          Find out whether you have ISA slots on your motherboard.  ISA is the
1433          name of a bus system, i.e. the way the CPU talks to the other stuff
1434          inside your box.  Other bus systems are PCI, EISA, MicroChannel
1435          (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1436          newer boards don't support it.  If you have ISA, say Y, otherwise N.
1437
1438# Select ISA DMA controller support
1439config ISA_DMA
1440        bool
1441        select ISA_DMA_API
1442
1443# Select ISA DMA interface
1444config ISA_DMA_API
1445        bool
1446
1447config PCI
1448        bool "PCI support" if MIGHT_HAVE_PCI
1449        help
1450          Find out whether you have a PCI motherboard. PCI is the name of a
1451          bus system, i.e. the way the CPU talks to the other stuff inside
1452          your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1453          VESA. If you have PCI, say Y, otherwise N.
1454
1455config PCI_DOMAINS
1456        bool
1457        depends on PCI
1458
1459config PCI_NANOENGINE
1460        bool "BSE nanoEngine PCI support"
1461        depends on SA1100_NANOENGINE
1462        help
1463          Enable PCI on the BSE nanoEngine board.
1464
1465config PCI_SYSCALL
1466        def_bool PCI
1467
1468# Select the host bridge type
1469config PCI_HOST_VIA82C505
1470        bool
1471        depends on PCI && ARCH_SHARK
1472        default y
1473
1474config PCI_HOST_ITE8152
1475        bool
1476        depends on PCI && MACH_ARMCORE
1477        default y
1478        select DMABOUNCE
1479
1480source "drivers/pci/Kconfig"
1481
1482source "drivers/pcmcia/Kconfig"
1483
1484endmenu
1485
1486menu "Kernel Features"
1487
1488config HAVE_SMP
1489        bool
1490        help
1491          This option should be selected by machines which have an SMP-
1492          capable CPU.
1493
1494          The only effect of this option is to make the SMP-related
1495          options available to the user for configuration.
1496
1497config SMP
1498        bool "Symmetric Multi-Processing"
1499        depends on CPU_V6K || CPU_V7
1500        depends on GENERIC_CLOCKEVENTS
1501        depends on HAVE_SMP
1502        depends on MMU
1503        select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1504        select USE_GENERIC_SMP_HELPERS
1505        help
1506          This enables support for systems with more than one CPU. If you have
1507          a system with only one CPU, like most personal computers, say N. If
1508          you have a system with more than one CPU, say Y.
1509
1510          If you say N here, the kernel will run on single and multiprocessor
1511          machines, but will use only one CPU of a multiprocessor machine. If
1512          you say Y here, the kernel will run on many, but not all, single
1513          processor machines. On a single processor machine, the kernel will
1514          run faster if you say N here.
1515
1516          See also <file:Documentation/x86/i386/IO-APIC.txt>,
1517          <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1518          <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1519
1520          If you don't know what to do here, say N.
1521
1522config SMP_ON_UP
1523        bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1524        depends on EXPERIMENTAL
1525        depends on SMP && !XIP_KERNEL
1526        default y
1527        help
1528          SMP kernels contain instructions which fail on non-SMP processors.
1529          Enabling this option allows the kernel to modify itself to make
1530          these instructions safe.  Disabling it allows about 1K of space
1531          savings.
1532
1533          If you don't know what to do here, say Y.
1534
1535config ARM_CPU_TOPOLOGY
1536        bool "Support cpu topology definition"
1537        depends on SMP && CPU_V7
1538        default y
1539        help
1540          Support ARM cpu topology definition. The MPIDR register defines
1541          affinity between processors which is then used to describe the cpu
1542          topology of an ARM System.
1543
1544config SCHED_MC
1545        bool "Multi-core scheduler support"
1546        depends on ARM_CPU_TOPOLOGY
1547        help
1548          Multi-core scheduler support improves the CPU scheduler's decision
1549          making when dealing with multi-core CPU chips at a cost of slightly
1550          increased overhead in some places. If unsure say N here.
1551
1552config SCHED_SMT
1553        bool "SMT scheduler support"
1554        depends on ARM_CPU_TOPOLOGY
1555        help
1556          Improves the CPU scheduler's decision making when dealing with
1557          MultiThreading at a cost of slightly increased overhead in some
1558          places. If unsure say N here.
1559
1560config HAVE_ARM_SCU
1561        bool
1562        help
1563          This option enables support for the ARM system coherency unit
1564
1565config ARM_ARCH_TIMER
1566        bool "Architected timer support"
1567        depends on CPU_V7
1568        help
1569          This option enables support for the ARM architected timer
1570
1571config HAVE_ARM_TWD
1572        bool
1573        depends on SMP
1574        help
1575          This options enables support for the ARM timer and watchdog unit
1576
1577choice
1578        prompt "Memory split"
1579        default VMSPLIT_3G
1580        help
1581          Select the desired split between kernel and user memory.
1582
1583          If you are not absolutely sure what you are doing, leave this
1584          option alone!
1585
1586        config VMSPLIT_3G
1587                bool "3G/1G user/kernel split"
1588        config VMSPLIT_2G
1589                bool "2G/2G user/kernel split"
1590        config VMSPLIT_1G
1591                bool "1G/3G user/kernel split"
1592endchoice
1593
1594config PAGE_OFFSET
1595        hex
1596        default 0x40000000 if VMSPLIT_1G
1597        default 0x80000000 if VMSPLIT_2G
1598        default 0xC0000000
1599
1600config NR_CPUS
1601        int "Maximum number of CPUs (2-32)"
1602        range 2 32
1603        depends on SMP
1604        default "4"
1605
1606config HOTPLUG_CPU
1607        bool "Support for hot-pluggable CPUs"
1608        depends on SMP && HOTPLUG
1609        help
1610          Say Y here to experiment with turning CPUs off and on.  CPUs
1611          can be controlled through /sys/devices/system/cpu.
1612
1613config LOCAL_TIMERS
1614        bool "Use local timer interrupts"
1615        depends on SMP
1616        default y
1617        select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1618        help
1619          Enable support for local timers on SMP platforms, rather then the
1620          legacy IPI broadcast method.  Local timers allows the system
1621          accounting to be spread across the timer interval, preventing a
1622          "thundering herd" at every timer tick.
1623
1624config ARCH_NR_GPIO
1625        int
1626        default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1627        default 355 if ARCH_U8500
1628        default 264 if MACH_H4700
1629        default 512 if SOC_OMAP5
1630        default 288 if ARCH_VT8500
1631        default 0
1632        help
1633          Maximum number of GPIOs in the system.
1634
1635          If unsure, leave the default value.
1636
1637source kernel/Kconfig.preempt
1638
1639config HZ
1640        int
1641        default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1642                ARCH_S5PV210 || ARCH_EXYNOS4
1643        default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1644        default AT91_TIMER_HZ if ARCH_AT91
1645        default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1646        default 100
1647
1648config THUMB2_KERNEL
1649        bool "Compile the kernel in Thumb-2 mode"
1650        depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1651        select AEABI
1652        select ARM_ASM_UNIFIED
1653        select ARM_UNWIND
1654        help
1655          By enabling this option, the kernel will be compiled in
1656          Thumb-2 mode. A compiler/assembler that understand the unified
1657          ARM-Thumb syntax is needed.
1658
1659          If unsure, say N.
1660
1661config THUMB2_AVOID_R_ARM_THM_JUMP11
1662        bool "Work around buggy Thumb-2 short branch relocations in gas"
1663        depends on THUMB2_KERNEL && MODULES
1664        default y
1665        help
1666          Various binutils versions can resolve Thumb-2 branches to
1667          locally-defined, preemptible global symbols as short-range "b.n"
1668          branch instructions.
1669
1670          This is a problem, because there's no guarantee the final
1671          destination of the symbol, or any candidate locations for a
1672          trampoline, are within range of the branch.  For this reason, the
1673          kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1674          relocation in modules at all, and it makes little sense to add
1675          support.
1676
1677          The symptom is that the kernel fails with an "unsupported
1678          relocation" error when loading some modules.
1679
1680          Until fixed tools are available, passing
1681          -fno-optimize-sibling-calls to gcc should prevent gcc generating
1682          code which hits this problem, at the cost of a bit of extra runtime
1683          stack usage in some cases.
1684
1685          The problem is described in more detail at:
1686              https://bugs.launchpad.net/binutils-linaro/+bug/725126
1687
1688          Only Thumb-2 kernels are affected.
1689
1690          Unless you are sure your tools don't have this problem, say Y.
1691
1692config ARM_ASM_UNIFIED
1693        bool
1694
1695config AEABI
1696        bool "Use the ARM EABI to compile the kernel"
1697        help
1698          This option allows for the kernel to be compiled using the latest
1699          ARM ABI (aka EABI).  This is only useful if you are using a user
1700          space environment that is also compiled with EABI.
1701
1702          Since there are major incompatibilities between the legacy ABI and
1703          EABI, especially with regard to structure member alignment, this
1704          option also changes the kernel syscall calling convention to
1705          disambiguate both ABIs and allow for backward compatibility support
1706          (selected with CONFIG_OABI_COMPAT).
1707
1708          To use this you need GCC version 4.0.0 or later.
1709
1710config OABI_COMPAT
1711        bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1712        depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1713        default y
1714        help
1715          This option preserves the old syscall interface along with the
1716          new (ARM EABI) one. It also provides a compatibility layer to
1717          intercept syscalls that have structure arguments which layout
1718          in memory differs between the legacy ABI and the new ARM EABI
1719          (only for non "thumb" binaries). This option adds a tiny
1720          overhead to all syscalls and produces a slightly larger kernel.
1721          If you know you'll be using only pure EABI user space then you
1722          can say N here. If this option is not selected and you attempt
1723          to execute a legacy ABI binary then the result will be
1724          UNPREDICTABLE (in fact it can be predicted that it won't work
1725          at all). If in doubt say Y.
1726
1727config ARCH_HAS_HOLES_MEMORYMODEL
1728        bool
1729
1730config ARCH_SPARSEMEM_ENABLE
1731        bool
1732
1733config ARCH_SPARSEMEM_DEFAULT
1734        def_bool ARCH_SPARSEMEM_ENABLE
1735
1736config ARCH_SELECT_MEMORY_MODEL
1737        def_bool ARCH_SPARSEMEM_ENABLE
1738
1739config HAVE_ARCH_PFN_VALID
1740        def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1741
1742config HIGHMEM
1743        bool "High Memory Support"
1744        depends on MMU
1745        help
1746          The address space of ARM processors is only 4 Gigabytes large
1747          and it has to accommodate user address space, kernel address
1748          space as well as some memory mapped IO. That means that, if you
1749          have a large amount of physical memory and/or IO, not all of the
1750          memory can be "permanently mapped" by the kernel. The physical
1751          memory that is not permanently mapped is called "high memory".
1752
1753          Depending on the selected kernel/user memory split, minimum
1754          vmalloc space and actual amount of RAM, you may not need this
1755          option which should result in a slightly faster kernel.
1756
1757          If unsure, say n.
1758
1759config HIGHPTE
1760        bool "Allocate 2nd-level pagetables from highmem"
1761        depends on HIGHMEM
1762
1763config HW_PERF_EVENTS
1764        bool "Enable hardware performance counter support for perf events"
1765        depends on PERF_EVENTS
1766        default y
1767        help
1768          Enable hardware performance counter support for perf events. If
1769          disabled, perf events will use software events only.
1770
1771source "mm/Kconfig"
1772
1773config FORCE_MAX_ZONEORDER
1774        int "Maximum zone order" if ARCH_SHMOBILE
1775        range 11 64 if ARCH_SHMOBILE
1776        default "12" if SOC_AM33XX
1777        default "9" if SA1111
1778        default "11"
1779        help
1780          The kernel memory allocator divides physically contiguous memory
1781          blocks into "zones", where each zone is a power of two number of
1782          pages.  This option selects the largest power of two that the kernel
1783          keeps in the memory allocator.  If you need to allocate very large
1784          blocks of physically contiguous memory, then you may need to
1785          increase this value.
1786
1787          This config option is actually maximum order plus one. For example,
1788          a value of 11 means that the largest free memory block is 2^10 pages.
1789
1790config ALIGNMENT_TRAP
1791        bool
1792        depends on CPU_CP15_MMU
1793        default y if !ARCH_EBSA110
1794        select HAVE_PROC_CPU if PROC_FS
1795        help
1796          ARM processors cannot fetch/store information which is not
1797          naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1798          address divisible by 4. On 32-bit ARM processors, these non-aligned
1799          fetch/store instructions will be emulated in software if you say
1800          here, which has a severe performance impact. This is necessary for
1801          correct operation of some network protocols. With an IP-only
1802          configuration it is safe to say N, otherwise say Y.
1803
1804config UACCESS_WITH_MEMCPY
1805        bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1806        depends on MMU
1807        default y if CPU_FEROCEON
1808        help
1809          Implement faster copy_to_user and clear_user methods for CPU
1810          cores where a 8-word STM instruction give significantly higher
1811          memory write throughput than a sequence of individual 32bit stores.
1812
1813          A possible side effect is a slight increase in scheduling latency
1814          between threads sharing the same address space if they invoke
1815          such copy operations with large buffers.
1816
1817          However, if the CPU data cache is using a write-allocate mode,
1818          this option is unlikely to provide any performance gain.
1819
1820config SECCOMP
1821        bool
1822        prompt "Enable seccomp to safely compute untrusted bytecode"
1823        ---help---
1824          This kernel feature is useful for number crunching applications
1825          that may need to compute untrusted bytecode during their
1826          execution. By using pipes or other transports made available to
1827          the process as file descriptors supporting the read/write
1828          syscalls, it's possible to isolate those applications in
1829          their own address space using seccomp. Once seccomp is
1830          enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1831          and the task is only allowed to execute a few safe syscalls
1832          defined by each seccomp mode.
1833
1834config CC_STACKPROTECTOR
1835        bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1836        depends on EXPERIMENTAL
1837        help
1838          This option turns on the -fstack-protector GCC feature. This
1839          feature puts, at the beginning of functions, a canary value on
1840          the stack just before the return address, and validates
1841          the value just before actually returning.  Stack based buffer
1842          overflows (that need to overwrite this return address) now also
1843          overwrite the canary, which gets detected and the attack is then
1844          neutralized via a kernel panic.
1845          This feature requires gcc version 4.2 or above.
1846
1847config XEN_DOM0
1848        def_bool y
1849        depends on XEN
1850
1851config XEN
1852        bool "Xen guest support on ARM (EXPERIMENTAL)"
1853        depends on EXPERIMENTAL && ARM && OF
1854        depends on CPU_V7 && !CPU_V6
1855        help
1856          Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1857
1858endmenu
1859
1860menu "Boot options"
1861
1862config USE_OF
1863        bool "Flattened Device Tree support"
1864        select IRQ_DOMAIN
1865        select OF
1866        select OF_EARLY_FLATTREE
1867        help
1868          Include support for flattened device tree machine descriptions.
1869
1870config ATAGS
1871        bool "Support for the traditional ATAGS boot data passing" if USE_OF
1872        default y
1873        help
1874          This is the traditional way of passing data to the kernel at boot
1875          time. If you are solely relying on the flattened device tree (or
1876          the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1877          to remove ATAGS support from your kernel binary.  If unsure,
1878          leave this to y.
1879
1880config DEPRECATED_PARAM_STRUCT
1881        bool "Provide old way to pass kernel parameters"
1882        depends on ATAGS
1883        help
1884          This was deprecated in 2001 and announced to live on for 5 years.
1885          Some old boot loaders still use this way.
1886
1887# Compressed boot loader in ROM.  Yes, we really want to ask about
1888# TEXT and BSS so we preserve their values in the config files.
1889config ZBOOT_ROM_TEXT
1890        hex "Compressed ROM boot loader base address"
1891        default "0"
1892        help
1893          The physical address at which the ROM-able zImage is to be
1894          placed in the target.  Platforms which normally make use of
1895          ROM-able zImage formats normally set this to a suitable
1896          value in their defconfig file.
1897
1898          If ZBOOT_ROM is not enabled, this has no effect.
1899
1900config ZBOOT_ROM_BSS
1901        hex "Compressed ROM boot loader BSS address"
1902        default "0"
1903        help
1904          The base address of an area of read/write memory in the target
1905          for the ROM-able zImage which must be available while the
1906          decompressor is running. It must be large enough to hold the
1907          entire decompressed kernel plus an additional 128 KiB.
1908          Platforms which normally make use of ROM-able zImage formats
1909          normally set this to a suitable value in their defconfig file.
1910
1911          If ZBOOT_ROM is not enabled, this has no effect.
1912
1913config ZBOOT_ROM
1914        bool "Compressed boot loader in ROM/flash"
1915        depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1916        help
1917          Say Y here if you intend to execute your compressed kernel image
1918          (zImage) directly from ROM or flash.  If unsure, say N.
1919
1920choice
1921        prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1922        depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1923        default ZBOOT_ROM_NONE
1924        help
1925          Include experimental SD/MMC loading code in the ROM-able zImage.
1926          With this enabled it is possible to write the ROM-able zImage
1927          kernel image to an MMC or SD card and boot the kernel straight
1928          from the reset vector. At reset the processor Mask ROM will load
1929          the first part of the ROM-able zImage which in turn loads the
1930          rest the kernel image to RAM.
1931
1932config ZBOOT_ROM_NONE
1933        bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1934        help
1935          Do not load image from SD or MMC
1936
1937config ZBOOT_ROM_MMCIF
1938        bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1939        help
1940          Load image from MMCIF hardware block.
1941
1942config ZBOOT_ROM_SH_MOBILE_SDHI
1943        bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1944        help
1945          Load image from SDHI hardware block
1946
1947endchoice
1948
1949config ARM_APPENDED_DTB
1950        bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1951        depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1952        help
1953          With this option, the boot code will look for a device tree binary
1954          (DTB) appended to zImage
1955          (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1956
1957          This is meant as a backward compatibility convenience for those
1958          systems with a bootloader that can't be upgraded to accommodate
1959          the documented boot protocol using a device tree.
1960
1961          Beware that there is very little in terms of protection against
1962          this option being confused by leftover garbage in memory that might
1963          look like a DTB header after a reboot if no actual DTB is appended
1964          to zImage.  Do not leave this option active in a production kernel
1965          if you don't intend to always append a DTB.  Proper passing of the
1966          location into r2 of a bootloader provided DTB is always preferable
1967          to this option.
1968
1969config ARM_ATAG_DTB_COMPAT
1970        bool "Supplement the appended DTB with traditional ATAG information"
1971        depends on ARM_APPENDED_DTB
1972        help
1973          Some old bootloaders can't be updated to a DTB capable one, yet
1974          they provide ATAGs with memory configuration, the ramdisk address,
1975          the kernel cmdline string, etc.  Such information is dynamically
1976          provided by the bootloader and can't always be stored in a static
1977          DTB.  To allow a device tree enabled kernel to be used with such
1978          bootloaders, this option allows zImage to extract the information
1979          from the ATAG list and store it at run time into the appended DTB.
1980
1981choice
1982        prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1983        default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1984
1985config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1986        bool "Use bootloader kernel arguments if available"
1987        help
1988          Uses the command-line options passed by the boot loader instead of
1989          the device tree bootargs property. If the boot loader doesn't provide
1990          any, the device tree bootargs property will be used.
1991
1992config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1993        bool "Extend with bootloader kernel arguments"
1994        help
1995          The command-line arguments provided by the boot loader will be
1996          appended to the the device tree bootargs property.
1997
1998endchoice
1999
2000config CMDLINE
2001        string "Default kernel command string"
2002        default ""
2003        help
2004          On some architectures (EBSA110 and CATS), there is currently no way
2005          for the boot loader to pass arguments to the kernel. For these
2006          architectures, you should supply some command-line options at build
2007          time by entering them here. As a minimum, you should specify the
2008          memory size and the root device (e.g., mem=64M root=/dev/nfs).
2009
2010choice
2011        prompt "Kernel command line type" if CMDLINE != ""
2012        default CMDLINE_FROM_BOOTLOADER
2013        depends on ATAGS
2014
2015config CMDLINE_FROM_BOOTLOADER
2016        bool "Use bootloader kernel arguments if available"
2017        help
2018          Uses the command-line options passed by the boot loader. If
2019          the boot loader doesn't provide any, the default kernel command
2020          string provided in CMDLINE will be used.
2021
2022config CMDLINE_EXTEND
2023        bool "Extend bootloader kernel arguments"
2024        help
2025          The command-line arguments provided by the boot loader will be
2026          appended to the default kernel command string.
2027
2028config CMDLINE_FORCE
2029        bool "Always use the default kernel command string"
2030        help
2031          Always use the default kernel command string, even if the boot
2032          loader passes other arguments to the kernel.
2033          This is useful if you cannot or don't want to change the
2034          command-line options your boot loader passes to the kernel.
2035endchoice
2036
2037config XIP_KERNEL
2038        bool "Kernel Execute-In-Place from ROM"
2039        depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2040        help
2041          Execute-In-Place allows the kernel to run from non-volatile storage
2042          directly addressable by the CPU, such as NOR flash. This saves RAM
2043          space since the text section of the kernel is not loaded from flash
2044          to RAM.  Read-write sections, such as the data section and stack,
2045          are still copied to RAM.  The XIP kernel is not compressed since
2046          it has to run directly from flash, so it will take more space to
2047          store it.  The flash address used to link the kernel object files,
2048          and for storing it, is configuration dependent. Therefore, if you
2049          say Y here, you must know the proper physical address where to
2050          store the kernel image depending on your own flash memory usage.
2051
2052          Also note that the make target becomes "make xipImage" rather than
2053          "make zImage" or "make Image".  The final kernel binary to put in
2054          ROM memory will be arch/arm/boot/xipImage.
2055
2056          If unsure, say N.
2057
2058config XIP_PHYS_ADDR
2059        hex "XIP Kernel Physical Location"
2060        depends on XIP_KERNEL
2061        default "0x00080000"
2062        help
2063          This is the physical address in your flash memory the kernel will
2064          be linked for and stored to.  This address is dependent on your
2065          own flash usage.
2066
2067config KEXEC
2068        bool "Kexec system call (EXPERIMENTAL)"
2069        depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2070        help
2071          kexec is a system call that implements the ability to shutdown your
2072          current kernel, and to start another kernel.  It is like a reboot
2073          but it is independent of the system firmware.   And like a reboot
2074          you can start any kernel with it, not just Linux.
2075
2076          It is an ongoing process to be certain the hardware in a machine
2077          is properly shutdown, so do not be surprised if this code does not
2078          initially work for you.  It may help to enable device hotplugging
2079          support.
2080
2081config ATAGS_PROC
2082        bool "Export atags in procfs"
2083        depends on ATAGS && KEXEC
2084        default y
2085        help
2086          Should the atags used to boot the kernel be exported in an "atags"
2087          file in procfs. Useful with kexec.
2088
2089config CRASH_DUMP
2090        bool "Build kdump crash kernel (EXPERIMENTAL)"
2091        depends on EXPERIMENTAL
2092        help
2093          Generate crash dump after being started by kexec. This should
2094          be normally only set in special crash dump kernels which are
2095          loaded in the main kernel with kexec-tools into a specially
2096          reserved region and then later executed after a crash by
2097          kdump/kexec. The crash dump kernel must be compiled to a
2098          memory address not used by the main kernel
2099
2100          For more details see Documentation/kdump/kdump.txt
2101
2102config AUTO_ZRELADDR
2103        bool "Auto calculation of the decompressed kernel image address"
2104        depends on !ZBOOT_ROM && !ARCH_U300
2105        help
2106          ZRELADDR is the physical address where the decompressed kernel
2107          image will be placed. If AUTO_ZRELADDR is selected, the address
2108          will be determined at run-time by masking the current IP with
2109          0xf8000000. This assumes the zImage being placed in the first 128MB
2110          from start of memory.
2111
2112endmenu
2113
2114menu "CPU Power Management"
2115
2116if ARCH_HAS_CPUFREQ
2117
2118source "drivers/cpufreq/Kconfig"
2119
2120config CPU_FREQ_IMX
2121        tristate "CPUfreq driver for i.MX CPUs"
2122        depends on ARCH_MXC && CPU_FREQ
2123        select CPU_FREQ_TABLE
2124        help
2125          This enables the CPUfreq driver for i.MX CPUs.
2126
2127config CPU_FREQ_SA1100
2128        bool
2129
2130config CPU_FREQ_SA1110
2131        bool
2132
2133config CPU_FREQ_INTEGRATOR
2134        tristate "CPUfreq driver for ARM Integrator CPUs"
2135        depends on ARCH_INTEGRATOR && CPU_FREQ
2136        default y
2137        help
2138          This enables the CPUfreq driver for ARM Integrator CPUs.
2139
2140          For details, take a look at <file:Documentation/cpu-freq>.
2141
2142          If in doubt, say Y.
2143
2144config CPU_FREQ_PXA
2145        bool
2146        depends on CPU_FREQ && ARCH_PXA && PXA25x
2147        default y
2148        select CPU_FREQ_DEFAULT_GOV_USERSPACE
2149        select CPU_FREQ_TABLE
2150
2151config CPU_FREQ_S3C
2152        bool
2153        help
2154          Internal configuration node for common cpufreq on Samsung SoC
2155
2156config CPU_FREQ_S3C24XX
2157        bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2158        depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2159        select CPU_FREQ_S3C
2160        help
2161          This enables the CPUfreq driver for the Samsung S3C24XX family
2162          of CPUs.
2163
2164          For details, take a look at <file:Documentation/cpu-freq>.
2165
2166          If in doubt, say N.
2167
2168config CPU_FREQ_S3C24XX_PLL
2169        bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2170        depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2171        help
2172          Compile in support for changing the PLL frequency from the
2173          S3C24XX series CPUfreq driver. The PLL takes time to settle
2174          after a frequency change, so by default it is not enabled.
2175
2176          This also means that the PLL tables for the selected CPU(s) will
2177          be built which may increase the size of the kernel image.
2178
2179config CPU_FREQ_S3C24XX_DEBUG
2180        bool "Debug CPUfreq Samsung driver core"
2181        depends on CPU_FREQ_S3C24XX
2182        help
2183          Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2184
2185config CPU_FREQ_S3C24XX_IODEBUG
2186        bool "Debug CPUfreq Samsung driver IO timing"
2187        depends on CPU_FREQ_S3C24XX
2188        help
2189          Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2190
2191config CPU_FREQ_S3C24XX_DEBUGFS
2192        bool "Export debugfs for CPUFreq"
2193        depends on CPU_FREQ_S3C24XX && DEBUG_FS
2194        help
2195          Export status information via debugfs.
2196
2197endif
2198
2199source "drivers/cpuidle/Kconfig"
2200
2201endmenu
2202
2203menu "Floating point emulation"
2204
2205comment "At least one emulation must be selected"
2206
2207config FPE_NWFPE
2208        bool "NWFPE math emulation"
2209        depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2210        ---help---
2211          Say Y to include the NWFPE floating point emulator in the kernel.
2212          This is necessary to run most binaries. Linux does not currently
2213          support floating point hardware so you need to say Y here even if
2214          your machine has an FPA or floating point co-processor podule.
2215
2216          You may say N here if you are going to load the Acorn FPEmulator
2217          early in the bootup.
2218
2219config FPE_NWFPE_XP
2220        bool "Support extended precision"
2221        depends on FPE_NWFPE
2222        help
2223          Say Y to include 80-bit support in the kernel floating-point
2224          emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2225          Note that gcc does not generate 80-bit operations by default,
2226          so in most cases this option only enlarges the size of the
2227          floating point emulator without any good reason.
2228
2229          You almost surely want to say N here.
2230
2231config FPE_FASTFPE
2232        bool "FastFPE math emulation (EXPERIMENTAL)"
2233        depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2234        ---help---
2235          Say Y here to include the FAST floating point emulator in the kernel.
2236          This is an experimental much faster emulator which now also has full
2237          precision for the mantissa.  It does not support any exceptions.
2238          It is very simple, and approximately 3-6 times faster than NWFPE.
2239
2240          It should be sufficient for most programs.  It may be not suitable
2241          for scientific calculations, but you have to check this for yourself.
2242          If you do not feel you need a faster FP emulation you should better
2243          choose NWFPE.
2244
2245config VFP
2246        bool "VFP-format floating point maths"
2247        depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2248        help
2249          Say Y to include VFP support code in the kernel. This is needed
2250          if your hardware includes a VFP unit.
2251
2252          Please see <file:Documentation/arm/VFP/release-notes.txt> for
2253          release notes and additional status information.
2254
2255          Say N if your target does not have VFP hardware.
2256
2257config VFPv3
2258        bool
2259        depends on VFP
2260        default y if CPU_V7
2261
2262config NEON
2263        bool "Advanced SIMD (NEON) Extension support"
2264        depends on VFPv3 && CPU_V7
2265        help
2266          Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2267          Extension.
2268
2269endmenu
2270
2271menu "Userspace binary formats"
2272
2273source "fs/Kconfig.binfmt"
2274
2275config ARTHUR
2276        tristate "RISC OS personality"
2277        depends on !AEABI
2278        help
2279          Say Y here to include the kernel code necessary if you want to run
2280          Acorn RISC OS/Arthur binaries under Linux. This code is still very
2281          experimental; if this sounds frightening, say N and sleep in peace.
2282          You can also say M here to compile this support as a module (which
2283          will be called arthur).
2284
2285endmenu
2286
2287menu "Power management options"
2288
2289source "kernel/power/Kconfig"
2290
2291config ARCH_SUSPEND_POSSIBLE
2292        depends on !ARCH_S5PC100
2293        depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2294                CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2295        def_bool y
2296
2297config ARM_CPU_SUSPEND
2298        def_bool PM_SLEEP
2299
2300endmenu
2301
2302source "net/Kconfig"
2303
2304source "drivers/Kconfig"
2305
2306source "fs/Kconfig"
2307
2308source "arch/arm/Kconfig.debug"
2309
2310source "security/Kconfig"
2311
2312source "crypto/Kconfig"
2313
2314source "lib/Kconfig"
2315
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