linux/virt/kvm/ioapic.c
<<
>>
Prefs
   1/*
   2 *  Copyright (C) 2001  MandrakeSoft S.A.
   3 *  Copyright 2010 Red Hat, Inc. and/or its affiliates.
   4 *
   5 *    MandrakeSoft S.A.
   6 *    43, rue d'Aboukir
   7 *    75002 Paris - France
   8 *    http://www.linux-mandrake.com/
   9 *    http://www.mandrakesoft.com/
  10 *
  11 *  This library is free software; you can redistribute it and/or
  12 *  modify it under the terms of the GNU Lesser General Public
  13 *  License as published by the Free Software Foundation; either
  14 *  version 2 of the License, or (at your option) any later version.
  15 *
  16 *  This library is distributed in the hope that it will be useful,
  17 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19 *  Lesser General Public License for more details.
  20 *
  21 *  You should have received a copy of the GNU Lesser General Public
  22 *  License along with this library; if not, write to the Free Software
  23 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  24 *
  25 *  Yunhong Jiang <yunhong.jiang@intel.com>
  26 *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
  27 *  Based on Xen 3.1 code.
  28 */
  29
  30#include <linux/kvm_host.h>
  31#include <linux/kvm.h>
  32#include <linux/mm.h>
  33#include <linux/highmem.h>
  34#include <linux/smp.h>
  35#include <linux/hrtimer.h>
  36#include <linux/io.h>
  37#include <linux/slab.h>
  38#include <asm/processor.h>
  39#include <asm/page.h>
  40#include <asm/current.h>
  41#include <trace/events/kvm.h>
  42
  43#include "ioapic.h"
  44#include "lapic.h"
  45#include "irq.h"
  46
  47#if 0
  48#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
  49#else
  50#define ioapic_debug(fmt, arg...)
  51#endif
  52static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
  53
  54static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
  55                                          unsigned long addr,
  56                                          unsigned long length)
  57{
  58        unsigned long result = 0;
  59
  60        switch (ioapic->ioregsel) {
  61        case IOAPIC_REG_VERSION:
  62                result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
  63                          | (IOAPIC_VERSION_ID & 0xff));
  64                break;
  65
  66        case IOAPIC_REG_APIC_ID:
  67        case IOAPIC_REG_ARB_ID:
  68                result = ((ioapic->id & 0xf) << 24);
  69                break;
  70
  71        default:
  72                {
  73                        u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
  74                        u64 redir_content;
  75
  76                        ASSERT(redir_index < IOAPIC_NUM_PINS);
  77
  78                        redir_content = ioapic->redirtbl[redir_index].bits;
  79                        result = (ioapic->ioregsel & 0x1) ?
  80                            (redir_content >> 32) & 0xffffffff :
  81                            redir_content & 0xffffffff;
  82                        break;
  83                }
  84        }
  85
  86        return result;
  87}
  88
  89static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
  90{
  91        union kvm_ioapic_redirect_entry *pent;
  92        int injected = -1;
  93
  94        pent = &ioapic->redirtbl[idx];
  95
  96        if (!pent->fields.mask) {
  97                injected = ioapic_deliver(ioapic, idx);
  98                if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
  99                        pent->fields.remote_irr = 1;
 100        }
 101
 102        return injected;
 103}
 104
 105static void update_handled_vectors(struct kvm_ioapic *ioapic)
 106{
 107        DECLARE_BITMAP(handled_vectors, 256);
 108        int i;
 109
 110        memset(handled_vectors, 0, sizeof(handled_vectors));
 111        for (i = 0; i < IOAPIC_NUM_PINS; ++i)
 112                __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
 113        memcpy(ioapic->handled_vectors, handled_vectors,
 114               sizeof(handled_vectors));
 115        smp_wmb();
 116}
 117
 118static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
 119{
 120        unsigned index;
 121        bool mask_before, mask_after;
 122        union kvm_ioapic_redirect_entry *e;
 123
 124        switch (ioapic->ioregsel) {
 125        case IOAPIC_REG_VERSION:
 126                /* Writes are ignored. */
 127                break;
 128
 129        case IOAPIC_REG_APIC_ID:
 130                ioapic->id = (val >> 24) & 0xf;
 131                break;
 132
 133        case IOAPIC_REG_ARB_ID:
 134                break;
 135
 136        default:
 137                index = (ioapic->ioregsel - 0x10) >> 1;
 138
 139                ioapic_debug("change redir index %x val %x\n", index, val);
 140                if (index >= IOAPIC_NUM_PINS)
 141                        return;
 142                e = &ioapic->redirtbl[index];
 143                mask_before = e->fields.mask;
 144                if (ioapic->ioregsel & 1) {
 145                        e->bits &= 0xffffffff;
 146                        e->bits |= (u64) val << 32;
 147                } else {
 148                        e->bits &= ~0xffffffffULL;
 149                        e->bits |= (u32) val;
 150                        e->fields.remote_irr = 0;
 151                }
 152                update_handled_vectors(ioapic);
 153                mask_after = e->fields.mask;
 154                if (mask_before != mask_after)
 155                        kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
 156                if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
 157                    && ioapic->irr & (1 << index))
 158                        ioapic_service(ioapic, index);
 159                break;
 160        }
 161}
 162
 163static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
 164{
 165        union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
 166        struct kvm_lapic_irq irqe;
 167
 168        ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
 169                     "vector=%x trig_mode=%x\n",
 170                     entry->fields.dest_id, entry->fields.dest_mode,
 171                     entry->fields.delivery_mode, entry->fields.vector,
 172                     entry->fields.trig_mode);
 173
 174        irqe.dest_id = entry->fields.dest_id;
 175        irqe.vector = entry->fields.vector;
 176        irqe.dest_mode = entry->fields.dest_mode;
 177        irqe.trig_mode = entry->fields.trig_mode;
 178        irqe.delivery_mode = entry->fields.delivery_mode << 8;
 179        irqe.level = 1;
 180        irqe.shorthand = 0;
 181
 182#ifdef CONFIG_X86
 183        /* Always delivery PIT interrupt to vcpu 0 */
 184        if (irq == 0) {
 185                irqe.dest_mode = 0; /* Physical mode. */
 186                /* need to read apic_id from apic regiest since
 187                 * it can be rewritten */
 188                irqe.dest_id = ioapic->kvm->bsp_vcpu_id;
 189        }
 190#endif
 191        return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
 192}
 193
 194int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
 195                       int level)
 196{
 197        u32 old_irr;
 198        u32 mask = 1 << irq;
 199        union kvm_ioapic_redirect_entry entry;
 200        int ret, irq_level;
 201
 202        BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);
 203
 204        spin_lock(&ioapic->lock);
 205        old_irr = ioapic->irr;
 206        irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
 207                                         irq_source_id, level);
 208        entry = ioapic->redirtbl[irq];
 209        irq_level ^= entry.fields.polarity;
 210        if (!irq_level) {
 211                ioapic->irr &= ~mask;
 212                ret = 1;
 213        } else {
 214                int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
 215                ioapic->irr |= mask;
 216                if ((edge && old_irr != ioapic->irr) ||
 217                    (!edge && !entry.fields.remote_irr))
 218                        ret = ioapic_service(ioapic, irq);
 219                else
 220                        ret = 0; /* report coalesced interrupt */
 221        }
 222        trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
 223        spin_unlock(&ioapic->lock);
 224
 225        return ret;
 226}
 227
 228void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
 229{
 230        int i;
 231
 232        spin_lock(&ioapic->lock);
 233        for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
 234                __clear_bit(irq_source_id, &ioapic->irq_states[i]);
 235        spin_unlock(&ioapic->lock);
 236}
 237
 238static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
 239                                     int trigger_mode)
 240{
 241        int i;
 242
 243        for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 244                union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
 245
 246                if (ent->fields.vector != vector)
 247                        continue;
 248
 249                /*
 250                 * We are dropping lock while calling ack notifiers because ack
 251                 * notifier callbacks for assigned devices call into IOAPIC
 252                 * recursively. Since remote_irr is cleared only after call
 253                 * to notifiers if the same vector will be delivered while lock
 254                 * is dropped it will be put into irr and will be delivered
 255                 * after ack notifier returns.
 256                 */
 257                spin_unlock(&ioapic->lock);
 258                kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
 259                spin_lock(&ioapic->lock);
 260
 261                if (trigger_mode != IOAPIC_LEVEL_TRIG)
 262                        continue;
 263
 264                ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
 265                ent->fields.remote_irr = 0;
 266                if (!ent->fields.mask && (ioapic->irr & (1 << i)))
 267                        ioapic_service(ioapic, i);
 268        }
 269}
 270
 271bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
 272{
 273        struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 274        smp_rmb();
 275        return test_bit(vector, ioapic->handled_vectors);
 276}
 277
 278void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
 279{
 280        struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 281
 282        spin_lock(&ioapic->lock);
 283        __kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
 284        spin_unlock(&ioapic->lock);
 285}
 286
 287static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
 288{
 289        return container_of(dev, struct kvm_ioapic, dev);
 290}
 291
 292static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
 293{
 294        return ((addr >= ioapic->base_address &&
 295                 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
 296}
 297
 298static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
 299                            void *val)
 300{
 301        struct kvm_ioapic *ioapic = to_ioapic(this);
 302        u32 result;
 303        if (!ioapic_in_range(ioapic, addr))
 304                return -EOPNOTSUPP;
 305
 306        ioapic_debug("addr %lx\n", (unsigned long)addr);
 307        ASSERT(!(addr & 0xf));  /* check alignment */
 308
 309        addr &= 0xff;
 310        spin_lock(&ioapic->lock);
 311        switch (addr) {
 312        case IOAPIC_REG_SELECT:
 313                result = ioapic->ioregsel;
 314                break;
 315
 316        case IOAPIC_REG_WINDOW:
 317                result = ioapic_read_indirect(ioapic, addr, len);
 318                break;
 319
 320        default:
 321                result = 0;
 322                break;
 323        }
 324        spin_unlock(&ioapic->lock);
 325
 326        switch (len) {
 327        case 8:
 328                *(u64 *) val = result;
 329                break;
 330        case 1:
 331        case 2:
 332        case 4:
 333                memcpy(val, (char *)&result, len);
 334                break;
 335        default:
 336                printk(KERN_WARNING "ioapic: wrong length %d\n", len);
 337        }
 338        return 0;
 339}
 340
 341static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
 342                             const void *val)
 343{
 344        struct kvm_ioapic *ioapic = to_ioapic(this);
 345        u32 data;
 346        if (!ioapic_in_range(ioapic, addr))
 347                return -EOPNOTSUPP;
 348
 349        ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
 350                     (void*)addr, len, val);
 351        ASSERT(!(addr & 0xf));  /* check alignment */
 352
 353        switch (len) {
 354        case 8:
 355        case 4:
 356                data = *(u32 *) val;
 357                break;
 358        case 2:
 359                data = *(u16 *) val;
 360                break;
 361        case 1:
 362                data = *(u8  *) val;
 363                break;
 364        default:
 365                printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
 366                return 0;
 367        }
 368
 369        addr &= 0xff;
 370        spin_lock(&ioapic->lock);
 371        switch (addr) {
 372        case IOAPIC_REG_SELECT:
 373                ioapic->ioregsel = data & 0xFF; /* 8-bit register */
 374                break;
 375
 376        case IOAPIC_REG_WINDOW:
 377                ioapic_write_indirect(ioapic, data);
 378                break;
 379#ifdef  CONFIG_IA64
 380        case IOAPIC_REG_EOI:
 381                __kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
 382                break;
 383#endif
 384
 385        default:
 386                break;
 387        }
 388        spin_unlock(&ioapic->lock);
 389        return 0;
 390}
 391
 392void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
 393{
 394        int i;
 395
 396        for (i = 0; i < IOAPIC_NUM_PINS; i++)
 397                ioapic->redirtbl[i].fields.mask = 1;
 398        ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 399        ioapic->ioregsel = 0;
 400        ioapic->irr = 0;
 401        ioapic->id = 0;
 402        update_handled_vectors(ioapic);
 403}
 404
 405static const struct kvm_io_device_ops ioapic_mmio_ops = {
 406        .read     = ioapic_mmio_read,
 407        .write    = ioapic_mmio_write,
 408};
 409
 410int kvm_ioapic_init(struct kvm *kvm)
 411{
 412        struct kvm_ioapic *ioapic;
 413        int ret;
 414
 415        ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
 416        if (!ioapic)
 417                return -ENOMEM;
 418        spin_lock_init(&ioapic->lock);
 419        kvm->arch.vioapic = ioapic;
 420        kvm_ioapic_reset(ioapic);
 421        kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
 422        ioapic->kvm = kvm;
 423        mutex_lock(&kvm->slots_lock);
 424        ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
 425                                      IOAPIC_MEM_LENGTH, &ioapic->dev);
 426        mutex_unlock(&kvm->slots_lock);
 427        if (ret < 0) {
 428                kvm->arch.vioapic = NULL;
 429                kfree(ioapic);
 430        }
 431
 432        return ret;
 433}
 434
 435void kvm_ioapic_destroy(struct kvm *kvm)
 436{
 437        struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 438
 439        if (ioapic) {
 440                kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
 441                kvm->arch.vioapic = NULL;
 442                kfree(ioapic);
 443        }
 444}
 445
 446int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
 447{
 448        struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
 449        if (!ioapic)
 450                return -EINVAL;
 451
 452        spin_lock(&ioapic->lock);
 453        memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
 454        spin_unlock(&ioapic->lock);
 455        return 0;
 456}
 457
 458int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
 459{
 460        struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
 461        if (!ioapic)
 462                return -EINVAL;
 463
 464        spin_lock(&ioapic->lock);
 465        memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
 466        update_handled_vectors(ioapic);
 467        spin_unlock(&ioapic->lock);
 468        return 0;
 469}
 470
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.