linux/drivers/watchdog/nv_tco.h
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   1/*
   2 *      nv_tco: TCO timer driver for nVidia chipsets.
   3 *
   4 *      (c) Copyright 2005 Google Inc., All Rights Reserved.
   5 *
   6 *      Supported Chipsets:
   7 *              - MCP51/MCP55
   8 *
   9 *      (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
  10 *      Reserved.
  11 *                              http://www.kernelconcepts.de
  12 *
  13 *      This program is free software; you can redistribute it and/or
  14 *      modify it under the terms of the GNU General Public License
  15 *      as published by the Free Software Foundation; either version
  16 *      2 of the License, or (at your option) any later version.
  17 *
  18 *      Neither kernel concepts nor Nils Faerber admit liability nor provide
  19 *      warranty for any of this software. This material is provided
  20 *      "AS-IS" and at no charge.
  21 *
  22 *      (c) Copyright 2000      kernel concepts <nils@kernelconcepts.de>
  23 *                              developed for
  24 *                              Jentro AG, Haar/Munich (Germany)
  25 *
  26 *      TCO timer driver for NV chipsets
  27 *      based on softdog.c by Alan Cox <alan@redhat.com>
  28 */
  29
  30/*
  31 * Some address definitions for the TCO
  32 */
  33
  34#define TCO_RLD(base)   ((base) + 0x00) /* TCO Timer Reload and Current Value */
  35#define TCO_TMR(base)   ((base) + 0x01) /* TCO Timer Initial Value      */
  36
  37#define TCO_STS(base)   ((base) + 0x04) /* TCO Status Register          */
  38/*
  39 * TCO Boot Status bit: set on TCO reset, reset by software or standby
  40 * power-good (survives reboots), unfortunately this bit is never
  41 * set.
  42 */
  43#  define TCO_STS_BOOT_STS      (1 << 9)
  44/*
  45 * first and 2nd timeout status bits, these also survive a warm boot,
  46 * and they work, so we use them.
  47 */
  48#  define TCO_STS_TCO_INT_STS   (1 << 1)
  49#  define TCO_STS_TCO2TO_STS    (1 << 10)
  50#  define TCO_STS_RESET         (TCO_STS_BOOT_STS | TCO_STS_TCO2TO_STS | \
  51                                 TCO_STS_TCO_INT_STS)
  52
  53#define TCO_CNT(base)   ((base) + 0x08) /* TCO Control Register */
  54#  define TCO_CNT_TCOHALT       (1 << 12)
  55
  56#define MCP51_SMBUS_SETUP_B 0xe8
  57#  define MCP51_SMBUS_SETUP_B_TCO_REBOOT (1 << 25)
  58
  59/*
  60 * The SMI_EN register is at the base io address + 0x04,
  61 * while TCOBASE is + 0x40.
  62 */
  63#define MCP51_SMI_EN(base)      ((base) - 0x40 + 0x04)
  64#  define MCP51_SMI_EN_TCO      ((1 << 4) | (1 << 5))
  65
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