linux/drivers/pinctrl/pinctrl-tegra30.c
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   1/*
   2 * Pinctrl data for the NVIDIA Tegra30 pinmux
   3 *
   4 * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 */
  15
  16#include <linux/module.h>
  17#include <linux/of.h>
  18#include <linux/platform_device.h>
  19#include <linux/pinctrl/pinctrl.h>
  20#include <linux/pinctrl/pinmux.h>
  21
  22#include "pinctrl-tegra.h"
  23
  24/*
  25 * Most pins affected by the pinmux can also be GPIOs. Define these first.
  26 * These must match how the GPIO driver names/numbers its pins.
  27 */
  28#define _GPIO(offset)                           (offset)
  29
  30#define TEGRA_PIN_CLK_32K_OUT_PA0       _GPIO(0)
  31#define TEGRA_PIN_UART3_CTS_N_PA1       _GPIO(1)
  32#define TEGRA_PIN_DAP2_FS_PA2           _GPIO(2)
  33#define TEGRA_PIN_DAP2_SCLK_PA3         _GPIO(3)
  34#define TEGRA_PIN_DAP2_DIN_PA4          _GPIO(4)
  35#define TEGRA_PIN_DAP2_DOUT_PA5         _GPIO(5)
  36#define TEGRA_PIN_SDMMC3_CLK_PA6        _GPIO(6)
  37#define TEGRA_PIN_SDMMC3_CMD_PA7        _GPIO(7)
  38#define TEGRA_PIN_GMI_A17_PB0           _GPIO(8)
  39#define TEGRA_PIN_GMI_A18_PB1           _GPIO(9)
  40#define TEGRA_PIN_LCD_PWR0_PB2          _GPIO(10)
  41#define TEGRA_PIN_LCD_PCLK_PB3          _GPIO(11)
  42#define TEGRA_PIN_SDMMC3_DAT3_PB4       _GPIO(12)
  43#define TEGRA_PIN_SDMMC3_DAT2_PB5       _GPIO(13)
  44#define TEGRA_PIN_SDMMC3_DAT1_PB6       _GPIO(14)
  45#define TEGRA_PIN_SDMMC3_DAT0_PB7       _GPIO(15)
  46#define TEGRA_PIN_UART3_RTS_N_PC0       _GPIO(16)
  47#define TEGRA_PIN_LCD_PWR1_PC1          _GPIO(17)
  48#define TEGRA_PIN_UART2_TXD_PC2         _GPIO(18)
  49#define TEGRA_PIN_UART2_RXD_PC3         _GPIO(19)
  50#define TEGRA_PIN_GEN1_I2C_SCL_PC4      _GPIO(20)
  51#define TEGRA_PIN_GEN1_I2C_SDA_PC5      _GPIO(21)
  52#define TEGRA_PIN_LCD_PWR2_PC6          _GPIO(22)
  53#define TEGRA_PIN_GMI_WP_N_PC7          _GPIO(23)
  54#define TEGRA_PIN_SDMMC3_DAT5_PD0       _GPIO(24)
  55#define TEGRA_PIN_SDMMC3_DAT4_PD1       _GPIO(25)
  56#define TEGRA_PIN_LCD_DC1_PD2           _GPIO(26)
  57#define TEGRA_PIN_SDMMC3_DAT6_PD3       _GPIO(27)
  58#define TEGRA_PIN_SDMMC3_DAT7_PD4       _GPIO(28)
  59#define TEGRA_PIN_VI_D1_PD5             _GPIO(29)
  60#define TEGRA_PIN_VI_VSYNC_PD6          _GPIO(30)
  61#define TEGRA_PIN_VI_HSYNC_PD7          _GPIO(31)
  62#define TEGRA_PIN_LCD_D0_PE0            _GPIO(32)
  63#define TEGRA_PIN_LCD_D1_PE1            _GPIO(33)
  64#define TEGRA_PIN_LCD_D2_PE2            _GPIO(34)
  65#define TEGRA_PIN_LCD_D3_PE3            _GPIO(35)
  66#define TEGRA_PIN_LCD_D4_PE4            _GPIO(36)
  67#define TEGRA_PIN_LCD_D5_PE5            _GPIO(37)
  68#define TEGRA_PIN_LCD_D6_PE6            _GPIO(38)
  69#define TEGRA_PIN_LCD_D7_PE7            _GPIO(39)
  70#define TEGRA_PIN_LCD_D8_PF0            _GPIO(40)
  71#define TEGRA_PIN_LCD_D9_PF1            _GPIO(41)
  72#define TEGRA_PIN_LCD_D10_PF2           _GPIO(42)
  73#define TEGRA_PIN_LCD_D11_PF3           _GPIO(43)
  74#define TEGRA_PIN_LCD_D12_PF4           _GPIO(44)
  75#define TEGRA_PIN_LCD_D13_PF5           _GPIO(45)
  76#define TEGRA_PIN_LCD_D14_PF6           _GPIO(46)
  77#define TEGRA_PIN_LCD_D15_PF7           _GPIO(47)
  78#define TEGRA_PIN_GMI_AD0_PG0           _GPIO(48)
  79#define TEGRA_PIN_GMI_AD1_PG1           _GPIO(49)
  80#define TEGRA_PIN_GMI_AD2_PG2           _GPIO(50)
  81#define TEGRA_PIN_GMI_AD3_PG3           _GPIO(51)
  82#define TEGRA_PIN_GMI_AD4_PG4           _GPIO(52)
  83#define TEGRA_PIN_GMI_AD5_PG5           _GPIO(53)
  84#define TEGRA_PIN_GMI_AD6_PG6           _GPIO(54)
  85#define TEGRA_PIN_GMI_AD7_PG7           _GPIO(55)
  86#define TEGRA_PIN_GMI_AD8_PH0           _GPIO(56)
  87#define TEGRA_PIN_GMI_AD9_PH1           _GPIO(57)
  88#define TEGRA_PIN_GMI_AD10_PH2          _GPIO(58)
  89#define TEGRA_PIN_GMI_AD11_PH3          _GPIO(59)
  90#define TEGRA_PIN_GMI_AD12_PH4          _GPIO(60)
  91#define TEGRA_PIN_GMI_AD13_PH5          _GPIO(61)
  92#define TEGRA_PIN_GMI_AD14_PH6          _GPIO(62)
  93#define TEGRA_PIN_GMI_AD15_PH7          _GPIO(63)
  94#define TEGRA_PIN_GMI_WR_N_PI0          _GPIO(64)
  95#define TEGRA_PIN_GMI_OE_N_PI1          _GPIO(65)
  96#define TEGRA_PIN_GMI_DQS_PI2           _GPIO(66)
  97#define TEGRA_PIN_GMI_CS6_N_PI3         _GPIO(67)
  98#define TEGRA_PIN_GMI_RST_N_PI4         _GPIO(68)
  99#define TEGRA_PIN_GMI_IORDY_PI5         _GPIO(69)
 100#define TEGRA_PIN_GMI_CS7_N_PI6         _GPIO(70)
 101#define TEGRA_PIN_GMI_WAIT_PI7          _GPIO(71)
 102#define TEGRA_PIN_GMI_CS0_N_PJ0         _GPIO(72)
 103#define TEGRA_PIN_LCD_DE_PJ1            _GPIO(73)
 104#define TEGRA_PIN_GMI_CS1_N_PJ2         _GPIO(74)
 105#define TEGRA_PIN_LCD_HSYNC_PJ3         _GPIO(75)
 106#define TEGRA_PIN_LCD_VSYNC_PJ4         _GPIO(76)
 107#define TEGRA_PIN_UART2_CTS_N_PJ5       _GPIO(77)
 108#define TEGRA_PIN_UART2_RTS_N_PJ6       _GPIO(78)
 109#define TEGRA_PIN_GMI_A16_PJ7           _GPIO(79)
 110#define TEGRA_PIN_GMI_ADV_N_PK0         _GPIO(80)
 111#define TEGRA_PIN_GMI_CLK_PK1           _GPIO(81)
 112#define TEGRA_PIN_GMI_CS4_N_PK2         _GPIO(82)
 113#define TEGRA_PIN_GMI_CS2_N_PK3         _GPIO(83)
 114#define TEGRA_PIN_GMI_CS3_N_PK4         _GPIO(84)
 115#define TEGRA_PIN_SPDIF_OUT_PK5         _GPIO(85)
 116#define TEGRA_PIN_SPDIF_IN_PK6          _GPIO(86)
 117#define TEGRA_PIN_GMI_A19_PK7           _GPIO(87)
 118#define TEGRA_PIN_VI_D2_PL0             _GPIO(88)
 119#define TEGRA_PIN_VI_D3_PL1             _GPIO(89)
 120#define TEGRA_PIN_VI_D4_PL2             _GPIO(90)
 121#define TEGRA_PIN_VI_D5_PL3             _GPIO(91)
 122#define TEGRA_PIN_VI_D6_PL4             _GPIO(92)
 123#define TEGRA_PIN_VI_D7_PL5             _GPIO(93)
 124#define TEGRA_PIN_VI_D8_PL6             _GPIO(94)
 125#define TEGRA_PIN_VI_D9_PL7             _GPIO(95)
 126#define TEGRA_PIN_LCD_D16_PM0           _GPIO(96)
 127#define TEGRA_PIN_LCD_D17_PM1           _GPIO(97)
 128#define TEGRA_PIN_LCD_D18_PM2           _GPIO(98)
 129#define TEGRA_PIN_LCD_D19_PM3           _GPIO(99)
 130#define TEGRA_PIN_LCD_D20_PM4           _GPIO(100)
 131#define TEGRA_PIN_LCD_D21_PM5           _GPIO(101)
 132#define TEGRA_PIN_LCD_D22_PM6           _GPIO(102)
 133#define TEGRA_PIN_LCD_D23_PM7           _GPIO(103)
 134#define TEGRA_PIN_DAP1_FS_PN0           _GPIO(104)
 135#define TEGRA_PIN_DAP1_DIN_PN1          _GPIO(105)
 136#define TEGRA_PIN_DAP1_DOUT_PN2         _GPIO(106)
 137#define TEGRA_PIN_DAP1_SCLK_PN3         _GPIO(107)
 138#define TEGRA_PIN_LCD_CS0_N_PN4         _GPIO(108)
 139#define TEGRA_PIN_LCD_SDOUT_PN5         _GPIO(109)
 140#define TEGRA_PIN_LCD_DC0_PN6           _GPIO(110)
 141#define TEGRA_PIN_HDMI_INT_PN7          _GPIO(111)
 142#define TEGRA_PIN_ULPI_DATA7_PO0        _GPIO(112)
 143#define TEGRA_PIN_ULPI_DATA0_PO1        _GPIO(113)
 144#define TEGRA_PIN_ULPI_DATA1_PO2        _GPIO(114)
 145#define TEGRA_PIN_ULPI_DATA2_PO3        _GPIO(115)
 146#define TEGRA_PIN_ULPI_DATA3_PO4        _GPIO(116)
 147#define TEGRA_PIN_ULPI_DATA4_PO5        _GPIO(117)
 148#define TEGRA_PIN_ULPI_DATA5_PO6        _GPIO(118)
 149#define TEGRA_PIN_ULPI_DATA6_PO7        _GPIO(119)
 150#define TEGRA_PIN_DAP3_FS_PP0           _GPIO(120)
 151#define TEGRA_PIN_DAP3_DIN_PP1          _GPIO(121)
 152#define TEGRA_PIN_DAP3_DOUT_PP2         _GPIO(122)
 153#define TEGRA_PIN_DAP3_SCLK_PP3         _GPIO(123)
 154#define TEGRA_PIN_DAP4_FS_PP4           _GPIO(124)
 155#define TEGRA_PIN_DAP4_DIN_PP5          _GPIO(125)
 156#define TEGRA_PIN_DAP4_DOUT_PP6         _GPIO(126)
 157#define TEGRA_PIN_DAP4_SCLK_PP7         _GPIO(127)
 158#define TEGRA_PIN_KB_COL0_PQ0           _GPIO(128)
 159#define TEGRA_PIN_KB_COL1_PQ1           _GPIO(129)
 160#define TEGRA_PIN_KB_COL2_PQ2           _GPIO(130)
 161#define TEGRA_PIN_KB_COL3_PQ3           _GPIO(131)
 162#define TEGRA_PIN_KB_COL4_PQ4           _GPIO(132)
 163#define TEGRA_PIN_KB_COL5_PQ5           _GPIO(133)
 164#define TEGRA_PIN_KB_COL6_PQ6           _GPIO(134)
 165#define TEGRA_PIN_KB_COL7_PQ7           _GPIO(135)
 166#define TEGRA_PIN_KB_ROW0_PR0           _GPIO(136)
 167#define TEGRA_PIN_KB_ROW1_PR1           _GPIO(137)
 168#define TEGRA_PIN_KB_ROW2_PR2           _GPIO(138)
 169#define TEGRA_PIN_KB_ROW3_PR3           _GPIO(139)
 170#define TEGRA_PIN_KB_ROW4_PR4           _GPIO(140)
 171#define TEGRA_PIN_KB_ROW5_PR5           _GPIO(141)
 172#define TEGRA_PIN_KB_ROW6_PR6           _GPIO(142)
 173#define TEGRA_PIN_KB_ROW7_PR7           _GPIO(143)
 174#define TEGRA_PIN_KB_ROW8_PS0           _GPIO(144)
 175#define TEGRA_PIN_KB_ROW9_PS1           _GPIO(145)
 176#define TEGRA_PIN_KB_ROW10_PS2          _GPIO(146)
 177#define TEGRA_PIN_KB_ROW11_PS3          _GPIO(147)
 178#define TEGRA_PIN_KB_ROW12_PS4          _GPIO(148)
 179#define TEGRA_PIN_KB_ROW13_PS5          _GPIO(149)
 180#define TEGRA_PIN_KB_ROW14_PS6          _GPIO(150)
 181#define TEGRA_PIN_KB_ROW15_PS7          _GPIO(151)
 182#define TEGRA_PIN_VI_PCLK_PT0           _GPIO(152)
 183#define TEGRA_PIN_VI_MCLK_PT1           _GPIO(153)
 184#define TEGRA_PIN_VI_D10_PT2            _GPIO(154)
 185#define TEGRA_PIN_VI_D11_PT3            _GPIO(155)
 186#define TEGRA_PIN_VI_D0_PT4             _GPIO(156)
 187#define TEGRA_PIN_GEN2_I2C_SCL_PT5      _GPIO(157)
 188#define TEGRA_PIN_GEN2_I2C_SDA_PT6      _GPIO(158)
 189#define TEGRA_PIN_SDMMC4_CMD_PT7        _GPIO(159)
 190#define TEGRA_PIN_PU0                   _GPIO(160)
 191#define TEGRA_PIN_PU1                   _GPIO(161)
 192#define TEGRA_PIN_PU2                   _GPIO(162)
 193#define TEGRA_PIN_PU3                   _GPIO(163)
 194#define TEGRA_PIN_PU4                   _GPIO(164)
 195#define TEGRA_PIN_PU5                   _GPIO(165)
 196#define TEGRA_PIN_PU6                   _GPIO(166)
 197#define TEGRA_PIN_JTAG_RTCK_PU7         _GPIO(167)
 198#define TEGRA_PIN_PV0                   _GPIO(168)
 199#define TEGRA_PIN_PV1                   _GPIO(169)
 200#define TEGRA_PIN_PV2                   _GPIO(170)
 201#define TEGRA_PIN_PV3                   _GPIO(171)
 202#define TEGRA_PIN_DDC_SCL_PV4           _GPIO(172)
 203#define TEGRA_PIN_DDC_SDA_PV5           _GPIO(173)
 204#define TEGRA_PIN_CRT_HSYNC_PV6         _GPIO(174)
 205#define TEGRA_PIN_CRT_VSYNC_PV7         _GPIO(175)
 206#define TEGRA_PIN_LCD_CS1_N_PW0         _GPIO(176)
 207#define TEGRA_PIN_LCD_M1_PW1            _GPIO(177)
 208#define TEGRA_PIN_SPI2_CS1_N_PW2        _GPIO(178)
 209#define TEGRA_PIN_SPI2_CS2_N_PW3        _GPIO(179)
 210#define TEGRA_PIN_CLK1_OUT_PW4          _GPIO(180)
 211#define TEGRA_PIN_CLK2_OUT_PW5          _GPIO(181)
 212#define TEGRA_PIN_UART3_TXD_PW6         _GPIO(182)
 213#define TEGRA_PIN_UART3_RXD_PW7         _GPIO(183)
 214#define TEGRA_PIN_SPI2_MOSI_PX0         _GPIO(184)
 215#define TEGRA_PIN_SPI2_MISO_PX1         _GPIO(185)
 216#define TEGRA_PIN_SPI2_SCK_PX2          _GPIO(186)
 217#define TEGRA_PIN_SPI2_CS0_N_PX3        _GPIO(187)
 218#define TEGRA_PIN_SPI1_MOSI_PX4         _GPIO(188)
 219#define TEGRA_PIN_SPI1_SCK_PX5          _GPIO(189)
 220#define TEGRA_PIN_SPI1_CS0_N_PX6        _GPIO(190)
 221#define TEGRA_PIN_SPI1_MISO_PX7         _GPIO(191)
 222#define TEGRA_PIN_ULPI_CLK_PY0          _GPIO(192)
 223#define TEGRA_PIN_ULPI_DIR_PY1          _GPIO(193)
 224#define TEGRA_PIN_ULPI_NXT_PY2          _GPIO(194)
 225#define TEGRA_PIN_ULPI_STP_PY3          _GPIO(195)
 226#define TEGRA_PIN_SDMMC1_DAT3_PY4       _GPIO(196)
 227#define TEGRA_PIN_SDMMC1_DAT2_PY5       _GPIO(197)
 228#define TEGRA_PIN_SDMMC1_DAT1_PY6       _GPIO(198)
 229#define TEGRA_PIN_SDMMC1_DAT0_PY7       _GPIO(199)
 230#define TEGRA_PIN_SDMMC1_CLK_PZ0        _GPIO(200)
 231#define TEGRA_PIN_SDMMC1_CMD_PZ1        _GPIO(201)
 232#define TEGRA_PIN_LCD_SDIN_PZ2          _GPIO(202)
 233#define TEGRA_PIN_LCD_WR_N_PZ3          _GPIO(203)
 234#define TEGRA_PIN_LCD_SCK_PZ4           _GPIO(204)
 235#define TEGRA_PIN_SYS_CLK_REQ_PZ5       _GPIO(205)
 236#define TEGRA_PIN_PWR_I2C_SCL_PZ6       _GPIO(206)
 237#define TEGRA_PIN_PWR_I2C_SDA_PZ7       _GPIO(207)
 238#define TEGRA_PIN_SDMMC4_DAT0_PAA0      _GPIO(208)
 239#define TEGRA_PIN_SDMMC4_DAT1_PAA1      _GPIO(209)
 240#define TEGRA_PIN_SDMMC4_DAT2_PAA2      _GPIO(210)
 241#define TEGRA_PIN_SDMMC4_DAT3_PAA3      _GPIO(211)
 242#define TEGRA_PIN_SDMMC4_DAT4_PAA4      _GPIO(212)
 243#define TEGRA_PIN_SDMMC4_DAT5_PAA5      _GPIO(213)
 244#define TEGRA_PIN_SDMMC4_DAT6_PAA6      _GPIO(214)
 245#define TEGRA_PIN_SDMMC4_DAT7_PAA7      _GPIO(215)
 246#define TEGRA_PIN_PBB0                  _GPIO(216)
 247#define TEGRA_PIN_CAM_I2C_SCL_PBB1      _GPIO(217)
 248#define TEGRA_PIN_CAM_I2C_SDA_PBB2      _GPIO(218)
 249#define TEGRA_PIN_PBB3                  _GPIO(219)
 250#define TEGRA_PIN_PBB4                  _GPIO(220)
 251#define TEGRA_PIN_PBB5                  _GPIO(221)
 252#define TEGRA_PIN_PBB6                  _GPIO(222)
 253#define TEGRA_PIN_PBB7                  _GPIO(223)
 254#define TEGRA_PIN_CAM_MCLK_PCC0         _GPIO(224)
 255#define TEGRA_PIN_PCC1                  _GPIO(225)
 256#define TEGRA_PIN_PCC2                  _GPIO(226)
 257#define TEGRA_PIN_SDMMC4_RST_N_PCC3     _GPIO(227)
 258#define TEGRA_PIN_SDMMC4_CLK_PCC4       _GPIO(228)
 259#define TEGRA_PIN_CLK2_REQ_PCC5         _GPIO(229)
 260#define TEGRA_PIN_PEX_L2_RST_N_PCC6     _GPIO(230)
 261#define TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7  _GPIO(231)
 262#define TEGRA_PIN_PEX_L0_PRSNT_N_PDD0   _GPIO(232)
 263#define TEGRA_PIN_PEX_L0_RST_N_PDD1     _GPIO(233)
 264#define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2  _GPIO(234)
 265#define TEGRA_PIN_PEX_WAKE_N_PDD3       _GPIO(235)
 266#define TEGRA_PIN_PEX_L1_PRSNT_N_PDD4   _GPIO(236)
 267#define TEGRA_PIN_PEX_L1_RST_N_PDD5     _GPIO(237)
 268#define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6  _GPIO(238)
 269#define TEGRA_PIN_PEX_L2_PRSNT_N_PDD7   _GPIO(239)
 270#define TEGRA_PIN_CLK3_OUT_PEE0         _GPIO(240)
 271#define TEGRA_PIN_CLK3_REQ_PEE1         _GPIO(241)
 272#define TEGRA_PIN_CLK1_REQ_PEE2         _GPIO(242)
 273#define TEGRA_PIN_HDMI_CEC_PEE3         _GPIO(243)
 274#define TEGRA_PIN_PEE4                  _GPIO(244)
 275#define TEGRA_PIN_PEE5                  _GPIO(245)
 276#define TEGRA_PIN_PEE6                  _GPIO(246)
 277#define TEGRA_PIN_PEE7                  _GPIO(247)
 278
 279/* All non-GPIO pins follow */
 280#define NUM_GPIOS                               (TEGRA_PIN_PEE7 + 1)
 281#define _PIN(offset)                            (NUM_GPIOS + (offset))
 282
 283/* Non-GPIO pins */
 284#define TEGRA_PIN_CLK_32K_IN            _PIN(0)
 285#define TEGRA_PIN_CORE_PWR_REQ          _PIN(1)
 286#define TEGRA_PIN_CPU_PWR_REQ           _PIN(2)
 287#define TEGRA_PIN_JTAG_TCK              _PIN(3)
 288#define TEGRA_PIN_JTAG_TDI              _PIN(4)
 289#define TEGRA_PIN_JTAG_TDO              _PIN(5)
 290#define TEGRA_PIN_JTAG_TMS              _PIN(6)
 291#define TEGRA_PIN_JTAG_TRST_N           _PIN(7)
 292#define TEGRA_PIN_OWR                   _PIN(8)
 293#define TEGRA_PIN_PWR_INT_N             _PIN(9)
 294#define TEGRA_PIN_SYS_RESET_N           _PIN(10)
 295#define TEGRA_PIN_TEST_MODE_EN          _PIN(11)
 296
 297static const struct pinctrl_pin_desc tegra30_pins[] = {
 298        PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
 299        PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
 300        PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
 301        PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
 302        PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
 303        PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
 304        PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
 305        PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
 306        PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
 307        PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
 308        PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
 309        PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
 310        PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
 311        PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
 312        PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
 313        PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
 314        PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
 315        PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
 316        PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
 317        PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
 318        PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
 319        PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
 320        PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
 321        PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
 322        PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT5_PD0, "SDMMC3_DAT5 PD0"),
 323        PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, "SDMMC3_DAT4 PD1"),
 324        PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, "LCD_DC1 PD2"),
 325        PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, "SDMMC3_DAT6 PD3"),
 326        PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, "SDMMC3_DAT7 PD4"),
 327        PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
 328        PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
 329        PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
(TEGRA_PIN_VI_HSYNC_PD7, &quo" class="sref">_GPIO3200)
33 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321     _PIN_sre="L271" class="line" name="_PIN_sre="CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, _GPIO3201)
33 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     _PIN_PIN="L272" class="line" name="_PIN_PIN="CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, _GPIO3202)
33 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     _PIN_3IN="+code=PINCTRL_PIN" class="sre_3IN="CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _GPIO3203)
33 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324        TEGRA_PIN_SDMMC3_DAT7_PD4, _GPIO3204)
33 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315        TEGRA_PIN_VI_D1_PD5, _GPIO3205)
33 href="drivers/pinctrl/pinctrl-tegra30.c#L326" id="L326" class="line" name="L326"> 326     _PIN_L_P#L276" id="L276" class="lin_PIN_L_P#LCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO3206)
33 href="drivers/pinctrl/pinctrl-tegra30.c#L327" id="L327" class="line" name="L327"> 327     _PIN_L_Pclass="sref">NUM_GPIOS _PIN_L_PclCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, &" class="sref">_GPIO3207)
33 href="drivers/pinctrl/pinctrl-tegra30.c#L308" id="L308" class="line" name="L308"> 308        (TEGRA_PIN_VI_HSYNC_PD7, &quo" class="sref">_GPIO3208)
33 href="drivers/pinctrl/pinctrl-tegra30.c#L309" id="L309" class="line" name="L309"> 309        (TEGRA_PIN_SDMMC3_DAT4_PD1, _GPIO3209)
34 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ    (TEGRA_PIN_LCD_DC1_PD2, _GPIO3210)
34 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321     _PIN_ssreF"+code=PINCTRL_PIN" class="sre_ssreF"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _GPIO3211)
34 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     _PIN_1PINFL274" id="L274" class="lin   (TEGRA_PIN_SDMMC3_DAT7_PD4, _GPIO3212)
34 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     _PIN_13INFL275" id="L275" class="lin   (TEGRA_PIN_VI_D1_PD5, _GPIO3213)
34 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324        TEGRA_PIN_VI_VSYNC_PD6, _GPIO3214)
34 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315        NUM_GPIOS _PIN_1L_PFlCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _GPIO3215)
34 href="drivers/pinctrl/pinctrl-tegra30.c#L306" id="L306" class="line" name="L306"> 306        TEGRA_PIN_VI_HSYNC_PD7, _GPIO3216)
34 href="drivers/pinctrl/pinctrl-tegra30.c#L307" id="L307" class="line" name="L307"> 307        TEGRA_PIN_SDMMC3_DAT4_PD1, &" class="sref">_GPIO3217)
34 href="drivers/pinctrl/pinctrl-tegra30.c#L318" id="L318" class="line" name="L318"> 318      PIN__PING"L272" class="line" name=" PIN__PING"CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, &quo" class="sref">_GPIO3218)
34 href="drivers/pinctrl/pinctrl-tegra30.c#L319" id="L319" class="line" name="L319"> 319      PIN__3ING"+code=PINCTRL_PIN" class= PIN__3ING"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _GPIO3219)
35 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ _PIN__L_PGde=PINCTRL_PIN" class="srefPIN__L_PGdCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, _GPIO3220)
35 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321        TEGRA_PIN_VI_D1_PD5, _GPIO3221)
35 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     _PIN__6_PGL276" id="L276" class="lin_PIN__6_PGLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO3222)
35 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     _PIN__7_PG"+code=PINCTRL_PIN" class="sre__7_PG"CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _GPIO3223)
35 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324     _PIN__8_PH="+code=PINCTRL_PIN" class="sreD8_PH=CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _GPIO3224)
35 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     _PIN__9_PH="+code=PINCTRL_PIN" class="sre_9_PH=CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, _GPIO3225)
35 href="drivers/pinctrl/pinctrl-tegra30.c#L306" id="L306" class="line" name="L306"> 306        (TEGRA_PIN_LCD_DC1_PD2, _GPIO3226)
35 href="drivers/pinctrl/pinctrl-tegra30.c#L307" id="L307" class="line" name="L307"> 307        (TEGRA_PIN_SDMMC3_DAT6_PD3, &" class="sref">_GPIO3227)
35 href="drivers/pinctrl/pinctrl-tegra30.c#L318" id="L318" class="line" name="L318"> 318      PIN__1PINHde=PINCTRL_PIN" class="srefPIN__1PINHdCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, &quo" class="sref">_GPIO3228)
35 href="drivers/pinctrl/pinctrl-tegra30.c#L319" id="L319" class="line" name="L319"> 319      PIN__13INHde=PINCTRL_PIN" class="sref  (TEGRA_PIN_VI_D1_PD5, _GPIO3229)
36 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ _PIN__1L_PHL276" id="L276" class="lin_PIN__1L_PHLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO3230)
36 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321        (TEGRA_PIN_VI_HSYNC_PD7, _GPIO3231)
36 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     _PINWR>PINI="+code=PINCTRL_PIN" class="srWR>PINI=RL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _GPIO3232)
36 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     _PINO5I="+code=PINCTRL_PIN" class="srO5I=RL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, _GPIO3233)
36 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324     _PINDQS   "L272" class="line" name=" PINDQS   "RL_PIN(TEGRA_PIN_LCD_DC1_PD2, _GPIO3234)
36 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     _PINCS6I"+code=PINCTRL_PIN" class= PINCS6I"RL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _GPIO3235)
36 href="drivers/pinctrl/pinctrl-tegra30.c#L306" id="L306" class="line" name="L306"> 306        #defIde=PINCTRL_PIN" class="srefPIN/a>#defIdRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, _GPIO3236)
36 href="drivers/pinctrl/pinctrl-tegra30.c#L307" id="L307" class="line" name="L307"> 307        TEGRA_PIN_VI_D1_PD5, &" class="sref">_GPIO3237)
36 href="drivers/pinctrl/pinctrl-tegra30.c#L318" id="L318" class="line" name="L318"> 318      PINCS7#defIL276" id="L276" class="lin_PINCS7#defILRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, &quo" class="sref">_GPIO3238)
36 href="drivers/pinctrl/pinctrl-tegra30.c#L319" id="L319" class="line" name="L319"> 319      PINWAIT   "+code=PINCTRL_PIN" class="srefAIT   "RL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _GPIO3239)
37 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ _PINCS0#defJ="+code=PINCTRL_PIN" class="srCS0#defJ=RL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _GPIO3240)
37 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321     _PIN_EefJ"L271" class="line" name="_PIN_EefJ"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, _GPIO3241)
37 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     _PINCS1#defJ"L272" class="line" name=" PINCS1#defJ"RL_PIN(TEGRA_PIN_LCD_DC1_PD2, _GPIO3242)
37 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     _PINef">PINJ"+code=PINCTRL_PIN" class="sreef">PINJ"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _GPIO3243)
37 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324        PINJL274" id="L274" class="lin   PINJLCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, _GPIO3244)
37 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     _UART2NCTRL_PJde=PINCTRL_PIN" class="sre_UART2NCTRL_PJdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, _GPIO3245)
37 href="drivers/pinctrl/pinctrl-tegra30.c#L316" id="L316" class="line" name="L316"> 316        TEGRA_PIN_VI_VSYNC_PD6, _GPIO3246)
37 href="drivers/pinctrl/pinctrl-tegra30.c#L307" id="L307" class="line" name="L307"> 307        (TEGRA_PIN_VI_HSYNC_PD7, &" class="sref">_GPIO3247)
37 href="drivers/pinctrl/pinctrl-tegra30.c#L318" id="L318" class="line" name="L318"> 318      PIN__VRL_PK="+code=PINCTRL_PIN" class="sreDVRL_PK=CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, &quos="line" name="L278"> 273
37 href="drivers/pinctrl/pinctrl-tegra30.c#L319" id="L319" class="line" name="L319"> 319      PIN">PINK="+code=PINCTRL_PIN" class="sr">PINK=RL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, /* All 3on-GPIO pins follow */
38 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ _PINCS4RL_PK"L272" class="line" name=" PINCS4RL_PK"RL_PIN(TEGRA_PIN_LCD_DC1_PD2, TEGRA_PIN_PEE73+ 1)
38 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321        (TEGRA_PIN_SDMMC3_DAT6_PD3, offset<3a>))
38 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     _PINCS3RL_PKde=PINCTRL_PIN" class="srefPINCS3RL_PKdRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4,  283
38 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323      PDIFCTRL_PKode=PINCTRL_PIN" class="srePDIFCTRL_PKoRL_PIN(TEGRA_PIN_VI_D1_PD5, /* Non-GPIO pins */
38 href="drivers/pinctrl/pinctrl-tegra30.c#L304" id="L304" class="line" name="L304"> 304      PDIFCIL_PKode=PINCTRL_PIN" class="srePDIFCIL_PKoRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _PIN(0)
38 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     _PIN_19_PK"+code=PINCTRL_PIN" class="sre_ 9_PK"CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _PIN(1)
38 href="drivers/pinctrl/pinctrl-tegra30.c#L316" id="L316" class="line" name="L316"> 316     EGRA2_PL="+code=PINCTRL_PIN" classEGRA2_PL=CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _PIN(2)
38 href="drivers/pinctrl/pinctrl-tegra30.c#L327" id="L327" class="line" name="L327"> 327        <3_PL="+code=PINCTRL_PIN" class   <3_PL=CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, &PIN" class="sref">_PIN(3)
38 href="drivers/pinctrl/pinctrl-tegra30.c#L328" id="L328" class="line" name="L328"> 328        _L_PL"L272" class="line" name="   _L_PL"CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, &quoPIN" class="sref">_PIN(4)
38 href="drivers/pinctrl/pinctrl-tegra30.c#L329" id="L329" class="line" name="L329"> 329        DL_PL"+code=PINCTRL_PIN" class=   DL_PL"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _PIN(5)
39 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ EGRA6_PLde=PINCTRL_PIN" class="sreEGRA6_PLdCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, _PIN(6)
39 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321     EGRA7_PLef="+code=PINCTRL_PIN" class="7_PLeCTRL_PIN(TEGRA_PIN_VI_D1_PD5, _PIN(7)
39 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     EGRA8_PL"+code=PINCTRL_PIN" class="srA8_PL"CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _PIN(8)
39 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     EGRA9_PL"+code=PINCTRL_PIN" class="srA9_PL"CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _PIN(9)
39 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324        (TEGRA_PIN_VI_HSYNC_PD7, _PIN 315        (TEGRA_PIN_SDMMC3_DAT4_PD1, _PIN 326     _PIN_f">PM"L272" class="line" name="_PIN_1">PM"CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2,  293
39 href="drivers/pinctrl/pinctrl-tegra30.c#L327" id="L327" class="line" name="L327"> 327     _PIN_ 9_PM"+code=PINCTRL_PIN" class="sre_s9_PM"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, &"sref">tegra30_pins[3 = {
3a href="drivers/pinctrl/pinctrl-tegra30.c#L298" id="L298" class="line" name="L298"> 298     _PIN_P0_PML274" id="L274" class="lin   (TEGRA_PIN_SDMMC3_DAT7_PD4, &quoLK_32K_OUT PA0"),
3a href="drivers/pinctrl/pinctrl-tegra30.c#L299" id="L299" class="line" name="L299"> 299     _PIN_21_PML275" id="L275" class="lin   (TEGRA_PIN_VI_D1_PD5, "4ART3_CTS_N PA1"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L300" id="L300" class="line" name="L300"> 300     _PIN_22_PML276" id="L276" class="lin_PIN_22_PMLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, &q4ot;DAP2_FS PA2"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L301" id="L301" class="line" name="L301"> 301     _PIN_23_PMlass="sref">NUM_GPIOS _PIN_23_PMlCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, &quo4;DAP2_SCLK PA3"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L302" id="L302" class="line" name="L302"> 302        1ef">PN"L270" class="line" name="   1ef">PN"CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, &quo4;IN" class="sref">_PIN),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L303" id="L303" class="line" name="L303"> 303        1f">PINN"L271" class="line" name="   1f">PINN"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, &quo4;DAP2_DOUT PA5"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L304" id="L304" class="line" name="L304"> 304        1ePTRL_PN="+code=PINCTRL_PIN" class="s1ePTRL_PN=CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, "4SDMMC3_CLK PA6"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L305" id="L305" class="line" name="L305"> 305        1e>PINCTN+code=PINCTRL_PIN" class="sre1e>PINCTN+CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, "4SDMMC3_CMD PA7"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L306" id="L306" class="line" name="L306"> 306     _PINCS0#defNL274" id="L274" class="lin   (TEGRA_PIN_SDMMC3_DAT7_PD4, &q4ot;GMI_A17 PB0"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L307" id="L307" class="line" name="L307"> 307     _PINSPTRL_PNL275" id="L275" class="lin   (TEGRA_PIN_VI_D1_PD5, &q4osref">tegra30_pins[4n>),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L308" id="L308" class="line" name="L308"> 308        TEGRA_PIN_VI_VSYNC_PD6, &q4oK_32K_OUT PA0"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L309" id="L309" class="line" name="L309"> 309     HDN_GINL_PNlass="sref">NUM_GPIOS HDN_GINL_PNlCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, &qu4t;LCD_PCLK PB3"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L310" id="L310" class="line" name="L310"> 310     ULPIT7_PA7_POode=PINCTRL_PIN" class="sreLPIT7_PA7_POoCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, &q4DMMC3_DAT3 PB4"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L311" id="L311" class="line" name="L311"> 311     _LPIT7_PA0_PO"L271" class="line" name="_LPIT7_PA0_PO"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, "4DMMC3_DAT2 PB5"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L312" id="L312" class="line" name="L312"> 312     _LPIT7_PA1_PO+code=PINCTRL_PIN" class="sLPIT7_PA1_PO+CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, "4DMMC3_DAT1 PB6"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L313" id="L313" class="line" name="L313"> 313     _LPIT7_PA2_PO+code=PINCTRL_PIN" class="sLPIT7_PA2_PO+CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, "4DMMC3_DAT0 PB7"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L314" id="L314" class="line" name="L314"> 314      LPIT7_PA3_POL274" id="L274" class="lin LPIT7_PA3_POLCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, "4ART3_RTS_N PC0"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     _LPIT7_PA4_POde=PINCTRL_PIN" class="sre_LPIT7_PA4_POdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, &qu4t;LCD_PWR1 PC1"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L316" id="L316" class="line" name="L316"> 316      LPIT7_PA5_POL276" id="L276" class="lin LPIT7_PA5_POLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, &quo4;UART2_TXD PC2"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L317" id="L317" class="line" name="L317"> 317      LPIT7_PA6_POlass="sref">NUM_GPIOS  LPIT7_PA6_POlCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, &q4;UART2_RXD PC3"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L318" id="L318" class="line" name="L318"> 318        3ef">PP"L270" class="line" name="   3ef">PP"CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, &q4N1_I2C_SCL PC4"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L319" id="L319" class="line" name="L319"> 319        3e">PINP"L271" class="line" name="   3e">PINP"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, "G4N1_I2C_SDA PC5"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L320" id="L320" class="line" name="L320"> 320        3ePTRL_PP="+code=PINCTRL_PIN" class="s3ePTRL_PP=CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, &qu4t;LCD_PWR2 PC6"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321        3e>PINCTP+code=PINCTRL_PIN" class="sre3e>PINCTP+CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, &qu4t;GMI_WP_N PC7"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322        4ef">PPL274" id="L274" class="lin   4ef">PPLCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, "4DMMC3_DAT5 PD0"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323        4e">PINPde=PINCTRL_PIN" class="sre   4e">PINPdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "4DMMC3_DAT4 PD1"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324        4ePTRL_PPL276" id="L276" class="lin   4ePTRL_PPLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, &q4ot;LCD_DC1 PD2"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L325" id="L325" class="line" name="L325"> 325        4e>PINCTPlass="sref">NUM_GPIOS    4e>PINCTPlCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "4DMMC3_DAT6 PD3"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L326" id="L326" class="line" name="L326"> 326     KB_COL0_PQ"L270" class="line" name="KB_COL0_PQ"CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, &quo4DMMC3_DAT7 PD4"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L327" id="L327" class="line" name="L327"> 327     KB_COL1_PQ"L271" class="line" name="KB_COL1_PQ"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, &q4quot;VI_D1 PD5"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L328" id="L328" class="line" name="L328"> 328     KB_COL2_PQ="+code=PINCTRL_PIN" classKB_COL2_PQ=CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, &q4t;VI_VSYNC PD6"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L329" id="L329" class="line" name="L329"> 329     KB_COL3_PQ+code=PINCTRL_PIN" class="KB_COL3_PQ+CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, &qu4t;VI_HSYNC PD7"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ KB_COL4_PQL274" id="L274" class="linKB_COL4_PQLCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, &qu4" class="sref">_GPIO4200)
43 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321     KB_COL5_PQde=PINCTRL_PIN" class="sreKB_COL5_PQdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, _GPIO4201)
43 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     KB_COL6_PQL276" id="L276" class="linKB_COL6_PQLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO4202)
43 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     KB_COL7_PQlass="sref">NUM_GPIOS KB_COL7_PQlCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _GPIO4203)
43 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324     KB_ROW0_PR"L270" class="line" name="KB_ROW0_PR"CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, &q4" class="sref">_GPIO4204)
43 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     KB_ROW1_PR"L271" class="line" name="KB_ROW1_PR"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, _GPIO4205)
43 href="drivers/pinctrl/pinctrl-tegra30.c#L326" id="L326" class="line" name="L326"> 326     KB_ROW2_PR="+code=PINCTRL_PIN" classKB_ROW2_PR=CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, _GPIO4206)
43 href="drivers/pinctrl/pinctrl-tegra30.c#L327" id="L327" class="line" name="L327"> 327     KB_ROW3_PR+code=PINCTRL_PIN" class="KB_ROW3_PR+CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, &q4" class="sref">_GPIO4207)
43 href="drivers/pinctrl/pinctrl-tegra30.c#L308" id="L308" class="line" name="L308"> 308     KB_ROW4_PRL274" id="L274" class="linKB_ROW4_PRLCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, &q4" class="sref">_GPIO4208)
43 href="drivers/pinctrl/pinctrl-tegra30.c#L309" id="L309" class="line" name="L309"> 309     KB_ROW5_PRde=PINCTRL_PIN" class="sreKB_ROW5_PRdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, _GPIO4209)
44 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ KB_ROW6_PRL276" id="L276" class="linKB_ROW6_PRLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO4210)
44 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321     KB_ROW7_PRlass="sref">NUM_GPIOS KB_ROW7_PRlCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _GPIO4211)
44 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     KB_ROW8_PS"L270" class="line" name="KB_ROW8_PS"CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _GPIO4212)
44 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     KB_ROW9_PS"L271" class="line" name="KB_ROW9_PS"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, _GPIO4213)
44 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324     KB_ROW10_PS="+code=PINCTRL_PIN" classKB_ROW10_PS=CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, _GPIO4214)
44 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     KB_ROW11_PS+code=PINCTRL_PIN" class="KB_ROW11_PS+CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _GPIO4215)
44 href="drivers/pinctrl/pinctrl-tegra30.c#L306" id="L306" class="line" name="L306"> 306     KB_ROW12_PSL274" id="L274" class="linKB_ROW12_PSLCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, _GPIO4216)
44 href="drivers/pinctrl/pinctrl-tegra30.c#L307" id="L307" class="line" name="L307"> 307     KB_ROW13_PSde=PINCTRL_PIN" class="sreKB_ROW13_PSdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, &q4" class="sref">_GPIO4217)
44 href="drivers/pinctrl/pinctrl-tegra30.c#L318" id="L318" class="line" name="L318"> 318     KB_ROW14_PSL276" id="L276" class="linKB_ROW14_PSLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, &q4" class="sref">_GPIO4218)
44 href="drivers/pinctrl/pinctrl-tegra30.c#L319" id="L319" class="line" name="L319"> 319     KB_ROW15_PSlass="sref">NUM_GPIOS KB_ROW15_PSlCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _GPIO4219)
45 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ VI_PPINCTT="+code=PINCTRL_PIN" classEGRPPINCTT=CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _GPIO4220)
45 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321     EGRMPINCTT="+code=PINCTRL_PIN" class   MPINCTT=CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, _GPIO4221)
45 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     EGRA10_PT"L272" class="line" name="   _10_PT"CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, _GPIO4222)
45 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     EGR__1_PT"+code=PINCTRL_PIN" class=   D_1_PT"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _GPIO4223)
45 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324     EGR_0_PTde=PINCTRL_PIN" class="sreEGRA0_PTdCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, _GPIO4224)
45 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     _EN2_I2Ce_SC_PTde=PINCTRL_PIN" class="srefEN2_I2Ce_SC_PTdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, _GPIO4225)
45 href="drivers/pinctrl/pinctrl-tegra30.c#L306" id="L306" class="line" name="L306"> 306      EN2_I2Ce_D>  TL276" id="L276" class="lin_EN2_I2Ce_D>  TLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO4226)
45 href="drivers/pinctrl/pinctrl-tegra30.c#L307" id="L307" class="line" name="L307"> 307     SDMMC4_CMD  Tlass="sref">NUM_GPIOS SDMMC4_CMD  TlCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, &q4" class="sref">_GPIO4227)
45 href="drivers/pinctrl/pinctrl-tegra30.c#L318" id="L318" class="line" name="L318"> 318     PU="+code=PINCTRL_PIN" classPU=CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, &q4" class="sref">_GPIO4228)
45 href="drivers/pinctrl/pinctrl-tegra30.c#L319" id="L319" class="line" name="L319"> 319     PU="+code=PINCTRL_PIN" classPU=CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, _GPIO4229)
46 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ PU"L272" class="line" name="PU"CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, _GPIO4230)
46 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321     PU"+code=PINCTRL_PIN" class=PU"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _GPIO4231)
46 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     PUde=PINCTRL_PIN" class="srePUdCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, _GPIO4232)
46 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     PUde=PINCTRL_PIN" class="srePUdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, _GPIO4233)
46 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324     PUL276" id="L276" class="linPULCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO4234)
46 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     JTAG_RTCNCTUlass="sref">NUM_GPIOS JTAG_RTCNCTUlCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO4235)
46 href="drivers/pinctrl/pinctrl-tegra30.c#L306" id="L306" class="line" name="L306"> 306     PV="+code=PINCTRL_PIN" classPV=CTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, _GPIO4236)
46 href="drivers/pinctrl/pinctrl-tegra30.c#L307" id="L307" class="line" name="L307"> 307     PV="+code=PINCTRL_PIN" classPV=CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, &q4" class="sref">_GPIO4237)
46 href="drivers/pinctrl/pinctrl-tegra30.c#L318" id="L318" class="line" name="L318"> 318     PV"L272" class="line" name="PV"CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, &q4" class="sref">_GPIO4238)
46 href="drivers/pinctrl/pinctrl-tegra30.c#L319" id="L319" class="line" name="L319"> 319     PV"+code=PINCTRL_PIN" class=PV"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _GPIO4239)
47 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ DDCe_SC_PVL274" id="L274" class="lin DCe_SC_PVLCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _GPIO4240)
47 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321      DCe_D>  Vde=PINCTRL_PIN" class="sre DCe_D>  VdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, _GPIO4241)
47 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     CRTeef">PINVL276" id="L276" class="linCRTeef">PINVLCTRL_PIN(P PV_PD6" class="sref">TEGRA_PIN_VI_VSYNC_PD6, _GPIO4242)
47 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     CRTeef">PINVlass="sref">NUM_GPIOS CRTeef">PINVlCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO4243)
47 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324        (TEGRA_PIN_VI_VSYNC_PD6, _GPIO4244)
47 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315        (TEGRA_PIN_SDMMC3_DAT4_PD1, _GPIO4245)
47 href="drivers/pinctrl/pinctrl-tegra30.c#L316" id="L316" class="line" name="L316"> 316     SPI2(TEGRA_PIN_LCD_DC1_PD2, _GPIO4246)
47 href="drivers/pinctrl/pinctrl-tegra30.c#L307" id="L307" class="line" name="L307"> 307     SPI2(TEGRA_PIN_SDMMC3_DAT6_PD3, &q4" class="sref">_GPIO4247)
47 href="drivers/pinctrl/pinctrl-tegra30.c#L318" id="L318" class="line" name="L318"> 318     CLK1CTRL_PWL274" id="L274" class="linCLK1CTRL_PWLCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, &q4s="line" name="L278"> 274
47 href="drivers/pinctrl/pinctrl-tegra30.c#L319" id="L319" class="line" name="L319"> 319     CLK2CTRL_PWde=PINCTRL_PIN" class="sreCLK2CTRL_PWdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, /* All 4on-GPIO pins follow */
48 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ _UAR3_TXD_PWL276" id="L276" class="lin   <3_TXD_PWLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, TEGRA_PIN_PEE74+ 1)
48 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321        <3_RXD_PWlass="sref">NUM_GPIOS    <3_RXD_PWlCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, offset<4a>))
48 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     SPI2(TEGRA_PIN_VI_VSYNC_PD6,  284
48 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323      PI2(TEGRA_PIN_SDMMC3_DAT4_PD1, /* Non-GPIO pins */
48 href="drivers/pinctrl/pinctrl-tegra30.c#L304" id="L304" class="line" name="L304"> 304      PI2(TEGRA_PIN_LCD_DC1_PD2, _PIN(0)
48 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     SPI2(TEGRA_PIN_SDMMC3_DAT6_PD3, _PIN(1)
48 href="drivers/pinctrl/pinctrl-tegra30.c#L316" id="L316" class="line" name="L316"> 316     SPI1TEGRA_PIN_SDMMC3_DAT6_PD3, _PIN(2)
48 href="drivers/pinctrl/pinctrl-tegra30.c#L327" id="L327" class="line" name="L327"> 327     SPI1TEGRA_PIN_VI_D1_PD5, &q4PIN" class="sref">_PIN(3)
48 href="drivers/pinctrl/pinctrl-tegra30.c#L328" id="L328" class="line" name="L328"> 328     SPI1TEGRA_PIN_VI_VSYNC_PD6, &q4PIN" class="sref">_PIN(4)
48 href="drivers/pinctrl/pinctrl-tegra30.c#L329" id="L329" class="line" name="L329"> 329     SPI1NUM_GPIOS SPI1(TEGRA_PIN_VI_VSYNC_PD6, _PIN(5)
49 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ _LPITPINCTYode=PINCTRL_PIN" class="sreLPITPINCTYoCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _PIN(6)
49 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321     _LPIT7IRCTY"L271" class="line" name="_LPIT7IRCTY"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, _PIN(7)
49 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322      LPITNXL_PY+code=PINCTRL_PIN" class="sLPITNXL_PY+CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, _PIN(8)
49 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323      LPITSTP_PY+code=PINCTRL_PIN" class="sLPITSTP_PY+CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _PIN(9)
49 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324     SDMMC1T7_P3_PYL274" id="L274" class="linSDMMC1T7_P3_PYLCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _PIN 315     SDMMC1T7_P2_PYde=PINCTRL_PIN" class="sreSDMMC1T7_P2_PYdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, _PIN 326     SDMMC1T7_P1_PYode=PINCTRL_PIN" class="sreDMMC1T7_P1_PYoCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6,  294
49 href="drivers/pinctrl/pinctrl-tegra30.c#L327" id="L327" class="line" name="L327"> 327     SDMMC1T7_P0_PYlass="sref">NUM_GPIOS SDMMC1T7_P0_PYlCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, &q4"sref">tegra30_pins[4 = {
4a href="drivers/pinctrl/pinctrl-tegra30.c#L298" id="L298" class="line" name="L298"> 298     SDMMC1TPINCTZ"L270" class="line" name="SDMMC1TPINCTZ"CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, &q4LK_32K_OUT PA0"),
4a href="drivers/pinctrl/pinctrl-tegra30.c#L299" id="L299" class="line" name="L299"> 299     SDMMC1TPMD  Z"L271" class="line" name=" DMMC1TPMD  Z"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, "5ART3_CTS_N PA1"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L300" id="L300" class="line" name="L300"> 300     _PINS">PINZ"L272" class="line" name="_PINS">PINZ"CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, &q5ot;DAP2_FS PA2"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L301" id="L301" class="line" name="L301"> 301     _PINWR#defZ"+code=PINCTRL_PIN" class="sreWR#defZ"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, &quo5;DAP2_SCLK PA3"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L302" id="L302" class="line" name="L302"> 302        TEGRA_PIN_SDMMC3_DAT6_PD3, &quo5;IN" class="sref">_PIN),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L303" id="L303" class="line" name="L303"> 303     SYSTPINCREQCTZde=PINCTRL_PIN" class="sreSYSTPINCREQCTZdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, &quo5;DAP2_DOUT PA5"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L304" id="L304" class="line" name="L304"> 304     PWR#I2Ce_SC_PZL276" id="L276" class="linPWR#I2Ce_SC_PZLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5SDMMC3_CLK PA6"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L305" id="L305" class="line" name="L305"> 305     PWR#I2Ce_D>  Zlass="sref">NUM_GPIOS PWR#I2Ce_D>  ZlCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5SDMMC3_CMD PA7"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L306" id="L306" class="line" name="L306"> 306     SDMMC4_7_P0_PAA"L270" class="line" name="SDMMC4_7_P0_PAA"CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5S="line" name="L296"> 295n>),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L307" id="L307" class="line" name="L307"> 307     SDMMC4T7_P1_PAA"L271" class="line" name=" DMMC4T7_P1_PAA"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, "5Ssref">tegra30_pins[5n>),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L308" id="L308" class="line" name="L308"> 308     SDMMC4T7_P2_PAA"L272" class="line" name="SDMMC4T7_P2_PAA"CTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, "5SK_32K_OUT PA0"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L309" id="L309" class="line" name="L309"> 309     SDMMC4T7_P3_PAA"+code=PINCTRL_PIN" class=SDMMC4T7_P3_PAA"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, &qu5t;LCD_PCLK PB3"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L310" id="L310" class="line" name="L310"> 310     SDMMC4T7_P4_PAAL274" id="L274" class="linSDMMC4T7_P4_PAALCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, &q5DMMC3_DAT3 PB4"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L311" id="L311" class="line" name="L311"> 311     SDMMC4T7_P5_PAAde=PINCTRL_PIN" class="sreSDMMC4T7_P5_PAAdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "5DMMC3_DAT2 PB5"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L312" id="L312" class="line" name="L312"> 312     SDMMC4T7_P6_PAAode=PINCTRL_PIN" class="sreDMMC4T7_P6_PAAoCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5DMMC3_DAT1 PB6"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L313" id="L313" class="line" name="L313"> 313     SDMMC4T7_P7_PAAlass="sref">NUM_GPIOS SDMMC4_7_P7_PAAlCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5DMMC3_DAT0 PB7"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L314" id="L314" class="line" name="L314"> 314     PBB="+code=PINCTRL_PIN" classPBB=CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5ART3_RTS_N PC0"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     CAM#I2Ce_SC_PBB"L271" class="line" name="CAM#I2Ce_SC_PBB"CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5t;LCD_PWR1 PC1"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L316" id="L316" class="line" name="L316"> 316     CAM#I2Ce_D>  BB"L272" class="line" name="CAM#I2Ce_D>  BB"CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5;UART2_TXD PC2"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L317" id="L317" class="line" name="L317"> 317     PBB"+code=PINCTRL_PIN" class=PBB"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, "5;UART2_RXD PC3"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L318" id="L318" class="line" name="L318"> 318     PBBde=PINCTRL_PIN" class="srePBBdCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, "5N1_I2C_SCL PC4"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L319" id="L319" class="line" name="L319"> 319     PBBde=PINCTRL_PIN" class="srePBBdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "G5N1_I2C_SDA PC5"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L320" id="L320" class="line" name="L320"> 320     PBBL276" id="L276" class="linPBBLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, &qu5t;LCD_PWR2 PC6"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321     PBBlass="sref">NUM_GPIOS PBBlCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, &qu5t;GMI_WP_N PC7"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     CAM#MPINCTCC="+code=PINCTRL_PIN" classCAM#MPINCTCC=CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5DMMC3_DAT5 PD0"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     TCC="+code=PINCTRL_PIN" classPCC=CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5DMMC3_DAT4 PD1"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324     PCC"L272" class="line" name="PCC"CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, &q5ot;LCD_DC1 PD2"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L325" id="L325" class="line" name="L325"> 325     SDMMC4TRST_="PCC"+code=PINCTRL_PIN" class=SDMMC4TRST_="PCC"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, "5DMMC3_DAT6 PD3"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L326" id="L326" class="line" name="L326"> 326     SDMMC4_CINCTCCL274" id="L274" class="linSDMMC4TCINCTCCLCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, &quo5DMMC3_DAT7 PD4"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L327" id="L327" class="line" name="L327"> 327     CLK2CREQCTCCde=PINCTRL_PIN" class="sreCLK2CREQCTCCdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "5quot;VI_D1 PD5"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L328" id="L328" class="line" name="L328"> 328     PEX_L2TRST_="PCCL276" id="L276" class="linPEX_L2TRST_="PCCLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5t;VI_VSYNC PD6"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L329" id="L329" class="line" name="L329"> 329     PEX_L2TCLKREQC="PCClass="sref">NUM_GPIOS PEX_L2TCLKREQC="PCClCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, &qu5t;VI_HSYNC PD7"),
5a href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ PEX_L0_PRSNT_="PDD="+code=PINCTRL_PIN" classPEX_L0_PRSNT_="PDD=CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, &qu5" class="sref">_GPIO5200)
53 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321     PEX_L0_RST_="PDD="+code=PINCTRL_PIN" classPEX_L0_RST_="PDD=CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, &qu5" class="sref">_GPIO5201)
53 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     PEX_L0_CLKREQC="PDD"L272" class="line" name="PEX_L0_CLKREQC="PDD"CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5" class="sref">_GPIO5202)
53 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     PEX_WAKEC="PDD"+code=PINCTRL_PIN" class=PEX_WAKEC="PDD"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _GPIO5203)
53 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324     PEX_L1_PRSNT_="PDDde=PINCTRL_PIN" class="srePEX_L1_PRSNT_="PDDdCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, &q5" class="sref">_GPIO5204)
53 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     PEX_L1_RST_="PDDde=PINCTRL_PIN" class="srePEX_L1_RST_="PDDdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, _GPIO5205)
53 href="drivers/pinctrl/pinctrl-tegra30.c#L326" id="L326" class="line" name="L326"> 326     PEX_L1_CLKREQC="PDDL276" id="L276" class="linPEX_L1_CLKREQC="PDDLCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5206)
53 href="drivers/pinctrl/pinctrl-tegra30.c#L327" id="L327" class="line" name="L327"> 327     PEX_L2TPRSNT_="PDDlass="sref">NUM_GPIOS PEX_L2TPRSNT_="PDDlCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5" class="sref">_GPIO5207)
53 href="drivers/pinctrl/pinctrl-tegra30.c#L308" id="L308" class="line" name="L308"> 308     CLK3CTRL_PEE="+code=PINCTRL_PIN" classCLK3CTRL_PEE=CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5" class="sref">_GPIO5208)
53 href="drivers/pinctrl/pinctrl-tegra30.c#L309" id="L309" class="line" name="L309"> 309     CLK3CREQCTEE"L271" class="line" name="CLK3CREQCTEE"CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5209)
54 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ CLK1CREQCTEE"L272" class="line" name="CLK1CREQCTEE"CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5210)
54 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321     HDMI_CECCTEE"+code=PINCTRL_PIN" class=HDMI_CECCTEE"CTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _GPIO5211)
54 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     TEEde=PINCTRL_PIN" class="srePEEdCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, _GPIO5212)
54 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     PEEde=PINCTRL_PIN" class="srePEEdCTRL_PIN(TEGRA_PIN_VI_D1_PD5, _GPIO5213)
54 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324     PEEL276" id="L276" class="linPEELCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5214)
54 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     PEElass="sref">NUM_GPIOS PEElCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5215)
54 href="drivers/pinctrl/pinctrl-tegra30.c#L306" id="L306" class="line" name="L306"> 306     CINC32K_0.c#L306" id="L306     CINC32K_0.CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5216)
54 href="drivers/pinctrl/pinctrl-tegra30.c#L307" id="L307" class="line" name="L307"> 307     CORE PWR#REQc#L306" id="L306     CORE PWR#REQCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5" class="sref">_GPIO5217)
54 href="drivers/pinctrl/pinctrl-tegra30.c#L318" id="L318" class="line" name="L318"> 318     CPU PWR#REQc#L306" id="L306     CPU PWR#REQCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5" class="sref">_GPIO5218)
54 href="drivers/pinctrl/pinctrl-tegra30.c#L319" id="L319" class="line" name="L319"> 319     JTAG_TCKc#L306" id="L306     JTAG_TCKCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5219)
55 href="drivers/pinctrl/pinctrl-tegra30.c#L330" id="L3l-tegra30.EGRA_PIN_PEE5        PD1&qZ JTAG_TDIc#L306" id="L306     JTAG_TDICTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5220)
55 href="drivers/pinctrl/pinctrl-tegra30.c#L321" id="L321" class="line" name="L321"> 321     JTAG_TDOc#L306" id="L306     JTAG_TDOCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5221)
55 href="drivers/pinctrl/pinctrl-tegra30.c#L322" id="L322" class="line" name="L322"> 322     JTAG_TMSc#L306" id="L306     JTAG_TMSCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5222)
55 href="drivers/pinctrl/pinctrl-tegra30.c#L323" id="L323" class="line" name="L323"> 323     JTAG_TRST_=c#L306" id="L306     JTAG_TRST_=CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5223)
55 href="drivers/pinctrl/pinctrl-tegra30.c#L324" id="L324" class="line" name="L324"> 324     OWRc#L306" id="L306     OWRCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5224)
55 href="drivers/pinctrl/pinctrl-tegra30.c#L315" id="L315" class="line" name="L315"> 315     PWR#INT_=c#L306" id="L306     PWR#INT_=CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5225)
55 href="drivers/pinctrl/pinctrl-tegra30.c#L306" id="L306" class="line" name="L306"> 306     SYSTRESET_=c#L306" id="L306     SYSTRESET_=CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, _GPIO5226)
55 href="drivers/pinctrl/pinctrl-tegra30.c#L307" id="L307" class="line" name="L307"> 307     TEST_MODE_E=c#L306" id="L306     TEST_MODE_E=CTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "5" class="sref">_GPIO5227)
55 href};f">TEGRA_PIN_VI_VSYNC_PD6, "5" class="sref">_GPIO5228)
55 hreff">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5229)
56 hrefstatic const unsignedrs/pinctrl/pinctclkC32k_out_pa0_/a>sc#L306" id="L30clkC32k_out_pa0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5230)
56 href="drivers/pinctrl/pinct6     CINC32K_TRL_PA"L270" class="line" name="CINC32K_TRL_PA"CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5231)
56 href};f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5232)
56 hreff">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5233)
56 hrefstatic const unsignedrs/pinctrl/pinctuart3_cts_n_pa1_/a>sc#L306" id="L30uart3_cts_n_pa1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5234)
56 href="drivers/pinctrl/pinctne" name="   <3_CTS_="PA"L271" class="line" name="   <3_CTS_="PA"CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5235)
56 href};f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5236)
56 hreff">TEGRA_PIN_VI_VSYNC_PD6, "5" class="sref">_GPIO5237)
56 hrefstatic const unsignedrs/pinctrl/pinctdap2_fs_pa2_/a>sc#L306" id="L30dap2_fs_pa2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, "5" class="sref">_GPIO5238)
56 href="drivers/pinctrl/pinctne" name="DAP2_FS"PA"L272" class="line" name="DAP2_FS"PA"CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5239)
57 href};f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5240)
57 hreff">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5241)
57 hrefstatic const unsignedrs/pinctrl/pinctdap2_sclkCpa3_/a>sc#L306" id="L30dap2_sclkCpa3_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5242)
57 href="drivers/pinctrl/pinctne" name="DAP2_SCINCTA"+code=PINCTRL_PIN" class=DAP2_SCINCTA"CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5243)
57 href};f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5244)
57 hreff">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5245)
57 hrefstatic const unsignedrs/pinctrl/pinctdap2_din_pa4_/a>sc#L306" id="L30dap2_din_pa4_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO5246)
57 href="drivers/pinctrl/pinctIN" class=DAP2_">PINAL274" id="L274" class="linDAP2_">PINALCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, "5" class="sref">_GPIO5247)
57 href};f">TEGRA_PIN_VI_VSYNC_PD6, &q5s="line" name="L278"> 275
57 hreff">TEGRA_PIN_VI_VSYNC_PD6, /* All 5on-GPIO pins follow */
58 hrefstatic const unsignedrs/pinctrl/pinctdap2_dout_pa5_/a>sc#L306" id="L30dap2_dout_pa5_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, TEGRA_PIN_PEE75+ 1)
58 href="drivers/pinctrl/pinctclass="linDAP2_"TRL_PAde=PINCTRL_PIN" class="sreDAP2_"TRL_PAdCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, offset<5a>))
58 href};f">TEGRA_PIN_VI_VSYNC_PD6,  285
58 hreff">TEGRA_PIN_VI_VSYNC_PD6, /* Non-GPIO pins */
58 hrefstatic const unsignedrs/pinctrl/pinctsdmmc3_clkCpa6_/a>sc#L306" id="L30sdmmc3_clkCpa6_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(0)
58 href="drivers/pinctrl/pinctclass="linSDMMC3TCINCTAode=PINCTRL_PIN" class="sreDMMC3TCINCTAoCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(1)
58 href};f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(2)
58 hreff">TEGRA_PIN_VI_VSYNC_PD6, &q5PIN" class="sref">_PIN(3)
58 hrefstatic const unsignedrs/pinctrl/pinctsdmmc3_cmdCpa7_/a>sc#L306" id="L30sdmmc3_cmdCpa7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, &q5PIN" class="sref">_PIN(4)
58 href="drivers/pinctrl/pinct class="sreDMMC3TCMD  Alass="sref">NUM_GPIOS SDMMC3TCMD  AlCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(5)
59 href};f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(6)
59 hreff">TEGRA_PIN_VI_VSYNC_PD6, _PIN(7)
59 hrefstatic const unsignedrs/pinctrl/pinctgmi_a17_/b0_/a>sc#L306" id="L30gmi_a17_/b0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(8)
59 href="drivers/pinctrl/pinctGPIOS GMI_A17_PB="+code=PINCTRL_PIN" classGMI_A17_PB=CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(9)
59 href};f">TEGRA_PIN_VI_VSYNC_PD6, _PINTEGRA_PIN_VI_VSYNC_PD6, _PINsc#L306" id="L30gmi_a18_/b1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6,  295
59 href="drivers/pinctrl/pinctPIN" classGMI_A18_PB"L271" class="line" name="GMI_A18_PB"CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, &q5"sref">tegra30_pins[5 = {
59 href};f">TEGRA_PIN_VI_VSYNC_PD6, &q5LK_32K_OUT PA0"),
59 hreff">TEGRA_PIN_VI_VSYNC_PD6, "6ART3_CTS_N PA1"),
60 hrefstatic const unsignedrs/pinctrl/pinctlcdCpwr0_/b2_/a>sc#L306" id="L30lcdCpwr0_/b2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, &q6ot;DAP2_FS PA2"),
6a href="drivers/pinctrl/pinctne" name="   TEGRA_PIN_VI_VSYNC_PD6, &quo6;DAP2_SCLK PA3"),
60 href};f">TEGRA_PIN_VI_VSYNC_PD6, &quo6;IN" class="sref">_PIN),
60 hreff">TEGRA_PIN_VI_VSYNC_PD6, &quo6;DAP2_DOUT PA5"),
60 hrefstatic const unsignedrs/pinctrl/pinctlcdCpclkCpb3_/a>sc#L306" id="L30lcdCpclkCpb3_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, &quo6;N" class="sref">_PIN),
6a href="drivers/pinctrl/pinctne" name="_PINPCINCTB"+code=PINCTRL_PIN" class=_PINPCINCTB"CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, &quo6;N" class="sref">_PIN),
60 href};f">TEGRA_PIN_VI_VSYNC_PD6, "6S="line" name="L296"> 296n>),
60 hreff">TEGRA_PIN_VI_VSYNC_PD6, "6Ssref">tegra30_pins[6n>),
60 hrefstatic const unsignedrs/pinctrl/pinctsdmmc3_dat3_/b4_/a>sc#L306" id="L30sdmmc3_dat3_/b4_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, "6SK_32K_OUT PA0"),
6a href="drivers/pinctrl/pinctGPIOS SDMMC3T7_P3_PBde=PINCTRL_PIN" class="sreSDMMC3T7_P3_PBdCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, &qu6t;LCD_PCLK PB3"),
61 href};f">TEGRA_PIN_VI_VSYNC_PD6, &q6DMMC3_DAT3 PB4"),
61 hreff">TEGRA_PIN_VI_VSYNC_PD6, "6DMMC3_DAT2 PB5"),
61 hrefstatic const unsignedrs/pinctrl/pinctsdmmc3_dat2_/b5_/a>sc#L306" id="L30sdmmc3_dat2_/b5_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, "6DMMC3_DAT1 PB6"),
6a href="drivers/pinctrl/pinctclass="sreSDMMC3T7_P2_PBde=PINCTRL_PIN" class="sreSDMMC3T7_P2_PBdCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, &quo6DMMC3_DAT0 PB7"),
61 href};f">TEGRA_PIN_VI_VSYNC_PD6, "6ART3_RTS_N PC0"),
61 hreff">TEGRA_PIN_VI_VSYNC_PD6, "6t;LCD_PWR1 PC1"),
61 hrefstatic const unsignedrs/pinctrl/pinctsdmmc3_dat1_/b6_/a>sc#L306" id="L30sdmmc3_dat1_/b6_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, "6;UART2_TXD PC2"),
6a href="drivers/pinctrl/pinctclass="sreSDMMC3T7_P1_PBode=PINCTRL_PIN" class="sreDMMC3T7_P1_PBoCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, "6;UART2_RXD PC3"),
61 href};f">TEGRA_PIN_VI_VSYNC_PD6, "6N1_I2C_SCL PC4"),
61 hreff">TEGRA_PIN_VI_VSYNC_PD6, "G6N1_I2C_SDA PC5"),
62 hrefstatic const unsignedrs/pinctrl/pinctsdmmc3_dat0_/b7_/a>sc#L306" id="L30sdmmc3_dat0_/b7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, &qu6t;LCD_PWR2 PC6"),
6a href="drivers/pinctrl/pinct class="sreDMMC3T7_P0_PBlass="sref">NUM_GPIOS SDMMC3T7_P0_PBlCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, &qu6t;GMI_WP_N PC7"),
62 href};f">TEGRA_PIN_VI_VSYNC_PD6, "6DMMC3_DAT5 PD0"),
62 hreff">TEGRA_PIN_VI_VSYNC_PD6, "6DMMC3_DAT4 PD1"),
62 hrefstatic const unsignedrs/pinctrl/pinctuart3_rts_n_pc0_/a>sc#L306" id="L30uart3_rts_n_pc0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, "6ot;LCD_DC1 PD2"),
6a href="drivers/pinctrl/pinctne" name="   <3_RTS_="PC="+code=PINCTRL_PIN" class   <3_RTS_="PC=CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, "6DMMC3_DAT6 PD3"),
62 href};f">TEGRA_PIN_VI_VSYNC_PD6, &quo6DMMC3_DAT7 PD4"),
62 hreff">TEGRA_PIN_VI_VSYNC_PD6, "6quot;VI_D1 PD5"),
62 hrefstatic const unsignedrs/pinctrl/pinctlcdCpwr1_/c1_/a>sc#L306" id="L30lcdCpwr1_/c1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, "6t;VI_VSYNC PD6"),
6a href="drivers/pinctrl/pinctne" name="_PINPWR1_PC="+code=PINCTRL_PIN" class_PINPWR1_PC=CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, &qu6t;VI_HSYNC PD7"),
63 href};f">TEGRA_PIN_VI_VSYNC_PD6, &qu6" class="sref">_GPIO6200)
63 hreff">TEGRA_PIN_VI_VSYNC_PD6, &qu6" class="sref">_GPIO6201)
63 hrefstatic const unsignedrs/pinctrl/pinctuart2_txdCpc2_/a>sc#L306" id="L30uart2_txdCpc2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, "6" class="sref">_GPIO6202)
63 href="drivers/pinctrl/pinctPIN" class   <2_TXINPC+code=PINCTRL_PIN" class="s  <2_TXINPC+CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, "6" class="sref">_GPIO6203)
63 href};f">TEGRA_PIN_VI_VSYNC_PD6, &q6" class="sref">_GPIO6204)
63 hreff">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6205)
63 hrefstatic const unsignedrs/pinctrl/pinctuart2_rxdCpc3_/a>sc#L306" id="L30uart2_rxdCpc3_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, &quo6" class="sref">_GPIO6206)
63 href="drivers/pinctrl/pinctN" class="s  <2_RXINPC+code=PINCTRL_PIN" class="s  <2_RXINPC+CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, "6" class="sref">_GPIO6207)
63 href};f">TEGRA_PIN_VI_VSYNC_PD6, "6" class="sref">_GPIO6208)
63 hreff">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6209)
64 hrefstatic const unsignedrs/pinctrl/pinctgen1_i2c_sclCpc4_/a>sc#L306" id="L30gen1_i2c_sclCpc4_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6210)
64 href="drivers/pinctrl/pinctne" name="GEN1#I2Ce_SC_PCL274" id="L274" class="linGEN1#I2Ce_SC_PCLCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6211)
64 href};f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6212)
64 hreff">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6213)
64 hrefstatic const unsignedrs/pinctrl/pinctgen1_i2c_sdaCpc5_/a>sc#L306" id="L30gen1_i2c_sdaCpc5_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, &q6" class="sref">_GPIO6214)
64 href="drivers/pinctrl/pinctclass="linGEN1#I2Ce_D>  Cde=PINCTRL_PIN" class="sreGEN1#I2Ce_D>  CdCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6215)
64 href};f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6216)
64 hreff">TEGRA_PIN_VI_VSYNC_PD6, "6" class="sref">_GPIO6217)
64 hrefstatic const unsignedrs/pinctrl/pinctlcdCpwr2_/c6_/a>sc#L306" id="L30lcdCpwr2_/c6_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, "6" class="sref">_GPIO6218)
64 href="drivers/pinctrl/pinctPIN" class_PINPWR2  Code=PINCTRL_PIN" class="sr_PINPWR2  CoCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6219)
65 href};f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6220)
65 hreff">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6221)
65 hrefstatic const unsignedrs/pinctrl/pinctgmi_wp_n_pc7_/a>sc#L306" id="L30gmi_wp_n_pc7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6222)
65 href="drivers/pinctrl/pinctne" name="GMI_WP_="PClass="sref">NUM_GPIOS GMI_WP_="PClCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6223)
65 href};f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6224)
65 hreff">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6225)
65 hrefstatic const unsignedrs/pinctrl/pinctsdmmc3_dat5_/d0_/a>sc#L306" id="L30sdmmc3_dat5_/d0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6226)
65 href="drivers/pinctrl/pinctGPIOS SDMMC3T7_P5_PD="+code=PINCTRL_PIN" classSDMMC3T7_P5_PD=CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, "6" class="sref">_GPIO6227)
65 href};f">TEGRA_PIN_VI_VSYNC_PD6, "6" class="sref">_GPIO6228)
65 hreff">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6229)
66 hrefstatic const unsignedrs/pinctrl/pinctsdmmc3_dat4_/d1_/a>sc#L306" id="L30sdmmc3_dat4_/d1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6230)
66 href="drivers/pinctrl/pinct6     SDMMC3T7_P4_PD"L271" class="line" name=" DMMC3T7_P4_PD"CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6231)
66 href};f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6232)
66 hreff">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6233)
66 hrefstatic const unsignedrs/pinctrl/pinctlcdCdc1_/d2_/a>sc#L306" id="L30lcdCdc1_/d2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6234)
66 href="drivers/pinctrl/pinctne" name="_PINDC1_PD"L272" class="line" name="_PINDC1_PD"CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6235)
66 href};f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6236)
66 hreff">TEGRA_PIN_VI_VSYNC_PD6, "6" class="sref">_GPIO6237)
66 hrefstatic const unsignedrs/pinctrl/pinctsdmmc3_dat6_/d3_/a>sc#L306" id="L30sdmmc3_dat6_/d3_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, "6" class="sref">_GPIO6238)
66 href="drivers/pinctrl/pinctne" name=" DMMC3T7_P6_PD"+code=PINCTRL_PIN" class=SDMMC3T7_P6_PD"CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6239)
67 href};f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6240)
67 hreff">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6241)
67 hrefstatic const unsignedrs/pinctrl/pinctsdmmc3_dat7_/d4_/a>sc#L306" id="L30sdmmc3_dat7_/d4_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6242)
67 href="drivers/pinctrl/pinctne" name="SDMMC3T7_P7_PDde=PINCTRL_PIN" class="sreSDMMC3T7_P7_PDdCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6243)
67 href};f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6244)
67 hreff">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6245)
67 hrefstatic const unsignedrs/pinctrl/pinctvi_d1_/d5_/a>sc#L306" id="L30vi_d1_/d5_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _GPIO6246)
67 href="drivers/pinctrl/pinctIN" class=VI_D1_PDde=PINCTRL_PIN" class="sreVI_D1_PDdCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, "6" class="sref">_GPIO6247)
67 href};f">TEGRA_PIN_VI_VSYNC_PD6, &q6s="line" name="L278"> 276
67 hreff">TEGRA_PIN_VI_VSYNC_PD6, /* All 6on-GPIO pins follow */
68 hrefstatic const unsignedrs/pinctrl/pinctvi_vsync_/d6_/a>sc#L306" id="L30vi_vsync_/d6_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, TEGRA_PIN_PEE76+ 1)
68 href="drivers/pinctrl/pinctclass="linVI_VSYNC_PDode=PINCTRL_PIN" class="srVI_VSYNC_PDoCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, offset<6a>))
68 href};f">TEGRA_PIN_VI_VSYNC_PD6,  286
68 hreff">TEGRA_PIN_VI_VSYNC_PD6, /* Non-GPIO pins */
68 hrefstatic const unsignedrs/pinctrl/pinctvi_hsync_/d7_/a>sc#L306" id="L30vi_hsync_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(0)
68 href="drivers/pinctrl/pinctclass="linVI_HSYNC_PDlass="sref">NUM_GPIOS VI_HSYNC_PDlCTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(1)
68 href};f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(2)
68 hreff">TEGRA_PIN_VI_VSYNC_PD6, &q6PIN" class="sref">_PIN(3)
68 hrefstatic const unsignedrs/pinctrl/pinctlcdCd0_pe0_/a>sc#L306" id="L30lcdCd0_pe0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, &q6PIN" class="sref">_PIN(4)
68 href="drivers/pinctrl/pinct class="sr_PIND0_PE="+code=PINCTRL_PIN" class_PIND0_PE=CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(5)
69 href};f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(6)
69 hreff">TEGRA_PIN_VI_VSYNC_PD6, _PIN(7)
69 hrefstatic const unsignedrs/pinctrl/pinctlcdCd1_/e1_/a>sc#L306" id="L30lcdCd1_/e1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(8)
69 href="drivers/pinctrl/pinctGPIOS _PIND1_PE"L271" class="line" name="_PIND1_PE"CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, _PIN(9)
69 href};f">TEGRA_PIN_VI_VSYNC_PD6, _PINTEGRA_PIN_VI_VSYNC_PD6, _PINsc#L306" id="L30lcdCd2_/e2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6,  296
69 href="drivers/pinctrl/pinctPIN" class_PIND2_PE"L272" class="line" name="_PIND2_PE"CTRL_f">TEGRA_PIN_VI_VSYNC_PD6, &q6"sref">tegra30_pins[6 = {
69 href};f">TEGRA_PIN_VI_VSYNC_PD6, &q6LK_32K_OUT PA0"),
69 hreff">TEGRA_PIN_VI_VSYNC_PD6, "7ART3_CTS_N PA1"),
70 hrefstatic const unsignedrs/pinctrl/pinctlcdCd3_/e3_/a>sc#L306" id="L30lcdCd3_/e3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, shref[] = {f">TEGRA_PIN_VI_VYNC_PD6, &quo6;DAP2_SCLK PA3pan class="s5code=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6, TEGRA_PIN_VI_VSYNC_PD6, _GPIO, "6DMMC3_DPINCTRL_PIN" class="sreclassPA5"),
60 hrefstatic const unsignedrs/pin7trl/pinct7cdCpclkCpb3_/a>sc#L306" 7d="L37lcdCpclkCpb3_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD7, &quo6;N"7class7"sref">_PIN),
6a href="drivers/pinctrl/piPIN"ee" name="SDMMC3T7_P7_l/piPIN"ee" name=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>s5a>, sc#L306" id7ef">_7IN),
60 href};f">TEGRA_PIN_VI_VSYNC_PD4>_Ga>, , &q6a>, teg7a30_pins[6n>),
60 hrefstatic const unsignedrs/pin7trl/pinct7dmmc3_dat3_/b4_/a>sc#L307" id=7L30sdmmc3_dat3_/b4_/a>shref[] = {f">TEGRA_PIN_VI_VS7NC_PD6&qu7t6SK_72K_OUT PA0"),
6a href="drivers/l/piP5N"ess=VI_D1_PDde=PINCTRLl/piP5N"ess=VI_e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>s9_PD6sc#L306" id7CLK P73"),
61 href};f">TEGRA_PIN_NC_PD5>_Gpan class="s6c9ing">&q6s="NC_PD5>_GpIO, &/a>, "6DMMC7_DAT27PB5"),
61 hrefstatic const unsignedrs/pin7trl/pinct7dmmc3_dat2_/b5_/a>sc#L307" id=7L30sdmmc3_dat2_/b5_/a>shref[] = {f">TEGRA_PIN_VI_VS7NC_PD6&quo7;6DMM73_DAT1 PB6"),
6a href="drivers/l/piP6N"e class_PINPWR2  Code=PINCP6N"e classe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>>, &quo6DMMC3_7AT0 P77"),
61 href};f">TEGRA_PIN_NC_PD6>_G _G IO, &//a>, "6t;LC7_PWR17PC1"),
61 hrefstatic const unsignedrs/pin7trl/pinct7dmmc3_dat1_/b6_/a>sc#L307" id=7L30sdmmc3_dat1_/b6_/a>shref[] = {f">TEGRA_PIN_VI_VS7NC_PD6&qu7t6;UA7T2_TXD PC2"),
6a href="drivers/PINCP7N"es="linVI_HSYNC_PDlassPINCP7N"es="line=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>>rl/pinct7lass="s6r8">"6;UART27RXD P73"),
61 href};f">TEGRA_PIN_" clD7>_G _G IO, &/C_PD6"G6N1_I7C_SDA7PC5"),
62 hrefstatic const unsignedrs/pin7trl/pinct7dmmc3_dat0_/b7_/a>sc#L307" id=7L30sdmmc3_dat0_/b7_/a>shref[] = {f">TEGRA_PIN_VI_VS7NC_PD6&7u6t;L7D_PWR2 PC6"),
6a href="drivers/PINCP8_pf="sr_PIND0_PE="+code=PINCT8_pf="sr_Pe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>>, &qu6t;GMI_7P_N P77"),
62 href};f">TEGRA_PIN_" clD8_PFspan class="s6f" class=6PIN" cl8_PFsIO, &/a>, "6DMMC7_DAT47PD1"),
62 hrefstatic const unsignedrs/pin7trl/pinct7art3_rts_n_pc0_/a>sc#L307" id=7L30uart3_rts_n_pc0_/a>shref[] = {f">TEGRA_PIN_VI_VS7NC_PD6&qu7t6ot;7CD_DC1 PD2"),
6a href="drivers/PINCT9_pf/a> _PIND1_PE"L271" class=9_pf/a> _Pe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>>rl/pinct7lass="s6rg">"6DMMC3_7AT6 P73"),
62 href};f">TEGRA_PIN_N" cl9_PFspan class="s6="+code=_6IN" cla9_PFsIO, &/C_PD6"6quot7VI_D17PD5"),
62 hrefstatic const unsignedrs/pin7trl/pinct7cdCpwr1_/c1_/a>sc#L306" 7d="L37lcdCpwr1_/c1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD7, "6t;V7_VSYN7 PD6"),
6a href="drivers/pinctrl/pid1="sflass_PIND2_PE"L272" class=1="sflass_Pe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>>rl/pinct7s6ring">&qu6t;VI_HSYNC P77&quo7;),
63 href};f">TEGRA_PIN_VI_VSYNC_PD1="PFspan class="s6f9ing">&q6LK_32K_1="PFsIO, &/a>, &qu6" cl7ss="s7ef">_GPIO6201)
63 hrefstatic const unsignedrs/pin7trl/pinct7art2_txdCpc2_/a>sc#L306"7id="L70uart2_txdCpc2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_7D6, <7pan class="s6r">"6"7class7"sref">_GPIO6202)
63 href="drivers/pinclass=1/a>f>&quo6;DAP2_SCLK PA3pan cl1/a>f>&quo6e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>span clas7="s6r">"6" class="s7ef">_7PIO6203)
63 href};f">TEGRA_PIN_VI_V_32K_11"PFclass=s5code=_GPI5" class="sref11"PFcIO, &/C_PD6_GPIO6205)
63 hrefstatic const unsignedrs/pin7trl/pinct7art2_rxdCpc3_/a>sc#L306"7id="L70uart2_rxdCpc3_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_7D6, <7pan class="s6rng">&quo6"7class7"sref">_GPIO6206)
63 href="drivers/pincan cl1lasfe" name="SDMMC3T7_P7_l/piP1lasfe" name=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>srl/pinct7="s6r8">"6" class="s7ef">_7PIO6207)
63 href};f">TEGRA_PIN_VI_V"sref12"PFa>, &//a>, _GPIO6209)
64 hrefstatic const unsignedrs/pin7trl/pinct7en1_i2c_sclCpc4_/a>sc#L376" id7"L30gen1_i2c_sclCpc4_/a>shref[] = {f">TEGRA_PIN_VI_7SYNC_PD6<7a>, _GPIO6210)
64 href="driverl/piP1>&qfss=VI_D1_PDde=PINCTRLl/piP1>&qfss=VI_e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>/a>, _GPIO6211)
64 href};f">TEGRA_PINC_PD13"PFpan class="s6c9ing">&q6s="NC_PD13"PFpIO, &/a>, _GPIO6213)
64 hrefstatic const unsignedrs/pin7trl/pinct7en1_i2c_sdaCpc5_/a>sc#L376" id7"L30gen1_i2c_sdaCpc5_/a>shref[] = {f">TEGRA_PIN_VI_7SYNC_PD6<7a>, _GPIO6214)
64 href="driverl/piP1e" f class_PINPWR2  Code=PINCP1e" f classe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>/rl/pinct7 class="s6code=_GPI6" cl7ss="s7ef">_GPIO6215)
64 href};f">TEGRA_PINC_PD14"PF &/6, <7 class="s6c8">"6" cl7ss="s7ef">_GPIO6217)
64 hrefstatic const unsignedrs/pin7trl/pinct7cdCpwr2_/c6_/a>sc#L306" 7d="L37lcdCpwr2_/c6_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD7, "6" c7ass="7ref">_GPIO6218)
64 href="drivers/pinctrl/pid1ss=fs="linVI_HSYNC_PDlassPINCP1ss=fs="line=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>/rl/pinct7s6code=_GPI6" class="sre7">_GP7O6219)
65 href};f">TEGRA_PIN_VI_VSYNC_PD1ssPF &/a>, _GPIO6221)
65 hrefstatic const unsignedrs/pin7trl/pinct7mi_wp_n_pc7_/a>sc#L306" 7d="L37gmi_wp_n_pc7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD7, _GPIO6222)
65 href="drivers/pinctrl/piaTRL_g GMI_A17_PB="+code=PINTRL_g Ge=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>an class=7s6code=_GPI6" class="sre7">_GP7O6223)
65 href};f">TEGRA_PIN_VI_VSYNC_PAlassG&/YNC_PD6<7 class="s6code=_GPI6" cl7ss="s7ef">_GPIO6225)
65 hrefstatic const unsignedrs/pin7trl/pinct7dmmc3_dat5_/d0_/a>sc#L307" id=7L30sdmmc3_dat5_/d0_/a>shref[] = {f">TEGRA_PIN_VI_VS7NC_PD6_GPIO6226)
65 href="drivers/e=PINT/a>gclassGMI_A18_PB"L271" clasT/a>gclassGe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>arl/pinct7lass="s6c8">"6" clas7="sre7">_GPIO6227)
65 href};f">TEGRA_PIN_N" cll1"PG&q5LK_32Kl1"PG, &//a>, _GPIO6229)
66 hrefstatic const unsignedrs/pin7trl/pinct7dmmc3_dat4_/d1_/a>sc#L307" id=7L30sdmmc3_dat4_/d1_/a>shref[] = {f">TEGRA_PIN_VI_VS7NC_PD6_GPIO6230)
66 href="drivers/ clasTlasglass_PIND2_PE"L272" c clasTlasglass_Pe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>>, _GPIO6231)
66 href};f">TEGRA_PIN_K_32Kl2"PGspan class="s6f9ing">&q6LKK_32Kl2"PGsIO, &/a>, _GPIO6233)
66 hrefstatic const unsignedrs/pin7trl/pinct7cdCdc1_/d2_/a>sc#L306" i7="L307cdCdc1_/d2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6<7a>, _GPIO6234)
66 href="drivers/pinctrl/ clasT>&qg>&quo6;DAP2_SCLK PA3p clasT>&qg>&quo6e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>>rl/pinct7code=_GPI6" class="sref"7_GPIO7/a>6235)
66 href};f">TEGRA_PIN_VI_VSYNCK_32Kl3"PGclass=s5code=_GPI5" class=K_32Kl3"PGcIO, &/C_PD6"6" cl7ss="s7ef">_GPIO6237)
66 hrefstatic const unsignedrs/pin7trl/pinct7dmmc3_dat6_/d3_/a>sc#L307" id=7L30sdmmc3_dat6_/d3_/a>shref[] = {f">TEGRA_PIN_VI_VS7NC_PD6&qu7t6" c7ass="sref">_GPIO6238)
66 href="drivers/ clasTe" gne" name="GEN1#I2Ce_SCclasTe" gne" nae=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>>rl/pinct7lass="s6code=_GPI6" clas7="sre7">_GPIO6239)
67 href};f">TEGRA_PIN_K_32Kl4"PG/a>, &/a>, _GPIO6241)
67 hrefstatic const unsignedrs/pin7trl/pinct7dmmc3_dat7_/d4_/a>sc#L307" id=7L30sdmmc3_dat7_/d4_/a>shref[] = {f">TEGRA_PIN_VI_VS7NC_PD6_GPIO6242)
67 href="drivers/CclasTss=gclass="linGEN1#I2Ce_D>clasTss=gclass=e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>>, _GPIO6243)
67 href};f">TEGRA_PIN_G_32KlssPGpan class="s6c9ing">&q6s="G_32KlssPGpIO, &/>, _GPIO6245)
67 hrefstatic const unsignedrs/pin7trl/pinct7i_d1_/d5_/a>sc#L306" id=7L30vi7d1_/d5_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6,77GPIO6246)
67 href="drivers/pinctrl/pinc>clasT6s=g class_PINPWR2  Code=>clasT6s=g classe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>>rl/pinct7"6" class="sref">_GP7O7247)
67 href};f">TEGRA_PIN_VI_VSYNC_PD6G_32Kl6sPG , &/C_PD6/* All 6on-G7IO pi7s follow */
68 hrefstatic const unsignedrs/pin7trl/pinct7i_vsync_/d6_/a>sc#L306" 7d="L37vi_vsync_/d6_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD7, TEG7A_PIN_PEE76+ 1)
68 href="drivers/pinctr>clasT7s=gname="GMI_WP_="PClass="srsT7s=gname="e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>an class=7s6+code=off6et" class="s7ef">o7fset<6a>))
68 href};f">TEGRA_PIN_VI_VSYG_32Kl7sPG &/a>, /7 Non-7PIO pins */
68 hrefstatic const unsignedrs/pin7trl/pinct7i_hsync_/d7_/a>sc#L306" 7d="L37vi_hsync_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD7, _PIN(0)
68 href="drivers/pinctr="srsT8_ph GMI_A17_PB="+code=PINT8_ph Ge=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>arl/pinct7s6+ode=_GPI6PIN" class="7ref">7PIN(1)
68 href};f">TEGRA_PIN_VI_VSY" clKl8_PH&/span cla7 class="s6"8ing">&q6PIN"7class7"sref">_PIN(3)
68 hrefstatic const unsignedrs/pin7trl/pinct7cdCd0_pe0_/a>sc#L306" id7"L30l7dCd0_pe0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&q6PIN" cl7ss="s7ef">_PIN(4)
68 href="drivers/pinctrl/pie=PINT9_phclassGMI_A18_PB"L271" clasT9_phclassGe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>arl/pinct7"+code=6PIN" class="sref7>_PIN7/6>(5)
69 href};f">TEGRA_PIN_VI_VSYNC_PN" cll9_PH&q5LK_32Kl9_PH, &/a>, _PIN(7)
69 hrefstatic const unsignedrs/pin7trl/pinct7cdCd1_/e1_/a>sc#L306" id7"L30l7dCd1_/e1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6_PIN(8)
59 href="drivers/pinctrl/pinct=1="shlass_PIND2_PE"L272" c clasT1="shlass_Pe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>lass="s6f7="comme6PIN" class="sref7>_PIN7N(9)
59 href};f">TEGRA_PIN_VI_VSYNC_PD6<_1="PHspan class="s6f9ing">&q6LKK_32Kl1="PHsIO, &//a>, _PINsc#L306" id7"L30l7dCd2_/e2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6 295
59 href="drivers/pinctrl/pinctl1/a>h>&quo6;DAP2_SCLK PA3p clasT1/a>h>&quo6e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=1>lrl/pinct7ing">&q6"sref">tegra30_p7ns[5 = {
59 href};f">TEGRA_PIN_VI_VSYNC_PD6, &/ "7ART37CTS_N7PA1"),
70 hrefstatic const unsignedrs/pin7trl/pinct7cdCd3_/e3_/a>sc#L306" id7"L30l7dCd3_/e3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6s8ref[]8= {f">TEGRA_PIN_VI_VYNC_PD6, _GPIO5223)
55 href="drclass=18shref[] =8{f">TEGRA_PIN_VI_VSYNC_P868 TEGRA_PIN_VI_VSYNC_PD6, 8quot;6DMM83_DPINCTRL_PIN" class="s8eclas8PA5"),
60 hrefstatic const unsignedrs/pin8trl/pinct8cdCpclkCpb3_/a>sc#L306" 8d="L38lcdCpclkCpb3_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8, &quo6;N"8class8"sref">_PIN),
6a href="drivers/pinctrCclasT1>&qhclass="linGEN1#I2Ce_D>clasT1>&qhclass=e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18s5a>, sc#L306" id8ef">_8IN),
60 href};f">TEGRA_PIN_VI_VSYG_32Kl13"PHpan class="s6c9ing">&q6s="G_32Kl13"PHpIO, 8q6a>, teg8a30_pins[6n>),
60 hrefstatic const unsignedrs/pin8trl/pinct8dmmc3_dat3_/b4_/a>sc#L308" id=8L30sdmmc3_dat3_/b4_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD6&qu8t6SK_82K_OUT PA0"),
6a href="drivers/>clasT1ne"h class_PINPWR2  Code=>clasT1ne"h classe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18s9_PD6sc#L306" id8CLK P83"),
61 href};f">TEGRA_PIN_G_32Kl14"PH 8/a>, "6DMMC8_DAT28PB5"),
61 hrefstatic const unsignedrs/pin8trl/pinct8dmmc3_dat2_/b5_/a>sc#L308" id=8L30sdmmc3_dat2_/b5_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD6&quo8;6DMM83_DAT1 PB6"),
6a href="drivers/>clasT1clahname="GMI_WP_="PClass="srsT1clahname="e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18>, &quo6DMMC3_8AT0 P87"),
61 href};f">TEGRA_PIN_G_32Kl15"PH 8//a>, "6t;LC8_PWR18PC1"),
61 hrefstatic const unsignedrs/pin8trl/pinct8dmmc3_dat1_/b6_/a>sc#L308" id=8L30sdmmc3_dat1_/b6_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD6&qu8t6;UA8T2_TXD PC2"),
6a href="drivers/="srer">NUi GMI_A17_PB="+code=PIer">NUi Ge=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18>rl/pinct8lass="s6r8">"6;UART28RXD P83"),
61 href};f">TEGRA_PIN_" claRs="sI, 8/C_PD6"G6N1_I8C_SDA8PC5"),
62 hrefstatic const unsignedrs/pin8trl/pinct8dmmc3_dat0_/b7_/a>sc#L308" id=8L30sdmmc3_dat0_/b7_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD6&8u6t;L8D_PWR2 PC6"),
6a href="drivers/e=PIoe">NUiclassGMI_A18_PB"L271" claoe">NUiclassGe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18>, &qu6t;GMI_8P_N P87"),
62 href};f">TEGRA_PIN_N" cOEs="sI&q5LK_32OEs="sI, 8/a>, "6DMMC8_DAT48PD1"),
62 hrefstatic const unsignedrs/pin8trl/pinct8art3_rts_n_pc0_/a>sc#L308" id=8L30uart3_rts_n_pc0_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD6&qu8t6ot;8CD_DC1 PD2"),
6a href="drivers/ cladqslaslass_PIND2_PE"L272" c cladqslaslass_Pe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18>rl/pinct8lass="s6rg">"6DMMC3_8AT6 P83"),
62 href};f">TEGRA_PIN_K_32DQS_PIspan class="s6f9ing">&q6LKK_32DQS_PIsIO, 8/C_PD6"6quot8VI_D18PD5"),
62 hrefstatic const unsignedrs/pin8trl/pinct8cdCpwr1_/c1_/a>sc#L306" 8d="L38lcdCpwr1_/c1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8, "6t;V8_VSYN8 PD6"),
6a href="drivers/pinctr clacs6">NUi>&quo6;DAP2_SCLK PA3p clacs6">NUi>&quo6e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18>rl/pinct8s6ring">&qu6t;VI_HSYNC P87&quo8;),
63 href};f">TEGRA_PIN_VI_VSYK_32CS6s="sIclass=s5code=_GPI5" class=K_32CS6s="sIcIO, 8/a>, &qu6" cl8ss="s8ef">_GPIO6201)
63 hrefstatic const unsignedrs/pin8trl/pinct8art2_txdCpc2_/a>sc#L306"8id="L80uart2_txdCpc2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_8D6, <8pan class="s6r">"6"8class8"sref">_GPIO6202)
63 href="drivers/pinc clarst">NUine" name="GEN1#I2Ce_SCclarst">NUine" nae=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18span clas8="s6r">"6" class="s8ef">_8PIO6203)
63 href};f">TEGRA_PIN_VI_VK_32RSTs="sI/a>, 8/C_PD6_GPIO6205)
63 hrefstatic const unsignedrs/pin8trl/pinct8art2_rxdCpc3_/a>sc#L306"8id="L80uart2_rxdCpc3_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_8D6, <8pan class="s6rng">&quo6"8class8"sref">_GPIO6206)
63 href="drivers/pincCclaiordye" class="linGEN1#I2Ce_D>claiordye" class=e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18srl/pinct8="s6r8">"6" class="s8ef">_8PIO6207)
63 href};f">TEGRA_PIN_VI_VG_32IORDY_VIpan class="s6c9ing">&q6s="G_32IORDY_VIpIO, 8//a>, _GPIO6209)
64 hrefstatic const unsignedrs/pin8trl/pinct8en1_i2c_sclCpc4_/a>sc#L386" id8"L30gen1_i2c_sclCpc4_/a>shref[] = {f">TEGRA_PIN_VI_8SYNC_PD6<8a>, _GPIO6210)
64 href="driversclacs7">NUi class_PINPWR2  Code=>clacs7">NUi classe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18/a>, _GPIO6211)
64 href};f">TEGRA_PIN_32CS7s="sI 8/a>, _GPIO6213)
64 hrefstatic const unsignedrs/pin8trl/pinct8en1_i2c_sdaCpc5_/a>sc#L386" id8"L30gen1_i2c_sdaCpc5_/a>shref[] = {f">TEGRA_PIN_VI_8SYNC_PD6<8a>, _GPIO6214)
64 href="drivers=PIeaitclaname="GMI_WP_="PClass="sreaitclaname="e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18/rl/pinct8 class="s6code=_GPI6" cl8ss="s8ef">_GPIO6215)
64 href};f">TEGRA_PIN" caAITRA_ 8/6, <8 class="s6c8">"6" cl8ss="s8ef">_GPIO6217)
64 hrefstatic const unsignedrs/pin8trl/pinct8cdCpwr2_/c6_/a>sc#L306" 8d="L38lcdCpwr2_/c6_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8, "6" c8ass="8ref">_GPIO6218)
64 href="drivers/pinctr>clacs0">NUj GMI_A17_PB="+code=PIcs0">NUj Ge=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18/rl/pinct8s6code=_GPI6" class="sre8">_GP8O6219)
65 href};f">TEGRA_PIN_VI_VSYG_32CS0s="sJ, 8/a>, _GPIO6221)
65 hrefstatic const unsignedrs/pin8trl/pinct8mi_wp_n_pc7_/a>sc#L306" 8d="L38gmi_wp_n_pc7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8, _GPIO6222)
65 href="drivers/pinctrPINCPeNUj/a> _PIND1_PE"L271" class=eNUj/a> _Pe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18an class=8s6code=_GPI6" class="sre8">_GP8O6223)
65 href};f">TEGRA_PIN_VI_VSY" clDE"sJspan class="s6="+code=_6IN" claE"sJsIO, 8/YNC_PD6<8 class="s6code=_GPI6" cl8ss="s8ef">_GPIO6225)
65 hrefstatic const unsignedrs/pin8trl/pinct8dmmc3_dat5_/d0_/a>sc#L308" id=8L30sdmmc3_dat5_/d0_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD6_GPIO6226)
65 href="drivers/e=PIcs1">NUjlass_PIND2_PE"L272" c clacs1">NUjlass_Pe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18arl/pinct8lass="s6c8">"6" clas8="sre8">_GPIO6227)
65 href};f">TEGRA_PIN_N" cCS1s="sJspan class="s6f9ing">&q6LKK_32CS1s="sJsIO, 8//a>, _GPIO6229)
66 hrefstatic const unsignedrs/pin8trl/pinct8dmmc3_dat4_/d1_/a>sc#L308" id=8L30sdmmc3_dat4_/d1_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD6_GPIO6230)
66 href="drivers/lassref">NUj>&quo6;DAP2_SCLK PA3pan cref">NUj>&quo6e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18>, _GPIO6231)
66 href};f">TEGRA_PIN_" cl" classJclass=s5code=_GPI5" class="sre" classJcIO, 8/a>, _GPIO6233)
66 hrefstatic const unsignedrs/pin8trl/pinct8cdCdc1_/d2_/a>sc#L306" i8="L308cdCdc1_/d2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6<8a>, _GPIO6234)
66 href="drivers/pinctrl/pincCTRL_PIje" name="SDMMC3T7_P7_l/piCTRL_PIje" name=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18>rl/pinct8code=_GPI6" class="sref"8_GPIO8/a>6235)
66 href};f">TEGRA_PIN_VI_VSYNC_PD6line" nJa>, 8/C_PD6"6" cl8ss="s8ef">_GPIO6237)
66 hrefstatic const unsignedrs/pin8trl/pinct8dmmc3_dat6_/d3_/a>sc#L308" id=8L30sdmmc3_dat6_/d3_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD6&qu8t6" c8ass="sref">_GPIO6238)
66 href="drivers/ode=PIcts">NUjclass="linGEN1#I2Ce_Dode=PIcts">NUjclass=e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18>rl/pinct8lass="s6code=_GPI6" clas8="sre8">_GPIO6239)
67 href};f">TEGRA_PIN_6" claCTSs="sJpan class="s6c9ing">&q6s="6" claCTSs="sJpIO, 8/a>, _GPIO6241)
67 hrefstatic const unsignedrs/pin8trl/pinct8dmmc3_dat7_/d4_/a>sc#L308" id=8L30sdmmc3_dat7_/d4_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD6_GPIO6242)
67 href="drivers/ode=PIrts">NUj class_PINPWR2  Code=ode=PIrts">NUj classe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18>, _GPIO6243)
67 href};f">TEGRA_PIN_6" claRTSs="sJ , 8/>, _GPIO6245)
67 hrefstatic const unsignedrs/pin8trl/pinct8i_d1_/d5_/a>sc#L306" id=8L30vi8d1_/d5_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6,88GPIO6246)
67 href="drivers/pinctrl/pinc>clas1 cljname="GMI_WP_="PClass="srs1 cljname="e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18>rl/pinct8"6" class="sref">_GP8O8247)
67 href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1 cPJ 8/C_PD6/* All 6on-G8IO pi8s follow */
68 hrefstatic const unsignedrs/pin8trl/pinct8i_vsync_/d6_/a>sc#L306" 8d="L38vi_vsync_/d6_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8, TEG8A_PIN_PEE76+ 1)
68 href="drivers/pinctr>clasTv">NUk GMI_A17_PB="+code=PINTv">NUk Ge=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18an class=8s6+code=off6et" class="s8ef">o8fset<6a>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlVs="sK, 8/a>, /8 Non-8PIO pins */
68 hrefstatic const unsignedrs/pin8trl/pinct8i_hsync_/d7_/a>sc#L306" 8d="L38vi_hsync_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8, _PIN(0)
68 href="drivers/pinctr="srclkNUkclassGMI_A18_PB"L271" claclkNUkclassGe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18arl/pinct8s6+ode=_GPI6PIN" class="8ref">8PIN(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLK"sK&q5LK_32CLK"sK, 8/span cla8 class="s6"8ing">&q6PIN"8class8"sref">_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/pinct8cdCd0_pe0_/a>sc#L306" id8"L30l8dCd0_pe0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&q6PIN" cl8ss="s8ef">_PIN(4)
68 href="drivers/pinctrl/pie=PIcs4">NUklass_PIND2_PE"L272" c clacs4">NUklass_Pe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18arl/pinct8"+code=6PIN" class="sref8>_PIN8/6>(5)
69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCS4s="sKspan class="s6f9ing">&q6LKK_32CS4s="sKsIO, 8/a>, _PIN(7)
69 hrefstatic const unsignedrs/pin8trl/pinct8cdCd1_/e1_/a>sc#L306" id8"L30l8dCd1_/e1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6_PIN(8)
59 href="drivers/pinctrl/pinccs2">NUk>&quo6;DAP2_SCLK PA3p clacs2">NUk>&quo6e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18lass="s6f8="comme6PIN" class="sref8>_PIN8N(9)
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CS2s="sKclass=s5code=_GPI5" class=K_32CS2s="sKcIO, 8//a>, _PINsc#L306" id8"L30l8dCd2_/e2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6 295
59 href="drivers/pinctrl/pinccs3">NUkne" name="GEN1#I2Ce_SCclacs3">NUkne" nae=_GPI5" class="sref">_GPIO5223)
55 href="drclass=18lrl/pinct8ing">&q6"sref">tegra30_p8ns[5 = {
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CS3s="sK/a>, 8/ "7ART38CTS_N8PA1"),
70 hrefstatic const unsignedrs/pin8trl/pinct8cdCd3_/e3_/a>sc#L306" id8"L30l8dCd3_/e3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6s9ref[]9= {f">TEGRA_PIN_VI_VYNC_PD6, _GPIO5223)
55 href="drclass=19shref[] =9{f">TEGRA_PIN_VI_VSYNC_P969 TEGRA_PIN_VI_VSYNC_PD6&q6s="SPDIF_OUT"sKpIO, 9quot;6DMM93_DPINCTRL_PIN" class="s9eclas9PA5"),
60 hrefstatic const unsignedrs/pin9trl/pinct9cdCpclkCpb3_/a>sc#L306" 9d="L39lcdCpclkCpb3_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD9, &quo6;N"9class9"sref">_PIN),
6a href="drivers/pinctrspdif_i>NUk class_PINPWR2  Code=spdif_i>NUk classe=_GPI5" class="sref">_GPIO5223)
55 href="drclass=19s5a>, sc#L306" id9ef">_9IN),
60 href};f">TEGRA_PIN_VI_VSYSPDIF_I="sK 9q6a>, teg9a30_pins[6n>),
60 hrefstatic const unsignedrs/pin9trl/pinct9dmmc3_dat3_/b4_/a>sc#L309" id=9L30sdmmc3_dat3_/b4_/a>shref[] = {f">TEGRA_PIN_VI_VS9NC_PD6&qu9t6SK_92K_OUT PA0"),
6a href="drivers/>clas19NUkname="GMI_WP_="PClass="srs19NUkname="e=_GPI5" class="sref">_GPIO5223)
55 href="drclass=19s9_PD6sc#L306" id9CLK P93"),
61 href};f">TEGRA_PIN_G_32K19NPK 9/a>, "6DMMC9_DAT29PB5"),
61 hrefstatic const unsignedrs/pin9trl/pinct9dmmc3_dat2_/b5_/a>sc#L309" id=9L30sdmmc3_dat2_/b5_/a>shref[] = {f">TEGRA_PIN_VI_VS9NC_PD6&quo9;6DMM93_DAT1 PB6"),
6a href="drivers/vis="lil GMI_A17_PB="+codvis="lil Ge=_GPI5" class="sref">_GPIO5223)
55 href="drclass=19>, &quo6DMMC3_9AT0 P97"),
61 href};f">TEGRA_PIN_VIK_OUTL, 9//a>, "6t;LC9_PWR19PC1"),
61 hrefstatic const unsignedrs/pin9trl/pinct9dmmc3_dat1_/b6_/a>sc#L309" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">TEGRA_PIN_VI_VS9NC_PD6&qu9t6;UA9T2_TXD PC2"),
6a href="drivers/vis=>&q="drivsref">_PIN(4)
vi_hsync_/d7_/a>shref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44"a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD6, &q5LK_32CL6t5g>, 9//a>, "G6N1_I8C_SDA9PC5&q9ot;),
62 hrefstatic const unsignedrs/pin8trl/p9nct8dmmc39dat0_/b7_/a>sc#L308" id=9L30sd9mc3_dat0_/b7_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD9&8u6t;L9D_PWR9 PC6"),
6a href="drivers/e=PIoesynce=_lIND2_PE"L272" c clacssynce=_lIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&quan 8lass=9s6ring">&qu6t;GMI_8P_N P97&quo9;),
62 href};f">TEGRA_PIN_N" cOE6t5g4&q6LKK_32CS6t5g4, 9//a>, spa8 clas9="s6r">"6DMMC8_DAT49PD1&q9ot;),
62 hrefstatic const unsignedrs/pin8trl/p9nct8art3_9ts_n_pc0_/a>sc#L308" id=9L30ua9t3_rts_n_pc0_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD9&qu8t6ot;9CD_DC9 PD2"),
6a href="drivers/ cladqsynce=_l;DAP2_SCLK PA3p clacssynce=_l;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&quact9dmmc3_s6rg">"6DMMC3_8AT6 P93&quo9;),
62 href};f">TEGRA_PIN_K_32DQ6t5g5, 9//a>, s/a9, "6quot8VI_D19PD5&q9ot;),
62 hrefstatic const unsignedrs/pin8trl/p9nct8cdCpw91_/c1_/a>sc#L306" 8d="L39lcdCp9r1_/c1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,9"6t;V8_VSYN9 PD6&9uot;),
6a href="drivers/pinctr clacssynce=_lme="GEN1#I2Ce_SCclacssynce=_lme="GEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&quact8dmmc39">&qu6t;VI_HSYNC P87&quo9;),
63 href};f">TEGRA_PIN_VI_VSYK_32CS6t5g6, 9//a>, spa8 clas9="s6ring">&qu6" cl8ss="s9ef">_9PIO6201)
63 hrefstatic const unsignedrs/pin8trl/p9nct8art2_9xdCpc2_/a>sc#L306"8id="L90uart9_txdCpc2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_8D6"6"8class9"sref9>_GPIO6202)
63 href="drivers/pinc clarssynce=_l"linGEN1#I2Ce_Dspdif_synce=_l"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&qulas8="s6r9>"6" class="s8ef">_9PIO6203)
63 href};f">TEGRA_PIN_VI_VK_32RS6t5g7&q6s="SPDIF_6t5g7, 9//a>, s/a8, _9PIO6205)
63 hrefstatic const unsignedrs/pin8trl/p9nct8art2_9xdCpc3_/a>sc#L306"8id="L90uart9_rxdCpc3_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_8D6&quo6"8class9"sref9>_GPIO6206)
63 href="drivers/pincCclaiosync8=_l_PINPWR2  Code=spdif_sync8=_l_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&qulct8cdCpw9">"6" class="s8ef">_9PIO6207)
63 href};f">TEGRA_PIN_VI_VG_32IO6t5g8, 9//a>, ssp8n cla9="s6code=_GPI6" cl8ss="s9ef">_9PIO6209)
64 hrefstatic const unsignedrs/pin8trl/p9nct8en1_i9c_sclCpc4_/a>sc#L386" id9"L30g9n1_i2c_sclCpc4_/a>shref[] = {f">TEGRA_PIN_VI_8SYNC_9D6<8a>, <9pan class="s6code=8GPI6"9class9"sref">_GPIO6210)
64 href="driversclacssync9=_lGMI_WP_="PClass="srs1sync9=_lGMI_WPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&quspa8 clas9="s6code=_GPI6" cl8ss="s9ef">_9PIO6211)
64 href};f">TEGRA_PIN_32CS6t5g9, 9//a>, spa8 clas9="s6code=_GPI6" cl8ss="s9ef">_9PIO6213)
64 hrefstatic const unsignedrs/pin8trl/p9nct8en1_i9c_sdaCpc5_/a>sc#L386" id9"L30g9n1_i2c_sdaCpc5_/a>shref[] = {f">TEGRA_PIN_VI_8SYNC_9D6<8a>, <9pan class="s6cring8>&q6"9class9"sref">_GPIO6214)
64 href="driverl/piP1e" f c_PImIND0_PE="+code=PINCT8_pf="c_PImIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&qusct8art2_9="s6code=_GPI6" cl8ss="s9ef">_9PIO6215)
64 href};f">TEGRA_PINC_PD14"PF <6, 9//a>, s <8pan c9="s6c8">"6" cl8ss="s9ef">_9PIO6217)
64 hrefstatic const unsignedrs/pin8trl/p9nct8cdCpw92_/c6_/a>sc#L306" 8d="L39lcdCp9r2_/c6_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,9"6" c8ass="9ref">9GPIO6218)
64 href="drivers/pinctrl/pid1ss=fs=GMImIND1_PE"L271" class=eNUj/a=GMImIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&qusct8en1_i9=_GPI6" class="sre8">_GP9O9219)
65 href};f">TEGRA_PIN_VI_VSYNC_PD1ssPF <7, 9//a>, spa8 clas9="s6code=_GPI6" cl8ss="s9ef">_9PIO6221)
65 hrefstatic const unsignedrs/pin8trl/p9nct8mi_wp9n_pc7_/a>sc#L306" 8d="L39gmi_w9_n_pc7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,99GPIO6222)
65 href="drivers/pinctrPINCPeNUj/a18=_mIND2_PE"L272" class=1="sfla8=_mIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&quss=8s6cod9=_GPI6" class="sre8">_GP9O9223)
65 href};f">TEGRA_PIN_VI_VSY" clDE"sJspa8=PMlass="s6f9ing">&q6LK_32K_1="PFsI8=PMl"RA_PIN_VI_VSYNC_PD6, 9//a>, s6<8a>, <9="s6code=_GPI6" cl8ss="s9ef">_9PIO6225)
65 hrefstatic const unsignedrs/pin8trl/p9nct8dmmc39dat5_/d0_/a>sc#L308" id=9L30sd9mc3_dat5_/d0_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD9_GPIO6226)
65 href="drivers/e=PIcs="sfla9=_m;DAP2_SCLK PA3pan cl1/a>f>&9=_m;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&qusct8cdCpw9s6c8">"6" clas8="sre9">_GP9O6227)
65 href};f">TEGRA_PIN_N" cCS="PFsI9, 9//a>, ssp8n cla9="s6code=_GPI6" cl8ss="s9ef">_9PIO6229)
66 hrefstatic const unsignedrs/pin8trl/p9nct8dmmc39dat4_/d1_/a>sc#L308" id=9L30sd9mc3_dat4_/d1_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD9_GPIO6230)
66 href="drivers/lassref">Nd2INDme="SDMMC3T7_P7_l/piP1lasfe2INDme="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&quan 8lass=9s6code=_GPI6" clas8="sre9">_GP9O6231)
66 href};f">TEGRA_PIN_" cl" clasD2INPMpan class="s6code=_GNC_PD12"PFa2INPMp"RA_PIN_VI_VSYNC_PD6, 9//a>, spa8 clas9="s6code=_GPI6" cl8ss="s9ef">_9PIO6233)
66 hrefstatic const unsignedrs/pin8trl/p9nct8cdCdc9_/d2_/a>sc#L306" i8="L309cdCdc9_/d2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6<8a>, <9pan8class9"s6code=_GPI6" cla8s="sr9f">_G9IO6234)
66 href="drivers/pinctrl/pincCTRL_Pd2INDmD1_PDde=PINCTRLl/piP1>&qfs2INDmD1_PDdref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&quact8dmmc39GPI6" class="sref"8_GPIO9/a>6295)
66 href};f">TEGRA_PIN_VI_VSYNC_PD6line" D2INPMass="s6c9ing">&q6s="SPDIF_ne" D2INPMa"RA_PIN_VI_VSYNC_PD6, 9//a>, s/a8, "6" cl8ss="s9ef">_9PIO6237)
66 hrefstatic const unsignedrs/pin8trl/p9nct8dmmc39dat6_/d3_/a>sc#L308" id=9L30sd9mc3_dat6_/d3_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD9&qu8t6" c9ass="9ref">_GPIO6238)
66 href="drivers/ode=PI>&qfs2INDm_PINPWR2  Code=PINCP1e" f 2INDm_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&quact8dmmc39s6code=_GPI6" clas8="sre9">_GP9O6239)
67 href};f">TEGRA_PIN_6" clane" D22NPM class="s6code=_GPI6" clD14"PF 22NPM "RA_PIN_VI_VSYNC_PD6, 9//a>, spa8 clas9="s6code=_GPI6" cl8ss="s9ef">_9PIO6241)
67 hrefstatic const unsignedrs/pin8trl/p9nct8dmmc39dat7_/d4_/a>sc#L308" id=9L30sd9mc3_dat7_/d4_/a>shref[] = {f">TEGRA_PIN_VI_VS8NC_PD9_GPIO6242)
67 href="drivers/ode=PIe" f 2;DAmVI_HSYNC_PDlassPINCP1ss=fs2;DAmVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&quan 8lass=9s6code=_GPI6" clas8="sre9">_GP9O6243)
67 href};f">TEGRA_PIN_6" cla4"PF 23NPM class="s6fode=_GPI6" clD1ssPF 23NPM "RA_PIN_VI_VSYNC_PD6, 9//a>, san8class9="s6code=_GPI6" cl8ss="s9ef">_9PIO6245)
67 hrefstatic const unsignedrs/pin8trl/p9nct8i_d1_9d5_/a>sc#L306" id=8L30vi9d1_/d9_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6,89GPIO<9a>6246)
67 href="drivers/pinctrl/pinc>clas1dap1_fs_pnIND0_PE="+code=PINCT8dap1_fs_pnIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&quact8dmmc39" class="sref">_GP8O9247)
97 href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1DAP1_FS_PNlass="s6f" class=6PIN" cl8DAP1_FS_PNl"RA_PIN_VI_VSYNC_PD6, 9//a>, s/a8, /* All 6on-G8IO pi9s fol9ow */
68 hrefstatic const unsignedrs/pin8trl/p9nct8i_vsy9c_/d6_/a>sc#L306" 8d="L39vi_vs9nc_/d6_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,9TEG9A_PIN9PEE76+ 1)
68 href="drivers/pinctr>clasTdap1_dclasnIND1_PE"L271" class=edap1_dclasnIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&quss=8s6+co9e=off6et" class="s8ef">o9fset<9a>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlDAP1_DIO, 9//a>, spa8 clas9="s6ss="comme6t">/8 Non-9PIO p9ns */
68 hrefstatic const unsignedrs/pin8trl/p9nct8i_hsy9c_/d7_/a>sc#L306" 8d="L39vi_hs9nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,9_PIN(0)
68 href="drivers/pinctr="srcldap1_dclassnIND2_PE"L272" class=1dap1_dclassnIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&qusct8i_d1_9=_GPI6PIN" class="8ref">9PIN(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLDAP1_DpIO&q6LK_32K_1DAP1_DpIO, 9//a>, sla8s="s69="s6"8ing">&q6PIN"8class9"sref9>_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p9nct8cdCd09pe0_/a>sc#L306" id8"L30l9dCd0_9e0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&q6PIN" cl8ss="s9ef">_9IN(4)
68 href="drivers/pinctrl/pie=PIcsdap1_sclassn;DAP2_SCLK PA3pan cl1dap1_sclassn;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&qusct8i_vsy9=6PIN" class="sref8>_PIN9/6>(59
69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSDAP1_S, 9//a>, spa8 clas9="s6f="+code=6PIN"8class9"sref9>_PIN(7)
69 hrefstatic const unsignedrs/pin8trl/p9nct8cdCd19/e1_/a>sc#L306" id8"L30l9dCd1_9e1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6(8)
59 href="drivers/pinctrl/pinccsss=fUj ne="SDMMC3T7_P7_l/piP1lasfUj ne="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&qus6f8="com9e6PIN" class="sref8>_PIN9N99)
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CSssPFsJ, 9//a>, ssp8n cla9="s6="+code=_6IN" 8lass=9sref"9_PINsc#L306" id8"L30l9dCd2_9e2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6 295
59 href="drivers/pinctrl/pinccslasfsdclassnD1_PDde=PINCTRLl/piP1>&qfsdclassnD1_PDdref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&qusct8cdCd09q6"sref">tegra30_p8ns[5 9 {
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CS2"PFSDpIO&q6s="SPDIF_ne" SDpIO, 9//a>, s c8ass="9="s7g">"7ART38CTS_N9PA1&q9ot;),
70 hrefstatic const unsignedrs/pin8trl/p9nct8cdCd39/e3_/a>sc#L306" id8"L30l9dCd3_9e3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD610n f">_GPIO6242)
67 href="drivers/ode=PIe" f cINDn_PINPWR2  Code=PINCP1e" f cINDn_PINPWref[]264" id/pre>cref[] = {f">TEGRA_PIN_VI_VSYNC_PD610n6231)
66 href};f">TEGRA_PIN_" cl" clasDC0, 9//a>,10n2c9ass="10nf="+code=6PIN" cl8ss="s10nf=>10ns */
68 hrefstatic const unsignedrs/pin8trl/p10n3c9ass="10n6PIN" class="sref8>_PIN10n6P>10nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,10n4c9ass="10n"s6="+code=_6IN" 8lass=10n"s>10n>_PIN(0)
68 href="drivers/pinctr="srclhddye"nassnVI_HSYNC_PDlassPINCP1hddye"nassnVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q10n5c9ass="10ne2_/a>sc#L306" id8"L30l10ne2>10n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLHDDY_VNO, 9//a>,10n6c9ass="10nfode=_GPI6s="line8 name10nfo>10n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p10n7c9ass="10n6"sref">tegra30_p8ns10n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"7ART38CTS_N10n"s>10nef">_GPIO6238)
66 href="drivers/ode=PIclpi_dataVI_oIND0_PE="+code=PINCT8clpi_dataVI_oIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q10n9c9ass="10ne3_/a>sc#L306" id8"L30l10ne3>10n6239)
67 href};f">TEGRA_PIN_6" claCLPI1DATA7_POlass="s6f" class=6PIN" cl8CLPI1DATA7_POl"RA_PIN_VI_VSYNC_PD6, 9//a>,101 c9ass="10="s6g">"6DMMC9_DAT210="s>10="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1011c9ass="10dat2_/b5_/a>sc#L309" id=10dat>10=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&quo9;6DMM10n c>10=ef">_GPIO6242)
67 href="drivers/ode=PIrlpi_dataINDoIND1_PE"L271" class=erlpi_dataINDoIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1013c9ass="10s6rng">&quo6DMMC3_9AT0 P10s6r>10=6243)
67 href};f">TEGRA_PIN_6" claRLPI1DATA0, 9//a>,1014c9ass="10="s6gg">"6t;LC9_PWR110="s>10=PINsc#L309" id=10dat>10=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&qu9t6;UA10n c>10="> 295
59 href="drivers/pinctrl/pinccsrlpi_dataINDoIND2_PE"L272" class=1rlpi_dataINDoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1017c9ass="10] = {f">TEGRA_PIN_VI_VS810] =>10={
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CSRLPI1DATA1&q6LK_32K_1RLPI1DATA1, 9//a>,1018c9ass="10="s6">"G6N1_I8C_SDA10="s>10=t;),
70 hrefstatic const unsignedrs/pin8trl/p10=9c9ass="10dat0_/b7_/a>sc#L308" id=10dat>10=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&8u6t;L10n c>10n > 295
59 href="drivers/pinctrl/pinccsrlpi_dataINDo;DAP2_SCLK PA3pan cl1rlpi_dataINDo;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1021c9ass="10s6ring">&qu6t;GMI_8P_N P10s6r>10n6231)
66 href};f">TEGRA_PIN_" cl" RLPI1DATA2, 9//a>,1022c9ass="10="s6r">"6DMMC8_DAT410="s>10ns */
68 hrefstatic const unsignedrs/pin8trl/p1023c9ass="10ts_n_pc0_/a>sc#L308" id=10ts_>10nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1024c9ass="10n class="s6rg">&qu8t6ot;10n c>10n>_PIN(0)
68 href="drivers/pinctr="srclrlpi_data;DAoe="SDMMC3T7_P7_l/piP1rlpi_data;DAoe="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1025c9ass="10s6rg">"6DMMC3_8AT6 P10s6r>10n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLRLPI1DATA3, 9//a>,1026c9ass="10="s6"8">"6quot8VI_D110="s>10n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1027c9ass="101_/c1_/a>sc#L306" 8d="L3101_/>10n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6t;V8_VSYN10s=">10nef">_GPIO6238)
66 href="drivers/ode=PIclpi_datae="o"linGEN1#I2Ce_Dode=PIclpi_datae="o"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1029c9ass="10">&qu6t;VI_HSYNC P87&quo10">&>10n6239)
67 href};f">TEGRA_PIN_6" claCLPI1DATA4&q6s="SPDIF_CLPI1DATA4, 9//a>,103 c9ass="10="s6ring">&qu6" cl8ss="s10="s>10="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1031c9ass="10xdCpc2_/a>sc#L306"8id="L10xdC>10=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6"8class10ass>10=ef">_GPIO6242)
67 href="drivers/ode=PIrlpi_data"lio_PINPWR2  Code=ode=PIrlpi_data"lio_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1033c9ass="10>"6" class="s8ef">_10>&q>10=6243)
67 href};f">TEGRA_PIN_6" claRLPI1DATA5, 9//a>,1034c9ass="10="s6code=_GPI6" cl8ss="s10="s>10=PINTEGRA_PIN_VI_VSYNC_PD6&quo6"8class10ass>10="> 295
59 href="drivers/pinctrl/pinccsrlpi_data_PIoVI_HSYNC_PDlassPINCP1rlpi_data_PIoVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1037c9ass="10">"6" class="s8ef">_10">&>10={
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CSRLPI1DATA6, 9//a>,1038c9ass="10="s6code=_GPI6" cl8ss="s10="s>10=t;),
70 hrefstatic const unsignedrs/pin8trl/p1039c9ass="10c_sclCpc4_/a>sc#L386" id10c_s>10=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD610pa(4)
68 href="drivers/pinctrl/pie=PIcsdap3_fs_ppIND0_PE="+code=PINCT8dap3_fs_ppIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1041c9ass="10="s6code=_GPI6" cl8ss="s10="s>10p>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlDAP3_FS_PPlass="s6f" class=6PIN" cl8DAP3_FS_PPl"RA_PIN_VI_VSYNC_PD6, 9//a>,1042c9ass="10="s6code=_GPI6" cl8ss="s10="s>10ps */
68 hrefstatic const unsignedrs/pin8trl/p1043c9ass="10c_sdaCpc5_/a>sc#L386" id10c_s>10pc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1044c9ass="10pan class="s6cring8>&q6"10pan>10p>_PIN(0)
68 href="drivers/pinctr="srcldap3_dclaspIND1_PE"L271" class=edap3_dclaspIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1045c9ass="10="s6code=_GPI6" cl8ss="s10="s>10p(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLDAP3_DIO, 9//a>,1046c9ass="10="s6c8">"6" cl8ss="s10="s>10p_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1047c9ass="102_/c6_/a>sc#L306" 8d="L3102_/>10p0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6" c8ass="10s=">10pN(4)
68 href="drivers/pinctrl/pie=PIcsdap3_dclasspIND2_PE"L272" class=1dap3_dclasspIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1049c9ass="10=_GPI6" class="sre8">_GP10=_G>10p69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSDAP3_DpIO&q6LK_32K_1DAP3_DpIO, 9//a>,105 c9ass="10="s6code=_GPI6" cl8ss="s10="s>10="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1051c9ass="10n_pc7_/a>sc#L306" 8d="L310n_p>10=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD610=ef">_GPIO6242)
67 href="drivers/ode=PIdap3_sclassp;DAP2_SCLK PA3pan cl1dap3_sclassp;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1053c9ass="10=_GPI6" class="sre8">_GP10=_G>10=6243)
67 href};f">TEGRA_PIN_6" claDAP3_S, 9//a>,1054c9ass="10="s6code=_GPI6" cl8ss="s10="s>10=PIN10=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD610=>6246)
67 href="drivers/pinctrl/pinc>clas1dap4_fs_ppe="SDMMC3T7_P7_l/piP1dap4_fs_ppe="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1057c9ass="10s6c8">"6" clas8="sre10s6c>10= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1DAP4_FS_PPpan class="s6code=_GNC_PD1DAP4_FS_PPp"RA_PIN_VI_VSYNC_PD6, 9//a>,1058c9ass="10="s6code=_GPI6" cl8ss="s10="s>10=t;),
70 hrefstatic const unsignedrs/pin8trl/p1059c9ass="10dat4_/d1_/a>sc#L308" id=10dat>10=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD610n 6246)
67 href="drivers/pinctrl/pinc>clas1dap4_dclasp"linGEN1#I2Ce_Dode=PIdap4_dclasp"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1061c9ass="10s6code=_GPI6" clas8="sre10s6c>10n>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlDAP4_DIO&q6s="SPDIF_DAP4_DIO, 9//a>,1062c9ass="10="s6code=_GPI6" cl8ss="s10="s>10ns */
68 hrefstatic const unsignedrs/pin8trl/p1063c9ass="10_/d2_/a>sc#L306" i8="L3010_/d>10nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1064c9ass="10"s6code=_GPI6" cla8s="sr10"s6>10n>_PIN(0)
68 href="drivers/pinctr="srcldap4_dclassp_PINPWR2  Code=ode=PIdap4_dclassp_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1065c9ass="10GPI6" class="sref"8_GPIO10GPI>10n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLDAP4_DpIO, 9//a>,1066c9ass="10="s6c8">"6" cl8ss="s10="s>10n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1067c9ass="10dat6_/d3_/a>sc#L308" id=10dat>10n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&qu8t6" c10n c>10nN(4)
68 href="drivers/pinctrl/pie=PIcsdap4_sclasspVI_HSYNC_PDlassPINCP1dap4_sclasspVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1069c9ass="10s6code=_GPI6" clas8="sre10s6c>10n69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSDAP4_S, 9//a>,107 c9ass="10="s6code=_GPI6" cl8ss="s10="s>10="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1071c9ass="10dat7_/d4_/a>sc#L308" id=10dat>10=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD610=ef">_GPIO6242)
67 href="drivers/ode=PIkb_coGe=_qIND0_PE="+code=PINCT8kb_coGe=_qIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1073c9ass="10s6code=_GPI6" clas8="sre10s6c>10=6243)
67 href};f">TEGRA_PIN_6" claKB_COL0_PQlass="s6f" class=6PIN" cl8KB_COL0_PQl"RA_PIN_VI_VSYNC_PD6, 9//a>,1074c9ass="10="s6code=_GPI6" cl8ss="s10="s>10=PIN10=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD610ode>10=>6246)
67 href="drivers/pinctrl/pinc>clas1kb_coG1=_qIND1_PE"L271" class=ekb_coG1=_qIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1077c9ass="10" class="sref">_GP8O10" c>10= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1KB_COL1_PQlass="s6="+code=_6IN" claEKB_COL1_PQl"RA_PIN_VI_VSYNC_PD6, 9//a>,1078c9ass="10="s6">/* All 6on-G8IO pi10="s>10=t;),
70 hrefstatic const unsignedrs/pin8trl/p1079c9ass="10c_/d6_/a>sc#L306" 8d="L310c_/>10=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6TEG10s=">10s=6246)
67 href="drivers/pinctrl/pinc>clas1kb_coG2=_qIND2_PE"L272" class=1kb_coG2=_qIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1081c9ass="10e=off6et" class="s8ef">o10e=o>10s>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlKB_COL2_PQlass="s6f9ing">&q6LK_32K_1KB_COL2_PQl"RA_PIN_VI_VSYNC_PD6, 9//a>,1082c9ass="10="s6ss="comme6t">/8 Non-10="s>10ss */
68 hrefstatic const unsignedrs/pin8trl/p1083c9ass="10c_/d7_/a>sc#L306" 8d="L310c_/>10sc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1084c9ass="10s="s67ode=_GPI6PIN8 clas10s=">10s>_PIN(0)
68 href="drivers/pinctr="srclkb_coG3=_q;DAP2_SCLK PA3pan cl1kb_coG3=_q;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1085c9ass="10=_GPI6PIN" class="8ref">10=_G>10s(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLKB_COL3_PQs5code=_GPI5" class="sref1KB_COL3_PQs"RA_PIN_VI_VSYNC_PD6, 9//a>,1086c9ass="10="s6"8ing">&q6PIN"8class10="s>10s_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1087c9ass="10pe0_/a>sc#L306" id8"L30l10pe0>10s0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&q6PIN" cl8ss="s10679>10sN(4)
68 href="drivers/pinctrl/pie=PIcskb_coG4=_qe="SDMMC3T7_P7_l/piP1kb_coG4=_qe="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1089c9ass="10=6PIN" class="sref8>_PIN10=6P>10s69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSKB_COL4_PQpan class="s6code=_GNC_PD1KB_COL4_PQp"RA_PIN_VI_VSYNC_PD6, 9//a>,109 c9ass="10="s6f="+code=6PIN"8class10="s>10="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1091c9ass="10/e1_/a>sc#L306" id8"L30l10/e1>10=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6_GPIO6242)
67 href="drivers/ode=PIkb_coG5=_q"linGEN1#I2Ce_Dode=PIkb_coG5=_q"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1093c9ass="10e6PIN" class="sref8>_PIN10e6P>10=6243)
67 href};f">TEGRA_PIN_6" claKB_COL5_PQass="s6c9ing">&q6s="SPDIF_KB_COL5_PQa"RA_PIN_VI_VSYNC_PD6, 9//a>,1094c9ass="10="s6="+code=_6IN" 8lass=10="s>10=PIN10=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD610=>6246)
67 href="drivers/pinctrl/pinc>clas1kb_coG6=_q_PINPWR2  Code=ode=PIkb_coG6=_q_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1097c9ass="10q6"sref">tegra30_p8ns10= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1KB_COL6_PQ class="s6code=_GPI66" claKB_COL6_PQ "RA_PIN_VI_VSYNC_PD6, 9//a>,1098c9ass="10="s7g">"7ART38CTS_N10="s>10=t;),
70 hrefstatic const unsignedrs/pin8trl/p1099c9ass="10/e3_/a>sc#L306" id8"L30l10/e3>10=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD611n f">_GPIO6242)
67 href="drivers/ode=PIkb_coG7=_qVI_HSYNC_PDlassPINCP1kb_coG7=_qVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q11n1c9ass="11ne1_/a>sc#L306" id8"L30l11ne1>11n6231)
66 href};f">TEGRA_PIN_" cl" KB_COL7_PQ class="s6fode=_GPI6" clD1KB_COL7_PQ "RA_PIN_VI_VSYNC_PD6, 9//a>,11n2c9ass="11nf="+code=6PIN" cl8ss="s11nf=>11ns */
68 hrefstatic const unsignedrs/pin8trl/p11n3c9ass="11n6PIN" class="sref8>_PIN11n6P>11nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,11n4c9ass="11n"s6="+code=_6IN" 8lass=11n"s>11n>_PIN(0)
68 href="drivers/pinctr="srclkb_row0_prIND0_PE="+code=PINCT8kb_row0_prIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q11n5c9ass="11ne2_/a>sc#L306" id8"L30l11ne2>11n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLKB_ROW0_PRlass="s6f" class=6PIN" cl8KB_ROW0_PRl"RA_PIN_VI_VSYNC_PD6, 9//a>,11n6c9ass="11nfode=_GPI6s="line8 name11nfo>11n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p11n7c9ass="11n6"sref">tegra30_p8ns11n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"7ART38CTS_N11n"s>11nef">_GPIO6238)
66 href="drivers/ode=PIkb_row1_prIND1_PE"L271" class=ekb_row1_prIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q11n9c9ass="11ne3_/a>sc#L306" id8"L30l11ne3>11n6239)
67 href};f">TEGRA_PIN_6" claKB_ROW1_PRlass="s6="+code=_6IN" claEKB_ROW1_PRl"RA_PIN_VI_VSYNC_PD6, 9//a>,111 c9ass="11="s6g">"6DMMC9_DAT211="s>11="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1111c9ass="11dat2_/b5_/a>sc#L309" id=11dat>11=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&quo9;6DMM11n c>11=ef">_GPIO6242)
67 href="drivers/ode=PIkb_row2_prIND2_PE"L272" class=1kb_row2_prIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1113c9ass="11s6rng">&quo6DMMC3_9AT0 P11s6r>11=6243)
67 href};f">TEGRA_PIN_6" claKB_ROW2_PRlass="s6f9ing">&q6LK_32K_1KB_ROW2_PRl"RA_PIN_VI_VSYNC_PD6, 9//a>,1114c9ass="11="s6gg">"6t;LC9_PWR111="s>11=PINsc#L309" id=11dat>11=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&qu9t6;UA11n c>11="> 295
59 href="drivers/pinctrl/pinccskb_row3_pr;DAP2_SCLK PA3pan cl1kb_row3_pr;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1117c9ass="11] = {f">TEGRA_PIN_VI_VS811] =>11={
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CSKB_ROW3_PRs5code=_GPI5" class="sref1KB_ROW3_PRs"RA_PIN_VI_VSYNC_PD6, 9//a>,1118c9ass="11="s6">"G6N1_I8C_SDA11="s>11=t;),
70 hrefstatic const unsignedrs/pin8trl/p11=9c9ass="11dat0_/b7_/a>sc#L308" id=11dat>11=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&8u6t;L11n c>11n > 295
59 href="drivers/pinctrl/pinccskb_row4_pre="SDMMC3T7_P7_l/piP1kb_row4_pre="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1121c9ass="11s6ring">&qu6t;GMI_8P_N P11s6r>11n6231)
66 href};f">TEGRA_PIN_" cl" KB_ROW4_PRpan class="s6code=_GNC_PD1KB_ROW4_PRp"RA_PIN_VI_VSYNC_PD6, 9//a>,1122c9ass="11="s6r">"6DMMC8_DAT411="s>11ns */
68 hrefstatic const unsignedrs/pin8trl/p1123c9ass="11ts_n_pc0_/a>sc#L308" id=11ts_>11nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1124c9ass="11n class="s6rg">&qu8t6ot;11n c>11n>_PIN(0)
68 href="drivers/pinctr="srclkb_row5_pr"linGEN1#I2Ce_Dode=PIkb_row5_pr"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1125c9ass="11s6rg">"6DMMC3_8AT6 P11s6r>11n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLKB_ROW5_PRass="s6c9ing">&q6s="SPDIF_KB_ROW5_PRa"RA_PIN_VI_VSYNC_PD6, 9//a>,1126c9ass="11="s6"8">"6quot8VI_D111="s>11n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1127c9ass="111_/c1_/a>sc#L306" 8d="L3111_/>11n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6t;V8_VSYN11s=">11nef">_GPIO6238)
66 href="drivers/ode=PIkb_row6_pr_PINPWR2  Code=ode=PIkb_row6_pr_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1129c9ass="11">&qu6t;VI_HSYNC P87&quo11">&>11n6239)
67 href};f">TEGRA_PIN_6" claKB_ROW6_PR class="s6code=_GPI66" claKB_ROW6_PR "RA_PIN_VI_VSYNC_PD6, 9//a>,113 c9ass="11="s6ring">&qu6" cl8ss="s11="s>11="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1131c9ass="11xdCpc2_/a>sc#L306"8id="L11xdC>11=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6"8class11ass>11=ef">_GPIO6242)
67 href="drivers/ode=PIkb_row7_prVI_HSYNC_PDlassPINCP1kb_row7_prVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1133c9ass="11>"6" class="s8ef">_11>&q>11=6243)
67 href};f">TEGRA_PIN_6" claKB_ROW7_PR class="s6fode=_GPI6" clD1KB_ROW7_PR "RA_PIN_VI_VSYNC_PD6, 9//a>,1134c9ass="11="s6code=_GPI6" cl8ss="s11="s>11=PINTEGRA_PIN_VI_VSYNC_PD6&quo6"8class11ass>11="> 295
59 href="drivers/pinctrl/pinccskb_row8_psIND0_PE="+code=PINCT8kb_row8_psIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1137c9ass="11">"6" class="s8ef">_11">&>11={
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CSKB_ROW8_PSlass="s6f" class=6PIN" cl8KB_ROW8_PSl"RA_PIN_VI_VSYNC_PD6, 9//a>,1138c9ass="11="s6code=_GPI6" cl8ss="s11="s>11=t;),
70 hrefstatic const unsignedrs/pin8trl/p1139c9ass="11c_sclCpc4_/a>sc#L386" id11c_s>11=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD611pa(4)
68 href="drivers/pinctrl/pie=PIcskb_row9_psIND1_PE"L271" class=ekb_row9_psIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1141c9ass="11="s6code=_GPI6" cl8ss="s11="s>11p>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlKB_ROW9_PSlass="s6="+code=_6IN" claEKB_ROW9_PSl"RA_PIN_VI_VSYNC_PD6, 9//a>,1142c9ass="11="s6code=_GPI6" cl8ss="s11="s>11ps */
68 hrefstatic const unsignedrs/pin8trl/p1143c9ass="11c_sdaCpc5_/a>sc#L386" id11c_s>11pc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1144c9ass="11pan class="s6cring8>&q6"11pan>11p>_PIN(0)
68 href="drivers/pinctr="srclkb_row1INDsIND2_PE"L272" class=1kb_row1INDsIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1145c9ass="11="s6code=_GPI6" cl8ss="s11="s>11p(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLKB_ROW10_PSlass="s6f9ing">&q6LK_32K_1KB_ROW10_PSl"RA_PIN_VI_VSYNC_PD6, 9//a>,1146c9ass="11="s6c8">"6" cl8ss="s11="s>11p_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1147c9ass="112_/c6_/a>sc#L306" 8d="L3112_/>11p0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6" c8ass="11s=">11pN(4)
68 href="drivers/pinctrl/pie=PIcskb_row1INDs;DAP2_SCLK PA3pan cl1kb_row1INDs;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1149c9ass="11=_GPI6" class="sre8">_GP11=_G>11p69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSKB_ROW11_PSs5code=_GPI5" class="sref1KB_ROW11_PSs"RA_PIN_VI_VSYNC_PD6, 9//a>,115 c9ass="11="s6code=_GPI6" cl8ss="s11="s>11="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1151c9ass="11n_pc7_/a>sc#L306" 8d="L311n_p>11=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD611=ef">_GPIO6242)
67 href="drivers/ode=PIkb_row1INDse="SDMMC3T7_P7_l/piP1kb_row1INDse="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1153c9ass="11=_GPI6" class="sre8">_GP11=_G>11=6243)
67 href};f">TEGRA_PIN_6" claKB_ROW12_PSpan class="s6code=_GNC_PD1KB_ROW12_PSp"RA_PIN_VI_VSYNC_PD6, 9//a>,1154c9ass="11="s6code=_GPI6" cl8ss="s11="s>11=PIN11=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD611=>6246)
67 href="drivers/pinctrl/pinc>clas1kb_row1;DAs"linGEN1#I2Ce_Dode=PIkb_row1;DAs"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1157c9ass="11s6c8">"6" clas8="sre11s6c>11= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1KB_ROW13_PSass="s6c9ing">&q6s="SPDIF_KB_ROW13_PSa"RA_PIN_VI_VSYNC_PD6, 9//a>,1158c9ass="11="s6code=_GPI6" cl8ss="s11="s>11=t;),
70 hrefstatic const unsignedrs/pin8trl/p1159c9ass="11dat4_/d1_/a>sc#L308" id=11dat>11=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD611n 6246)
67 href="drivers/pinctrl/pinc>clas1kb_row1e="s_PINPWR2  Code=ode=PIkb_row1e="s_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1161c9ass="11s6code=_GPI6" clas8="sre11s6c>11n>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlKB_ROW14_PS class="s6code=_GPI66" claKB_ROW14_PS "RA_PIN_VI_VSYNC_PD6, 9//a>,1162c9ass="11="s6code=_GPI6" cl8ss="s11="s>11ns */
68 hrefstatic const unsignedrs/pin8trl/p1163c9ass="11_/d2_/a>sc#L306" i8="L3011_/d>11nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1164c9ass="11"s6code=_GPI6" cla8s="sr11"s6>11n>_PIN(0)
68 href="drivers/pinctr="srclkb_row1"lisVI_HSYNC_PDlassPINCP1kb_row1"lisVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1165c9ass="11GPI6" class="sref"8_GPIO11GPI>11n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLKB_ROW15_PS class="s6fode=_GPI6" clD1KB_ROW15_PS "RA_PIN_VI_VSYNC_PD6, 9//a>,1166c9ass="11="s6c8">"6" cl8ss="s11="s>11n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1167c9ass="11dat6_/d3_/a>sc#L308" id=11dat>11n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&qu8t6" c11n c>11nN(4)
68 href="drivers/pinctrl/pie=PIcsvi_pclasstIND0_PE="+code=PINCT8vi_pclasstIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1169c9ass="11s6code=_GPI6" clas8="sre11s6c>11n69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSVI_P, 9//a>,117 c9ass="11="s6code=_GPI6" cl8ss="s11="s>11="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1171c9ass="11dat7_/d4_/a>sc#L308" id=11dat>11=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD611=ef">_GPIO6242)
67 href="drivers/ode=PIvi_mclasstIND1_PE"L271" class=evi_mclasstIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1173c9ass="11s6code=_GPI6" clas8="sre11s6c>11=6243)
67 href};f">TEGRA_PIN_6" claVI_M, 9//a>,1174c9ass="11="s6code=_GPI6" cl8ss="s11="s>11=PIN11=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD611ode>11=>6246)
67 href="drivers/pinctrl/pinc>clas1vi_d1INDtIND2_PE"L272" class=1vi_d1INDtIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1177c9ass="11" class="sref">_GP8O11" c>11= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1VI_D10_PTlass="s6f9ing">&q6LK_32K_1VI_D10_PTl"RA_PIN_VI_VSYNC_PD6, 9//a>,1178c9ass="11="s6">/* All 6on-G8IO pi11="s>11=t;),
70 hrefstatic const unsignedrs/pin8trl/p1179c9ass="11c_/d6_/a>sc#L306" 8d="L311c_/>11=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6TEG11s=">11s=6246)
67 href="drivers/pinctrl/pinc>clas1vi_d1INDt;DAP2_SCLK PA3pan cl1vi_d1INDt;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1181c9ass="11e=off6et" class="s8ef">o11e=o>11s>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlVI_D11_PTs5code=_GPI5" class="sref1VI_D11_PTs"RA_PIN_VI_VSYNC_PD6, 9//a>,1182c9ass="11="s6ss="comme6t">/8 Non-11="s>11ss */
68 hrefstatic const unsignedrs/pin8trl/p1183c9ass="11c_/d7_/a>sc#L306" 8d="L311c_/>11sc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1184c9ass="11s="s67ode=_GPI6PIN8 clas11s=">11s>_PIN(0)
68 href="drivers/pinctr="srclvi_dINDte="SDMMC3T7_P7_l/piP1vi_dINDte="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1185c9ass="11=_GPI6PIN" class="8ref">11=_G>11s(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLVI_D0_PTpan class="s6code=_GNC_PD1VI_D0_PTp"RA_PIN_VI_VSYNC_PD6, 9//a>,1186c9ass="11="s6"8ing">&q6PIN"8class11="s>11s_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1187c9ass="11pe0_/a>sc#L306" id8"L30l11pe0>11s0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&q6PIN" cl8ss="s11679>11sN(4)
68 href="drivers/pinctrl/pie=PIcsgen2_i2c_sclNDt"linGEN1#I2Ce_Dode=PIgen2_i2c_sclNDt"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1189c9ass="11=6PIN" class="sref8>_PIN11=6P>11s69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSGEN2_I2C_S&q6s="SPDIF_GEN2_I2C_S, 9//a>,119 c9ass="11="s6f="+code=6PIN"8class11="s>11="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1191c9ass="11/e1_/a>sc#L306" id8"L30l11/e1>11=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6_GPIO6242)
67 href="drivers/ode=PIgen2_i2c_sdaNDt_PINPWR2  Code=ode=PIgen2_i2c_sdaNDt_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1193c9ass="11e6PIN" class="sref8>_PIN11e6P>11=6243)
67 href};f">TEGRA_PIN_6" claGEN2_I2C_SD6" T class="s6code=_GPI66" claGEN2_I2C_SD6" T "RA_PIN_VI_VSYNC_PD6, 9//a>,1194c9ass="11="s6="+code=_6IN" 8lass=11="s>11=PIN11=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD611=>6246)
67 href="drivers/pinctrl/pinc>clas1sdmmc4_cmdNDtVI_HSYNC_PDlassPINCP1sdmmc4_cmdNDtVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1197c9ass="11q6"sref">tegra30_p8ns11= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1SDMMC4_CMD" T class="s6fode=_GPI6" clD1SDMMC4_CMD" T "RA_PIN_VI_VSYNC_PD6, 9//a>,1198c9ass="11="s7g">"7ART38CTS_N11="s>11=t;),
70 hrefstatic const unsignedrs/pin8trl/p1199c9ass="11/e3_/a>sc#L306" id8"L30l11/e3>11=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD612n f">_GPIO6242)
67 href="drivers/ode=PIpuIND0_PE="+code=PINCT8puIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q12n1c9ass="12ne1_/a>sc#L306" id8"L30l12ne1>12n6231)
66 href};f">TEGRA_PIN_" cl" PUlass="s6f" class=6PIN" cl8PUl"RA_PIN_VI_VSYNC_PD6, 9//a>,12n2c9ass="12nf="+code=6PIN" cl8ss="s12nf=>12ns */
68 hrefstatic const unsignedrs/pin8trl/p12n3c9ass="12n6PIN" class="sref8>_PIN12n6P>12nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,12n4c9ass="12n"s6="+code=_6IN" 8lass=12n"s>12n>_PIN(0)
68 href="drivers/pinctr="srclpuIND1_PE"L271" class=epuIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q12n5c9ass="12ne2_/a>sc#L306" id8"L30l12ne2>12n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLPUlass="s6="+code=_6IN" claEPUl"RA_PIN_VI_VSYNC_PD6, 9//a>,12n6c9ass="12nfode=_GPI6s="line8 name12nfo>12n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p12n7c9ass="12n6"sref">tegra30_p8ns12n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"7ART38CTS_N12n"s>12nef">_GPIO6238)
66 href="drivers/ode=PIpuIND2_PE"L272" class=1puIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q12n9c9ass="12ne3_/a>sc#L306" id8"L30l12ne3>12n6239)
67 href};f">TEGRA_PIN_6" claPUlass="s6f9ing">&q6LK_32K_1PUl"RA_PIN_VI_VSYNC_PD6, 9//a>,121 c9ass="12="s6g">"6DMMC9_DAT212="s>12="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1211c9ass="12dat2_/b5_/a>sc#L309" id=12dat>12=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&quo9;6DMM12n c>12=ef">_GPIO6242)
67 href="drivers/ode=PIpu;DAP2_SCLK PA3pan cl1pu;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1213c9ass="12s6rng">&quo6DMMC3_9AT0 P12s6r>12=6243)
67 href};f">TEGRA_PIN_6" claPUs5code=_GPI5" class="sref1PUs"RA_PIN_VI_VSYNC_PD6, 9//a>,1214c9ass="12="s6gg">"6t;LC9_PWR112="s>12=PINsc#L309" id=12dat>12=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&qu9t6;UA12n c>12="> 295
59 href="drivers/pinctrl/pinccspue="SDMMC3T7_P7_l/piP1pue="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1217c9ass="12] = {f">TEGRA_PIN_VI_VS812] =>12={
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CSPUpan class="s6code=_GNC_PD1PUp"RA_PIN_VI_VSYNC_PD6, 9//a>,1218c9ass="12="s6">"G6N1_I8C_SDA12="s>12=t;),
70 hrefstatic const unsignedrs/pin8trl/p12=9c9ass="12dat0_/b7_/a>sc#L308" id=12dat>12=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&8u6t;L12n c>12n > 295
59 href="drivers/pinctrl/pinccspu"linGEN1#I2Ce_Dode=PIpu"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1221c9ass="12s6ring">&qu6t;GMI_8P_N P12s6r>12n6231)
66 href};f">TEGRA_PIN_" cl" PUass="s6c9ing">&q6s="SPDIF_PUa"RA_PIN_VI_VSYNC_PD6, 9//a>,1222c9ass="12="s6r">"6DMMC8_DAT412="s>12ns */
68 hrefstatic const unsignedrs/pin8trl/p1223c9ass="12ts_n_pc0_/a>sc#L308" id=12ts_>12nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1224c9ass="12n class="s6rg">&qu8t6ot;12n c>12n>_PIN(0)
68 href="drivers/pinctr="srclpu_PINPWR2  Code=ode=PIpu_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1225c9ass="12s6rg">"6DMMC3_8AT6 P12s6r>12n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLPU class="s6code=_GPI66" claPU "RA_PIN_VI_VSYNC_PD6, 9//a>,1226c9ass="12="s6"8">"6quot8VI_D112="s>12n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1227c9ass="121_/c1_/a>sc#L306" 8d="L3121_/>12n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6t;V8_VSYN12s=">12nef">_GPIO6238)
66 href="drivers/ode=PIjtag_rtck_puVI_HSYNC_PDlassPINCP1jtag_rtck_puVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1229c9ass="12">&qu6t;VI_HSYNC P87&quo12">&>12n6239)
67 href};f">TEGRA_PIN_6" claJTAG_RTCKaPU class="s6fode=_GPI6" clD1JTAG_RTCKaPU "RA_PIN_VI_VSYNC_PD6, 9//a>,123 c9ass="12="s6ring">&qu6" cl8ss="s12="s>12="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1231c9ass="12xdCpc2_/a>sc#L306"8id="L12xdC>12=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6"8class12ass>12=ef">_GPIO6242)
67 href="drivers/ode=PIpvIND0_PE="+code=PINCT8pvIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1233c9ass="12>"6" class="s8ef">_12>&q>12=6243)
67 href};f">TEGRA_PIN_6" claPVlass="s6f" class=6PIN" cl8PVl"RA_PIN_VI_VSYNC_PD6, 9//a>,1234c9ass="12="s6code=_GPI6" cl8ss="s12="s>12=PINTEGRA_PIN_VI_VSYNC_PD6&quo6"8class12ass>12="> 295
59 href="drivers/pinctrl/pinccspvIND1_PE"L271" class=epvIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1237c9ass="12">"6" class="s8ef">_12">&>12={
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CSPVlass="s6="+code=_6IN" claEPVl"RA_PIN_VI_VSYNC_PD6, 9//a>,1238c9ass="12="s6code=_GPI6" cl8ss="s12="s>12=t;),
70 hrefstatic const unsignedrs/pin8trl/p1239c9ass="12c_sclCpc4_/a>sc#L386" id12c_s>12=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD612pa(4)
68 href="drivers/pinctrl/pie=PIcspvIND2_PE"L272" class=1pvIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1241c9ass="12="s6code=_GPI6" cl8ss="s12="s>12p>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlPVlass="s6f9ing">&q6LK_32K_1PVl"RA_PIN_VI_VSYNC_PD6, 9//a>,1242c9ass="12="s6code=_GPI6" cl8ss="s12="s>12ps */
68 hrefstatic const unsignedrs/pin8trl/p1243c9ass="12c_sdaCpc5_/a>sc#L386" id12c_s>12pc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1244c9ass="12pan class="s6cring8>&q6"12pan>12p>_PIN(0)
68 href="drivers/pinctr="srclpv;DAP2_SCLK PA3pan cl1pv;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1245c9ass="12="s6code=_GPI6" cl8ss="s12="s>12p(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLPVs5code=_GPI5" class="sref1PVs"RA_PIN_VI_VSYNC_PD6, 9//a>,1246c9ass="12="s6c8">"6" cl8ss="s12="s>12p_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1247c9ass="122_/c6_/a>sc#L306" 8d="L3122_/>12p0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6" c8ass="12s=">12pN(4)
68 href="drivers/pinctrl/pie=PIcsddc_sclNDve="SDMMC3T7_P7_l/piP1ddc_sclNDve="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1249c9ass="12=_GPI6" class="sre8">_GP12=_G>12p69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSDDC_S, 9//a>,125 c9ass="12="s6code=_GPI6" cl8ss="s12="s>12="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1251c9ass="12n_pc7_/a>sc#L306" 8d="L312n_p>12=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD612=ef">_GPIO6242)
67 href="drivers/ode=PIddc_sdaNDv"linGEN1#I2Ce_Dode=PIddc_sdaNDv"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1253c9ass="12=_GPI6" class="sre8">_GP12=_G>12=6243)
67 href};f">TEGRA_PIN_6" claDDC_SD6" Vass="s6c9ing">&q6s="SPDIF_DDC_SD6" Va"RA_PIN_VI_VSYNC_PD6, 9//a>,1254c9ass="12="s6code=_GPI6" cl8ss="s12="s>12=PIN12=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD612=>6246)
67 href="drivers/pinctrl/pinc>clas1crt_hsyncNDv_PINPWR2  Code=ode=PIcrt_hsyncNDv_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1257c9ass="12s6c8">"6" clas8="sre12s6c>12= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1CRT_HSYNC" V class="s6code=_GPI66" claCRT_HSYNC" V "RA_PIN_VI_VSYNC_PD6, 9//a>,1258c9ass="12="s6code=_GPI6" cl8ss="s12="s>12=t;),
70 hrefstatic const unsignedrs/pin8trl/p1259c9ass="12dat4_/d1_/a>sc#L308" id=12dat>12=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD612n 6246)
67 href="drivers/pinctrl/pinc>clas1crt_vsyncNDvVI_HSYNC_PDlassPINCP1crt_vsyncNDvVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1261c9ass="12s6code=_GPI6" clas8="sre12s6c>12n>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlCRT_VSYNC" V class="s6fode=_GPI6" clD1CRT_VSYNC" V "RA_PIN_VI_VSYNC_PD6, 9//a>,1262c9ass="12="s6code=_GPI6" cl8ss="s12="s>12ns */
68 hrefstatic const unsignedrs/pin8trl/p1263c9ass="12_/d2_/a>sc#L306" i8="L3012_/d>12nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1264c9ass="12"s6code=_GPI6" cla8s="sr12"s6>12n>_PIN(0)
68 href="drivers/pinctr="srcllcd_cs1_n_pwIND0_PE="+code=PINCT8lcd_cs1_n_pwIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1265c9ass="12GPI6" class="sref"8_GPIO12GPI>12n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLLCD_CS1_f1PWlass="s6f" class=6PIN" cl8LCD_CS1_f1PWl"RA_PIN_VI_VSYNC_PD6, 9//a>,1266c9ass="12="s6c8">"6" cl8ss="s12="s>12n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1267c9ass="12dat6_/d3_/a>sc#L308" id=12dat>12n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&qu8t6" c12n c>12nN(4)
68 href="drivers/pinctrl/pie=PIcslcd_m1_pwIND1_PE"L271" class=elcd_m1_pwIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1269c9ass="12s6code=_GPI6" clas8="sre12s6c>12n69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSLCD_M11PWlass="s6="+code=_6IN" claELCD_M11PWl"RA_PIN_VI_VSYNC_PD6, 9//a>,127 c9ass="12="s6code=_GPI6" cl8ss="s12="s>12="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1271c9ass="12dat7_/d4_/a>sc#L308" id=12dat>12=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD612=ef">_GPIO6242)
67 href="drivers/ode=PIspi2_cs1_n_pwIND2_PE"L272" class=1spi2_cs1_n_pwIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1273c9ass="12s6code=_GPI6" clas8="sre12s6c>12=6243)
67 href};f">TEGRA_PIN_6" claSPI2_CS1_f1PWlass="s6f9ing">&q6LK_32K_1SPI2_CS1_f1PWl"RA_PIN_VI_VSYNC_PD6, 9//a>,1274c9ass="12="s6code=_GPI6" cl8ss="s12="s>12=PIN12=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD612ode>12=>6246)
67 href="drivers/pinctrl/pinc>clas1spi2_cs2_n_pw;DAP2_SCLK PA3pan cl1spi2_cs2_n_pw;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1277c9ass="12" class="sref">_GP8O12" c>12= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1SPI2_CS2_f1PWs5code=_GPI5" class="sref1SPI2_CS2_f1PWs"RA_PIN_VI_VSYNC_PD6, 9//a>,1278c9ass="12="s6">/* All 6on-G8IO pi12="s>12=t;),
70 hrefstatic const unsignedrs/pin8trl/p1279c9ass="12c_/d6_/a>sc#L306" 8d="L312c_/>12=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6TEG12s=">12s=6246)
67 href="drivers/pinctrl/pinc>clas1clk1_classwe="SDMMC3T7_P7_l/piP1clk1_classwe="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1281c9ass="12e=off6et" class="s8ef">o12e=o>12s>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlCLK1_pIO, 9//a>,1282c9ass="12="s6ss="comme6t">/8 Non-12="s>12ss */
68 hrefstatic const unsignedrs/pin8trl/p1283c9ass="12c_/d7_/a>sc#L306" 8d="L312c_/>12sc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1284c9ass="12s="s67ode=_GPI6PIN8 clas12s=">12s>_PIN(0)
68 href="drivers/pinctr="srclclk2_classw"linGEN1#I2Ce_Dode=PIclk2_classw"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1285c9ass="12=_GPI6PIN" class="8ref">12=_G>12s(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLCLK2_pIO&q6s="SPDIF_CLK2_pIO, 9//a>,1286c9ass="12="s6"8ing">&q6PIN"8class12="s>12s_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1287c9ass="12pe0_/a>sc#L306" id8"L30l12pe0>12s0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&q6PIN" cl8ss="s12679>12sN(4)
68 href="drivers/pinctrl/pie=PIcsuart3_txdssw_PINPWR2  Code=ode=PIuart3_txdssw_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1289c9ass="12=6PIN" class="sref8>_PIN12=6P>12s69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSUART3_TXD, 9//a>,129 c9ass="12="s6f="+code=6PIN"8class12="s>12="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1291c9ass="12/e1_/a>sc#L306" id8"L30l12/e1>12=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6_GPIO6242)
67 href="drivers/ode=PIuart3_rxdsswVI_HSYNC_PDlassPINCP1uart3_rxdsswVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1293c9ass="12e6PIN" class="sref8>_PIN12e6P>12=6243)
67 href};f">TEGRA_PIN_6" claUART3_RXD, 9//a>,1294c9ass="12="s6="+code=_6IN" 8lass=12="s>12=PIN12=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD612=>6246)
67 href="drivers/pinctrl/pinc>clas1spi2_mosi_pxIND0_PE="+code=PINCT8spi2_mosi_pxIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1297c9ass="12q6"sref">tegra30_p8ns12= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1SPI2_MOSI_PXlass="s6f" class=6PIN" cl8SPI2_MOSI_PXl"RA_PIN_VI_VSYNC_PD6, 9//a>,1298c9ass="12="s7g">"7ART38CTS_N12="s>12=t;),
70 hrefstatic const unsignedrs/pin8trl/p1299c9ass="12/e3_/a>sc#L306" id8"L30l12/e3>12=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD613n f">_GPIO6242)
67 href="drivers/ode=PIspi2_miso_pxIND1_PE"L271" class=espi2_miso_pxIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q13n1c9ass="13ne1_/a>sc#L306" id8"L30l13ne1>13n6231)
66 href};f">TEGRA_PIN_" cl" SPI2_MISO_PXlass="s6="+code=_6IN" claESPI2_MISO_PXl"RA_PIN_VI_VSYNC_PD6, 9//a>,13n2c9ass="13nf="+code=6PIN" cl8ss="s13nf=>13ns */
68 hrefstatic const unsignedrs/pin8trl/p13n3c9ass="13n6PIN" class="sref8>_PIN13n6P>13nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,13n4c9ass="13n"s6="+code=_6IN" 8lass=13n"s>13n>_PIN(0)
68 href="drivers/pinctr="srclspi2_sck_pxIND2_PE"L272" class=1spi2_sck_pxIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q13n5c9ass="13ne2_/a>sc#L306" id8"L30l13ne2>13n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLSPI2_SCKaPXlass="s6f9ing">&q6LK_32K_1SPI2_SCKaPXl"RA_PIN_VI_VSYNC_PD6, 9//a>,13n6c9ass="13nfode=_GPI6s="line8 name13nfo>13n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p13n7c9ass="13n6"sref">tegra30_p8ns13n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"7ART38CTS_N13n"s>13nef">_GPIO6238)
66 href="drivers/ode=PIspi2_cs0_n_px;DAP2_SCLK PA3pan cl1spi2_cs0_n_px;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q13n9c9ass="13ne3_/a>sc#L306" id8"L30l13ne3>13n6239)
67 href};f">TEGRA_PIN_6" claSPI2_CS0_f1PXs5code=_GPI5" class="sref1SPI2_CS0_f1PXs"RA_PIN_VI_VSYNC_PD6, 9//a>,131 c9ass="13="s6g">"6DMMC9_DAT213="s>13="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1311c9ass="13dat2_/b5_/a>sc#L309" id=13dat>13=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&quo9;6DMM13n c>13=ef">_GPIO6242)
67 href="drivers/ode=PIspi1_mosi_pxe="SDMMC3T7_P7_l/piP1spi1_mosi_pxe="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1313c9ass="13s6rng">&quo6DMMC3_9AT0 P13s6r>13=6243)
67 href};f">TEGRA_PIN_6" claSPI1_MOSI_PXpan class="s6code=_GNC_PD1SPI1_MOSI_PXp"RA_PIN_VI_VSYNC_PD6, 9//a>,1314c9ass="13="s6gg">"6t;LC9_PWR113="s>13=PINsc#L309" id=13dat>13=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&qu9t6;UA13n c>13="> 295
59 href="drivers/pinctrl/pinccsspi1_sck_px"linGEN1#I2Ce_Dode=PIspi1_sck_px"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1317c9ass="13] = {f">TEGRA_PIN_VI_VS813] =>13={
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CSSPI1_SCKaPXass="s6c9ing">&q6s="SPDIF_SPI1_SCKaPXa"RA_PIN_VI_VSYNC_PD6, 9//a>,1318c9ass="13="s6">"G6N1_I8C_SDA13="s>13=t;),
70 hrefstatic const unsignedrs/pin8trl/p13=9c9ass="13dat0_/b7_/a>sc#L308" id=13dat>13=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&8u6t;L13n c>13n > 295
59 href="drivers/pinctrl/pinccsspi1_cs0_n_px_PINPWR2  Code=ode=PIspi1_cs0_n_px_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1321c9ass="13s6ring">&qu6t;GMI_8P_N P13s6r>13n6231)
66 href};f">TEGRA_PIN_" cl" SPI1_CS0_f1PX class="s6code=_GPI66" claSPI1_CS0_f1PX "RA_PIN_VI_VSYNC_PD6, 9//a>,1322c9ass="13="s6r">"6DMMC8_DAT413="s>13ns */
68 hrefstatic const unsignedrs/pin8trl/p1323c9ass="13ts_n_pc0_/a>sc#L308" id=13ts_>13nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1324c9ass="13n class="s6rg">&qu8t6ot;13n c>13n>_PIN(0)
68 href="drivers/pinctr="srclspi1_miso_pxVI_HSYNC_PDlassPINCP1spi1_miso_pxVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1325c9ass="13s6rg">"6DMMC3_8AT6 P13s6r>13n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLSPI1_MISO_PX class="s6fode=_GPI6" clD1SPI1_MISO_PX "RA_PIN_VI_VSYNC_PD6, 9//a>,1326c9ass="13="s6"8">"6quot8VI_D113="s>13n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1327c9ass="131_/c1_/a>sc#L306" 8d="L3131_/>13n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6t;V8_VSYN13s=">13nef">_GPIO6238)
66 href="drivers/ode=PIulpi_classyIND0_PE="+code=PINCT8ulpi_classyIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1329c9ass="13">&qu6t;VI_HSYNC P87&quo13">&>13n6239)
67 href};f">TEGRA_PIN_6" claULPI_, 9//a>,133 c9ass="13="s6ring">&qu6" cl8ss="s13="s>13="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1331c9ass="13xdCpc2_/a>sc#L306"8id="L13xdC>13=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6"8class13ass>13=ef">_GPIO6242)
67 href="drivers/ode=PIulpi_dirssyIND1_PE"L271" class=eulpi_dirssyIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1333c9ass="13>"6" class="s8ef">_13>&q>13=6243)
67 href};f">TEGRA_PIN_6" claULPI_DIR, 9//a>,1334c9ass="13="s6code=_GPI6" cl8ss="s13="s>13=PINTEGRA_PIN_VI_VSYNC_PD6&quo6"8class13ass>13="> 295
59 href="drivers/pinctrl/pinccsulpi_nxtssyIND2_PE"L272" class=1ulpi_nxtssyIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1337c9ass="13">"6" class="s8ef">_13">&>13={
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CSULPI_NXT&q6LK_32K_1ULPI_NXT, 9//a>,1338c9ass="13="s6code=_GPI6" cl8ss="s13="s>13=t;),
70 hrefstatic const unsignedrs/pin8trl/p1339c9ass="13c_sclCpc4_/a>sc#L386" id13c_s>13=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD613pa(4)
68 href="drivers/pinctrl/pie=PIcsulpi_stpssy;DAP2_SCLK PA3pan cl1ulpi_stpssy;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1341c9ass="13="s6code=_GPI6" cl8ss="s13="s>13p>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlULPI_STP, 9//a>,1342c9ass="13="s6code=_GPI6" cl8ss="s13="s>13ps */
68 hrefstatic const unsignedrs/pin8trl/p1343c9ass="13c_sdaCpc5_/a>sc#L386" id13c_s>13pc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1344c9ass="13pan class="s6cring8>&q6"13pan>13p>_PIN(0)
68 href="drivers/pinctr="srclsdmmc1_dat;DAye="SDMMC3T7_P7_l/piP1sdmmc1_dat;DAye="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1345c9ass="13="s6code=_GPI6" cl8ss="s13="s>13p(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLSDMMC1_DAT3, 9//a>,1346c9ass="13="s6c8">"6" cl8ss="s13="s>13p_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1347c9ass="132_/c6_/a>sc#L306" 8d="L3132_/>13p0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6" c8ass="13s=">13pN(4)
68 href="drivers/pinctrl/pie=PIcssdmmc1_datINDy"linGEN1#I2Ce_Dode=PIsdmmc1_datINDy"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1349c9ass="13=_GPI6" class="sre8">_GP13=_G>13p69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSSDMMC1_DAT2&q6s="SPDIF_SDMMC1_DAT2, 9//a>,135 c9ass="13="s6code=_GPI6" cl8ss="s13="s>13="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1351c9ass="13n_pc7_/a>sc#L306" 8d="L313n_p>13=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD613=ef">_GPIO6242)
67 href="drivers/ode=PIsdmmc1_datINDy_PINPWR2  Code=ode=PIsdmmc1_datINDy_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1353c9ass="13=_GPI6" class="sre8">_GP13=_G>13=6243)
67 href};f">TEGRA_PIN_6" claSDMMC1_DAT1, 9//a>,1354c9ass="13="s6code=_GPI6" cl8ss="s13="s>13=PIN13=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD613=>6246)
67 href="drivers/pinctrl/pinc>clas1sdmmc1_datINDyVI_HSYNC_PDlassPINCP1sdmmc1_datINDyVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1357c9ass="13s6c8">"6" clas8="sre13s6c>13= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1SDMMC1_DAT0, 9//a>,1358c9ass="13="s6code=_GPI6" cl8ss="s13="s>13=t;),
70 hrefstatic const unsignedrs/pin8trl/p1359c9ass="13dat4_/d1_/a>sc#L308" id=13dat>13=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD613n 6246)
67 href="drivers/pinctrl/pinc>clas1sdmmc1_classzIND0_PE="+code=PINCT8sdmmc1_classzIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1361c9ass="13s6code=_GPI6" clas8="sre13s6c>13n>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlSDMMC1_, 9//a>,1362c9ass="13="s6code=_GPI6" cl8ss="s13="s>13ns */
68 hrefstatic const unsignedrs/pin8trl/p1363c9ass="13_/d2_/a>sc#L306" i8="L3013_/d>13nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1364c9ass="13"s6code=_GPI6" cla8s="sr13"s6>13n>_PIN(0)
68 href="drivers/pinctr="srclsdmmc1_cmdNDzIND1_PE"L271" class=esdmmc1_cmdNDzIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1365c9ass="13GPI6" class="sref"8_GPIO13GPI>13n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLSDMMC1_, 9//a>,1366c9ass="13="s6c8">"6" cl8ss="s13="s>13n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1367c9ass="13dat6_/d3_/a>sc#L308" id=13dat>13n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&qu8t6" c13n c>13nN(4)
68 href="drivers/pinctrl/pie=PIcslcd_sdinNDzIND2_PE"L272" class=1lcd_sdinNDzIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1369c9ass="13s6code=_GPI6" clas8="sre13s6c>13n69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSLCD_SDef1PZlass="s6f9ing">&q6LK_32K_1LCD_SDef1PZl"RA_PIN_VI_VSYNC_PD6, 9//a>,137 c9ass="13="s6code=_GPI6" cl8ss="s13="s>13="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1371c9ass="13dat7_/d4_/a>sc#L308" id=13dat>13=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD613=ef">_GPIO6242)
67 href="drivers/ode=PIlcd_wr_n_pz;DAP2_SCLK PA3pan cl1lcd_wr_n_pz;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1373c9ass="13s6code=_GPI6" clas8="sre13s6c>13=6243)
67 href};f">TEGRA_PIN_6" claLCD_WR_f1PZs5code=_GPI5" class="sref1LCD_WR_f1PZs"RA_PIN_VI_VSYNC_PD6, 9//a>,1374c9ass="13="s6code=_GPI6" cl8ss="s13="s>13=PIN13=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD613ode>13=>6246)
67 href="drivers/pinctrl/pinc>clas1lcd_sck_pze="SDMMC3T7_P7_l/piP1lcd_sck_pze="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1377c9ass="13" class="sref">_GP8O13" c>13= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1LCD_SCKaPZpan class="s6code=_GNC_PD1LCD_SCKaPZp"RA_PIN_VI_VSYNC_PD6, 9//a>,1378c9ass="13="s6">/* All 6on-G8IO pi13="s>13=t;),
70 hrefstatic const unsignedrs/pin8trl/p1379c9ass="13c_/d6_/a>sc#L306" 8d="L313c_/>13=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6TEG13s=">13s=6246)
67 href="drivers/pinctrl/pinc>clas1sys_clasreq_pz"linGEN1#I2Ce_Dode=PIsys_clasreq_pz"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1381c9ass="13e=off6et" class="s8ef">o13e=o>13s>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlSYS_&q6s="SPDIF_SYS_, 9//a>,1382c9ass="13="s6ss="comme6t">/8 Non-13="s>13ss */
68 hrefstatic const unsignedrs/pin8trl/p1383c9ass="13c_/d7_/a>sc#L306" 8d="L313c_/>13sc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1384c9ass="13s="s67ode=_GPI6PIN8 clas13s=">13s>_PIN(0)
68 href="drivers/pinctr="srclpwr_i2c_sclNDz_PINPWR2  Code=ode=PIpwr_i2c_sclNDz_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1385c9ass="13=_GPI6PIN" class="8ref">13=_G>13s(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLPWR_I2C_S, 9//a>,1386c9ass="13="s6"8ing">&q6PIN"8class13="s>13s_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1387c9ass="13pe0_/a>sc#L306" id8"L30l13pe0>13s0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&q6PIN" cl8ss="s13679>13sN(4)
68 href="drivers/pinctrl/pie=PIcspwr_i2c_sdaNDzVI_HSYNC_PDlassPINCP1pwr_i2c_sdaNDzVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1389c9ass="13=6PIN" class="sref8>_PIN13=6P>13s69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSPWR_I2C_SD6" Z class="s6fode=_GPI6" clD1PWR_I2C_SD6" Z "RA_PIN_VI_VSYNC_PD6, 9//a>,139 c9ass="13="s6f="+code=6PIN"8class13="s>13="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1391c9ass="13/e1_/a>sc#L306" id8"L30l13/e1>13=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6_GPIO6242)
67 href="drivers/ode=PIsdmmc4_datINDaaIND0_PE="+code=PINCT8sdmmc4_datINDaaIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1393c9ass="13e6PIN" class="sref8>_PIN13e6P>13=6243)
67 href};f">TEGRA_PIN_6" claSDMMC4_DAT0, 9//a>,1394c9ass="13="s6="+code=_6IN" 8lass=13="s>13=PIN13=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD613=>6246)
67 href="drivers/pinctrl/pinc>clas1sdmmc4_datINDaaIND1_PE"L271" class=esdmmc4_datINDaaIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1397c9ass="13q6"sref">tegra30_p8ns13= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1SDMMC4_DAT1, 9//a>,1398c9ass="13="s7g">"7ART38CTS_N13="s>13=t;),
70 hrefstatic const unsignedrs/pin8trl/p1399c9ass="13/e3_/a>sc#L306" id8"L30l13/e3>13=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD614n f">_GPIO6242)
67 href="drivers/ode=PIsdmmc4_dat2NDaaIND2_PE"L272" class=1sdmmc4_dat2NDaaIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q14n1c9ass="14ne1_/a>sc#L306" id8"L30l14ne1>14n6231)
66 href};f">TEGRA_PIN_" cl" SDMMC4_DAT2&q6LK_32K_1SDMMC4_DAT2, 9//a>,14n2c9ass="14nf="+code=6PIN" cl8ss="s14nf=>14ns */
68 hrefstatic const unsignedrs/pin8trl/p14n3c9ass="14n6PIN" class="sref8>_PIN14n6P>14nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,14n4c9ass="14n"s6="+code=_6IN" 8lass=14n"s>14n>_PIN(0)
68 href="drivers/pinctr="srclsdmmc4_dat3NDaa;DAP2_SCLK PA3pan cl1sdmmc4_dat3NDaa;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q14n5c9ass="14ne2_/a>sc#L306" id8"L30l14ne2>14n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLSDMMC4_DAT3, 9//a>,14n6c9ass="14nfode=_GPI6s="line8 name14nfo>14n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p14n7c9ass="14n6"sref">tegra30_p8ns14n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"7ART38CTS_N14n"s>14nef">_GPIO6238)
66 href="drivers/ode=PIsdmmc4_dat4NDaae="SDMMC3T7_P7_l/piP1sdmmc4_dat4NDaae="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q14n9c9ass="14ne3_/a>sc#L306" id8"L30l14ne3>14n6239)
67 href};f">TEGRA_PIN_6" claSDMMC4_DAT4, 9//a>,141 c9ass="14="s6g">"6DMMC9_DAT214="s>14="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1411c9ass="14dat2_/b5_/a>sc#L309" id=14dat>14=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&quo9;6DMM14n c>14=ef">_GPIO6242)
67 href="drivers/ode=PIsdmmc4_dat5NDaa"linGEN1#I2Ce_Dode=PIsdmmc4_dat5NDaa"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1413c9ass="14s6rng">&quo6DMMC3_9AT0 P14s6r>14=6243)
67 href};f">TEGRA_PIN_6" claSDMMC4_DAT5&q6s="SPDIF_SDMMC4_DAT5, 9//a>,1414c9ass="14="s6gg">"6t;LC9_PWR114="s>14=PINsc#L309" id=14dat>14=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&qu9t6;UA14n c>14="> 295
59 href="drivers/pinctrl/pinccssdmmc4_dat6NDaa_PINPWR2  Code=ode=PIsdmmc4_dat6NDaa_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1417c9ass="14] = {f">TEGRA_PIN_VI_VS814] =>14={
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CSSDMMC4_DAT6, 9//a>,1418c9ass="14="s6">"G6N1_I8C_SDA14="s>14=t;),
70 hrefstatic const unsignedrs/pin8trl/p14=9c9ass="14dat0_/b7_/a>sc#L308" id=14dat>14=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&8u6t;L14n c>14n > 295
59 href="drivers/pinctrl/pinccssdmmc4_dat7NDaaVI_HSYNC_PDlassPINCP1sdmmc4_dat7NDaaVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1421c9ass="14s6ring">&qu6t;GMI_8P_N P14s6r>14n6231)
66 href};f">TEGRA_PIN_" cl" SDMMC4_DAT7, 9//a>,1422c9ass="14="s6r">"6DMMC8_DAT414="s>14ns */
68 hrefstatic const unsignedrs/pin8trl/p1423c9ass="14ts_n_pc0_/a>sc#L308" id=14ts_>14nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1424c9ass="14n class="s6rg">&qu8t6ot;14n c>14n>_PIN(0)
68 href="drivers/pinctr="srclpbbIND0_PE="+code=PINCT8pbbIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1425c9ass="14s6rg">"6DMMC3_8AT6 P14s6r>14n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLPBBlass="s6f" class=6PIN" cl8PBBl"RA_PIN_VI_VSYNC_PD6, 9//a>,1426c9ass="14="s6"8">"6quot8VI_D114="s>14n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1427c9ass="141_/c1_/a>sc#L306" 8d="L3141_/>14n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6t;V8_VSYN14s=">14nef">_GPIO6238)
66 href="drivers/ode=PIcam_i2c_sclNDbbIND1_PE"L271" class=ecam_i2c_sclNDbbIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1429c9ass="14">&qu6t;VI_HSYNC P87&quo14">&>14n6239)
67 href};f">TEGRA_PIN_6" claCAM_I2C_S, 9//a>,143 c9ass="14="s6ring">&qu6" cl8ss="s14="s>14="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1431c9ass="14xdCpc2_/a>sc#L306"8id="L14xdC>14=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6"8class14ass>14=ef">_GPIO6242)
67 href="drivers/ode=PIcam_i2c_sdaNDbbIND2_PE"L272" class=1cam_i2c_sdaNDbbIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1433c9ass="14>"6" class="s8ef">_14>&q>14=6243)
67 href};f">TEGRA_PIN_6" claCAM_I2C_SD6" BBlass="s6f9ing">&q6LK_32K_1CAM_I2C_SD6" BBl"RA_PIN_VI_VSYNC_PD6, 9//a>,1434c9ass="14="s6code=_GPI6" cl8ss="s14="s>14=PINTEGRA_PIN_VI_VSYNC_PD6&quo6"8class14ass>14="> 295
59 href="drivers/pinctrl/pinccspbb;DAP2_SCLK PA3pan cl1pbb;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1437c9ass="14">"6" class="s8ef">_14">&>14={
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CSPBBs5code=_GPI5" class="sref1PBBs"RA_PIN_VI_VSYNC_PD6, 9//a>,1438c9ass="14="s6code=_GPI6" cl8ss="s14="s>14=t;),
70 hrefstatic const unsignedrs/pin8trl/p1439c9ass="14c_sclCpc4_/a>sc#L386" id14c_s>14=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD614pa(4)
68 href="drivers/pinctrl/pie=PIcspbbe="SDMMC3T7_P7_l/piP1pbbe="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1441c9ass="14="s6code=_GPI6" cl8ss="s14="s>14p>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlPBBpan class="s6code=_GNC_PD1PBBp"RA_PIN_VI_VSYNC_PD6, 9//a>,1442c9ass="14="s6code=_GPI6" cl8ss="s14="s>14ps */
68 hrefstatic const unsignedrs/pin8trl/p1443c9ass="14c_sdaCpc5_/a>sc#L386" id14c_s>14pc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1444c9ass="14pan class="s6cring8>&q6"14pan>14p>_PIN(0)
68 href="drivers/pinctr="srclpbb"linGEN1#I2Ce_Dode=PIpbb"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1445c9ass="14="s6code=_GPI6" cl8ss="s14="s>14p(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLPBBass="s6c9ing">&q6s="SPDIF_PBBa"RA_PIN_VI_VSYNC_PD6, 9//a>,1446c9ass="14="s6c8">"6" cl8ss="s14="s>14p_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1447c9ass="142_/c6_/a>sc#L306" 8d="L3142_/>14p0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6" c8ass="14s=">14pN(4)
68 href="drivers/pinctrl/pie=PIcspbb_PINPWR2  Code=ode=PIpbb_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1449c9ass="14=_GPI6" class="sre8">_GP14=_G>14p69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSPBB class="s6code=_GPI66" claPBB "RA_PIN_VI_VSYNC_PD6, 9//a>,145 c9ass="14="s6code=_GPI6" cl8ss="s14="s>14="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1451c9ass="14n_pc7_/a>sc#L306" 8d="L314n_p>14=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD614=ef">_GPIO6242)
67 href="drivers/ode=PIpbbVI_HSYNC_PDlassPINCP1pbbVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1453c9ass="14=_GPI6" class="sre8">_GP14=_G>14=6243)
67 href};f">TEGRA_PIN_6" claPBB class="s6fode=_GPI6" clD1PBB "RA_PIN_VI_VSYNC_PD6, 9//a>,1454c9ass="14="s6code=_GPI6" cl8ss="s14="s>14=PIN14=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD614=>6246)
67 href="drivers/pinctrl/pinc>clas1cam_mclassccIND0_PE="+code=PINCT8cam_mclassccIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1457c9ass="14s6c8">"6" clas8="sre14s6c>14= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1CAM_M, 9//a>,1458c9ass="14="s6code=_GPI6" cl8ss="s14="s>14=t;),
70 hrefstatic const unsignedrs/pin8trl/p1459c9ass="14dat4_/d1_/a>sc#L308" id=14dat>14=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD614n 6246)
67 href="drivers/pinctrl/pinc>clas1sccIND1_PE"L271" class=epccIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1461c9ass="14s6code=_GPI6" clas8="sre14s6c>14n>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlmCClass="s6="+code=_6IN" claEPCCl"RA_PIN_VI_VSYNC_PD6, 9//a>,1462c9ass="14="s6code=_GPI6" cl8ss="s14="s>14ns */
68 hrefstatic const unsignedrs/pin8trl/p1463c9ass="14_/d2_/a>sc#L306" i8="L3014_/d>14nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1464c9ass="14"s6code=_GPI6" cla8s="sr14"s6>14n>_PIN(0)
68 href="drivers/pinctr="srclpccIND2_PE"L272" class=1pccIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1465c9ass="14GPI6" class="sref"8_GPIO14GPI>14n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLPCClass="s6f9ing">&q6LK_32K_1PCCl"RA_PIN_VI_VSYNC_PD6, 9//a>,1466c9ass="14="s6c8">"6" cl8ss="s14="s>14n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1467c9ass="14dat6_/d3_/a>sc#L308" id=14dat>14n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&qu8t6" c14n c>14nN(4)
68 href="drivers/pinctrl/pie=PIcssdmmc4_rst_n_pcc;DAP2_SCLK PA3pan cl1sdmmc4_rst_n_pcc;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1469c9ass="14s6code=_GPI6" clas8="sre14s6c>14n69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSSDMMC4_RST__1PCCs5code=_GPI5" class="sref1SDMMC4_RST__1PCCs"RA_PIN_VI_VSYNC_PD6, 9//a>,147 c9ass="14="s6code=_GPI6" cl8ss="s14="s>14="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1471c9ass="14dat7_/d4_/a>sc#L308" id=14dat>14=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD614=ef">_GPIO6242)
67 href="drivers/ode=PIsdmmc4_classcce="SDMMC3T7_P7_l/piP1sdmmc4_classcce="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1473c9ass="14s6code=_GPI6" clas8="sre14s6c>14=6243)
67 href};f">TEGRA_PIN_6" claSDMMC4_, 9//a>,1474c9ass="14="s6code=_GPI6" cl8ss="s14="s>14=PIN14=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD614ode>14=>6246)
67 href="drivers/pinctrl/pinc>clas1clk2_req_pcc"linGEN1#I2Ce_Dode=PIclk2_req_pcc"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1477c9ass="14" class="sref">_GP8O14" c>14= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1CLK2_REQaPCCass="s6c9ing">&q6s="SPDIF_CLK2_REQaPCCa"RA_PIN_VI_VSYNC_PD6, 9//a>,1478c9ass="14="s6">/* All 6on-G8IO pi14="s>14=t;),
70 hrefstatic const unsignedrs/pin8trl/p1479c9ass="14c_/d6_/a>sc#L306" 8d="L314c_/>14=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6TEG14s=">14s=6246)
67 href="drivers/pinctrl/pinc>clas1pex_l2_rst_n_pcc_PINPWR2  Code=ode=PIpex_l2_rst_n_pcc_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1481c9ass="14e=off6et" class="s8ef">o14e=o>14s>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlPEX_L2_RST__1PCC class="s6code=_GPI66" claPEX_L2_RST__1PCC "RA_PIN_VI_VSYNC_PD6, 9//a>,1482c9ass="14="s6ss="comme6t">/8 Non-14="s>14ss */
68 hrefstatic const unsignedrs/pin8trl/p1483c9ass="14c_/d7_/a>sc#L306" 8d="L314c_/>14sc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1484c9ass="14s="s67ode=_GPI6PIN8 clas14s=">14s>_PIN(0)
68 href="drivers/pinctr="srclpex_l2_clkreq_n_pccVI_HSYNC_PDlassPINCP1pex_l2_clkreq_n_pccVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1485c9ass="14=_GPI6PIN" class="8ref">14=_G>14s(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLPEX_L2_CLKREQa_1PCC class="s6fode=_GPI6" clD1PEX_L2_CLKREQa_1PCC "RA_PIN_VI_VSYNC_PD6, 9//a>,1486c9ass="14="s6"8ing">&q6PIN"8class14="s>14s_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1487c9ass="14pe0_/a>sc#L306" id8"L30l14pe0>14s0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&q6PIN" cl8ss="s14679>14sN(4)
68 href="drivers/pinctrl/pie=PIcspex_l0_prsnt_n_pddIND0_PE="+code=PINCT8pex_l0_prsnt_n_pddIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1489c9ass="14=6PIN" class="sref8>_PIN14=6P>14s69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSPEX_L0_PRSNT__1PDDlass="s6f" class=6PIN" cl8PEX_L0_PRSNT__1PDDl"RA_PIN_VI_VSYNC_PD6, 9//a>,149 c9ass="14="s6f="+code=6PIN"8class14="s>14="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1491c9ass="14/e1_/a>sc#L306" id8"L30l14/e1>14=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6_GPIO6242)
67 href="drivers/ode=PIpex_l0_rst_n_pddIND1_PE"L271" class=epex_l0_rst_n_pddIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1493c9ass="14e6PIN" class="sref8>_PIN14e6P>14=6243)
67 href};f">TEGRA_PIN_6" claPEX_L0_RST__1PDDlass="s6="+code=_6IN" claEPEX_L0_RST__1PDDl"RA_PIN_VI_VSYNC_PD6, 9//a>,1494c9ass="14="s6="+code=_6IN" 8lass=14="s>14=PIN14=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD614=>6246)
67 href="drivers/pinctrl/pinc>clas1pex_l0_clkreq_n_pddIND2_PE"L272" class=1pex_l0_clkreq_n_pddIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1497c9ass="14q6"sref">tegra30_p8ns146G_32K1SDMMC4_DAT1&q6LK_32K_1PlaEPEXCLKREQa_1PDDl"RA_PIN_VI_VSYNC_PD6, 9//a>,1498c9ass="14="s7g">"7ART38CTS_N14="s>14=t;),
70 hrefstatic const unsignedrs/pin8trl/p1499c9ass="14/e3_/a>sc#L306" id8"L30l14/e3>14=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD615n f">_GPIO6242)
67 href="drivers/ode=PIpex_wake_n_pdd;DAP2_SCLK PA3pan cl1pex_wake_n_pdd;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q15n1c9ass="15ne1_/a>sc#L306" id8"L30l15ne1>15n6231)
66 href};f">TEGRA_PIN_" cl" PlaEWAKEa_1PDDs5code=_GPI5" class="sref1PlaEWAKEa_1PDDs"RA_PIN_VI_VSYNC_PD6, 9//a>,15n2c9ass="15nf="+code=6PIN" cl8ss="s15nf=>15ns */
68 hrefstatic const unsignedrs/pin8trl/p15n3c9ass="15n6PIN" class="sref8>_PIN15n6P>15nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,15n4c9ass="15n"s6="+code=_6IN" 8lass=15n"s>15n>_PIN(0)
68 href="drivers/pinctr="srclpex_l1_prsnt_n_pdde="SDMMC3T7_P7_l/piP1pex_l1_prsnt_n_pdde="SDMref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q15n5c9ass="15ne2_/a>sc#L306" id8"L30l15ne2>15n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLPlaEP1_PRSNT__1PDDpan class="s6code=_GNC_PD1PlaEP1_PRSNT__1PDDp"RA_PIN_VI_VSYNC_PD6, 9//a>,15n6c9ass="15nfode=_GPI6s="line8 name15nfo>15n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p15n7c9ass="15n6"sref">tegra30_p8ns15n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"7ART38CTS_N15n"s>15nef">_GPIO6238)
66 href="drivers/ode=PIpex_l1_rst_n_pdd"linGEN1#I2Ce_Dode=PIpex_l1_rst_n_pdd"linGEref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q15n9c9ass="15ne3_/a>sc#L306" id8"L30l15ne3>15n6239)
67 href};f">TEGRA_PIN_6" claPlaEP1_RST__1PDDass="s6c9ing">&q6s="SPDIF_PlaEP1_RST__1PDDa"RA_PIN_VI_VSYNC_PD6, 9//a>,151 c9ass="15="s6g">"6DMMC9_DAT215="s>15="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1511c9ass="15dat2_/b5_/a>sc#L309" id=15dat>15=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&quo9;6DMM15n c>15=ef">_GPIO6242)
67 href="drivers/ode=PIpex_l1_clkreq_n_pdd_PINPWR2  Code=ode=PIpex_l1_clkreq_n_pdd_PINPWref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1513c9ass="15s6rng">&quo6DMMC3_9AT0 P15s6r>15=6243)
67 href};f">TEGRA_PIN_6" claPlaEP1_CLKREQa_1PDD class="s6code=_GPI66" claPEX_L1_CLKREQa_1PDD "RA_PIN_VI_VSYNC_PD6, 9//a>,1514c9ass="15="s6gg">"6t;LC9_PWR115="s>15=PINsc#L309" id=15dat>15=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&qu9t6;UA15n c>15="> 295
59 href="drivers/pinctrl/pinccspex_l2_prsnt_n_pddVI_HSYNC_PDlassPINCP1pex_l2_prsnt_n_pddVI_HSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1517c9ass="15] = {f">TEGRA_PIN_VI_VS815] =>15={
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CSPEX_L2_PRSNT__1PDD class="s6fode=_GPI6" clD1PEX_L2_PRSNT__1PDD "RA_PIN_VI_VSYNC_PD6, 9//a>,1518c9ass="15="s6">"G6N1_I8C_SDA15="s>15=t;),
70 hrefstatic const unsignedrs/pin8trl/p15=9c9ass="15dat0_/b7_/a>sc#L308" id=15dat>15=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&8u6t;L15n c>15n > 295
59 href="drivers/pinctrl/pinccsclk3_out_peeIND0_PE="+code=PINCT8clk3_out_peeIND0_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1521c9ass="15s6ring">&qu6t;GMI_8P_N P15s6r>15n6231)
66 href};f">TEGRA_PIN_" cl" CLK3_OUT1PEElass="s6f" class=6PIN" cl8CLK3_OUT1PEEl"RA_PIN_VI_VSYNC_PD6, 9//a>,1522c9ass="15="s6r">"6DMMC8_DAT415="s>15ns */
68 hrefstatic const unsignedrs/pin8trl/p1523c9ass="15ts_n_pc0_/a>sc#L308" id=15ts_>15nc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1524c9ass="15n class="s6rg">&qu8t6ot;15n c>15n>_PIN(0)
68 href="drivers/pinctr="srclclk3_req_peeIND1_PE"L271" class=eclk3_req_peeIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1525c9ass="15s6rg">"6DMMC3_8AT6 P15s6r>15n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLCLK3_REQaPEElass="s6="+code=_6IN" claECLK3_REQaPEEl"RA_PIN_VI_VSYNC_PD6, 9//a>,1526c9ass="15="s6"8">"6quot8VI_D115="s>15n_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1527c9ass="151_/c1_/a>sc#L306" 8d="L3151_/>15n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6t;V8_VSYN15s=">15nef">_GPIO6238)
66 href="drivers/ode=PIclk1_req_peeIND2_PE"L272" class=1clk1_req_peeIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1529c9ass="15">&qu6t;VI_HSYNC P87&quo15">&>15n6239)
67 href};f">TEGRA_PIN_6" claCLK1_REQaPEElass="s6f9ing">&q6LK_32K_1CLK1_REQaPEEl"RA_PIN_VI_VSYNC_PD6, 9//a>,153 c9ass="15="s6ring">&qu6" cl8ss="s15="s>15="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1531c9ass="15xdCpc2_/a>sc#L306"8id="L15xdC>15=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6"8class15ass>15=ef">_GPIO6242)
67 href="drivers/ode=PIhdmi_cec_pee;DAP2_SCLK PA3pan cl1hdmi_cec_pee;DAP2_ref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1533c9ass="15>"6" class="s8ef">_15>&q>15=6243)
67 href};f">TEGRA_PIN_6" claHDMI_CECaPEEs5code=_GPI5" class="sref1HDMI_CECaPEEs"RA_PIN_VI_VSYNC_PD6, 9//a>,1534c9ass="15="s6code=_GPI6" cl8ss="s15="s>15=PINTEGRA_PIN_VI_VSYNC_PD6&quo6"8class15ass>15="> 295
59 href="drivers/pinctrl/pinccsclas32k_inND2_PE"L272" class=1clks32k_inND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1537c9ass="15">"6" class="s8ef">_15">&>15={
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CS&q6LK_32K_1CLK<32K_IN"RA_PIN_VI_VSYNC_PD6, 9//a>,1538c9ass="15="s6code=_GPI6" cl8ss="s15="s>15=t;),
70 hrefstatic const unsignedrs/pin8trl/p1539c9ass="15c_sclCpc4_/a>sc#L386" id15c_s>15=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD615pa(4)
68 href="drivers/pinctrl/pie=PIcscore_pwr_req_p2_PE"L272" class=1core_pwr_req_p2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1541c9ass="15="s6code=_GPI6" cl8ss="s15="s>15p>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlCORE1PWR_REQass="s6f9ing">&q6LK_32K_1CORE1PWR_REQ"RA_PIN_VI_VSYNC_PD6, 9//a>,1542c9ass="15="s6code=_GPI6" cl8ss="s15="s>15ps */
68 hrefstatic const unsignedrs/pin8trl/p1543c9ass="15c_sdaCpc5_/a>sc#L386" id15c_s>15pc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8,1544c9ass="15pan class="s6cring8>&q6"15pan>15p>_PIN(0)
68 href="drivers/pinctr="srclcpu_pwr_req_p2_PE"L272" class=1cpu_pwr_req_p2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1545c9ass="15="s6code=_GPI6" cl8ss="s15="s>15p(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLCPU1PWR_REQass="s6f9ing">&q6LK_32K_1CPU1PWR_REQ"RA_PIN_VI_VSYNC_PD6, 9//a>,1546c9ass="15="s6c8">"6" cl8ss="s15="s>15p_PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1547c9ass="152_/c6_/a>sc#L306" 8d="L3152_/>15p0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6" c8ass="15s=">15pN(4)
68 href="drivers/pinctrl/pie=PIcsowr_p2_PE"L272" class=1owr_p2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1549c9ass="15=_GPI6" class="sre8">_GP15=_G>15p69 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSOWRass="s6f9ing">&q6LK_32K_1OWR"RA_PIN_VI_VSYNC_PD6, 9//a>,155 c9ass="15="s6code=_GPI6" cl8ss="s15="s>15="PIN(3)
68 hrefstatic const unsignedrs/pin8trl/p1551c9ass="15n_pc7_/a>sc#L306" 8d="L315n_p>15=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD615=ef">_GPIO6242)
67 href="drivers/ode=PIpwr_int_n_pHSYNC_PDlassPINCP1pwr_int_n_pHSYref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1553c9ass="15=_GPI6" class="sre8">_GP15=_G>15=6243)
67 href};f">TEGRA_PIN_6" claPWR_INT__class="s6fode=_GPI6" clD1PWR_INT__"RA_PIN_VI_VSYNC_PD6, 9//a>,1554c9ass="15="s6code=_GPI6" cl8ss="s15="s>15=PIN15=2_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD615=>6246)
67 href="drivers/pinctrl/pinc>clas1{f">T_aoIND1_PE"L271" class=e{f">T_aoIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1557c9ass="15s6c8">"6" clas8="sre15s6c>15= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1KB_ROW0_PRlass="s6f" class=6PIN" cl8KB_ROW0_PRl"RA_PIN_VI_VSYNC_PD6, 9//a>,1558c9ass="15="s6code=_GPI6" cl8ss="s15="s>15=t;TEGRA_PIN_VI_VSYNC_PD6G_32K1KB_ROW1_PRlass="s6="+code=_6IN" claEKB_ROW1_PRl"RA_PIN_VI_VSYNC_PD6, 9//a>,1559c9ass="15dat4_/d1_/a>sc#L308" id=15dat>15569 href};f">TEGRA_PIN_VI_VSYNC_PN" cCSKB_ROW2_PRlass="s6f9ing">&q6LK_32K_1KB_ROW2_PRl"RA_PIN_VI_VSYNC_PD6, 9//a>,156 c9ass="15n class="s6code=_G8I6" c15n c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PN" cCSKB_ROW3_PRs5code=_GPI5" class="sref1KB_ROW3_PRs"RA_PIN_VI_VSYNC_PD6, 9//a>,1561c9ass="15s6code=_GPI6" clas8="sre15s6c>15n>))
68 href};f">TEGRA_PIN_VI_VSYG_32KlKB_ROW4_PRpan class="s6code=_GNC_PD1KB_ROW4_PRp"RA_PIN_VI_VSYNC_PD6, 9//a>,1562c9ass="15="s6code=_GPI6" cl8ss="s15="s>15ns */<8 href};f">TEGRA_PIN_VI_VSYG_32KlKB_ROW5_PRass="s6c9ing">&q6s="SPDIF_KB_ROW5_PRa"RA_PIN_VI_VSYNC_PD6, 9//a>,1563c9ass="15_/d2_/a>sc#L306" i8="L3015_/d>1566243)
67 href};f">TEGRA_PIN_6" claKB_ROW6_PR class="s6code=_GPI66" claKB_ROW6_PR "RA_PIN_VI_VSYNC_PD6, 9//a>,1564c9ass="15"s6code=_GPI6" cla8s="sr15"s6>15n>_PIN243)
67 href};f">TEGRA_PIN_6" claKB_ROW7_PR class="s6fode=_GPI6" clD1KB_ROW7_PR "RA_PIN_VI_VSYNC_PD6, 9//a>,1565c9ass="15GPI6" class="sref"8_GPIO15GPI>15n(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLPWR_I2C_S, 9//a>,1566c9ass="15="s6c8">"6" cl8ss="s15="s>15n_PIN<8 href};f">TEGRA_PIN_VI_VSY" clCLPWR_I2C_SD6" Z class="s6fode=_GPI6" clD1PWR_I2C_SD6" Z "RA_PIN_VI_VSYNC_PD6, 9//a>,1567c9ass="15dat6_/d3_/a>sc#L308" id=15dat>156{
59 href};f">TEGRA_PIN_VI_VSYNC_PD6CSSYS_RESET__class="s6fode=_GPI6" clD1SYS_RESET__"RA_PIN_VI_VSYNC_PD6, 9//a>,1568c9ass="15n class="s6c9">&qu8t6" c15n c>156t;),
70 hrefstatic const unsignedrs/pin8trl/p1569c9ass="15s6code=_GPI6" clas8="sre15s6c>1563_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6157a(4)
68 href="drivers/pinctrl/pie=PIcs{f">T_aoIND2_PE"L272" class=1{f">T_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T44&q1571c9ass="15dat7_/d4_/a>sc#L308" id=15dat>1576231)
66 href};f">TEGRA_PIN_" cl" CLK<32K_OUT1PAlass="s6f" class=6PIN" cl8CLK<32K_OUT1PAl"RA_PIN_VI_VSYNC_PD6, 9//a>,1572c9ass="15n class="s6code=_G8I6" c15n c>157s */<8 href};f">TEGRA_PIN_VI_VSYG_32KlKB_COL0_PQlass="s6f" class=6PIN" cl8KB_COL0_PQl"RA_PIN_VI_VSYNC_PD6, 9//a>,1573c9ass="15s6code=_GPI6" clas8="sre15s6c>15=6243)
67 href};f">TEGRA_PIN_6" claKB_COL1_PQlass="s6="+code=_6IN" claEKB_COL1_PQl"RA_PIN_VI_VSYNC_PD6, 9//a>,1574c9ass="15="s6code=_GPI6" cl8ss="s15="s>157>_PIN243)
67 href};f">TEGRA_PIN_6" claKB_COL2_PQlass="s6f9ing">&q6LK_32K_1KB_COL2_PQl"RA_PIN_VI_VSYNC_PD6, 9//a>,1575c9ass="15d5_/a>sc#L306" id=8L30vi15d5_>157(1)
68 href};f">TEGRA_PIN_VI_VSY" clCLKB_COL3_PQs5code=_GPI5" class="sref1KB_COL3_PQs"RA_PIN_VI_VSYNC_PD6, 9//a>,1576c9ass="15ode=_GPI6" class="8ref">15ode>157_PIN<8 href};f">TEGRA_PIN_VI_VSY" clCLKB_COL4_PQpan class="s6code=_GNC_PD1KB_COL4_PQps="s6code=_GNC_PD1KB_COL4_PQps="s6code=_GNC_PD1KB_COL779)
67 href};f">TEGRA_PIN>))
68 hr 9 c>14= href};f">TEGRA_PIN_VI_VSYNC_PD6GC_PD1KB_RQW5_PRass="s6c9ing">&q6s="SPDID1KB_RQW4_PQps="s6code=_GNC_PD1KB_COL4_PQps="s6code=_GNC_PD1K>,1568c9ass="14="s6">/* All 6on-G8I5 pi1457s>15=t;TEGRA_PIN_VI_VSYNC_PD6G_32D1KB_RQW6_PR class="s6code=_GPI66" cD1KB_RQW4_PQps="s6code=_GNC_PD1KB_COL4_PQps="s6code=_GNC_PD1K/p1569c9ass="14c_/d6_/a>sc#L306" 8d5"L31457t>15569 href};f">TEGRA_PIN_VI_VSYNC_PN" cD1KB_RQW7_PR class="s6fode=_GPI6" clD1KB_RQW4_PQps="s6code=_GNC_PD1KB_COL4_PQps="s6code=_GNC_PD115n 6246ef};f">TEGRA_PIN_VI_VSYNC_PN" cCSK8_PSW0_PRlass="s6f" class=6PIN" cl8K8_PSW4_PQps="s6code=_GNC_PD1KB_COL4_PQps="s6code=_GNC_PD1<&q1571c9ass="14e=off6et" class="s8e5">o145=o>14s>))
68 href};f">TEGRA_PIN_VI_VSYG" cl8K9_PSW1_PRlass="s6="+code=_6IN" claEK9_PSW4_PQps="s6code=_GNC_PD1KB_COL4_PQps="s6code=_GNC_PD1<>,1572c9ass="14="s6ss="comme6t">/8 5on-1458s>15ns */<8 href};f">TEGRA_PIN_VI_VSYG_32KlK1B_CSW2_PRlass="s6f9ing">&q6LK_32K_1K1B_CSW4_PQps="s6code=_GNC_PD1KB_COL4_PQps="s6code=_GNC_PD1<>,1573c9ass="14c_/d7_/a>sc#L306" 8d5"L31458d>1566243)
67 href};f">TEGRA_PIN_6" claK1B_CSW3_PRs5code=_GPI5" class="sref1K1B_CSW4_PQps="s6code=_GNC_PD1KB_COL4_PQps="s6code=_GNC_PD1<>,1574c9ass="14s="s67ode=_GPI6PIN8 5las14586>15n>_PIN243)
67 href};f">TEGRA_PIN_6" claK1B_CSW4_PRpan class="s6code=_GNC_PD1K1B_CSW4_PQps="s6code=_GNC_PD1KB_COL4_PQps="s6code=_GNC_PD1<>,1575c9ass="14=_GPI6PIN" class="8r5f">145_G>14s(1)
68 href};f">TEGRA_PIN_VI_VSY"C_PD1K1B_CSW5_PRass="s6c9ing">&q6s="SPDIF_K1B_CSW4_PQps="s6code=_GNC_PD1KB_COL4_PQps="s6code=_GNC_PD1<>,1576c9ass="14="s6"8ing">&q6PIN"8c5ass1458e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY" clF_K1B_CSW6_PR class="s6code=_GPI66" claK1B_CSW4_PQps="s6code=_GNC_PD1KB_COL4_PQps="s6code=_GNC_PD115= href};f">TEGRA_PIN_VI_VSYNC_PD6G_32K1K1B_RSW7_PR class="s6fode=_GPI6" clD1K1B_RSW4_PQps="s6code=_GNC_PD1KB_COL4_PQps="s6code=_GNC_PD1<>,1568c9ass="14679ing">&q6PIN" cl8s5="s1458s>15=t;TEGRA_PIN_VI_VSYNC_PD6G_32KlSYS_&q6s="SPDIF_SYS_, 9/54&q1489c9a5s="14=6PIN" class="sref8>5PIN1456P>14s69 href};f">TEGRA_PIN_VI_VSYNC_PNPD6CS&q6LK_32K_1CLK<32K_IN"RA_PIN_VI_VSYNC_PD6, 9//a>,149 c9a5s="14="s6f="+code=6PIN"8c5ass1459c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PN_32KlCORE1PWR_REQass="s6f9ing">&q6LK_32K_1CORE1PWR_REQ"RA_PIN_VI_VSYNC_PD6, 9//l/p1491c9a5s="14/e1_/a>sc#L306" id8"530l1459t>1576231)
66 href};f">TEGRA_PIN_" clCLCPU1PWR_REQass="s6f9ing">&q6LK_32K_1CPU1PWR_REQ"RA_PIN_VI_VSYNC_PD6, 9//TEGRA_PIN_VI_VSYG" claPWR_INT__class="s6fode=_GPI6" clD1PWR_INT__"RA_PIN_VI_VSYNC_PD6, 9//4&q1493c9a5s="14e6PIN" class="sref8>5PIN1456P>14=t;),
70 hrefstatic const unsignedrs/pin8tra>,1494c9a5s="14="s6="+code=_6IN" 8l5ss=145"s>14=),
70 hrefstatic const unsignedrs/pin8tra>,1575c9ass="14/e2_/a>sc#L306" id8"530l145e2>14=a(4)
68 href="drivers/pinctrl/pie=PIcs{ft>T_aoIND1_PE"L271" class=e{ft>T_aoIND1_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T4157_PIN<8 href};f">TEGRA_PIN_VI_VSY"GMI_AD8_PHW0_PRlass="s6f" class=6PINGMI_AD8_PHWINT__"RA_PIN_VI_VSYNC_PD6, 9//4B_COL779)
s="14q6"sref">tegra30_p8n5146G_32K1SDMMC4_DAT1, 9//4>,1568c9ass="14="s7g">"7ART38C5S_N1459s>15=t;TEGRA_PIN_VI_VSYNC_PD6GGMI_AD1B_CHW2_PRlass="s6f9ing">&q6LK_GMI_AD1B_CHWINT__"RA_PIN_VI_VSYNC_PD6, 9//4&q1489c9a5s="14/e3_/a>sc#L306" id8"530l1459P>14s69 href};f">TEGRA_PIN_VI_VSYNC_PNGMI_AD1B_CHW3_PRs5code=_GPI5" class="GMI_AD1B_CHWINT__"RA_PIN_VI_VSYNC_PD6, 9/615n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNGMI_AD1B_CHW4_PRpan class="s6code=_GNGMI_AD1B_CHWINT__"RA_PIN_VI_VSYNC_PD6, 9/6<1p15n c9a6s="14/e1_/a>sc#L306" id8"630l156e1>15n6231)
66 href};f">TEGRA_PIN_"GMI_AD1B_CHEQaPZass="s6c9ing">&q6s="SGMI_AD1B_CHEINT__"RA_PIN_VI_VSYNC_PD6, 9/6<2p15n c9a6s="146f="+code=6PIN" cl8s6="s1560s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGGMI_AD1B_CHW6_PR class="s6code=_GPI66GMI_AD1B_CHWINT__"RA_PIN_VI_VSYNC_PD6, 9/6<3p15n c9a6s="14e6PIN" class="sref8>6PIN1560d>1566243)
67 href};f">TEGRA_PIN_6GMI_AD1B_RHW7_PR class="s6fode=_GPI6"GMI_AD1B_RHWINT__"RA_PIN_VI_VSYNC_PD6, 9/6<4p15n c9a6s="14="s6="+code=_6IN" 8l6ss=15606>15n>_PIN243)
67 href};f">TEGRA_PIN_6GMI_IORDYPINEQaPZass="s6c9ing">&q6s="SGMI_IORDYPINEINT__"RA_PIN_VI_VSYNC_PD6, 9/6<5p15n c9a6s="14/e2_/a>sc#L306" id8"630l156e2>15n(1)
68 href};f">TEGRA_PIN_VI_VSY"GMI_CS7PRSNIW6_PR class="s6code=_GPI66GMI_CS7PRSNIWINT__"RA_PIN_VI_VSYNC_PD6, 9/6<6p15n c9a6s="146fode=_GPI6s="line8 6ame156fo>15n_PIN(3)
68 hrefstatic const unsignedrs/pin8t6l/p15n7c9a6s="15n6"sref">tegra30_p8n615n0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"7ART38C6S_N156"s>15nef">_GPIO6238)
66 href="drivers/oass=e{ft>T_aoIND2_PE"L272" class=1{ft>T_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T64&q15n9c9a6s="15ne3_/a>sc#L306" id8"630l156e3>15n6239)
67 href};f">TEGRA_PIN_6GMI_ADB_CGW0_PRlass="s6f" class=6PINGMI_ADB_CGWINT__"RA_PIN_VI_VSYNC_PD6, 9/6a>,151 c9a6s="15="s6g">"6DMMC9_6AT21561c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNGMI_AD1_CGW1_PRlass="s6="+code=_6IN"GMI_AD1_CGWINT__"RA_PIN_VI_VSYNC_PD6, 9/6a1p15n c9a6s="15dat2_/b5_/a>sc#L309"6id=15611>15n6231)
66 href};f">TEGRA_PIN_"GMI_ADB_CGW2_PRlass="s6f9ing">&q6LK_GMI_ADB_CGWINT__"RA_PIN_VI_VSYNC_PD6, 9/6a2p15n c9a6s="15n class="s6g">&quo9;6DMM1561s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGGMI_ADB_CGW3_PRs5code=_GPI5" class="GMI_ADB_CGWINT__"RA_PIN_VI_VSYNC_PD6, 9/6a3p15n c9a6s="15s6rng">&quo6DMMC3_9A60 P1566r>15=6243)
67 href};f">TEGRA_PIN_6GMI_ADB_CGW4_PRpan class="s6code=_GNGMI_ADB_CGWINT__"RA_PIN_VI_VSYNC_PD6, 9/6a4p15n c9a6s="15="s6gg">"6t;LC9_6WR115616>15n>_PIN243)
67 href};f">TEGRA_PIN_6GMI_ADB_RGEQaPZass="s6c9ing">&q6s="SGMI_ADB_RGEINT__"RA_PIN_VI_VSYNC_PD6, 9/6a5p15n c9a6s="15dat1_/b6_/a>sc#L309"6id=15612>15n(1)
68 href};f">TEGRA_PIN_VI_VSY"GMI_AD6_RGW6_PR class="s6code=_GPI66GMI_AD6_RGWINT__"RA_PIN_VI_VSYNC_PD6, 9/6a6p15n c9a6s="15n class="s6g7">&qu9t6;UA1561e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"GMI_AD7_RGW7_PR class="s6fode=_GPI6"GMI_AD7_RGWINT__"RA_PIN_VI_VSYNC_PD6, 9/6a/p15n7c9a6s="15] = {f">TEGRA_PIN_VI6VS8156 =>15={
59 href};f">TEGRA_PIN_VI_VSYNC_GMI_WRPRSNIW0_PRlass="s6f" class=6PINGMI_WRPRSNIWINT__"RA_PIN_VI_VSYNC_PD6, 9/6asp15n8c9a6s="15="s6">"G6N1_I8C6SDA1561s>15=t;TEGRA_PIN_VI_VSYNC_PD6GGMI_OaEWAKIW1_PRlass="s6="+code=_6IN"GMI_OaEWAKIWINT__"RA_PIN_VI_VSYNC_PD6, 9/6a&q15n9c9a6s="15dat0_/b7_/a>sc#L308"6id=15613>15n6239)
67 href};f">TEGRA_PIN_6GMI_DQSPINW2_PRlass="s6f9ing">&q6LK_GMI_DQSPINWINT__"RA_PIN_VI_VSYNC_PD6, 9/6&8u6t;L1562c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNGMI_CS6EWAKIW3_PRs5code=_GPI5" class="GMI_CS6EWAKIWINT__"RA_PIN_VI_VSYNC_PD6, 9/6<1p15n c9a6s="15s6ring">&qu6t;GMI_8P6N P1566r>15n6231)
66 href};f">TEGRA_PIN_"GMI_aEP1_RSIW4_PRpan class="s6code=_GNGMI_aEP1_RSIWINT__"RA_PIN_VI_VSYNC_PD6, 9/6<2p15n c9a6s="15="s6r">"6DMMC8_6AT41562s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGGMI_WAIT_VSW7_PR class="s6fode=_GPI6"GMI_WAIT_VSWINT__"RA_PIN_VI_VSYNC_PD6, 9/6<3p15n c9a6s="15ts_n_pc0_/a>sc#L308"6id=1562r>15=6243)
67 href};f">TEGRA_PIN_6GMI_ADV1_RSKW0_PRlass="s6f" class=6PINGMI_ADV1_RSKWINT__"RA_PIN_VI_VSYNC_PD6, 9/6<4p15n c9a6s="15n class="s6rg">&qu8t6ot;15626>15n>_PIN243)
67 href};f">TEGRA_PIN_6GMI_MMC4_KW1_PRlass="s6="+code=_6IN"GMI_MMC4_KWINT__"RA_PIN_VI_VSYNC_PD6, 9/6<5p15n c9a6s="15s6rg">"6DMMC3_8A66 P1566r>15n(1)
68 href};f">TEGRA_PIN_VI_VSY"GMI_CS41_RSKW2_PRlass="s6f9ing">&q6LK_GMI_CS41_RSKWINT__"RA_PIN_VI_VSYNC_PD6, 9/6<6p15n c9a6s="15="s6"8">"6quot8V6_D11562e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"GMI_CS21_RSKW3_PRs5code=_GPI5" class="GMI_CS21_RSKWINT__"RA_PIN_VI_VSYNC_PD6, 9/6sc#L306" 8d6"L31562=>15={
59 href};f">TEGRA_PIN_VI_VSYNC_GMI_CS31_RSKW4_PRpan class="s6code=_GNGMI_CS31_RSKWINT__"RA_PIN_VI_VSYNC_PD6, 9/6"6t;V8_6SYN1562c>156t;),
70 hrefstatic const unsignedrs/pin8t64&q1529c9a6s="15">&qu6t;VI_HSYNC P876quo1562c>1563_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6,153 c9a6s="15="s6ring">&qu6" cl8s6="s1563s>157a(4)
68 href="drivers/pinctrl/pie=PIcs{ftc_pee;DAP2_SCLK PA3pa=PIcs{ftc_pee;ND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T6l/p1531c9a6s="15xdCpc2_/a>sc#L306"8i6="L1563r>15n6231)
66 href};f">TEGRA_PIN_"GMI_WPLKREQW7_PR class="s6fode=_GPI6"GMI_WPLKREQWINT__"RA_PIN_VI_VSYNC_PD6, 9/6"6"8c6ass1563s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGGMI_CS0LKREJW0_PRlass="s6f" class=6PINGMI_CS0LKREJWINT__"RA_PIN_VI_VSYNC_PD6, 9/6<3p15n c9a6s="15>"6" class="s8e6">_1563P>14=t;),
70 hrefstatic const unsignedrs/pin8t6a>,1534c9a6s="15="s6code=_GPI6" cl8s6="s1563s>14=),
70 hrefstatic const unsignedrs/pin8t6l/p1535c9a6s="15xdCpc3_/a>sc#L306"8i6="L15632>14=a(4)
68 href="drivers/pinctrl/pie=PIcs{ftn_pdde="SDMMC3T7_P7_l=PIcs{ftn_pddeND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T6l6p15n c9a6s="15ass="s6rng">&quo6"8c6ass1563e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"GMI_A17_RlCLPBBlass="s6f" class=6PINGMI_A17_RlCINT__"RA_PIN_VI_VSYNC_PD6, 9/6"6" class="s8e6">_156>&>15={
59 href};f">TEGRA_PIN_VI_VSYNC_GMI_A18_RlW1_PRlass="s6="+code=_6IN"GMI_A18_RlWINT__"RA_PIN_VI_VSYNC_PD6, 9/6TEGRA_PIN_VI_VSYNC_PD6GGMI_CS1LKREJW2_PRlass="s6f9ing">&q6LK_GMI_CS1LKREJWINT__"RA_PIN_VI_VSYNC_PD6, 9/6<&q1529c9a6s="15c_sclCpc4_/a>sc#L3866 id15633>15n6239)
67 href};f">TEGRA_PIN_6GMI_A16_RJW7_PR class="s6fode=_GPI6"GMI_A16_RJWINT__"RA_PIN_VI_VSYNC_PD6, 9/615n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNGMI_A19RSKW7_PR class="s6fode=_GPI6"GMI_A19RSKWINT__"RA_PIN_VI_VSYNC_PD6, 9/615pt;),
70 hrefstatic const unsignedrs/pin8t6a>,1542c9a6s="15="s6code=_GPI6" cl8s6="s156"s>15p),
70 hrefstatic const unsignedrs/pin8t6a3p15n c9a6s="15c_sdaCpc5_/a>sc#L3866 id156_s>15pa(4)
68 href="drivers/pinctrl/pie=PIcs{ftn_pdd"linGEN1#I2Ce_Do=PIcs{ftn_pdd"ND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T6a>,1544c9a6s="15pan class="s6cring8>6q6"15646>15n>_PIN243)
67 href};f">TEGRA_PIN_6GEN2laPWR_I2C_TEQaPZass="s6c9ing">&q6s="SGEN2laPWR_I2C_TEINT__"RA_PIN_VI_VSYNC_PD6, 9/615p(1)
68 href};f">TEGRA_PIN_VI_VSY"GEN2laPWR_I2C_TW6_PR class="s6code=_GPI66GEN2laPWR_I2C_TWINT__"RA_PIN_VI_VSYNC_PD6, 9/6<6p15n c9a6s="15="s6c8">"6" cl8s6="s156"s>15p_PIN(3)
68 hrefstatic const unsignedrs/pin8t6l/p1547c9a6s="152_/c6_/a>sc#L306" 8d6"L3156_/>15p0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6" c8a6s="156=">15pN(4)
68 href="drivers/pinctrl/pie=PIcs{cdev>T_aoIND1_PE"L271" class=e{cdev>T_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T6a&q1529c9a6s="15=_GPI6" class="sre8"6_GP156_G>15p69 href};f">TEGRA_PIN_VI_VSYNC_PN32K_1<32K_WW4_PRpan class="s6code=_GN32K_1<32K_WWINT__"RA_PIN_VI_VSYNC_PD6, 9/6a>,155 c9a6s="15="s6code=_GPI6" cl8s6="s1565c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PN_ claCLK1_REQaPEElass="s6f9ing">&q6LK_32K_1CLK1_REQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/6l/p1551c9a6s="15n_pc7_/a>sc#L306" 8d6"L31565s>15pt;),
70 hrefstatic const unsignedrs/pin8t615pa(4)
68 href="drivers/pinctrl/pie=PIcs{cdev>T_aoIND2_PE"L272" class=1{cdev>T_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T6a>,1554c9a6s="15="s6code=_GPI6" cl8s6="s15656>15n>_PIN243)
67 href};f">TEGRA_PIN_6PDIF_<32K_WEQaPZass="s6c9ing">&q6s="SPDIF_<32K_WEaPEEl"RA_PIN_VI_VSYNC_PD6, 9/6l/p1535c9a6s="15dat5_/d0_/a>sc#L308"6id=1565r>15n(1)
68 href};f">TEGRA_PIN_VI_VSY" clK1CLK2_REQaPCCass="s6c9ing">&q6s="SPDIF_CLK2_REQaPCCa"RA_PIN_VI_VSYNC_PD6, 9/615p_PIN(3)
68 hrefstatic const unsignedrs/pin8t64&q1557c9a6s="15s6c8">"6" clas8=6sre1565/>15p0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6,1558c9a6s="15="s6code=_GPI6" cl8s6="s1565">15pN(4)
68 href="drivers/pinctrl/pie=PIcs{cdmi_aoIND2_PE"L272" class=1{cdmi_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T6a&q1529c9a6s="15dat4_/d1_/a>sc#L308"6id=156at>15569 href};f">TEGRA_PIN_VI_VSYNC_PN" claHDMI_CECaPEEs5code=_GPI5" class="sref1HDMI_CECaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a>,156 c9a6s="15n class="s6code=_G8I6" c1566s>15="PIN(3)
68 hrefstatic const unsignedrs/pin8t6a>,1561c9a6s="15s6code=_GPI6" clas8=6sre1566p>15=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6,1562c9a6s="15="s6code=_GPI6" cl8s6="s1566">15=ef">_GPIO6242)
67 href="drivers/oass=1{crti_aoIND2_PE"L272" class=1{crti_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T6a>,1563c9a6s="15_/d2_/a>sc#L306" i8=6L30156/d>1566243)
67 href};f">TEGRA_PIN_6CRT_HSYNMI_VW6_PR class="s6code=_GPI66CRT_HSYNMI_VWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a>,1554c9a6s="15"s6code=_GPI6" cla8s6"sr156s6>15n>_PIN243)
67 href};f">TEGRA_PIN_6CRT_VSYNMI_VW7_PR class="s6fode=_GPI6"CRT_VSYNMI_VWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a/p1535c9a6s="15GPI6" class="sref"8_6PIO156PI>15n"PIN(3)
68 hrefstatic const unsignedrs/pin8t6asp1556c9a6s="15="s6c8">"6" cl8s6="s156"s>15nIN(3)
68 hrefstatic const unsignedrs/pin8t6a&q1557c9a6s="15dat6_/d3_/a>sc#L308"6id=156at>156ef">_GPIO6242)
67 href="drivers/oass=1{csusi_aoIND2_PE"L272" class=1{csusi_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T6a>,1558c9a6s="15n class="s6c9">&qu8t6" c1566s>15=t;TEGRA_PIN_VI_VSYNC_PD6GVI_MMMC4_TW1_PRlass="s6="+code=_6IN"VI_MMMC4_TWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a&q1529c9a6s="15s6code=_GPI6" clas8=6sre1566c>156"PIN(3)
68 hrefstatic const unsignedrs/pin8t6157IN(3)
68 hrefstatic const unsignedrs/pin8t6<>,1561c9a6s="15dat7_/d4_/a>sc#L308"6id=156at>157ef">_GPIO6242)
67 href="drivers/oass=1{dap>T_aoIND1_PE"L271" class=e{dap>T_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T6a>,1572c9a6s="15n class="s6code=_G8I6" c156 c>157s */<8 href};f">TEGRA_PIN_VI_VSYGSPDIF_<32K_KEQaPZass="s6c9ing">&q6s="SPPDIF_<32K_KEaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a>,1573c9a6s="15s6code=_GPI6" clas8=6sre1566c>14=6243)
67 href};f">TEGRA_PIN_6"PDIF_I6" KW6_PR class="s6code=_GPI66"PDIF_I6" KWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a>,1554c9a6s="15="s6code=_GPI6" cl8s6="s156"s>157>_PIN243)
67 href};f">TEGRA_PIN_6DAP1_FS_PNCLPBBlass="s6f" class=6PINDAP1_FS_PNCaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a/p1535c9a6s="15d5_/a>sc#L306" id=8L60vi1565_>157(1)
68 href};f">TEGRA_PIN_VI_VSY"DAP1_DI6" NW1_PRlass="s6="+code=_6IN"DAP1_DI6" NWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6asp1556c9a6s="15ode=_GPI6" class="8r6f">156de>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"DAP1_D<32K_NQaPEElass="s6f9ing">&q6LK_DAP1_D<32K_NQaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a&q1557c9a667 href};f">TEGRA_PIN>))
68 hr 6 c>14= href};f">TEGRA_PIN_VI_VSYNC_PD6GDAP1_SMMC4_NCaPEEs5code=_GPI5" class="DAP1_SMMC4_NCaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a>,1558c9a6s="14="s6">/* All 6on-G8I6 pi146"s>14=t;),
70 hrefstatic const unsignedrs/pin8t6K/p1569c9a6s="14c_/d6_/a>sc#L306" 8d6"L3146_/>14=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD614s=6246)
67 href="drivers/pinctrl/pinc>ass=e{dap>T_aoIND2_PE"L272" class=1{dap>T_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T6<&q1571c9a6s="14e=off6et" class="s8e6">o146=o>14s>))
68 href};f">TEGRA_PIN_VI_VSYGDAP2_FS_PAQaPEElass="s6f9ing">&q6LK_DAP2_FS_PAQaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6<>,1572c9a6s="14="s6ss="comme6t">/8 6on-1468s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGDAP2_SMMC4_ACaPEEs5code=_GPI5" class="DAP2_SMMC4_ACaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6<>,1573c9a6s="14c_/d7_/a>sc#L306" 8d6"L31468d>1566243)
67 href};f">TEGRA_PIN_6DAP2_DI6" AW4_PRpan class="s6code=_GNDAP2_DI6" AWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6<>,1554c9a6s="14s="s67ode=_GPI6PIN8 6las14686>15n>_PIN243)
67 href};f">TEGRA_PIN_6DAP2_D<32K_OEQaPZass="s6c9ing">&q6s="SDAP2_D<32K_OEaPEEs"RA_PIN_VI_VSYNC_PD6, 9/61468I>15n"PIN(3)
68 hrefstatic const unsignedrs/pin8t6<>,1576c9a6s="14="s6"8ing">&q6PIN"8c6ass1468s>15nIN(3)
68 hrefstatic const unsignedrs/pin8t6sc#L306" id8"630l1468t>156ef">_GPIO6242)
67 href="drivers/oass=1{dapc_pee;DAP2_SCLK PA3pa=PIcs{dapc_pee;ND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T6<>,1558c9a6s="14679ing">&q6PIN" cl8s6="s1468s>15=t;TEGRA_PIN_VI_VSYNC_PD6GDAP3_FS_PPCLPBBlass="s6f" class=6PINDAP3_FS_PPCaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6TEGRA_PIN_VI_VSYNC_PNDAP3_DI6" PW1_PRlass="s6="+code=_6IN"DAP3_DI6" PWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a>,149 c9a6s="14="s6f="+code=6PIN"8c6ass1469c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNDAP3_D<32K_PQaPEElass="s6f9ing">&q6LK_DAP3_D<32K_PQaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a&q1571c9a6s="14/e1_/a>sc#L306" id8"630l1469t>1576231)
66 href};f">TEGRA_PIN_"DAP3_SMMC4_PCaPEEs5code=_GPI5" class="DAP3_SMMC4_PCaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a>,1572c9a6s="146f="+code=6PIN" cl8s6="s1469s>15ps */
68 hrefstatic const unsignedrs/pin8t64&q1493c9a6s="14e6PIN" class="sref8>6PIN1469s>15pc_/d7_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD8<6a>,1494c9a6s="14="s6="+code=_6IN" 8l6ss=1469n>15p>_PIN(0)
68 href="drivers/pinctr==PIcs{dapn_pdde="SDMMC3T7_P7_l=PIcs{dapn_pddeND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T6a>,1575c9a6s="14/e2_/a>sc#L306" id8"630l1469_>157(1)
68 href};f">TEGRA_PIN_VI_VSY"DAP4_FS_PPW4_PRpan class="s6code=_GNDAP4_FS_PPWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a>,1576c9a6s="146fode=_GPI6s="line8 6ame1469e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"DAP4_DI6" PEQaPZass="s6c9ing">&q6s="SDAP4_DI6" PEaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6aB_COL779)6s="14q6"sref">tegra30_p8n6146G_32K1SDMMC4_DAT1, 9/6a>,1558c9a6s="14="s7g">"7ART38C6S_N1469s>15=t;TEGRA_PIN_VI_VSYNC_PD6GDAP4_SMMC4_PW7_PR class="s6fode=_GPI6"DAP4_SMMC4_PWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/6a/p1569c9a6s="14/e3_/a>sc#L306" id8"630l1469c>156"PIN(3)
68 hrefstatic const unsignedrs/pin8t7157IN(3)
68 hrefstatic const unsignedrs/pin8t7<1p15n c9a7s="14/e1_/a>sc#L306" id8"730l1570t>157ef">_GPIO6242)
67 href="drivers/oass=1{dbg_pdde="SDMMC3T7_P7_l=PIcs{dbg_pddeND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T7<2p15n c9a7s="146f="+code=6PIN" cl8s7="s1570s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGGEN1laPWR_I2C_CW4_PRpan class="s6code=_GNGEN1laPWR_I2C_CWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7<3p15n c9a7s="14e6PIN" class="sref8>7PIN1570d>1566243)
67 href};f">TEGRA_PIN_6GEN1laPWR_I2C_EQaPCCass="s6c9ing">&q6s="SGEN1laPWR_I2C_EQaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7<4p15n c9a7s="14="s6="+code=_6IN" 8l7ss=15706>15n>_PIN243)
67 href};f">TEGRA_PIN_6PUCLPBBlass="s6f" class=6PINPUCaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7<5p15n c9a7s="14/e2_/a>sc#L306" id8"730l157e2>15n(1)
68 href};f">TEGRA_PIN_VI_VSY" UW1_PRlass="s6="+code=_6IN" UWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7<6p15n c9a7s="146fode=_GPI6s="line8 7ame1570s>15n_PIN<8 href};f">TEGRA_PIN_VI_VSY" UQaPEElass="s6f9ing">&q6LK_ UQaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7<7p15n c9a7s="14q6"sref">tegra30_p8n715={
59 href};f">TEGRA_PIN_VI_VSYNC_PUCaPEEs5code=_GPI5" class="PUCaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7<8p15n c9a7s="14="s7g">"7ART38C7S_N1570s>15=t;TEGRA_PIN_VI_VSYNC_PD6GPU_1PDDpan class="s6code=_GNCUWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7<9p15n c9a7s="14/e3_/a>sc#L306" id8"730l157e3>15n6239)
67 href};f">TEGRA_PIN_6"UQaPCCass="s6c9ing">&q6s="S"UQaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7a>,151 c9a7s="15="s6g">"6DMMC9_7AT21571c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNPU, 9/7a1p15n c9a7s="15dat2_/b5_/a>sc#L309"7id=15711>15n6231)
66 href};f">TEGRA_PIN_"JTAG_RTCC4_UW7_PR class="s6fode=_GPI6"JTAG_RTCC4_UWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7a2p15n c9a7s="15n class="s6g">&quo9;7DMM1571s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGJTAG_TCC7_PR class="s6fode=_GPI6"JTAG_TCCaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7a3p15n c9a7s="15s6rng">&quo6DMMC3_9A70 P1576r>15=6243)
67 href};f">TEGRA_PIN_6JTAG_TDI7_PR class="s6fode=_GPI6"JTAG_TDIaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7a4p15n c9a7s="15="s6gg">"6t;LC9_7WR115716>15n>_PIN243)
67 href};f">TEGRA_PIN_6JTAG_TDO7_PR class="s6fode=_GPI6"JTAG_TDOaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7a5p15n c9a7s="15dat1_/b6_/a>sc#L309"7id=15712>15n(1)
68 href};f">TEGRA_PIN_VI_VSY"JTAG_TMS7_PR class="s6fode=_GPI6"JTAG_TMSaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7a6p15n c9a7s="15n class="s6g7">&qu9t7;UA1571e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"JTAG_TaEP1_7_PR class="s6fode=_GPI6"JTAG_TaEP1_aPEEs"RA_PIN_VI_VSYNC_PD6, 9/7a7p15n c9a7s="15] = {f">TEGRA_PIN_VI7VS8157 =>15={
59 href};f">TEGRA_PIN_VI_VSYNC_TEEP1MODE_E_7_PR class="s6fode=_GPI6"TEEP1MODE_E_aPEEs"RA_PIN_VI_VSYNC_PD6, 9/7a8p15n c9a7s="15="s6">"G6N1_I8C7SDA157"s>15=t;),
70 hrefstatic const unsignedrs/pin8t7a&q15n9c9a7s="15dat0_/b7_/a>sc#L308"7id=157at>15=3_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6&8u7t;L157 c>15n > 295
59 href="drivers/pinctrl/p=PIcs{ddmi_aoIND2_PE"L272" class=1{ddmi_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T7<1p15n c9a7s="15s6ring">&qu6t;GMI_8P7N P1576r>15n6231)
66 href};f">TEGRA_PIN_"DDWR_I2C_VW4_PRpan class="s6code=_GNDDWR_I2C_VWaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7<2p15n c9a7s="15="s6r">"6DMMC8_7AT41572s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGDDWR_I2C_VEQaPZass="s6c9ing">&q6s="SDDWR_I2C_VEaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7<3p15n c9a7s="15ts_n_pc0_/a>sc#L308"7id=1572P>14=t;),
70 hrefstatic const unsignedrs/pin8t7<4p15n c9a7s="15n class="s6rg">&qu8t7ot;1572s>14=),
70 hrefstatic const unsignedrs/pin8t7<5p15n c9a7s="15s6rg">"6DMMC3_8A76 P15722>14=a(4)
68 href="drivers/pinctrl/pie=PIcs{devc_pee;DAP2_SCLK PA3pa=PIcs{devc_pee;ND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T7<6p15n c9a7s="15="s6"8">"6quot8V7_D11572e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY" claE<32K_EEUT1PAlass="s6f" class=6PIN" caE<32K_EEUaPEEs"RA_PIN_VI_VSYNC_PD6, 9/7<7p15n c9a7s="151_/c1_/a>sc#L306" 8d7"L31572=>15={
59 href};f">TEGRA_PIN_VI_VSYNC_ clCLCLK3_REQaPEElass="s6="+code=_6IN" claECLK3_REQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7"6t;V8_7SYN1572c>156t;),
70 hrefstatic const unsignedrs/pin8t74&q1529c9a7s="15">&qu6t;VI_HSYNC P877quo1572c>1563_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6,153 c9a7s="15="s6ring">&qu6" cl8s7="s1573s>157a(4)
68 href="drivers/pinctrl/pie=PIcs{gma_pee;DAP2_SCLK PA3pa=PIcs{gma_pee;ND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T7l/p1531c9a7s="15xdCpc2_/a>sc#L306"8i7="L1573r>15n6231)
66 href};f">TEGRA_PIN_"SDMMC4_DAT0_PAOUT1PAlass="s6f" class=6PINSDMMC4_DAT0_PAOUaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7"6"8c7ass1573s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGSDMMC4_DAT1_PAOQaPEElass="s6="+code=_6IN"SDMMC4_DAT1_PAOQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7<3p15n c9a7s="15>"6" class="s8e7">_157&q>15=6243)
67 href};f">TEGRA_PIN_6SDMMC4_DAT2_PAOQaPEElass="s6f9ing">&q6LK_SDMMC4_DAT2_PAOQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7<4p15n c9a7s="15="s6code=_GPI6" cl8s7="s15736>15n>_PIN243)
67 href};f">TEGRA_PIN_6SDMMC4_DAT3_PAOCaPEEs5code=_GPI5" class="SDMMC4_DAT3_PAOCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7<5p15n c9a7s="15xdCpc3_/a>sc#L306"8i7="L15732>15n(1)
68 href};f">TEGRA_PIN_VI_VSY"SDMMC4_aEP1_RSCCCaPEEs5code=_GPI5" class="SDMMC4_aEP1_RSCCCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7<6p15n c9a7s="15ass="s6rng">&quo6"8c7ass1573s>15p_PIN(3)
68 hrefstatic const unsignedrs/pin8t7"6" class="s8e7">_1573/>15p0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD615pN(4)
68 href="drivers/pinctrl/pie=PIcs{gmb_pee;DAP2_SCLK PA3pa=PIcs{gmb_pee;ND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T7l&q1529c9a7s="15c_sclCpc4_/a>sc#L3867 id15733>15n6239)
67 href};f">TEGRA_PIN_6SDMMC4_DAT4_PAOW4_PRpan class="s6code=_GNSDMMC4_DAT4_PAOWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/715n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNSDMMC4_DAT5_PAOEQaPZass="s6c9ing">&q6s="SPDMMC4_DAT5_PAOEaPEEl"RA_PIN_VI_VSYNC_PD6, 9/715p>))
68 href};f">TEGRA_PIN_VI_VSYGPDMMC4_DAT6_PAOW6_PR class="s6code=_GPI66"DMMC4_DAT6_PAOWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7TEGRA_PIN_VI_VSYGSDMMC4_DAT7_PAOW7_PR class="s6fode=_GPI6"SDMMC4_DAT7_PAOWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7<3p15n c9a7s="15c_sdaCpc5_/a>sc#L3867 id1574P>14=t;),
70 hrefstatic const unsignedrs/pin8t7a>,1544c9a7s="15pan class="s6cring8>7q6"1574s>14=),
70 hrefstatic const unsignedrs/pin8t7shref[] = {f">T7<6p15n c9a7s="15="s6c8">"6" cl8s7="s1574e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"SDMMC4_MMC4_CCW4_PRpan class="s6code=_GNSDMMC4_MMC4_CCWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7sc#L306" 8d7"L3157_/>15pt;),
70 hrefstatic const unsignedrs/pin8t7asp15n8c9a7s="15s="s6c9">"6" c8a7s="157=">15p),
70 hrefstatic const unsignedrs/pin8t7a&q1529c9a7s="15=_GPI6" class="sre8"7_GP157_G>15pa(4)
68 href="drivers/pinctrl/pie=PIcs{gmdi_aoIND2_PE"L272" class=1{gmdi_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T7a>,155 c9a7s="15="s6code=_GPI6" cl8s7="s1575c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNSDMMC4_MMD_PTW7_PR class="s6fode=_GPI6"SDMMC4_MMD_PTWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7l/p1551c9a7s="15n_pc7_/a>sc#L306" 8d7"L31575s>15pt;),
70 hrefstatic const unsignedrs/pin8t715pa(4)
68 href="drivers/pinctrl/pie=PIcs{gmei_aoIND2_PE"L272" class=1{gmei_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T7a>,1544c9a7s="15="s6code=_GPI6" cl8s7="s15756>15n>_PIN243)
67 href};f">TEGRA_PIN_6PBlCLPBBlass="s6f" class=6PINPBlCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7l/p1535c9a7s="15dat5_/d0_/a>sc#L308"7id=1575r>15n(1)
68 href};f">TEGRA_PIN_VI_VSY" AMlaPWR_I2C_BlW1_PRlass="s6="+code=_6IN" AMlaPWR_I2C_BlWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7l6p15n c9a7s="15n class="s6code=_G8I7" c1575e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY" AMlaPWR_I2C_BBQaPEElass="s6f9ing">&q6LK_3AMlaPWR_I2C_BBQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7l/p15n7c9a7s="15s6c8">"6" clas8=7sre1575=>15={
59 href};f">TEGRA_PIN_VI_VSYNC_PBBCaPEEs5code=_GPI5" class="PBBCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7lsp15n8c9a7s="15="s6code=_GPI6" cl8s7="s1575s>15=t;TEGRA_PIN_VI_VSYNC_PD6GPCCQaPEElass="s6f9ing">&q6LK_ CCQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7l&q1529c9a7s="15dat4_/d1_/a>sc#L308"7id=1575c>156"PIN(3)
68 hrefstatic const unsignedrs/pin8t7a>,156 c9a7s="15n class="s6code=_G8I7" c1576s>157IN(3)
68 hrefstatic const unsignedrs/pin8t7a>,1561c9a7s="15s6code=_GPI6" clas8=7sre1576t>157ef">_GPIO6242)
67 href="drivers/oass=1{gmfi_aoIND2_PE"L272" class=1{gmfi_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T7a>,1562c9a7s="15="s6code=_GPI6" cl8s7="s157"s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGPBB_1PDDpan class="s6code=_GNCBB_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/7a>,1563c9a7s="15_/d2_/a>sc#L306" i8=7L30157/d>1566243)
67 href};f">TEGRA_PIN_6CBBQaPCCass="s6c9ing">&q6s="S"BBQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7a>,1544c9a7s="15"s6code=_GPI6" cla8s7"sr157s6>15n>_PIN243)
67 href};f">TEGRA_PIN_6"BB, 9/7a/p1535c9a7s="15GPI6" class="sref"8_7PIO157PI>15n(1)
68 href};f">TEGRA_PIN_VI_VSY" BBD6" Z class="s6fode=_GPI6" BBDaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7a6p15n c9a7s="15="s6c8">"6" cl8s7="s1576s>15p_PIN(3)
68 hrefstatic const unsignedrs/pin8t7a&q1557c9a7s="15dat6_/d3_/a>sc#L308"7id=1576/>15p0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6,1558c9a7s="15n class="s6c9">&qu8t7" c1576">15pN(4)
68 href="drivers/pinctrl/pie=PIcs{gmg_pdde="SDMMC3T7_P7_l=PIcs{gmg_pddeND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T7a&q1529c9a7s="15s6code=_GPI6" clas8=7sre1576G>15p69 href};f">TEGRA_PIN_VI_VSYNC_PN3AMlMMMC4_CCUT1PAlass="s6f" class=6PIN"AMlMMMC4_CCUaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7(3)
68 hrefstatic const unsignedrs/pin8t7<>,1561c9a7s="15dat7_/d4_/a>sc#L308"7id=1577p>15=1_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6,1572c9a7s="15n class="s6code=_G8I7" c1577">15=ef">_GPIO6242)
67 href="drivers/oass=1{gmh_pdde="SDMMC3T7_P7_l=PIcs{gmh_pddeND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T7a>,1573c9a7s="15s6code=_GPI6" clas8=7sre1576c>14=6243)
67 href};f">TEGRA_PIN_6_CCW1_PRlass="s6="+code=_6IN" CCWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7<>,1544c9a7s="15="s6code=_GPI6" cl8s7="s157"s>157"PIN(3)
68 hrefstatic const unsignedrs/pin8t7sc#L306" id=8L70vi1575_>157IN(3)
68 hrefstatic const unsignedrs/pin8t7<6p15n c9a7s="15ode=_GPI6" class="8r7f">157de>157ef">_GPIO6242)
67 href="drivers/oass=1{gpv_pdde="SDMMC3T7_P7_l=PIcs{gpv_pddeND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T7a&q1557c9a767 href};f">TEGRA_PIN>))
78 hr 7 c>14= href};f">TEGRA_PIN_VI_VSYNC_PD6GPEX_L2_aEP1_RSCC, 9/7<>,1558c9a7s="14="s6">/* All 6on-G8I7 pi1477s>15=t;TEGRA_PIN_VI_VSYNC_PD6G"EX_L2_MMCCLK3_RSCCD6" Z class="s6fode=_GPI6" EX_L2_MMCCLK3_RSCCDaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7<&q1529c9a7s="14c_/d6_/a>sc#L306" 8d7"L31477t>15569 href};f">TEGRA_PIN_VI_VSYNC_PN EX_L0_PRSNP1_RSDDCLPBBlass="s6f" class=6PINPEX_L0_PRSNP1_RSDDCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/715n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNPEX_L0_aEP1_RSDDW1_PRlass="s6="+code=_6IN" EX_L0_aEP1_RSDDWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7<>,1561c9a7s="14e=off6et" class="s8e7">o147=o>14s>))
68 href};f">TEGRA_PIN_VI_VSYG EX_L0_MMCCLK3_RSDDQaPEElass="s6f9ing">&q6LK_ EX_L0_MMCCLK3_RSDDQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7<>,1572c9a7s="14="s6ss="comme6t">/8 7on-1478s>15ns */<8 href};f">TEGRA_PIN_VI_VSYG EX_WAKE3_RSDDCaPEEs5code=_GPI5" class="PEX_WAKE3_RSDDCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7<>,1573c9a7s="14c_/d7_/a>sc#L306" 8d7"L31478d>1566243)
67 href};f">TEGRA_PIN_6 EX_L1_PRSNP1_RSDD_1PDDpan class="s6code=_GNCEX_L1_PRSNP1_RSDD_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/7<>,1544c9a7s="14s="s67ode=_GPI6PIN8 7las14786>15n>_PIN243)
67 href};f">TEGRA_PIN_6CEX_L1_aEP1_RSDDQaPCCass="s6c9ing">&q6s="S"EX_L1_aEP1_RSDDQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7147_G>14s(1)
68 href};f">TEGRA_PIN_VI_VSY""EX_L1_MMCCLK3_RSDD, 9/7<6p15n c9a7s="14="s6"8ing">&q6PIN"8c7ass1478e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY" EX_L2_PRSNP1_RSDDD6" Z class="s6fode=_GPI6" EX_L2_PRSNP1_RSDDDaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7<&q1557c9a7s="14pe0_/a>sc#L306" id8"730l1478/>15pt;),
70 hrefstatic const unsignedrs/pin8t7<>,1558c9a7s="14679ing">&q6PIN" cl8s7="s1478">15p),
70 hrefstatic const unsignedrs/pin8t7T_aoIND1_PE"L271" class=e{lcd>T_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T7a>,149 c9a7s="14="s6f="+code=6PIN"8c7ass1479c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNLCD" cl1_PCW1_PRlass="s6="+code=_6IN"LCD" cl1_PCWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7a&q1571c9a7s="14/e1_/a>sc#L306" id8"730l1479t>1576231)
66 href};f">TEGRA_PIN_"LCD" cl2_PC, 9/7a>,1572c9a7s="146f="+code=6PIN" cl8s7="s1479s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGLCD"CS0LKREN_1PDDpan class="s6code=_GNLCD"CS0LKREN_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/7a>,1573c9a7s="14e6PIN" class="sref8>7PIN1479d>1566243)
67 href};f">TEGRA_PIN_6LCD"SD<32K_NQaPCCass="s6c9ing">&q6s="SLCD"SD<32K_NQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7a>,1544c9a7s="14="s6="+code=_6IN" 8l7ss=14796>15n>_PIN243)
67 href};f">TEGRA_PIN_6LCD"DC0_PN, 9/7a/p1535c9a7s="14/e2_/a>sc#L306" id8"730l1479_>157(1)
68 href};f">TEGRA_PIN_VI_VSY"LCD"SDI6" ZQaPEElass="s6f9ing">&q6LK_LCD"SDI6" ZQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7a6p15n c9a7s="146fode=_GPI6s="line8 7ame1479e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"LCD"WRPRSNZCaPEEs5code=_GPI5" class="LCD"WRPRSNZCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/7a&q1557c9a7s="14q6"sref">tegra30_p8n7146G_32K1SDMMC4_DAT1, 9/7a>,1558c9a7s="14="s7g">"7ART38C7S_N1479c>156t;),
70 hrefstatic const unsignedrs/pin8t7a/p1569c9a7s="14/e3_/a>sc#L306" id8"730l1479c>1563_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6157a(4)
68 href="drivers/pinctrl/pie=PIcs{lcd>T_aoIND2_PE"L272" class=1{lcd>T_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T8<1p15n c9a8s="14/e1_/a>sc#L306" id8"830l158e1>15n6231)
66 href};f">TEGRA_PIN_"LCD" cl0_PBQaPEElass="s6f9ing">&q6LK_LCD" cl0_PBQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<2p15n c9a8s="146f="+code=6PIN" cl8s8="s1580s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGLCD" MMC4_BCaPEEs5code=_GPI5" class="LCD" MMC4_BCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<3p15n c9a8s="14e6PIN" class="sref8>8PIN1580d>1566243)
67 href};f">TEGRA_PIN_6LCD"DC1_PDQaPEElass="s6f9ing">&q6LK_LCD"DC1_PDQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<4p15n c9a8s="14="s6="+code=_6IN" 8l8ss=15806>15n>_PIN243)
67 href};f">TEGRA_PIN_6LCD"D0_PEUT1PAlass="s6f" class=6PINLCD"D0_PEUaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<5p15n c9a8s="14/e2_/a>sc#L306" id8"830l158e2>15n(1)
68 href};f">TEGRA_PIN_VI_VSY"LCD"D1_PEQaPEElass="s6="+code=_6IN"LCD"D1_PEQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<6p15n c9a8s="146fode=_GPI6s="line8 8ame1580s>15n_PIN<8 href};f">TEGRA_PIN_VI_VSY"LCD"D2_PEQaPEElass="s6f9ing">&q6LK_LCD"D2_PEQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<7p15n c9a8s="14q6"sref">tegra30_p8n815={
59 href};f">TEGRA_PIN_VI_VSYNC_LCD"D3_PECaPEEs5code=_GPI5" class="LCD"D3_PECaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<8p15n c9a8s="14="s7g">"7ART38C8S_N1580s>15=t;TEGRA_PIN_VI_VSYNC_PD6GLCD"D4_PE_1PDDpan class="s6code=_GNLCD"D4_PE_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<9p15n c9a8s="14/e3_/a>sc#L306" id8"830l158e3>15n6239)
67 href};f">TEGRA_PIN_6LCD"D5_PEQaPCCass="s6c9ing">&q6s="SLCD"D5_PEQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a>,151 c9a8s="15="s6g">"6DMMC9_8AT21581c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNLCD"D6_PE, 9/8a1p15n c9a8s="15dat2_/b5_/a>sc#L309"8id=15811>15n6231)
66 href};f">TEGRA_PIN_"LCD"D7_PED6" Z class="s6fode=_GPI6"LCD"D7_PEDaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a2p15n c9a8s="15n class="s6g">&quo9;8DMM1581s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGLCD"D8_PFUT1PAlass="s6f" class=6PINLCD"D8_PFUaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a3p15n c9a8s="15s6rng">&quo6DMMC3_9A80 P1586r>15=6243)
67 href};f">TEGRA_PIN_6LCD"D9_PFQaPEElass="s6="+code=_6IN"LCD"D9_PFQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a4p15n c9a8s="15="s6gg">"6t;LC9_8WR115816>15n>_PIN243)
67 href};f">TEGRA_PIN_6LCD"D10_PFQaPEElass="s6f9ing">&q6LK_LCD"D10_PFQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a5p15n c9a8s="15dat1_/b6_/a>sc#L309"8id=15812>15n(1)
68 href};f">TEGRA_PIN_VI_VSY"LCD"D11_PFCaPEEs5code=_GPI5" class="LCD"D11_PFCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a6p15n c9a8s="15n class="s6g7">&qu9t8;UA1581e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"LCD"D12_PF_1PDDpan class="s6code=_GNLCD"D12_PF_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a7p15n c9a8s="15] = {f">TEGRA_PIN_VI8VS8158 =>15={
59 href};f">TEGRA_PIN_VI_VSYNC_LCD"D13_PFQaPCCass="s6c9ing">&q6s="SLCD"D13_PFQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a8p15n c9a8s="15="s6">"G6N1_I8C8SDA1581s>15=t;TEGRA_PIN_VI_VSYNC_PD6GLCD"D14_PF, 9/8a9p15n c9a8s="15dat0_/b7_/a>sc#L308"8id=15813>15n6239)
67 href};f">TEGRA_PIN_6LCD"D15_PFD6" Z class="s6fode=_GPI6"LCD"D15_PFDaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8&8u8t;L1582c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNLCD"DE_PJQaPEElass="s6="+code=_6IN"LCD"DE_PJQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<1p15n c9a8s="15s6ring">&qu6t;GMI_8P8N P1586r>15n6231)
66 href};f">TEGRA_PIN_"LCD"HSYNMI_JCaPEEs5code=_GPI5" class="LCD"HSYNMI_JCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<2p15n c9a8s="15="s6r">"6DMMC8_8AT41582s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGLCD"VSYNMI_J_1PDDpan class="s6code=_GNLCD"VSYNMI_J_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<3p15n c9a8s="15ts_n_pc0_/a>sc#L308"8id=1582r>15=6243)
67 href};f">TEGRA_PIN_6LCD"D16_PMUT1PAlass="s6f" class=6PINLCD"D16_PMUaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<4p15n c9a8s="15n class="s6rg">&qu8t8ot;15826>15n>_PIN243)
67 href};f">TEGRA_PIN_6LCD"D17_PMQaPEElass="s6="+code=_6IN"LCD"D17_PMQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<5p15n c9a8s="15s6rg">"6DMMC3_8A86 P1586r>15n(1)
68 href};f">TEGRA_PIN_VI_VSY"LCD"D18_PMQaPEElass="s6f9ing">&q6LK_LCD"D18_PMQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<6p15n c9a8s="15="s6"8">"6quot8V8_D11582e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"LCD"D19_PMCaPEEs5code=_GPI5" class="LCD"D19_PMCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<7p15n c9a8s="151_/c1_/a>sc#L306" 8d8"L31582=>15={
59 href};f">TEGRA_PIN_VI_VSYNC_LCD"D20_PM_1PDDpan class="s6code=_GNLCD"D20_PM_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<8p15n c9a8s="15s="s6r9">"6t;V8_8SYN1582s>15=t;TEGRA_PIN_VI_VSYNC_PD6GLCD"D21_PMQaPCCass="s6c9ing">&q6s="SLCD"D21_PMQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<9p15n c9a8s="15">&qu6t;VI_HSYNC P878quo15823>15n6239)
67 href};f">TEGRA_PIN_6LCD"D22_PM, 9/8a>,153 c9a8s="15="s6ring">&qu6" cl8s8="s1583c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNLCD"D23_PMD6" Z class="s6fode=_GPI6"LCD"D23_PMDaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a1p15n c9a8s="15xdCpc2_/a>sc#L306"8i8="L1583r>15n6231)
66 href};f">TEGRA_PIN_"sref1IN2K_ND6" Z class="s6fode=_GPI6"sref1IN2K_NDaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a2p15n c9a8s="15ass="s6r">"6"8c8ass1583s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGLCD"CS1LKREWUT1PAlass="s6f" class=6PINLCD"CS1LKREWUaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a3p15n c9a8s="15>"6" class="s8e8">_158&q>15=6243)
67 href};f">TEGRA_PIN_6LCD"M1_PWQaPEElass="s6="+code=_6IN"LCD"M1_PWQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a4p15n c9a8s="15="s6code=_GPI6" cl8s8="s1583s>157"PIN(3)
68 hrefstatic const unsignedrs/pin8t8<5p15n c9a8s="15xdCpc3_/a>sc#L306"8i8="L1583_>157IN(3)
68 hrefstatic const unsignedrs/pin8t8<6p15n c9a8s="15ass="s6rng">&quo6"8c8ass1583e>157ef">_GPIO6242)
67 href="drivers/oass=1{owrT_aoIND2_PE"L272" class=1{owrT_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T8"6" class="s8e8">_158>&>15={
59 href};f">TEGRA_PIN_VI_VSYNC_OWRaPEElass="s6="+code=_6IN"OWRaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a8p15n c9a8s="15="s6code=_GPI6" cl8s8="s1583c>156t;),
70 hrefstatic const unsignedrs/pin8t8l&q1529c9a8s="15c_sclCpc4_/a>sc#L3868 id1583c>1563_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6157a(4)
68 href="drivers/pinctrl/pie=PIcs{sdio>T_aoIND1_PE"L271" class=e{sdio>T_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T815p>))
68 href};f">TEGRA_PIN_VI_VSYGPDMMC1_DAT3_PYW4_PRpan class="s6code=_GNSDMMC1_DAT3_PYWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8TEGRA_PIN_VI_VSYGSDMMC1_DAT2_PYQaPCCass="s6c9ing">&q6s="SSDMMC1_DAT2_PYQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<3p15n c9a8s="15c_sdaCpc5_/a>sc#L3868 id1584q>15=6243)
67 href};f">TEGRA_PIN_6SDMMC1_DAT1_PYW6_PR class="s6code=_GPI66"DMMC1_DAT1_PYWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<4p15n c9a8s="15pan class="s6cring8>8q6"15846>15n>_PIN243)
67 href};f">TEGRA_PIN_6"DMMC1_DAT0_PYW7_PR class="s6fode=_GPI6"SDMMC1_DAT0_PYWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<5p15n c9a8s="15="s6code=_GPI6" cl8s8="s158"s>15p(1)
68 href};f">TEGRA_PIN_VI_VSY"SDMMC1_MMC4_ZUT1PAlass="s6f" class=6PINSDMMC1_MMC4_ZUaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<6p15n c9a8s="15="s6c8">"6" cl8s8="s1584e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"SDMMC1_MMD_PZQaPEElass="s6="+code=_6IN"SDMMC1_MMD_PZQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8sc#L306" 8d8"L3158_/>15pt;),
70 hrefstatic const unsignedrs/pin8t8asp15n8c9a8s="15s="s6c9">"6" c8a8s="158=">15p),
70 hrefstatic const unsignedrs/pin8t8a&q1529c9a8s="15=_GPI6" class="sre8"8_GP158_G>15pa(4)
68 href="drivers/pinctrl/pie=PIcs{sdio>T_aoIND2_PE"L272" class=1{sdio>T_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T8a>,155 c9a8s="15="s6code=_GPI6" cl8s8="s1585c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNSDMMC3_DAT5_PDCLPBBlass="s6f" class=6PINSDMMC3_DAT5_PDCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8l/p1551c9a8s="15n_pc7_/a>sc#L306" 8d8"L31585s>15p>))
68 href};f">TEGRA_PIN_VI_VSYGPDMMC3_DAT4_PDW1_PRlass="s6="+code=_6IN"PDMMC3_DAT4_PDWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8lsp1532c9a8s="15s="s6code=_GPI6" c8a8s="1585s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGSDMMC3_DAT6_PDCaPEEs5code=_GPI5" class="SDMMC3_DAT6_PDCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8l3p15n c9a8s="15=_GPI6" class="sre8"8_GP1585q>15=6243)
67 href};f">TEGRA_PIN_6SDMMC3_DAT7_PD_1PDDpan class="s6code=_GNSDMMC3_DAT7_PD_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/8l4p15n c9a8s="15="s6code=_GPI6" cl8s8="s1585s>157"PIN(3)
68 hrefstatic const unsignedrs/pin8t8l/p1535c9a8s="15dat5_/d0_/a>sc#L308"8id=1585_>157IN(3)
68 hrefstatic const unsignedrs/pin8t8l6p15n c9a8s="15n class="s6code=_G8I8" c1585e>157ef">_GPIO6242)
67 href="drivers/oass=1{sdioc_pee;DAP2_SCLK PA3pa=PIcs{sdioc_pee;ND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T8a/p15n7c9a8s="15s6c8">"6" clas8=8sre1585=>15={
59 href};f">TEGRA_PIN_VI_VSYNC_SDMMC3_MMC4_AW6_PR class="s6code=_GPI66"DMMC3_MMC4_AWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8lsp15n8c9a8s="15="s6code=_GPI6" cl8s8="s1585s>15=t;TEGRA_PIN_VI_VSYNC_PD6G"DMMC3_MMD_POW7_PR class="s6fode=_GPI6"SDMMC3_MMD_POWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8l&q1529c9a8s="15dat4_/d1_/a>sc#L308"8id=15853>15n6239)
67 href};f">TEGRA_PIN_6SDMMC3_DAT3_PB_1PDDpan class="s6code=_GNSDMMC3_DAT3_PB_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a>,156 c9a8s="15n class="s6code=_G8I8" c1586c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNSDMMC3_DAT2_PBQaPCCass="s6c9ing">&q6s="SSDMMC3_DAT2_PBQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a/p1551c9a8s="15s6code=_GPI6" clas8=8sre1586s>15p>))
68 href};f">TEGRA_PIN_VI_VSYGPDMMC3_DAT1_PB, 9/8asp1532c9a8s="15="s6code=_GPI6" cl8s8="s158"s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGPDMMC3_DAT0_PBW7_PR class="s6fode=_GPI6"SDMMC3_DAT0_PBWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a3p15n c9a8s="15_/d2_/a>sc#L306" i8=8L301586P>14=t;),
70 hrefstatic const unsignedrs/pin8t8a>,1544c9a8s="15"s6code=_GPI6" cla8s8"sr1586s>14=),
70 hrefstatic const unsignedrs/pin8t8a/p1535c9a8s="15GPI6" class="sref"8_8PIO15862>14=a(4)
68 href="drivers/pinctrl/pie=PIcs{spi_pee;DAP2_SCLK PA3pa=PIcs{spi_pee;ND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T8a6p15n c9a8s="15="s6c8">"6" cl8s8="s1586e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"SPI2"CS1LKREWQaPEElass="s6f9ing">&q6LK_SPI2"CS1LKREWQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a/p15n7c9a8s="15dat6_/d3_/a>sc#L308"8id=1586=>15={
59 href};f">TEGRA_PIN_VI_VSYNC_SPI2"CS2LKREWCaPEEs5code=_GPI5" class="SPI2"CS2LKREWCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8asp15n8c9a8s="15n class="s6c9">&qu8t8" c1586s>15=t;TEGRA_PIN_VI_VSYNC_PD6G"PI2"MOSI_PXCLPBBlass="s6f" class=6PINSPI2"MOSI_PXCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a&q1529c9a8s="15s6code=_GPI6" clas8=8sre1586G>15p69 href};f">TEGRA_PIN_VI_VSYNC_PNSPI2"MISO_PXW1_PRlass="s6="+code=_6IN"PPI2"MISO_PXWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8TEGRA_PIN_VI_VSYNC_PNSPI2"SCC4_XQaPEElass="s6f9ing">&q6LK_SPI2"SCC4_XQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8sc#L308"8id=1587s>15p>))
68 href};f">TEGRA_PIN_VI_VSYGPPI2"CS0LKREXCaPEEs5code=_GPI5" class="SPI2"CS0LKREXCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/815ns */<8 href};f">TEGRA_PIN_VI_VSYGPPI1"MOSI_PX_1PDDpan class="s6code=_GNSPI1"MOSI_PX_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<3p15n c9a8s="15s6code=_GPI6" clas8=8sre1586c>14=6243)
67 href};f">TEGRA_PIN_6SPI1"SCC4_XQaPCCass="s6c9ing">&q6s="SSPI1"SCC4_XQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<>,1544c9a8s="15="s6code=_GPI6" cl8s8="s15876>15n>_PIN243)
67 href};f">TEGRA_PIN_6"PI1"CS0LKREX, 9/8sc#L306" id=8L80vi1587s>15p(1)
68 href};f">TEGRA_PIN_VI_VSY"SPI1"MISO_PXW7_PR class="s6fode=_GPI6"SPI1"MISO_PXWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<6p15n c9a8s="15ode=_GPI6" class="8r8f">1587s>15p_PIN(3)
68 hrefstatic const unsignedrs/pin8t8a&q1557c9a867 href};f">TEGRA_PIN>))
88 hr 87/>15p0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6,1558c9a8s="14="s6">/* All 6on-G8I8 pi1487">15pN(4)
68 href="drivers/pinctrl/pie=PIcs{uaa_pee;DAP2_SCLK PA3pa=PIcs{uaa_pee;ND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T8<&q1529c9a8s="14c_/d6_/a>sc#L306" 8d8"L31487t>15569 href};f">TEGRA_PIN_VI_VSYNC_PNULPI_DATA0_POW1_PRlass="s6="+code=_6IN"ULPI_DATA0_POWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/815n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNULPI_DATA1_POQaPEElass="s6f9ing">&q6LK_ULPI_DATA1_POQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8o148=o>14s>))
68 href};f">TEGRA_PIN_VI_VSYGULPI_DATA2_POCaPEEs5code=_GPI5" class="ULPI_DATA2_POCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8/8 8on-1488s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGULPI_DATA3_PO_1PDDpan class="s6code=_GNULPI_DATA3_PO_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<3p15n c9a8s="14c_/d7_/a>sc#L306" 8d8"L31488P>14=t;),
70 hrefstatic const unsignedrs/pin8t8<>,1544c9a8s="14s="s67ode=_GPI6PIN8 8las1488s>14=),
70 hrefstatic const unsignedrs/pin8t814882>14=a(4)
68 href="drivers/pinctrl/pie=PIcs{uab_pee;DAP2_SCLK PA3pa=PIcs{uab_pee;ND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T8<6p15n c9a8s="14="s6"8ing">&q6PIN"8c8ass1488e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"ULPI_DATA7_POCLPBBlass="s6f" class=6PINULPI_DATA7_POCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<&q1557c9a8s="14pe0_/a>sc#L306" id8"830l1488=>15={
59 href};f">TEGRA_PIN_VI_VSYNC_ULPI_DATA4_POQaPCCass="s6c9ing">&q6s="SULPI_DATA4_POQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8<>,1558c9a8s="14679ing">&q6PIN" cl8s8="s1488s>15=t;TEGRA_PIN_VI_VSYNC_PD6GULPI_DATA5_PO, 9/8<&q1529c9a8s="14=6PIN" class="sref8>8PIN1488t>15569 href};f">TEGRA_PIN_VI_VSYNC_PNULPI_DATA6_POW7_PR class="s6fode=_GPI6"ULPI_DATA6_POWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a>,149 c9a8s="14="s6f="+code=6PIN"8c8ass1489c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNPVCLPBBlass="s6f" class=6PINPVCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a&q1571c9a8s="14/e1_/a>sc#L306" id8"830l1489t>1576231)
66 href};f">TEGRA_PIN_"PVW1_PRlass="s6="+code=_6IN" VWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a>,1572c9a8s="146f="+code=6PIN" cl8s8="s1489s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGPVQaPEElass="s6f9ing">&q6LK_ VQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a>,1573c9a8s="14e6PIN" class="sref8>8PIN1489d>1566243)
67 href};f">TEGRA_PIN_6PVCaPEEs5code=_GPI5" class="PVCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a>,1544c9a8s="14="s6="+code=_6IN" 8l8ss=1489s>157"PIN(3)
68 hrefstatic const unsignedrs/pin8t8a/p1535c9a8s="14/e2_/a>sc#L306" id8"830l1489_>157IN(3)
68 hrefstatic const unsignedrs/pin8t8a6p15n c9a8s="146fode=_GPI6s="line8 8ame1489e>157ef">_GPIO6242)
67 href="drivers/oass=1{uart>T_aoIND2_PE"L272" class=1{uart>T_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T8a&q1557c9a8s="14q6"sref">tegra30_p8n8146G_32K1SDMMC4_DAT1&q6LK_UART2_TXD" MQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a>,1558c9a8s="14="s7g">"7ART38C8S_N1489s>15=t;TEGRA_PIN_VI_VSYNC_PD6GUART2_RXD" MCaPEEs5code=_GPI5" class="UART2_RXD" MCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/8a&q1529c9a8s="14/e3_/a>sc#L306" id8"830l1489t>15569 href};f">TEGRA_PIN_VI_VSYNC_PNUART2_CTSLKREJQaPCCass="s6c9ing">&q6s="SUART2_CTSLKREJQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/915n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNUART2_RTSLKREJ, 9/9<1p15n c9a9s="14/e1_/a>sc#L306" id8"930l1590s>15pt;),
70 hrefstatic const unsignedrs/pin8t9<2p15n c9a9s="146f="+code=6PIN" cl8s9="s1590s>15p),
70 hrefstatic const unsignedrs/pin8t9<3p15n c9a9s="14e6PIN" class="sref8>9PIN1590s>15pa(4)
68 href="drivers/pinctrl/pie=PIcs{uartc_pee;DAP2_SCLK PA3pa=PIcs{uartc_pee;ND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T9<4p15n c9a9s="14="s6="+code=_6IN" 8l9ss=15906>15n>_PIN243)
67 href};f">TEGRA_PIN_6UART3_CTSLKREOQaPEElass="s6="+code=_6IN"UART3_CTSLKREOQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<5p15n c9a9s="14/e2_/a>sc#L306" id8"930l159e2>15n(1)
68 href};f">TEGRA_PIN_VI_VSY"UART3_RTSLKRECUT1PAlass="s6f" class=6PINUART3_RTSLKRECUaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<6p15n c9a9s="146fode=_GPI6s="line8 9ame1590s>15n_PIN<8 href};f">TEGRA_PIN_VI_VSY"UART3_TXD" W, 9/9<7p15n c9a9s="14q6"sref">tegra30_p8n915={
59 href};f">TEGRA_PIN_VI_VSYNC_UART3_RXD" WW7_PR class="s6fode=_GPI6"UART3_RXD" WWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<8p15n c9a9s="14="s7g">"7ART38C9S_N1590c>156t;),
70 hrefstatic const unsignedrs/pin8t9<9p15n c9a9s="14/e3_/a>sc#L306" id8"930l1590c>1563_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6,151 c9a9s="15="s6g">"6DMMC9_9AT21591s>157a(4)
68 href="drivers/pinctrl/pie=PIcs{uda_pee;DAP2_SCLK PA3pa=PIcs{uda_pee;ND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T9a1p15n c9a9s="15dat2_/b5_/a>sc#L309"9id=15911>15n6231)
66 href};f">TEGRA_PIN_"ULPI_MMC4_YCLPBBlass="s6f" class=6PINULPI_MMC4_YCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a2p15n c9a9s="15n class="s6g">&quo9;9DMM1591s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGULPI_DIR4_YW1_PRlass="s6="+code=_6IN"ULPI_DIR4_YWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a3p15n c9a9s="15s6rng">&quo6DMMC3_9A90 P1596r>15=6243)
67 href};f">TEGRA_PIN_6ULPI_NXT4_YQaPEElass="s6f9ing">&q6LK_ULPI_NXT4_YQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a4p15n c9a9s="15="s6gg">"6t;LC9_9WR115916>15n>_PIN243)
67 href};f">TEGRA_PIN_6ULPI_STP4_YCaPEEs5code=_GPI5" class="ULPI_STP4_YCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a5p15n c9a9s="15dat1_/b6_/a>sc#L309"9id=15912>15nt;),
70 hrefstatic const unsignedrs/pin8t9a6p15n c9a9s="15n class="s6g7">&qu9t9;UA1591e>157),
70 hrefstatic const unsignedrs/pin8t9a7p15n c9a9s="15] = {f">TEGRA_PIN_VI9VS8159 =>15=a(4)
68 href="drivers/pinctrl/pie=PIcs{vi>T_aoIND1_PE"L271" class=e{vi>T_aoIND2_Pref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T9a8p15n c9a9s="15="s6">"G6N1_I8C9SDA1591s>15=t;TEGRA_PIN_VI_VSYNC_PD6GVI"D1_PDQaPCCass="s6c9ing">&q6s="SVI"D1_PDQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a9p15n c9a9s="15dat0_/b7_/a>sc#L308"9id=15913>15n6239)
67 href};f">TEGRA_PIN_6VI"VSYNMI_D, 9/9&8u9t;L1592c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNVI"HSYNMI_DD6" Z class="s6fode=_GPI6"VI"HSYNMI_DDaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<1p15n c9a9s="15s6ring">&qu6t;GMI_8P9N P1596r>15n6231)
66 href};f">TEGRA_PIN_"VI"D2_PLCLPBBlass="s6f" class=6PINVI"D2_PLCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<2p15n c9a9s="15="s6r">"6DMMC8_9AT41592s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGVI"D3_PLW1_PRlass="s6="+code=_6IN"VI"D3_PLWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<3p15n c9a9s="15ts_n_pc0_/a>sc#L308"9id=1592r>15=6243)
67 href};f">TEGRA_PIN_6VI"D4_PLQaPEElass="s6f9ing">&q6LK_VI"D4_PLQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<4p15n c9a9s="15n class="s6rg">&qu8t9ot;15926>15n>_PIN243)
67 href};f">TEGRA_PIN_6VI"D5_PLCaPEEs5code=_GPI5" class="VI"D5_PLCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<5p15n c9a9s="15s6rg">"6DMMC3_8A96 P1596r>15n(1)
68 href};f">TEGRA_PIN_VI_VSY"VI"D6_PL_1PDDpan class="s6code=_GNVI"D6_PL_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<6p15n c9a9s="15="s6"8">"6quot8V9_D11592e>157_PIN<8 href};f">TEGRA_PIN_VI_VSY"VI"D7_PLQaPCCass="s6c9ing">&q6s="SVI"D7_PLQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<7p15n c9a9s="151_/c1_/a>sc#L306" 8d9"L31592=>15={
59 href};f">TEGRA_PIN_VI_VSYNC_VI"D8_PL, 9/9<8p15n c9a9s="15s="s6r9">"6t;V8_9SYN1592s>15=t;TEGRA_PIN_VI_VSYNC_PD6GVI"D9_PLD6" Z class="s6fode=_GPI6"VI"D9_PLDaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<9p15n c9a9s="15">&qu6t;VI_HSYNC P879quo15923>15n6239)
67 href};f">TEGRA_PIN_6VI" MMC4_TCLPBBlass="s6f" class=6PINVI" MMC4_TCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a>,153 c9a9s="15="s6ring">&qu6" cl8s9="s1593c>15n 6246ef};f">TEGRA_PIN_VI_VSYNC_PNVI"D104_TQaPEElass="s6f9ing">&q6LK_VI"D104_TQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a1p15n c9a9s="15xdCpc2_/a>sc#L306"8i9="L1593r>15n6231)
66 href};f">TEGRA_PIN_"VI"D11_PTCaPEEs5code=_GPI5" class="VI"D11_PTCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a2p15n c9a9s="15ass="s6r">"6"8c9ass1593s>15ns */<8 href};f">TEGRA_PIN_VI_VSYGVI"D04_T_1PDDpan class="s6code=_GNVI"D04_T_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a3p15n c9a9s="15>"6" class="s8e9">_1593P>14=t;),
70 hrefstatic const unsignedrs/pin8t9a4p15n c9a9s="15="s6code=_GPI6" cl8s9="s1593s>14=),
70 hrefstatic const unsignedrs/pin8t9<5p15n c9a9s="15xdCpc3_/a>sc#L306"8i9="L1593_>157enumhref};f">TEGRA_Pgnedr_mux1PDDpan class="gnedr_mux>15ns]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">T9<6p15n c9a9s="15ass="s6rng">&quo6"8c9ass1593e>157_PIN<8 href};f">TEGRA_PIN_VI_MUX_BLINK1PDDpan class="s6codeMUX_BLINKaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a7p15n c9a9s="15">"6" class="s8e9">_159>&>15={
59 href};f">TEGRA_PIN_VI_VSMUX_CEC1PDDpan class="s6codeMUX_CECaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a8p15n c9a9s="15="s6code=_GPI6" cl8s9="s1593s>15=t;TEGRA_PIN_VI_VSYNC_MUX_CMC412M_OUT1PDDpan class="s6codeMUX_CMC412M_OUTaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a9p15n c9a9s="15c_sclCpc4_/a>sc#L3869 id15933>15n6239)
67 href};f">TEGRA_PMUX_CMC432K_IN1PDDpan class="s6codeMUX_CMC432K_INaPEEl"RA_PIN_VI_VSYNC_PD6, 9/915n 6246ef};f">TEGRA_PIN_VI_VSYNMUX_CORE" cl_REQ1PDDpan class="s6codeMUX_CORE" cl_REQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<1p15n c9a9s="15="s6code=_GPI6" cl8s9="s159"s>15p>))
68 href};f">TEGRA_PIN_VI_MUX_CPU" cl_REQ1PDDpan class="s6codeMUX_CPU" cl_REQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<2p15n c9a9s="15="s6code=_GPI6" cl8s9="s1594s>15ns */<8 href};f">TEGRA_PIN_VI_MUX_CRT1PDDpan class="s6codeMUX_CRTaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<3p15n c9a9s="15c_sdaCpc5_/a>sc#L3869 id1594q>15=6243)
67 href};f">TEGRA_PMUX_DAP1PDDpan class="s6codeMUX_DAPaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<4p15n c9a9s="15pan class="s6cring8>9q6"15946>15n>_PIN243)
67 href};f">TEGRA_PMUX_DDRaPEElass="s6="+code=_MUX_DDRaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<5p15n c9a9s="15="s6code=_GPI6" cl8s9="s159"s>15p(1)
68 href};f">TEGRA_PIN_VI_MUX_DEVCaPEEs5code=_GPI5" claMUX_DEVCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<6p15n c9a9s="15="s6c8">"6" cl8s9="s1594e>157_PIN<8 href};f">TEGRA_PIN_VI_MUX_DISPLAYAaPEEs5code=_GPI5" claMUX_DISPLAYAaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<7p15n c9a9s="152_/c6_/a>sc#L306" 8d9"L31594&>15={
59 href};f">TEGRA_PIN_VI_VSMUX_DISPLAYBaPEEs5code=_GPI5" claMUX_DISPLAYBaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<8p15n c9a9s="15s="s6c9">"6" c8a9s="1594s>15=t;TEGRA_PIN_VI_VSYNC_MUX_DTVaPEEs5code=_GPI5" claMUX_DTVaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<9p15n c9a9s="15=_GPI6" class="sre8"9_GP15943>15n6239)
67 href};f">TEGRA_PMUX_EXTPERIPHW1_PRlass="s6="+code=_MUX_EXTPERIPHWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a>,155 c9a9s="15="s6code=_GPI6" cl8s9="s1595c>15n 6246ef};f">TEGRA_PIN_VI_VSYNMUX_EXTPERIPHQaPEElass="s6f9ing">&qMUX_EXTPERIPHQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a1p15n c9a9s="15n_pc7_/a>sc#L306" 8d9"L31595s>15p>))
68 href};f">TEGRA_PIN_VI_MUX_EXTPERIPHCaPEEs5code=_GPI5" claMUX_EXTPERIPHCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a2p15n c9a9s="15s="s6code=_GPI6" c8a9s="1595s>15ns */<8 href};f">TEGRA_PIN_VI_MUX_GMIaPEEs5code=_GPI5" claMUX_GMIaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a3p15n c9a9s="15=_GPI6" class="sre8"9_GP1595q>15=6243)
67 href};f">TEGRA_PMUX_GMI_ALT1PDDpan class="s6codeMUX_GMI_ALTaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a4p15n c9a9s="15="s6code=_GPI6" cl8s9="s15956>15n>_PIN243)
67 href};f">TEGRA_PMUX_HDAaPEEs5code=_GPI5" claMUX_HDAaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a5p15n c9a9s="15dat5_/d0_/a>sc#L308"9id=1595s>15p(1)
68 href};f">TEGRA_PIN_VI_MUX_HDCP1PDDpan class="s6codeMUX_HDCPaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a6p15n c9a9s="15n class="s6code=_G8I9" c1595e>157_PIN<8 href};f">TEGRA_PIN_VI_MUX_sref1PDDpan class="s6codeMUX_HDMIaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a7p15n c9a9s="15s6c8">"6" clas8=9sre1595=>15={
59 href};f">TEGRA_PIN_VI_VSMUX_HSf1PDDpan class="s6codeMUX_HSIaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a8p15n c9a9s="15="s6code=_GPI6" cl8s9="s1595s>15=t;TEGRA_PIN_VI_VSYNC_MUX_I2CW1_PRlass="s6="+code=_MUX_I2CWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a9p15n c9a9s="15dat4_/d1_/a>sc#L308"9id=15953>15n6239)
67 href};f">TEGRA_PMUX_I2CQaPEElass="s6f9ing">&qMUX_I2CQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a>,156 c9a9s="15n class="s6code=_G8I9" c1596c>15n 6246ef};f">TEGRA_PIN_VI_VSYNMUX_I2CCaPEEs5code=_GPI5" claMUX_I2CCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a1p15n c9a9s="15s6code=_GPI6" clas8=9sre1596s>15p>))
68 href};f">TEGRA_PIN_VI_MUX_I2C_1PDDpan class="s6codeMUX_I2C_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a2p15n c9a9s="15="s6code=_GPI6" cl8s9="s159"s>15ns */<8 href};f">TEGRA_PIN_VI_MUX_I2CPWRaPEElass="s6="+code=_MUX_I2CPWRaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a3p15n c9a9s="15_/d2_/a>sc#L306" i8=9L301596q>15=6243)
67 href};f">TEGRA_PMUX_I2SCLPBBlass="s6f" class=MUX_I2SCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a4p15n c9a9s="15"s6code=_GPI6" cla8s9"sr15966>15n>_PIN243)
67 href};f">TEGRA_PMUX_I2SW1_PRlass="s6="+code=_MUX_I2SWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a/p1535c9a9s="15GPI6" class="sref"8_9PIO1596s>15p(1)
68 href};f">TEGRA_PIN_VI_MUX_I2SQaPEElass="s6f9ing">&qMUX_I2SQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a6p15n c9a9s="15="s6c8">"6" cl8s9="s1596e>157_PIN<8 href};f">TEGRA_PIN_VI_MUX_I2SCaPEEs5code=_GPI5" claMUX_I2SCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a7p15n c9a9s="15dat6_/d3_/a>sc#L308"9id=1596=>15={
59 href};f">TEGRA_PIN_VI_VSMUX_I2S_1PDDpan class="s6codeMUX_I2S_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a8p15n c9a9s="15n class="s6c9">&qu8t9" c1596s>15=t;TEGRA_PIN_VI_VSYNC_MUX_INVALID1PDDpan class="s6codeMUX_INVALIDaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a9p15n c9a9s="15s6code=_GPI6" clas8=9sre1596G>15p69 href};f">TEGRA_PIN_VI_VSYNMUX_KBC1PDDpan class="s6codeMUX_KBCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9TEGRA_PIN_VI_VSYNMUX_MIO1PDDpan class="s6codeMUX_MIOaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<1p15n c9a9s="15dat7_/d4_/a>sc#L308"9id=1597s>15p>))
68 href};f">TEGRA_PIN_VI_MUX_NAND1PDDpan class="s6codeMUX_NANDaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<2p15n c9a9s="15n class="s6code=_G8I9" c1597s>15ns */<8 href};f">TEGRA_PIN_VI_MUX_NAND_ALT1PDDpan class="s6codeMUX_NAND_ALTaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<3p15n c9a9s="15s6code=_GPI6" clas8=9sre1596c>14=6243)
67 href};f">TEGRA_PMUX_OWRaPEElass="s6="+code=_MUX_OWRaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<4p15n c9a9s="15="s6code=_GPI6" cl8s9="s15976>15n>_PIN243)
67 href};f">TEGRA_PMUX_PCIEaPEElass="s6="+code=_MUX_PCIEaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9sc#L306" id=8L90vi1597s>15p(1)
68 href};f">TEGRA_PIN_VI_MUX_PWMUT1PAlass="s6f" class=MUX_PWMUaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<6p15n c9a9s="15ode=_GPI6" class="8r9f">1597e>157_PIN<8 href};f">TEGRA_PIN_VI_MUX_PWMW1_PRlass="s6="+code=_MUX_PWMWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<7p15n c9a967 href};f">TEGRA_PIN>))
98 hr 97=>15={
59 href};f">TEGRA_PIN_VI_VSMUX_PWMQaPEElass="s6f9ing">&qMUX_PWMQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<8p15n c9a9s="14="s6">/* All 6on-G8I9 pi1497s>15=t;TEGRA_PIN_VI_VSYNC_MUX_PWMCaPEEs5code=_GPI5" claMUX_PWMCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<9p15n c9a9s="14c_/d6_/a>sc#L306" 8d9"L31497t>15569 href};f">TEGRA_PIN_VI_VSYNMUX_PWR1IN2KN1PDDpan class="s6codeMUX_PWR1IN2KNaPEEl"RA_PIN_VI_VSYNC_PD6, 9/915n 6246ef};f">TEGRA_PIN_VI_VSYNMUX_RSVDW1_PRlass="s6="+code=_MUX_RSVDWaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<1p15n c9a9s="14e=off6et" class="s8e9">o149=o>14s>))
68 href};f">TEGRA_PIN_VI_MUX_RSVDQaPEElass="s6f9ing">&qMUX_RSVDQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<2p15n c9a9s="14="s6ss="comme6t">/8 9on-1498s>15ns */<8 href};f">TEGRA_PIN_VI_MUX_RSVDCaPEEs5code=_GPI5" claMUX_RSVDCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<3p15n c9a9s="14c_/d7_/a>sc#L306" 8d9"L31498c>14=6243)
67 href};f">TEGRA_PMUX_RSVD_1PDDpan class="s6codeMUX_RSVD_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<4p15n c9a9s="14s="s67ode=_GPI6PIN8 9las14986>15n>_PIN243)
67 href};f">TEGRA_PMUX_RTCK1PDDpan class="s6codeMUX_RTCKaPEEl"RA_PIN_VI_VSYNC_PD6, 9/91498s>15p(1)
68 href};f">TEGRA_PIN_VI_MUX_SATAaPEEs5code=_GPI5" claMUX_SATAaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<6p15n c9a9s="14="s6"8ing">&q6PIN"8c9ass1498e>157_PIN<8 href};f">TEGRA_PIN_VI_MUX_SDMMC1aPEEs5code=_GPI5" claMUX_SDMMC1aPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<7p15n c9a9s="14pe0_/a>sc#L306" id8"930l1498=>15={
59 href};f">TEGRA_PIN_VI_VSMUX_SDMMCQaPEElass="s6f9ing">&qMUX_SDMMCQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<8p15n c9a9s="14679ing">&q6PIN" cl8s9="s1498s>15=t;TEGRA_PIN_VI_VSYNC_MUX_SDMMCCaPEEs5code=_GPI5" claMUX_SDMMCCaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9<9p15n c9a9s="14=6PIN" class="sref8>9PIN1498t>15569 href};f">TEGRA_PIN_VI_VSYNMUX_SDMMC_1PDDpan class="s6codeMUX_SDMMC_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a>,149 c9a9s="14="s6f="+code=6PIN"8c9ass1499c>15n 6246ef};f">TEGRA_PIN_VI_VSYNMUX_SPDIF1PDDpan class="s6codeMUX_SPDIFaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a1p15n c9a9s="14/e1_/a>sc#L306" id8"930l1499t>1576231)
66 href};f">TEGRA_PMUX_SPI1aPEEs5code=_GPI5" claMUX_SPI1aPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a2p15n c9a9s="146f="+code=6PIN" cl8s9="s1499s>15ns */<8 href};f">TEGRA_PIN_VI_MUX_SPIQaPEElass="s6f9ing">&qMUX_SPIQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a3p15n c9a9s="14e6PIN" class="sref8>9PIN1499d>1566243)
67 href};f">TEGRA_PMUX_SPIQ_ALT1PDDpan class="s6codeMUX_SPIQ_ALTaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a4p15n c9a9s="14="s6="+code=_6IN" 8l9ss=14996>15n>_PIN243)
67 href};f">TEGRA_PMUX_SPICaPEEs5code=_GPI5" claMUX_SPICaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a/p1535c9a9s="14/e2_/a>sc#L306" id8"930l1499s>15p(1)
68 href};f">TEGRA_PIN_VI_MUX_SPI_1PDDpan class="s6codeMUX_SPI_aPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a6p15n c9a9s="146fode=_GPI6s="line8 9ame1499e>157_PIN<8 href};f">TEGRA_PIN_VI_MUX_SPIQaPCCass="s6c9ing">&q6MUX_SPIQaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a7p15n c9a9s="14q6"sref">tegra30_p8n9146G_32K1SDMMC4_DAT1, 9/9a8p15n c9a9s="14="s7g">"7ART38C9S_N1499s>15=t;TEGRA_PIN_VI_VSYNC_MUX_SYSCLK1PDDpan class="s6codeMUX_SYSCLKaPEEl"RA_PIN_VI_VSYNC_PD6, 9/9a9p15n c9a9s="14/e3_/a>sc#L306" id8"930l1499t>15569 href};f">TEGRA_PIN_VI_VSYNMUX_TEST1PDDpan class="s6codeMUX_TESTaPEEl"RA_PIN_VI_VSYNC_PD6, 920sc#L306" id8202015569 href};f">TEGRA_PIN_VI_VSYNMUX_TRACEaPEElass="s6="+code=_MUX_TRACEaPEEl"R/pre>RA_PIN_VI_VSYNC_PD6, 920<1p15n c920<="14/e1_/a>sc#L306" id820<=">201576231)
66 href};f">TEGRA_PMUX_UARTAaPEEs5code=_GPI5" claMUX_UARTAaPEEl"RA_PIN_VI_VSYNC_PD6, 920<2p15n c920<="146f="+code=6PIN" cl820<=">2015ns */<8 href};f">TEGRA_PIN_VI_MUX_UARTBaPEEs5code=_GPI5" claMUX_UARTBaPEEl"RA_PIN_VI_VSYNC_PD6, 920<3p15n c920<="14e6PIN" class="sref820<=">201566243)
67 href};f">TEGRA_PMUX_UARTC1PDDpan class="s6codeMUX_UARTCaPEEl"RA_PIN_VI_VSYNC_PD6, 920<4p15n c920<="14="s6="+code=_6IN" 820<=">20<6>15n>_PIN243)
67 href};f">TEGRA_PMUX_UARTD1PDDpan class="s6codeMUX_UARTDaPEEl"RA_PIN_VI_VSYNC_PD6, 920<5p15n c920<="14/e2_/a>sc#L306" id820<=">2015p(1)
68 href};f">TEGRA_PIN_VI_MUX_UARTEaPEElass="s6="+code=_MUX_UARTEaPEEl"RA_PIN_VI_VSYNC_PD6, 920<6p15n c920<="146fode=_GPI6s="line820<=">20157_PIN<8 href};f">TEGRA_PIN_VI_MUX_ULPIaPEElass="s6="+code=_MUX_ULPIaPEEl"RA_PIN_VI_VSYNC_PD6, 920<7p15n c920<="14q6"sref">tegra30_p820<=">20<">146G_32K1SDMMC4_DAT1, 920<8p15n c920<="14="s7g">"7ART3820<=">2015=t;TEGRA_PIN_VI_VSYNC_MUX_VGPQaPEElass="s6f9ing">&qMUX_VGPQaPEEl"RA_PIN_VI_VSYNC_PD6, 920<9p15n c920<="14/e3_/a>sc#L306" id820<=">2015569 href};f">TEGRA_PIN_VI_VSYNMUX_VGPCaPEEs5code=_GPI5" claMUX_VGPCaPEEl"RA_PIN_VI_VSYNC_PD6, 9201sp15n c920s="15="s6g">"6DMMC920s=">20s=>15569 href};f">TEGRA_PIN_VI_VSYNMUX_VGP_1PDDpan class="s6codeMUX_VGP_aPEEl"RA_PIN_VI_VSYNC_PD6, 92011p15n c920s="15dat2_/b5_/a>sc#L30920s=">20st>1576231)
66 href};f">TEGRA_PMUX_VGPQaPCCass="s6c9ing">&q6MUX_VGPQaPEEl"RA_PIN_VI_VSYNC_PD6, 92012p15n c920s="15n class="s6g">&quo920s=">20ss>15ns */<8 href};f">TEGRA_PIN_VI_MUX_VGP, 92013p15n c920s="15s6rng">&quo6DMMC3_920s=">20sd>1566243)
67 href};f">TEGRA_PMUX_VIaPEElass="s6="+code=_MUX_VIaPEEl"RA_PIN_VI_VSYNC_PD6, 92014p15n c920s="15="s6gg">"6t;LC920s=">20s6>15n>_PIN243)
67 href};f">TEGRA_PMUX_VI_ALT1aPEEs5code=_GPI5" claMUX_VI_ALT1aPEEl"RA_PIN_VI_VSYNC_PD6, 92015p15n c920s="15dat1_/b6_/a>sc#L30920s=">20ss>15p(1)
68 href};f">TEGRA_PIN_VI_MUX_VI_ALTQaPEElass="s6f9ing">&qMUX_VI_ALTQaPEEl"RA_PIN_VI_VSYNC_PD6, 92016p15n c920s="15n class="s6g7">&qu920s=">20se>157_PIN<8 href};f">TEGRA_PIN_VI_MUX_VI_ALTCaPEEs5code=_GPI5" claMUX_VI_ALTCaPEEl"RA_PIN_VI_VSYNC_PD6, 92017p15n c920s="15] = {f">TEGRA_PIN_V20s=">20s/>15pt;),
70 hrefstatic const unsignedrs/pin820s8p15n c920s="15="s6">"G6N1_I820s=">20s">15pN(4)
68 hchar *4)
68 href};f">TEGRA_Pb&quk_groupIND1_PE"L271" clb&quk_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">20s9p15n c920s="15dat0_/b7_/a>sc#L30820s=">20st>15569 href};spanD1_PE"L27tring">"clk_32k_out_pa0", 9202sp15n c920s="15n class="s6ring">&820s=">20s=>15pt;),
70 hrefstatic const unsignedrs/pin82021p15n c920s="15s6ring">&qu6t;GMI_820s=">20s1aPEE),
70 hrefstatic const unsignedrs/pin82022p15n c920s="15="s6r">"6DMMC820s=">20s2>15pN(4)
68 hchar *4)
68 href};f">TEGRA_Pcec_groupIND1_PE"L271" clcec_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2023p15n c920s="15ts_n_pc0_/a>sc#L30820s=">20s3>15569 href};spanD1_PE"L27tring">"hdmi_cec_pee3", 92024p15n c920s="15n class="s6rg">&qu820s=">20s4>15569 href};spanD1_PE"L27tring">"owr", 92025p15n c920s="15s6rg">"6DMMC3_820s=">20s2>15nt;),
70 hrefstatic const unsignedrs/pin820s6p15n c920s="15="s6"8">"6quot820s=">20se>157),
70 hrefstatic const unsignedrs/pin820s7p15n c920s="151_/c1_/a>sc#L306" 820s=">20s=>15=a(4)
68 hchar *4)
68 href};f">TEGRA_Pclk_12m_out_groupIND1_PE"L271" clclk_12m_out_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2028p15n c920s="15s="s6r9">"6t;V820s=">20s8>15569 href};spanD1_PE"L27tring">"pv3", 92029p15n c920s="15">&qu6t;VI_HSYNC P820s=">20s9>15nt;),
70 hrefstatic const unsignedrs/pin8203sp15n c920s="15="s6ring">&qu6" cl820s=">20s=>157),
70 hrefstatic const unsignedrs/pin82031p15n c920s="15xdCpc2_/a>sc#L306"820s=">20s1>15=a(4)
68 hchar *4)
68 href};f">TEGRA_Pclk_32k_in_groupIND1_PE"L271" clclk_32k_in_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2032p15n c920s="15ass="s6r">"6"820s=">20s2>15569 href};spanD1_PE"L27tring">"clk_32k_in", 92033p15n c920s="15>"6" class="s820s=">20sP>14=t;),
70 hrefstatic const unsignedrs/pin820s4p15n c920s="15="s6code=_GPI6" cl820s=">20ss>14=),
70 hrefstatic const unsignedrs/pin820s5p15n c920s="15xdCpc3_/a>sc#L306"820s=">20s2>14=a(4)
68 hchar *4)
68 href};f">TEGRA_Pcore_pwr_req_groupIND1_PE"L271" clcore_pwr_req_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2036p15n c920s="15ass="s6rng">&quo6"820s=">20s6>15569 href};spanD1_PE"L27tring">"core_pwr_req", 92037p15n c920s="15">"6" class="s820s=">20s/>15pt;),
70 hrefstatic const unsignedrs/pin82038p15n c920s="15="s6code=_GPI6" cl820s=">20s">15p),
70 hrefstatic const unsignedrs/pin820s9p15n c920s="15c_sclCpc4_/a>sc#L3820s=">20sG>15pa(4)
68 hchar *4)
68 href};f">TEGRA_Pcpu_pwr_req_groupIND1_PE"L271" clcpu_pwr_req_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">204sp15n c920s="15pan class="s6code=820s=">20s=>15569 href};spanD1_PE"L27tring">"cpu_pwr_req", 92041p15n c920s="15="s6code=_GPI6" cl820s=">20ss>15pt;),
70 hrefstatic const unsignedrs/pin820s2p15n c920s="15="s6code=_GPI6" cl820s=">20ss>15p),
70 hrefstatic const unsignedrs/pin820s3p15n c920s="15c_sdaCpc5_/a>sc#L3820s=">20ss>15pa(4)
68 hchar *4)
68 href};f">TEGRA_Pcrt_groupIND1_PE"L271" clcrt_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2044p15n c920s="15pan class="s6cring820s=">20s4>15569 href};spanD1_PE"L27tring">"crt_hsync_pv6", 92045p15n c920s="15="s6code=_GPI6" cl820s=">20s5>15569 href};spanD1_PE"L27tring">"crt_vsync_pv7", 92046p15n c920s="15="s6c8">"6" cl820s=">20ss>15p_PIN(3)
68 hrefstatic const unsignedrs/pin820s7p15n c920s="152_/c6_/a>sc#L306" 820s=">20s/>15p0_/a>shref[] = {f">TEGRA_PIN_VI_VSYNC_PD6"6" c820s=">20s">15pN(4)
68 hchar *4)
68 href};f">TEGRA_Pdap_groupIND1_PE"L271" cldap_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2049p15n c920s="15=_GPI6" class="sre820s=">20st>15569 href};spanD1_PE"L27tring">"clk1_req_pee2", 9205sp15n c920s="15="s6code=_GPI6" cl820s=">20s=>15569 href};spanD1_PE"L27tring">"clk2_req_pcc5", 92051p15n c920s="15n_pc7_/a>sc#L306" 820s=">20ss>15pt;),
70 hrefstatic const unsignedrs/pin82052p15n c920s="15s="s6code=_GPI6" c820s=">20ss>15p),
70 hrefstatic const unsignedrs/pin82053p15n c920s="15=_GPI6" class="sre820s=">20ss>15pa(4)
68 hchar *4)
68 href};f">TEGRA_Pddr_groupIND1_PE"L271" clddr_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2054p15n c920s="15="s6code=_GPI6" cl820s=">20s4>15569 href};spanD1_PE"L27tring">"vi_d0_pt4", 92055p15n c920s="15dat5_/d0_/a>sc#L30820s=">20s5>15569 href};spanD1_PE"L27tring">"vi_d1_pd5", 92056p15n c920s="15n class="s6code=_G820s=">20s6>15569 href};spanD1_PE"L27tring">"vi_d10_pt2", 92057p15n c920s="15s6c8">"6" clas820s=">20s7>15569 href};spanD1_PE"L27tring">"vi_d11_pt3", 92058p15n c920s="15="s6code=_GPI6" cl820s=">20s8>15569 href};spanD1_PE"L27tring">"vi_d2_pl0", 92059p15n c920s="15dat4_/d1_/a>sc#L30820s=">20st>15569 href};spanD1_PE"L27tring">"vi_d3_pl1", 9206sp15n c920s="15n class="s6code=_G820s=">20s=>15569 href};spanD1_PE"L27tring">"vi_d4_pl2", 92061p15n c920s="15s6code=_GPI6" clas820s=">20s1>15569 href};spanD1_PE"L27tring">"vi_d5_pl3", 92062p15n c920s="15="s6code=_GPI6" cl820s=">20s2>15569 href};spanD1_PE"L27tring">"vi_d6_pl4", 92063p15n c920s="15_/d2_/a>sc#L306" i820s=">20s3>15569 href};spanD1_PE"L27tring">"vi_d7_pl5", 92064p15n c920s="15"s6code=_GPI6" cla820s=">20s4>15569 href};spanD1_PE"L27tring">"vi_d8_pl6", 92065p15n c920s="15GPI6" class="sref"820s=">20s5>15569 href};spanD1_PE"L27tring">"vi_d9_pl7", 92066p15n c920s="15="s6c8">"6" cl820s=">20s6>15569 href};spanD1_PE"L27tring">"vi_hsync_pd7", 92067p15n c920s="15dat6_/d3_/a>sc#L30820s=">20s7>15569 href};spanD1_PE"L27tring">"vi_vsync_pd6", 92068p15n c920s="15n class="s6c9">&qu820s=">20sc>156t;),
70 hrefstatic const unsignedrs/pin820s9p15n c920s="15s6code=_GPI6" clas820s=">20sc>1563_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6TEGRA_Pdev3_groupIND1_PE"L271" cldev3_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2071p15n c920s="15dat7_/d4_/a>sc#L30820s=">20s1>15569 href};spanD1_PE"L27tring">"clk3_req_pee1", 92072p15n c920s="15n class="s6code=_G820s=">20s2>156t;),
70 hrefstatic const unsignedrs/pin82073p15n c920s="15s6code=_GPI6" clas820s=">20s3>1563_/a>scref[] = {f">TEGRA_PIN_VI_VSYNC_PD6TEGRA_Pdisplaya_groupIND1_PE"L271" cldisplaya_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2075p15n c920s="15d5_/a>sc#L306" id=820s=">20s5>15569 href};spanD1_PE"L27tring">"dap3_din_pp1", 92076p15n c920s="15ode=_GPI6" class="820s=">20s6>15569 href};spanD1_PE"L27tring">"dap3_dout_pp2", 92077p15n c92067 href};f">TEGRA_PIN>))2067 >20s7>15569 href};spanD1_PE"L27tring">"dap3_fs_pp0", 92078p15n c920s="14="s6">/* All 6on-G820s=">20s8>15569 href};spanD1_PE"L27tring">"dap3_sclk_pp3", 92079p15n c920s="14c_/d6_/a>sc#L306" 820s=">20st>15569 href};spanD1_PE"L27tring">"pbb3", 9208sp15n c920s="14s="s67" class=6sre820s=">20s=>15569 href};spanD1_PE"L27tring">"pbb4", 92081p15n c920s="14e=off6et" class="s820s=">20s1>15569 href};spanD1_PE"L27tring">"pbb5", 92082p15n c920s="14="s6ss="comme6t">/820s=">20s2>15569 href};spanD1_PE"L27tring">"pbb6", 92083p15n c920s="14c_/d7_/a>sc#L306" 820s=">20s3>15569 href};spanD1_PE"L27tring">"lcd_cs0_n_pn4", 92084p15n c920s="14s="s67ode=_GPI6PIN820s=">20s4>15569 href};spanD1_PE"L27tring">"lcd_cs1_n_pw0", 92085p15n c920s="14=_GPI6PIN" class="820s=">20s5>15569 href};spanD1_PE"L27tring">"lcd_d0_pe0", 92086p15n c920s="14="s6"8ing">&q6PIN"820s=">20s6>15569 href};spanD1_PE"L27tring">"lcd_d1_pe1", 92087p15n c920s="14pe0_/a>sc#L306" id820s=">20s7>15569 href};spanD1_PE"L27tring">"lcd_d10_pf2", 92088p15n c920s="14679ing">&q6PIN" cl820s=">20s8>15569 href};spanD1_PE"L27tring">"lcd_d11_pf3", 92089p15n c920s="14=6PIN" class="sref820s=">20st>15569 href};spanD1_PE"L27tring">"lcd_d12_pf4", 9209sp15n c920s="14="s6f="+code=6PIN"820s=">20s=>15569 href};spanD1_PE"L27tring">"lcd_d13_pf5", 92091p15n c920s="14/e1_/a>sc#L306" id820s=">20s1>15569 href};spanD1_PE"L27tring">"lcd_d14_pf6", 92092p15n c920s="146f="+code=6PIN" cl820s=">20s2>15569 href};spanD1_PE"L27tring">"lcd_d15_pf7", 92093p15n c920s="14e6PIN" class="sref820s=">20s3>15569 href};spanD1_PE"L27tring">"lcd_d16_pm0", 92094p15n c920s="14="s6="+code=_6IN" 820s=">20s4>15569 href};spanD1_PE"L27tring">"lcd_d17_pm1", 92095p15n c920s="14/e2_/a>sc#L306" id820s=">20s5>15569 href};spanD1_PE"L27tring">"lcd_d18_pm2", 92096p15n c920s="146fode=_GPI6s="line820s=">20s6>15569 href};spanD1_PE"L27tring">"lcd_d19_pm3", 92097p15n c920s="14q6"sref">tegra30_p820s=">20s7>15569 href};spanD1_PE"L27tring">"lcd_d2_pe2", 92098p15n c920s="14="s7g">"7ART3820s=">20s8>15569 href};spanD1_PE"L27tring">"lcd_d20_pm4", 92099p15n c920s="14/e3_/a>sc#L306" id820s=">20st>15569 href};spanD1_PE"L27tring">"lcd_d21_pm5", 921sc#L306" id821210=>15569 href};spanD1_PE"L27tring">"lcd_d22_pm6", 921<1p15n c921<="14/e1_/a>sc#L306" id821<=">2101>15569 href};spanD1_PE"L27tring">"lcd_d23_pm7", 921<2p15n c921<="146f="+code=6PIN" cl821<=">2102>15569 href};spanD1_PE"L27tring">"lcd_d3_pe3", 921<3p15n c921<="14e6PIN" class="sref821<=">2103>15569 href};spanD1_PE"L27tring">"lcd_d4_pe4", 921<4p15n c921<="14="s6="+code=_6IN" 821<=">2104>15569 href};spanD1_PE"L27tring">"lcd_d5_pe5", 921<5p15n c921<="14/e2_/a>sc#L306" id821<=">2105>15569 href};spanD1_PE"L27tring">"lcd_d6_pe6", 921<6p15n c921<="146fode=_GPI6s="line821<=">2106>15569 href};spanD1_PE"L27tring">"lcd_d7_pe7", 921<7p15n c921<="14q6"sref">tegra30_p821<=">2107>15569 href};spanD1_PE"L27tring">"lcd_d8_pf0", 921<8p15n c921<="14="s7g">"7ART3821<=">2108>15569 href};spanD1_PE"L27tring">"lcd_d9_pf1", 921<9p15n c921<="14/e3_/a>sc#L306" id821<=">210t>15569 href};spanD1_PE"L27tring">"lcd_dc0_pn6", 9211sp15n c921s="15="s6g">"6DMMC921s=">211=>15569 href};spanD1_PE"L27tring">"lcd_dc1_pd2", 92111p15n c921s="15dat2_/b5_/a>sc#L30921s=">2111>15569 href};spanD1_PE"L27tring">"lcd_de_pj1", 92112p15n c921s="15n class="s6g">&quo921s=">2112>15569 href};spanD1_PE"L27tring">"lcd_hsync_pj3", 92113p15n c921s="15s6rng">&quo6DMMC3_921s=">2113>15569 href};spanD1_PE"L27tring">"lcd_m1_pw1", 92114p15n c921s="15="s6gg">"6t;LC921s=">2114>15569 href};spanD1_PE"L27tring">"lcd_pclk_pb3", 92115p15n c921s="15dat1_/b6_/a>sc#L30921s=">2115>15569 href};spanD1_PE"L27tring">"lcd_pwr0_pb2", 92116p15n c921s="15n class="s6g7">&qu921s=">2116>15569 href};spanD1_PE"L27tring">"lcd_pwr1_pc1", 92117p15n c921s="15] = {f">TEGRA_PIN_V21s=">2117>15569 href};spanD1_PE"L27tring">"lcd_pwr2_pc6", 92118p15n c921s="15="s6">"G6N1_I821s=">2118>15569 href};spanD1_PE"L27tring">"lcd_sck_pz4", 921s9p15n c921s="15dat0_/b7_/a>sc#L30821s=">21st>15569 href};spanD1_PE"L27tring">"lcd_sdin_pz2", 9212sp15n c921s="15n class="s6ring">&821s=">212=>15569 href};spanD1_PE"L27tring">"lcd_sdout_pn5", 92121p15n c921s="15s6ring">&qu6t;GMI_821s=">2121>15569 href};spanD1_PE"L27tring">"lcd_vsync_pj4", 92122p15n c921s="15="s6r">"6DMMC821s=">2122>15569 href};spanD1_PE"L27tring">"lcd_wr_n_pz3", 92123p15n c921s="15ts_n_pc0_/a>sc#L30821s=">212P>14=t;),
70 hrefstatic const unsignedrs/pin82124p15n c921s="15n class="s6rg">&qu821s=">212s>14=),
70 hrefstatic const unsignedrs/pin82125p15n c921s="15s6rg">"6DMMC3_821s=">2122>14=a(4)
68 hchar *4)
68 href};f">TEGRA_Pdisplayb_groupIND1_PE"L271" cldisplayb_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">21s6p15n c921s="15="s6"8">"6quot821s=">2126>15569 href};spanD1_PE"L27tring">"dap3_din_pp1", 921s7p15n c921s="151_/c1_/a>sc#L306" 821s=">2127>15569 href};spanD1_PE"L27tring">"dap3_dout_pp2", 92128p15n c921s="15s="s6r9">"6t;V821s=">21s8>15569 href};spanD1_PE"L27tring">"dap3_fs_pp0", 92129p15n c921s="15">&qu6t;VI_HSYNC P821s=">212t>15569 href};spanD1_PE"L27tring">"dap3_sclk_pp3", 9213sp15n c921s="15="s6ring">&qu6" cl821s=">213=>15569 href};spanD1_PE"L27tring">"pbb3", 92131p15n c921s="15xdCpc2_/a>sc#L306"821s=">2131>15569 href};spanD1_PE"L27tring">"pbb4", 92132p15n c921s="15ass="s6r">"6"821s=">21s2>15569 href};spanD1_PE"L27tring">"pbb5", 92133p15n c921s="15>"6" class="s821s=">2133>15569 href};spanD1_PE"L27tring">"pbb6", 921s4p15n c921s="15="s6code=_GPI6" cl821s=">2134>15569 href};spanD1_PE"L27tring">"lcd_cs0_n_pn4", 921s5p15n c921s="15xdCpc3_/a>sc#L306"821s=">2135>15569 href};spanD1_PE"L27tring">"lcd_cs1_n_pw0", 92136p15n c921s="15ass="s6rng">&quo6"821s=">21s6>15569 href};spanD1_PE"L27tring">"lcd_d0_pe0", 92137p15n c921s="15">"6" class="s821s=">2137>15569 href};spanD1_PE"L27tring">"lcd_d1_pe1", 92138p15n c921s="15="s6code=_GPI6" cl821s=">2138>15569 href};spanD1_PE"L27tring">"lcd_d10_pf2", 921s9p15n c921s="15c_sclCpc4_/a>sc#L3821s=">213t>15569 href};spanD1_PE"L27tring">"lcd_d11_pf3", 9214sp15n c921s="15pan class="s6code=821s=">21s=>15569 href};spanD1_PE"L27tring">"lcd_d12_pf4", 92141p15n c921s="15="s6code=_GPI6" cl821s=">2141>15569 href};spanD1_PE"L27tring">"lcd_d13_pf5", 921s2p15n c921s="15="s6code=_GPI6" cl821s=">2142>15569 href};spanD1_PE"L27tring">"lcd_d14_pf6", 921s3p15n c921s="15c_sdaCpc5_/a>sc#L3821s=">2143>15569 href};spanD1_PE"L27tring">"lcd_d15_pf7", 92144p15n c921s="15pan class="s6cring821s=">21s4>15569 href};spanD1_PE"L27tring">"lcd_d16_pm0", 92145p15n c921s="15="s6code=_GPI6" cl821s=">21s5>15569 href};spanD1_PE"L27tring">"lcd_d17_pm1", 92146p15n c921s="15="s6c8">"6" cl821s=">2146>15569 href};spanD1_PE"L27tring">"lcd_d18_pm2", 921s7p15n c921s="152_/c6_/a>sc#L306" 821s=">2147>15569 href};spanD1_PE"L27tring">"lcd_d19_pm3", 921s8p15n c921s="15s="s6c9">"6" c821s=">2148>15569 href};spanD1_PE"L27tring">"lcd_d2_pe2", 92149p15n c921s="15=_GPI6" class="sre821s=">21st>15569 href};spanD1_PE"L27tring">"lcd_d20_pm4", 9215sp15n c921s="15="s6code=_GPI6" cl821s=">21s=>15569 href};spanD1_PE"L27tring">"lcd_d21_pm5", 92151p15n c921s="15n_pc7_/a>sc#L306" 821s=">2151>15569 href};spanD1_PE"L27tring">"lcd_d22_pm6", 92152p15n c921s="15s="s6code=_GPI6" c821s=">2152>15569 href};spanD1_PE"L27tring">"lcd_d23_pm7", 92153p15n c921s="15=_GPI6" class="sre821s=">2153>15569 href};spanD1_PE"L27tring">"lcd_d3_pe3", 92154p15n c921s="15="s6code=_GPI6" cl821s=">21s4>15569 href};spanD1_PE"L27tring">"lcd_d4_pe4", 92155p15n c921s="15dat5_/d0_/a>sc#L30821s=">21s5>15569 href};spanD1_PE"L27tring">"lcd_d5_pe5", 92156p15n c921s="15n class="s6code=_G821s=">21s6>15569 href};spanD1_PE"L27tring">"lcd_d6_pe6", 92157p15n c921s="15s6c8">"6" clas821s=">21s7>15569 href};spanD1_PE"L27tring">"lcd_d7_pe7", 92158p15n c921s="15="s6code=_GPI6" cl821s=">21s8>15569 href};spanD1_PE"L27tring">"lcd_d8_pf0", 92159p15n c921s="15dat4_/d1_/a>sc#L30821s=">21st>15569 href};spanD1_PE"L27tring">"lcd_d9_pf1", 9216sp15n c921s="15n class="s6code=_G821s=">21s=>15569 href};spanD1_PE"L27tring">"lcd_dc0_pn6", 92161p15n c921s="15s6code=_GPI6" clas821s=">21s1>15569 href};spanD1_PE"L27tring">"lcd_dc1_pd2", 92162p15n c921s="15="s6code=_GPI6" cl821s=">21s2>15569 href};spanD1_PE"L27tring">"lcd_de_pj1", 92163p15n c921s="15_/d2_/a>sc#L306" i821s=">21s3>15569 href};spanD1_PE"L27tring">"lcd_hsync_pj3", 92164p15n c921s="15"s6code=_GPI6" cla821s=">21s4>15569 href};spanD1_PE"L27tring">"lcd_m1_pw1", 92165p15n c921s="15GPI6" class="sref"821s=">21s5>15569 href};spanD1_PE"L27tring">"lcd_pclk_pb3", 92166p15n c921s="15="s6c8">"6" cl821s=">21s6>15569 href};spanD1_PE"L27tring">"lcd_pwr0_pb2", 92167p15n c921s="15dat6_/d3_/a>sc#L30821s=">21s7>15569 href};spanD1_PE"L27tring">"lcd_pwr1_pc1", 92168p15n c921s="15n class="s6c9">&qu821s=">2168>15569 href};spanD1_PE"L27tring">"lcd_pwr2_pc6", 921s9p15n c921s="15s6code=_GPI6" clas821s=">216t>15569 href};spanD1_PE"L27tring">"lcd_sck_pz4", 9217sp15n c921s="15="s6code=_GPI6" cl821s=">217=>15569 href};spanD1_PE"L27tring">"lcd_sdin_pz2", 92171p15n c921s="15dat7_/d4_/a>sc#L30821s=">21s1>15569 href};spanD1_PE"L27tring">"lcd_sdout_pn5", 92172p15n c921s="15n class="s6code=_G821s=">2172>15569 href};spanD1_PE"L27tring">"lcd_vsync_pj4", 92173p15n c921s="15s6code=_GPI6" clas821s=">2173>15569 href};spanD1_PE"L27tring">"lcd_wr_n_pz3", 92174p15n c921s="15="s6code=_GPI6" cl821s=">21s4>15pt;),
70 hrefstatic const unsignedrs/pin82175p15n c921s="15d5_/a>sc#L306" id=821s=">21s5>155),
70 hrefstatic const unsignedrs/pin82176p15n c921s="15ode=_GPI6" class="821s=">21s6>155a(4)
68 hchar *4)
68 href};f">TEGRA_Pdtv_groupIND1_PE"L271" cldtv_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2177p15n c92167 href};f">TEGRA_PIN>))2167 >21s7>15569 href};spanD1_PE"L27tring">"gmi_a17_pb0", 92178p15n c921s="14="s6">/* All 6on-G821s=">21s8>15569 href};spanD1_PE"L27tring">"gmi_a18_pb1", 92179p15n c921s="14c_/d6_/a>sc#L306" 821s=">21st>15569 href};spanD1_PE"L27tring">"gmi_cs0_n_pj0", 9218sp15n c921s="14s="s67" class=6sre821s=">21s=>15569 href};spanD1_PE"L27tring">"gmi_cs1_n_pj2", 92181p15n c921s="14e=off6et" class="s821s=">218s>15pt;),
70 hrefstatic const unsignedrs/pin82182p15n c921s="14="s6ss="comme6t">/821s=">218s>15p),
70 hrefstatic const unsignedrs/pin82183p15n c921s="14c_/d7_/a>sc#L306" 821s=">218s>15pa(4)
68 hchar *4)
68 href};f">TEGRA_Pextperiph1_groupIND1_PE"L271" clextperiph1_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2184p15n c921s="14s="s67ode=_GPI6PIN821s=">21s4>15569 href};spanD1_PE"L27tring">"clk1_out_pw4", 92185p15n c921s="14=_GPI6PIN" class="821s=">2182>15nt;),
70 hrefstatic const unsignedrs/pin82186p15n c921s="14="s6"8ing">&q6PIN"821s=">218e>157),
70 hrefstatic const unsignedrs/pin82187p15n c921s="14pe0_/a>sc#L306" id821s=">218=>15=a(4)
68 hchar *4)
68 href};f">TEGRA_Pextperiph2_groupIND1_PE"L271" clextperiph2_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2188p15n c921s="14679ing">&q6PIN" cl821s=">21s8>15569 href};spanD1_PE"L27tring">"clk2_out_pw5", 92189p15n c921s="14=6PIN" class="sref821s=">2189>15nt;),
70 hrefstatic const unsignedrs/pin8219sp15n c921s="14="s6f="+code=6PIN"821s=">219=>157),
70 hrefstatic const unsignedrs/pin82191p15n c921s="14/e1_/a>sc#L306" id821s=">2191>15=a(4)
68 hchar *4)
68 href};f">TEGRA_Pextperiph3_groupIND1_PE"L271" clextperiph3_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2192p15n c921s="146f="+code=6PIN" cl821s=">21s2>15569 href};spanD1_PE"L27tring">"clk3_out_pee0", 92193p15n c921s="14e6PIN" class="sref821s=">219P>14=t;),
70 hrefstatic const unsignedrs/pin82194p15n c921s="14="s6="+code=_6IN" 821s=">219s>14=),
70 hrefstatic const unsignedrs/pin82195p15n c921s="14/e2_/a>sc#L306" id821s=">2192>14=a(4)
68 hchar *4)
68 href};f">TEGRA_Pgmi_groupIND1_PE"L271" clgmi_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2196p15n c921s="146fode=_GPI6s="line821s=">21s6>15569 href};spanD1_PE"L27tring">"dap1_din_pn1", 92197p15n c921s="14q6"sref">tegra30_p821s=">21s7>15569 href};spanD1_PE"L27tring">"dap1_dout_pn2", 92198p15n c921s="14="s7g">"7ART3821s=">21s8>15569 href};spanD1_PE"L27tring">"dap1_fs_pn0", 92199p15n c921s="14/e3_/a>sc#L306" id821s=">21st>15569 href};spanD1_PE"L27tring">"dap1_sclk_pn3", 922sc#L306" id822220=>15569 href};spanD1_PE"L27tring">"dap2_din_pa4", 922<1p15n c922<="14/e1_/a>sc#L306" id822<=">2201>15569 href};spanD1_PE"L27tring">"dap2_dout_pa5", 922<2p15n c922<="146f="+code=6PIN" cl822<=">2202>15569 href};spanD1_PE"L27tring">"dap2_fs_pa2", 922<3p15n c922<="14e6PIN" class="sref822<=">2203>15569 href};spanD1_PE"L27tring">"dap2_sclk_pa3", 922<4p15n c922<="14="s6="+code=_6IN" 822<=">2204>15569 href};spanD1_PE"L27tring">"dap4_din_pp5", 922<5p15n c922<="14/e2_/a>sc#L306" id822<=">2205>15569 href};spanD1_PE"L27tring">"dap4_dout_pp6", 922<6p15n c922<="146fode=_GPI6s="line822<=">2206>15569 href};spanD1_PE"L27tring">"dap4_fs_pp4", 922<7p15n c922<="14q6"sref">tegra30_p822<=">2207>15569 href};spanD1_PE"L27tring">"dap4_sclk_pp7", 922<8p15n c922<="14="s7g">"7ART3822<=">2208>15569 href};spanD1_PE"L27tring">"gen2_i2c_scl_pt5", 922<9p15n c922<="14/e3_/a>sc#L306" id822<=">220t>15569 href};spanD1_PE"L27tring">"gen2_i2c_sda_pt6", 9221sp15n c922s="15="s6g">"6DMMC922s=">221=>15569 href};spanD1_PE"L27tring">"gmi_a16_pj7", 92211p15n c922s="15dat2_/b5_/a>sc#L30922s=">2211>15569 href};spanD1_PE"L27tring">"gmi_a17_pb0", 92212p15n c922s="15n class="s6g">&quo922s=">2212>15569 href};spanD1_PE"L27tring">"gmi_a18_pb1", 92213p15n c922s="15s6rng">&quo6DMMC3_922s=">2213>15569 href};spanD1_PE"L27tring">"gmi_a19_pk7", 92214p15n c922s="15="s6gg">"6t;LC922s=">2214>15569 href};spanD1_PE"L27tring">"gmi_ad0_pg0", 92215p15n c922s="15dat1_/b6_/a>sc#L30922s=">2215>15569 href};spanD1_PE"L27tring">"gmi_ad1_pg1", 92216p15n c922s="15n class="s6g7">&qu922s=">2216>15569 href};spanD1_PE"L27tring">"gmi_ad10_ph2", 92217p15n c922s="15] = {f">TEGRA_PIN_V22s=">2217>15569 href};spanD1_PE"L27tring">"gmi_ad11_ph3", 92218p15n c922s="15="s6">"G6N1_I822s=">2218>15569 href};spanD1_PE"L27tring">"gmi_ad12_ph4", 922s9p15n c922s="15dat0_/b7_/a>sc#L30822s=">22st>15569 href};spanD1_PE"L27tring">"gmi_ad13_ph5", 9222sp15n c922s="15n class="s6ring">&822s=">222=>15569 href};spanD1_PE"L27tring">"gmi_ad14_ph6", 92221p15n c922s="15s6ring">&qu6t;GMI_822s=">2221>15569 href};spanD1_PE"L27tring">"gmi_ad15_ph7", 92222p15n c922s="15="s6r">"6DMMC822s=">2222>15569 href};spanD1_PE"L27tring">"gmi_ad2_pg2", 92223p15n c922s="15ts_n_pc0_/a>sc#L30822s=">22s3>15569 href};spanD1_PE"L27tring">"gmi_ad3_pg3", 92224p15n c922s="15n class="s6rg">&qu822s=">22s4>15569 href};spanD1_PE"L27tring">"gmi_ad4_pg4", 92225p15n c922s="15s6rg">"6DMMC3_822s=">2225>15569 href};spanD1_PE"L27tring">"gmi_ad5_pg5", 92226p15n c922s="15="s6"8">"6quot822s=">2226>15569 href};spanD1_PE"L27tring">"gmi_ad6_pg6", 92227p15n c922s="151_/c1_/a>sc#L306" 822s=">2227>15569 href};spanD1_PE"L27tring">"gmi_ad7_pg7", 92228p15n c922s="15s="s6r9">"6t;V822s=">22s8>15569 href};spanD1_PE"L27tring">"gmi_ad8_ph0", 92229p15n c922s="15">&qu6t;VI_HSYNC P822s=">222t>15569 href};spanD1_PE"L27tring">"gmi_ad9_ph1", 9223sp15n c922s="15="s6ring">&qu6" cl822s=">223=>15569 href};spanD1_PE"L27tring">"gmi_adv_n_pk0", 92231p15n c922s="15xdCpc2_/a>sc#L306"822s=">2231>15569 href};spanD1_PE"L27tring">"gmi_clk_pk1", 92232p15n c922s="15ass="s6r">"6"822s=">22s2>15569 href};spanD1_PE"L27tring">"gmi_cs0_n_pj0", 92233p15n c922s="15>"6" class="s822s=">2233>15569 href};spanD1_PE"L27tring">"gmi_cs1_n_pj2", 922s4p15n c922s="15="s6code=_GPI6" cl822s=">2234>15569 href};spanD1_PE"L27tring">"gmi_cs2_n_pk3", 922s5p15n c922s="15xdCpc3_/a>sc#L306"822s=">2235>15569 href};spanD1_PE"L27tring">"gmi_cs3_n_pk4", 92236p15n c922s="15ass="s6rng">&quo6"822s=">22s6>15569 href};spanD1_PE"L27tring">"gmi_cs4_n_pk2", 922s7p15n c922s="15">"6" class="s822s=">2237>15569 href};spanD1_PE"L27tring">"gmi_cs6_n_pi3", 922s8p15n c922s="15="s6code=_GPI6" cl822s=">2238>15569 href};spanD1_PE"L27tring">"gmi_cs7_n_pi6", 922s9p15n c922s="15c_sclCpc4_/a>sc#L3822s=">223t>15569 href};spanD1_PE"L27tring">"gmi_dqs_pi2", 9224sp15n c922s="15pan class="s6code=822s=">22s=>15569 href};spanD1_PE"L27tring">"gmi_iordy_pi5", 92241p15n c922s="15="s6code=_GPI6" cl822s=">2241>15569 href};spanD1_PE"L27tring">"gmi_oe_n_pi1", 922s2p15n c922s="15="s6code=_GPI6" cl822s=">2242>15569 href};spanD1_PE"L27tring">"gmi_rst_n_pi4", 922s3p15n c922s="15c_sdaCpc5_/a>sc#L3822s=">2243>15569 href};spanD1_PE"L27tring">"gmi_wait_pi7", 92244p15n c922s="15pan class="s6cring822s=">22s4>15569 href};spanD1_PE"L27tring">"gmi_wp_n_pc7", 92245p15n c922s="15="s6code=_GPI6" cl822s=">22s5>15569 href};spanD1_PE"L27tring">"gmi_wr_n_pi0", 92246p15n c922s="15="s6c8">"6" cl822s=">2246>15569 href};spanD1_PE"L27tring">"pu0", 92247p15n c922s="152_/c6_/a>sc#L306" 822s=">2247>15569 href};spanD1_PE"L27tring">"pu1", 922s8p15n c922s="15s="s6c9">"6" c822s=">2248>15569 href};spanD1_PE"L27tring">"pu2", 92249p15n c922s="15=_GPI6" class="sre822s=">22st>15569 href};spanD1_PE"L27tring">"pu3", 9225sp15n c922s="15="s6code=_GPI6" cl822s=">22s=>15569 href};spanD1_PE"L27tring">"pu4", 92251p15n c922s="15n_pc7_/a>sc#L306" 822s=">2251>15569 href};spanD1_PE"L27tring">"pu5", 92252p15n c922s="15s="s6code=_GPI6" c822s=">2252>15569 href};spanD1_PE"L27tring">"pu6", 92253p15n c922s="15=_GPI6" class="sre822s=">2253>15569 href};spanD1_PE"L27tring">"sdmmc4_clk_pcc4", 92254p15n c922s="15="s6code=_GPI6" cl822s=">22s4>15569 href};spanD1_PE"L27tring">"sdmmc4_cmd_pt7", 92255p15n c922s="15dat5_/d0_/a>sc#L30822s=">22s5>15569 href};spanD1_PE"L27tring">"sdmmc4_dat0_paa0", 92256p15n c922s="15n class="s6code=_G822s=">22s6>15569 href};spanD1_PE"L27tring">"sdmmc4_dat1_paa1", 92257p15n c922s="15s6c8">"6" clas822s=">22s7>15569 href};spanD1_PE"L27tring">"sdmmc4_dat2_paa2", 92258p15n c922s="15="s6code=_GPI6" cl822s=">22s8>15569 href};spanD1_PE"L27tring">"sdmmc4_dat3_paa3", 92259p15n c922s="15dat4_/d1_/a>sc#L30822s=">22st>15569 href};spanD1_PE"L27tring">"sdmmc4_dat4_paa4", 9226sp15n c922s="15n class="s6code=_G822s=">22s=>15569 href};spanD1_PE"L27tring">"sdmmc4_dat5_paa5", 92261p15n c922s="15s6code=_GPI6" clas822s=">22s1>15569 href};spanD1_PE"L27tring">"sdmmc4_dat6_paa6", 92262p15n c922s="15="s6code=_GPI6" cl822s=">22s2>15569 href};spanD1_PE"L27tring">"sdmmc4_dat7_paa7", 92263p15n c922s="15_/d2_/a>sc#L306" i822s=">22s3>15569 href};spanD1_PE"L27tring">"spi1_cs0_n_px6", 92264p15n c922s="15"s6code=_GPI6" cla822s=">22s4>15569 href};spanD1_PE"L27tring">"spi1_mosi_px4", 92265p15n c922s="15GPI6" class="sref"822s=">22s5>15569 href};spanD1_PE"L27tring">"spi1_sck_px5", 92266p15n c922s="15="s6c8">"6" cl822s=">22s6>15569 href};spanD1_PE"L27tring">"spi2_cs0_n_px3", 92267p15n c922s="15dat6_/d3_/a>sc#L30822s=">22s7>15569 href};spanD1_PE"L27tring">"spi2_miso_px1", 92268p15n c922s="15n class="s6c9">&qu822s=">2268>15569 href};spanD1_PE"L27tring">"spi2_mosi_px0", 922s9p15n c922s="15s6code=_GPI6" clas822s=">226t>15569 href};spanD1_PE"L27tring">"spi2_sck_px2", 9227sp15n c922s="15="s6code=_GPI6" cl822s=">227=>15569 href};spanD1_PE"L27tring">"uart2_cts_n_pj5", 92271p15n c922s="15dat7_/d4_/a>sc#L30822s=">22s1>15569 href};spanD1_PE"L27tring">"uart2_rts_n_pj6", 92272p15n c922s="15n class="s6code=_G822s=">2272>15569 href};spanD1_PE"L27tring">"uart3_cts_n_pa1", 92273p15n c922s="15s6code=_GPI6" clas822s=">2273>15569 href};spanD1_PE"L27tring">"uart3_rts_n_pc0", 92274p15n c922s="15="s6code=_GPI6" cl822s=">2274>15569 href};spanD1_PE"L27tring">"uart3_rxd_pw7", 92275p15n c922s="15d5_/a>sc#L306" id=822s=">22s5>15569 href};spanD1_PE"L27tring">"uart3_txd_pw6", 92276p15n c922s="15ode=_GPI6" class="822s=">22s6>155t;),
70 hrefstatic const unsignedrs/pin82277p15n c92267 href};f">TEGRA_PIN>))2267 >22s7>155),
70 hrefstatic const unsignedrs/pin82278p15n c922s="14="s6">/* All 6on-G822s=">22s8>155a(4)
68 hchar *4)
68 href};f">TEGRA_Pgmi_alt_groupIND1_PE"L271" clgmi_alt_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2279p15n c922s="14c_/d6_/a>sc#L306" 822s=">22st>15569 href};spanD1_PE"L27tring">"gmi_a16_pj7", 9228sp15n c922s="14s="s67" class=6sre822s=">22s=>15569 href};spanD1_PE"L27tring">"gmi_cs3_n_pk4", 92281p15n c922s="14e=off6et" class="s822s=">22s1>15569 href};spanD1_PE"L27tring">"gmi_cs7_n_pi6", 92282p15n c922s="14="s6ss="comme6t">/822s=">22s2>15569 href};spanD1_PE"L27tring">"gmi_wp_n_pc7", 92283p15n c922s="14c_/d7_/a>sc#L306" 822s=">228P>14=t;),
70 hrefstatic const unsignedrs/pin82284p15n c922s="14s="s67ode=_GPI6PIN822s=">228s>14=),
70 hrefstatic const unsignedrs/pin82285p15n c922s="14=_GPI6PIN" class="822s=">2282>14=a(4)
68 hchar *4)
68 href};f">TEGRA_Phda_groupIND1_PE"L271" clhda_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2286p15n c922s="14="s6"8ing">&q6PIN"822s=">22s6>15569 href};spanD1_PE"L27tring">"clk1_req_pee2", 92287p15n c922s="14pe0_/a>sc#L306" id822s=">22s7>15569 href};spanD1_PE"L27tring">"dap1_din_pn1", 92288p15n c922s="14679ing">&q6PIN" cl822s=">22s8>15569 href};spanD1_PE"L27tring">"dap1_dout_pn2", 92289p15n c922s="14=6PIN" class="sref822s=">22st>15569 href};spanD1_PE"L27tring">"dap1_fs_pn0", 9229sp15n c922s="14="s6f="+code=6PIN"822s=">22s=>15569 href};spanD1_PE"L27tring">"dap1_sclk_pn3", 92291p15n c922s="14/e1_/a>sc#L306" id822s=">22s1>15569 href};spanD1_PE"L27tring">"dap2_din_pa4", 92292p15n c922s="146f="+code=6PIN" cl822s=">22s2>15569 href};spanD1_PE"L27tring">"dap2_dout_pa5", 92293p15n c922s="14e6PIN" class="sref822s=">22s3>15569 href};spanD1_PE"L27tring">"dap2_fs_pa2", 92294p15n c922s="14="s6="+code=_6IN" 822s=">22s4>15569 href};spanD1_PE"L27tring">"dap2_sclk_pa3", 92295p15n c922s="14/e2_/a>sc#L306" id822s=">22s5>15569 href};spanD1_PE"L27tring">"pex_l0_clkreq_n_pdd2", 92296p15n c922s="146fode=_GPI6s="line822s=">22s6>15569 href};spanD1_PE"L27tring">"pex_l0_prsnt_n_pdd0", 92297p15n c922s="14q6"sref">tegra30_p822s=">22s7>15569 href};spanD1_PE"L27tring">"pex_l0_rst_n_pdd1", 92298p15n c922s="14="s7g">"7ART3822s=">22s8>15569 href};spanD1_PE"L27tring">"pex_l1_clkreq_n_pdd6", 92299p15n c922s="14/e3_/a>sc#L306" id822s=">22st>15569 href};spanD1_PE"L27tring">"pex_l1_prsnt_n_pdd4", 923sc#L306" id823230=>15569 href};spanD1_PE"L27tring">"pex_l1_rst_n_pdd5", 923<1p15n c923<="14/e1_/a>sc#L306" id823<=">2301>15569 href};spanD1_PE"L27tring">"pex_l2_clkreq_n_pcc7", 923<2p15n c923<="146f="+code=6PIN" cl823<=">2302>15569 href};spanD1_PE"L27tring">"pex_l2_prsnt_n_pdd7", 923<3p15n c923<="14e6PIN" class="sref823<=">2303>15569 href};spanD1_PE"L27tring">"pex_l2_rst_n_pcc6", 923<4p15n c923<="14="s6="+code=_6IN" 823<=">2304>15569 href};spanD1_PE"L27tring">"pex_wake_n_pdd3", 923<5p15n c923<="14/e2_/a>sc#L306" id823<=">2305>15569 href};spanD1_PE"L27tring">"spdif_in_pk6", 923<6p15n c923<="146fode=_GPI6s="line823<=">2306>155t;),
70 hrefstatic const unsignedrs/pin823<7p15n c923<="14q6"sref">tegra30_p823<=">2307>155),
70 hrefstatic const unsignedrs/pin823<8p15n c923<="14="s7g">"7ART3823<=">2308>155a(4)
68 hchar *4)
68 href};f">TEGRA_Phdcp_groupIND1_PE"L271" clhdcp_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">23<9p15n c923<="14/e3_/a>sc#L306" id823<=">230t>15569 href};spanD1_PE"L27tring">"gen2_i2c_scl_pt5", 9231sp15n c923s="15="s6g">"6DMMC923s=">231=>15569 href};spanD1_PE"L27tring">"gen2_i2c_sda_pt6", 92311p15n c923s="15dat2_/b5_/a>sc#L30923s=">2311>15569 href};spanD1_PE"L27tring">"lcd_pwr0_pb2", 92312p15n c923s="15n class="s6g">&quo923s=">2312>15569 href};spanD1_PE"L27tring">"lcd_pwr2_pc6", 92313p15n c923s="15s6rng">&quo6DMMC3_923s=">2313>15569 href};spanD1_PE"L27tring">"lcd_sck_pz4", 92314p15n c923s="15="s6gg">"6t;LC923s=">2314>15569 href};spanD1_PE"L27tring">"lcd_sdout_pn5", 92315p15n c923s="15dat1_/b6_/a>sc#L30923s=">2315>15569 href};spanD1_PE"L27tring">"lcd_wr_n_pz3", 92316p15n c923s="15n class="s6g7">&qu923s=">2316>155t;),
70 hrefstatic const unsignedrs/pin82317p15n c923s="15] = {f">TEGRA_PIN_V23s=">2317>155),
70 hrefstatic const unsignedrs/pin82318p15n c923s="15="s6">"G6N1_I823s=">2318>155a(4)
68 hchar *4)
68 href};f">TEGRA_Phdmi_groupIND1_PE"L271" clhdmi_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">23s9p15n c923s="15dat0_/b7_/a>sc#L30823s=">23st>15569 href};spanD1_PE"L27tring">"hdmi_int_pn7", 9232sp15n c923s="15n class="s6ring">&823s=">232=>155t;),
70 hrefstatic const unsignedrs/pin82321p15n c923s="15s6ring">&qu6t;GMI_823s=">2321>155),
70 hrefstatic const unsignedrs/pin82322p15n c923s="15="s6r">"6DMMC823s=">2322>155a(4)
68 hchar *4)
68 href};f">TEGRA_Phsi_groupIND1_PE"L271" clhsi_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2323p15n c923s="15ts_n_pc0_/a>sc#L30823s=">23s3>15569 href};spanD1_PE"L27tring">"ulpi_data0_po1", 92324p15n c923s="15n class="s6rg">&qu823s=">23s4>15569 href};spanD1_PE"L27tring">"ulpi_data1_po2", 92325p15n c923s="15s6rg">"6DMMC3_823s=">2325>15569 href};spanD1_PE"L27tring">"ulpi_data2_po3", 92326p15n c923s="15="s6"8">"6quot823s=">2326>15569 href};spanD1_PE"L27tring">"ulpi_data3_po4", 92327p15n c923s="151_/c1_/a>sc#L306" 823s=">2327>15569 href};spanD1_PE"L27tring">"ulpi_data4_po5", 92328p15n c923s="15s="s6r9">"6t;V823s=">23s8>15569 href};spanD1_PE"L27tring">"ulpi_data5_po6", 92329p15n c923s="15">&qu6t;VI_HSYNC P823s=">232t>15569 href};spanD1_PE"L27tring">"ulpi_data6_po7", 9233sp15n c923s="15="s6ring">&qu6" cl823s=">233=>15569 href};spanD1_PE"L27tring">"ulpi_data7_po0", 92331p15n c923s="15xdCpc2_/a>sc#L306"823s=">233s>15pt;),
70 hrefstatic const unsignedrs/pin82332p15n c923s="15ass="s6r">"6"823s=">233s>15p),
70 hrefstatic const unsignedrs/pin82333p15n c923s="15>"6" class="s823s=">233s>15pa(4)
68 hchar *4)
68 href};f">TEGRA_Pi2c1_groupIND1_PE"L271" cli2c1_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">23s4p15n c923s="15="s6code=_GPI6" cl823s=">2334>15569 href};spanD1_PE"L27tring">"gen1_i2c_scl_pc4", 923s5p15n c923s="15xdCpc3_/a>sc#L306"823s=">2335>15569 href};spanD1_PE"L27tring">"gen1_i2c_sda_pc5", 92336p15n c923s="15ass="s6rng">&quo6"823s=">23s6>15569 href};spanD1_PE"L27tring">"spdif_in_pk6", 923s7p15n c923s="15">"6" class="s823s=">2337>15569 href};spanD1_PE"L27tring">"spdif_out_pk5", 92338p15n c923s="15="s6code=_GPI6" cl823s=">2338>15569 href};spanD1_PE"L27tring">"spi2_cs1_n_pw2", 923s9p15n c923s="15c_sclCpc4_/a>sc#L3823s=">233t>15569 href};spanD1_PE"L27tring">"spi2_cs2_n_pw3", 9234sp15n c923s="15pan class="s6code=823s=">234=>155t;),
70 hrefstatic const unsignedrs/pin82341p15n c923s="15="s6code=_GPI6" cl823s=">2341>155),
70 hrefstatic const unsignedrs/pin823s2p15n c923s="15="s6code=_GPI6" cl823s=">2342>155a(4)
68 hchar *4)
68 href};f">TEGRA_Pi2c2_groupIND1_PE"L271" cli2c2_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">23s3p15n c923s="15c_sdaCpc5_/a>sc#L3823s=">2343>15569 href};spanD1_PE"L27tring">"gen2_i2c_scl_pt5", 92344p15n c923s="15pan class="s6cring823s=">23s4>15569 href};spanD1_PE"L27tring">"gen2_i2c_sda_pt6", 92345p15n c923s="15="s6code=_GPI6" cl823s=">2342>15nt;),
70 hrefstatic const unsignedrs/pin82346p15n c923s="15="s6c8">"6" cl823s=">234e>157),
70 hrefstatic const unsignedrs/pin82347p15n c923s="152_/c6_/a>sc#L306" 823s=">234=>15=a(4)
68 hchar *4)
68 href};f">TEGRA_Pi2c3_groupIND1_PE"L271" cli2c3_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">23s8p15n c923s="15s="s6c9">"6" c823s=">2348>15569 href};spanD1_PE"L27tring">"cam_i2c_scl_pbb1", 92349p15n c923s="15=_GPI6" class="sre823s=">23st>15569 href};spanD1_PE"L27tring">"cam_i2c_sda_pbb2", 9235sp15n c923s="15="s6code=_GPI6" cl823s=">23s=>15569 href};spanD1_PE"L27tring">"sdmmc4_cmd_pt7", 92351p15n c923s="15n_pc7_/a>sc#L306" 823s=">2351>15569 href};spanD1_PE"L27tring">"sdmmc4_dat4_paa4", 92352p15n c923s="15s="s6code=_GPI6" c823s=">2352>155t;),
70 hrefstatic const unsignedrs/pin82353p15n c923s="15=_GPI6" class="sre823s=">2353>155),
70 hrefstatic const unsignedrs/pin82354p15n c923s="15="s6code=_GPI6" cl823s=">23s4>155a(4)
68 hchar *4)
68 href};f">TEGRA_Pi2c4_groupIND1_PE"L271" cli2c4_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2355p15n c923s="15dat5_/d0_/a>sc#L30823s=">23s5>15569 href};spanD1_PE"L27tring">"ddc_scl_pv4", 92356p15n c923s="15n class="s6code=_G823s=">23s6>15569 href};spanD1_PE"L27tring">"ddc_sda_pv5", 92357p15n c923s="15s6c8">"6" clas823s=">23s7>155t;),
70 hrefstatic const unsignedrs/pin82358p15n c923s="15="s6code=_GPI6" cl823s=">23s8>155),
70 hrefstatic const unsignedrs/pin82359p15n c923s="15dat4_/d1_/a>sc#L30823s=">23st>155a(4)
68 hchar *4)
68 href};f">TEGRA_Pi2cpwr_groupIND1_PE"L271" cli2cpwr_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">236sp15n c923s="15n class="s6code=_G823s=">23s=>15569 href};spanD1_PE"L27tring">"pwr_i2c_scl_pz6", 92361p15n c923s="15s6code=_GPI6" clas823s=">23s1>15569 href};spanD1_PE"L27tring">"pwr_i2c_sda_pz7", 92362p15n c923s="15="s6code=_GPI6" cl823s=">2362>155t;),
70 hrefstatic const unsignedrs/pin82363p15n c923s="15_/d2_/a>sc#L306" i823s=">2363>155),
70 hrefstatic const unsignedrs/pin82364p15n c923s="15"s6code=_GPI6" cla823s=">2364>155a(4)
68 hchar *4)
68 href};f">TEGRA_Pi2s0_groupIND1_PE"L271" cli2s0_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2365p15n c923s="15GPI6" class="sref"823s=">23s5>15569 href};spanD1_PE"L27tring">"dap1_din_pn1", 92366p15n c923s="15="s6c8">"6" cl823s=">23s6>15569 href};spanD1_PE"L27tring">"dap1_dout_pn2", 92367p15n c923s="15dat6_/d3_/a>sc#L30823s=">23s7>15569 href};spanD1_PE"L27tring">"dap1_fs_pn0", 92368p15n c923s="15n class="s6c9">&qu823s=">2368>15569 href};spanD1_PE"L27tring">"dap1_sclk_pn3", 923s9p15n c923s="15s6code=_GPI6" clas823s=">2369>15nt;),
70 hrefstatic const unsignedrs/pin8237sp15n c923s="15="s6code=_GPI6" cl823s=">237=>157),
70 hrefstatic const unsignedrs/pin82371p15n c923s="15dat7_/d4_/a>sc#L30823s=">2371>15=a(4)
68 hchar *4)
68 href};f">TEGRA_Pi2s1_groupIND1_PE"L271" cli2s1_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2372p15n c923s="15n class="s6code=_G823s=">2372>15569 href};spanD1_PE"L27tring">"dap2_din_pa4", 92373p15n c923s="15s6code=_GPI6" clas823s=">2373>15569 href};spanD1_PE"L27tring">"dap2_dout_pa5", 92374p15n c923s="15="s6code=_GPI6" cl823s=">2374>15569 href};spanD1_PE"L27tring">"dap2_fs_pa2", 92375p15n c923s="15d5_/a>sc#L306" id=823s=">23s5>15569 href};spanD1_PE"L27tring">"dap2_sclk_pa3", 92376p15n c923s="15ode=_GPI6" class="823s=">23s6>155t;),
70 hrefstatic const unsignedrs/pin82377p15n c92367 href};f">TEGRA_PIN>))2367 >23s7>155),
70 hrefstatic const unsignedrs/pin82378p15n c923s="14="s6">/* All 6on-G823s=">23s8>155a(4)
68 hchar *4)
68 href};f">TEGRA_Pi2s2_groupIND1_PE"L271" cli2s2_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2379p15n c923s="14c_/d6_/a>sc#L306" 823s=">23st>15569 href};spanD1_PE"L27tring">"dap3_din_pp1", 9238sp15n c923s="14s="s67" class=6sre823s=">23s=>15569 href};spanD1_PE"L27tring">"dap3_dout_pp2", 92381p15n c923s="14e=off6et" class="s823s=">23s1>15569 href};spanD1_PE"L27tring">"dap3_fs_pp0", 92382p15n c923s="14="s6ss="comme6t">/823s=">23s2>15569 href};spanD1_PE"L27tring">"dap3_sclk_pp3", 92383p15n c923s="14c_/d7_/a>sc#L306" 823s=">238P>14=t;),
70 hrefstatic const unsignedrs/pin82384p15n c923s="14s="s67ode=_GPI6PIN823s=">238s>14=),
70 hrefstatic const unsignedrs/pin82385p15n c923s="14=_GPI6PIN" class="823s=">2382>14=a(4)
68 hchar *4)
68 href};f">TEGRA_Pi2s3_groupIND1_PE"L271" cli2s3_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2386p15n c923s="14="s6"8ing">&q6PIN"823s=">23s6>15569 href};spanD1_PE"L27tring">"dap4_din_pp5", 92387p15n c923s="14pe0_/a>sc#L306" id823s=">23s7>15569 href};spanD1_PE"L27tring">"dap4_dout_pp6", 92388p15n c923s="14679ing">&q6PIN" cl823s=">23s8>15569 href};spanD1_PE"L27tring">"dap4_fs_pp4", 92389p15n c923s="14=6PIN" class="sref823s=">23st>15569 href};spanD1_PE"L27tring">"dap4_sclk_pp7", 9239sp15n c923s="14="s6f="+code=6PIN"823s=">239=>155t;),
70 hrefstatic const unsignedrs/pin82391p15n c923s="14/e1_/a>sc#L306" id823s=">2391>155),
70 hrefstatic const unsignedrs/pin82392p15n c923s="146f="+code=6PIN" cl823s=">2392>155a(4)
68 hchar *4)
68 href};f">TEGRA_Pi2s4_groupIND1_PE"L271" cli2s4_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2393p15n c923s="14e6PIN" class="sref823s=">23s3>15569 href};spanD1_PE"L27tring">"pbb0", 92394p15n c923s="14="s6="+code=_6IN" 823s=">23s4>15569 href};spanD1_PE"L27tring">"pbb7", 92395p15n c923s="14/e2_/a>sc#L306" id823s=">23s5>15569 href};spanD1_PE"L27tring">"pcc1", 92396p15n c923s="146fode=_GPI6s="line823s=">23s6>15569 href};spanD1_PE"L27tring">"pcc2", 92397p15n c923s="14q6"sref">tegra30_p823s=">23s7>15569 href};spanD1_PE"L27tring">"sdmmc4_dat4_paa4", 92398p15n c923s="14="s7g">"7ART3823s=">23s8>15569 href};spanD1_PE"L27tring">"sdmmc4_dat5_paa5", 92399p15n c923s="14/e3_/a>sc#L306" id823s=">23st>15569 href};spanD1_PE"L27tring">"sdmmc4_dat6_paa6", 924sc#L306" id824240=>15569 href};spanD1_PE"L27tring">"sdmmc4_dat7_paa7", 924<1p15n c924<="14/e1_/a>sc#L306" id824<=">240s>15pt;),
70 hrefstatic const unsignedrs/pin824<2p15n c924<="146f="+code=6PIN" cl824<=">240s>15p),
70 hrefstatic const unsignedrs/pin824<3p15n c924<="14e6PIN" class="sref824<=">240s>15pa(4)
68 hchar *4)
68 href};f">TEGRA_Pinvalid_groupIND1_PE"L271" clinvalid_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">24<4p15n c924<="14="s6="+code=_6IN" 824<=">2404>15569 href};spanD1_PE"L27tring">"kb_row3_pr3", 924<5p15n c924<="14/e2_/a>sc#L306" id824<=">2405>15569 href};spanD1_PE"L27tring">"sdmmc4_clk_pcc4", 924<6p15n c924<="146fode=_GPI6s="line824<=">2406>155t;),
70 hrefstatic const unsignedrs/pin824<7p15n c924<="14q6"sref">tegra30_p824<=">2407>155),
70 hrefstatic const unsignedrs/pin824<8p15n c924<="14="s7g">"7ART3824<=">2408>155a(4)
68 hchar *4)
68 href};f">TEGRA_Pkbc_groupIND1_PE"L271" clkbc_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">24<9p15n c924<="14/e3_/a>sc#L306" id824<=">240t>15569 href};spanD1_PE"L27tring">"kb_col0_pq0", 9241sp15n c924s="15="s6g">"6DMMC924s=">241=>15569 href};spanD1_PE"L27tring">"kb_col1_pq1", 92411p15n c924s="15dat2_/b5_/a>sc#L30924s=">2411>15569 href};spanD1_PE"L27tring">"kb_col2_pq2", 92412p15n c924s="15n class="s6g">&quo924s=">2412>15569 href};spanD1_PE"L27tring">"kb_col3_pq3", 92413p15n c924s="15s6rng">&quo6DMMC3_924s=">2413>15569 href};spanD1_PE"L27tring">"kb_col4_pq4", 92414p15n c924s="15="s6gg">"6t;LC924s=">2414>15569 href};spanD1_PE"L27tring">"kb_col5_pq5", 92415p15n c924s="15dat1_/b6_/a>sc#L30924s=">2415>15569 href};spanD1_PE"L27tring">"kb_col6_pq6", 92416p15n c924s="15n class="s6g7">&qu924s=">2416>15569 href};spanD1_PE"L27tring">"kb_col7_pq7", 92417p15n c924s="15] = {f">TEGRA_PIN_V24s=">2417>15569 href};spanD1_PE"L27tring">"kb_row0_pr0", 92418p15n c924s="15="s6">"G6N1_I824s=">2418>15569 href};spanD1_PE"L27tring">"kb_row1_pr1", 92419p15n c924s="15dat0_/b7_/a>sc#L30824s=">24st>15569 href};spanD1_PE"L27tring">"kb_row10_ps2", 9242sp15n c924s="15n class="s6ring">&824s=">242=>15569 href};spanD1_PE"L27tring">"kb_row11_ps3", 92421p15n c924s="15s6ring">&qu6t;GMI_824s=">2421>15569 href};spanD1_PE"L27tring">"kb_row12_ps4", 92422p15n c924s="15="s6r">"6DMMC824s=">2422>15569 href};spanD1_PE"L27tring">"kb_row13_ps5", 92423p15n c924s="15ts_n_pc0_/a>sc#L30824s=">24s3>15569 href};spanD1_PE"L27tring">"kb_row14_ps6", 92424p15n c924s="15n class="s6rg">&qu824s=">24s4>15569 href};spanD1_PE"L27tring">"kb_row15_ps7", 92425p15n c924s="15s6rg">"6DMMC3_824s=">2425>15569 href};spanD1_PE"L27tring">"kb_row2_pr2", 92426p15n c924s="15="s6"8">"6quot824s=">2426>15569 href};spanD1_PE"L27tring">"kb_row3_pr3", 92427p15n c924s="151_/c1_/a>sc#L306" 824s=">2427>15569 href};spanD1_PE"L27tring">"kb_row4_pr4", 92428p15n c924s="15s="s6r9">"6t;V824s=">24s8>15569 href};spanD1_PE"L27tring">"kb_row5_pr5", 92429p15n c924s="15">&qu6t;VI_HSYNC P824s=">242t>15569 href};spanD1_PE"L27tring">"kb_row6_pr6", 9243sp15n c924s="15="s6ring">&qu6" cl824s=">243=>15569 href};spanD1_PE"L27tring">"kb_row7_pr7", 92431p15n c924s="15xdCpc2_/a>sc#L306"824s=">2431>15569 href};spanD1_PE"L27tring">"kb_row8_ps0", 92432p15n c924s="15ass="s6r">"6"824s=">24s2>15569 href};spanD1_PE"L27tring">"kb_row9_ps1", 92433p15n c924s="15>"6" class="s824s=">243P>14=t;),
70 hrefstatic const unsignedrs/pin824s4p15n c924s="15="s6code=_GPI6" cl824s=">243s>14=),
70 hrefstatic const unsignedrs/pin824s5p15n c924s="15xdCpc3_/a>sc#L306"824s=">2432>14=a(4)
68 hchar *4)
68 href};f">TEGRA_Pmio_groupIND1_PE"L271" clmio_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2436p15n c924s="15ass="s6rng">&quo6"824s=">24s6>15569 href};spanD1_PE"L27tring">"kb_col6_pq6", 924s7p15n c924s="15">"6" class="s824s=">2437>15569 href};spanD1_PE"L27tring">"kb_col7_pq7", 92438p15n c924s="15="s6code=_GPI6" cl824s=">2438>15569 href};spanD1_PE"L27tring">"kb_row10_ps2", 924s9p15n c924s="15c_sclCpc4_/a>sc#L3824s=">243t>15569 href};spanD1_PE"L27tring">"kb_row11_ps3", 9244sp15n c924s="15pan class="s6code=824s=">24s=>15569 href};spanD1_PE"L27tring">"kb_row12_ps4", 92441p15n c924s="15="s6code=_GPI6" cl824s=">2441>15569 href};spanD1_PE"L27tring">"kb_row13_ps5", 924s2p15n c924s="15="s6code=_GPI6" cl824s=">2442>15569 href};spanD1_PE"L27tring">"kb_row14_ps6", 924s3p15n c924s="15c_sdaCpc5_/a>sc#L3824s=">2443>15569 href};spanD1_PE"L27tring">"kb_row15_ps7", 92444p15n c924s="15pan class="s6cring824s=">24s4>15569 href};spanD1_PE"L27tring">"kb_row6_pr6", 92445p15n c924s="15="s6code=_GPI6" cl824s=">24s5>15569 href};spanD1_PE"L27tring">"kb_row7_pr7", 92446p15n c924s="15="s6c8">"6" cl824s=">2446>15569 href};spanD1_PE"L27tring">"kb_row8_ps0", 92447p15n c924s="152_/c6_/a>sc#L306" 824s=">2447>15569 href};spanD1_PE"L27tring">"kb_row9_ps1", 924s8p15n c924s="15s="s6c9">"6" c824s=">2448>155t;),
70 hrefstatic const unsignedrs/pin82449p15n c924s="15=_GPI6" class="sre824s=">24st>155),
70 hrefstatic const unsignedrs/pin8245sp15n c924s="15="s6code=_GPI6" cl824s=">24s=>155a(4)
68 hchar *4)
68 href};f">TEGRA_Pnand_groupIND1_PE"L271" clnand_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2451p15n c924s="15n_pc7_/a>sc#L306" 824s=">2451>15569 href};spanD1_PE"L27tring">"gmi_ad0_pg0", 92452p15n c924s="15s="s6code=_GPI6" c824s=">2452>15569 href};spanD1_PE"L27tring">"gmi_ad1_pg1", 92453p15n c924s="15=_GPI6" class="sre824s=">2453>15569 href};spanD1_PE"L27tring">"gmi_ad10_ph2", 92454p15n c924s="15="s6code=_GPI6" cl824s=">24s4>15569 href};spanD1_PE"L27tring">"gmi_ad11_ph3", 92455p15n c924s="15dat5_/d0_/a>sc#L30824s=">24s5>15569 href};spanD1_PE"L27tring">"gmi_ad12_ph4", 92456p15n c924s="15n class="s6code=_G824s=">24s6>15569 href};spanD1_PE"L27tring">"gmi_ad13_ph5", 92457p15n c924s="15s6c8">"6" clas824s=">24s7>15569 href};spanD1_PE"L27tring">"gmi_ad14_ph6", 92458p15n c924s="15="s6code=_GPI6" cl824s=">24s8>15569 href};spanD1_PE"L27tring">"gmi_ad15_ph7", 92459p15n c924s="15dat4_/d1_/a>sc#L30824s=">24st>15569 href};spanD1_PE"L27tring">"gmi_ad2_pg2", 9246sp15n c924s="15n class="s6code=_G824s=">24s=>15569 href};spanD1_PE"L27tring">"gmi_ad3_pg3", 92461p15n c924s="15s6code=_GPI6" clas824s=">24s1>15569 href};spanD1_PE"L27tring">"gmi_ad4_pg4", 92462p15n c924s="15="s6code=_GPI6" cl824s=">24s2>15569 href};spanD1_PE"L27tring">"gmi_ad5_pg5", 92463p15n c924s="15_/d2_/a>sc#L306" i824s=">24s3>15569 href};spanD1_PE"L27tring">"gmi_ad6_pg6", 92464p15n c924s="15"s6code=_GPI6" cla824s=">24s4>15569 href};spanD1_PE"L27tring">"gmi_ad7_pg7", 92465p15n c924s="15GPI6" class="sref"824s=">24s5>15569 href};spanD1_PE"L27tring">"gmi_ad8_ph0", 92466p15n c924s="15="s6c8">"6" cl824s=">24s6>15569 href};spanD1_PE"L27tring">"gmi_ad9_ph1", 92467p15n c924s="15dat6_/d3_/a>sc#L30824s=">24s7>15569 href};spanD1_PE"L27tring">"gmi_adv_n_pk0", 92468p15n c924s="15n class="s6c9">&qu824s=">2468>15569 href};spanD1_PE"L27tring">"gmi_clk_pk1", 92469p15n c924s="15s6code=_GPI6" clas824s=">246t>15569 href};spanD1_PE"L27tring">"gmi_cs0_n_pj0", 9247sp15n c924s="15="s6code=_GPI6" cl824s=">247=>15569 href};spanD1_PE"L27tring">"gmi_cs1_n_pj2", 92471p15n c924s="15dat7_/d4_/a>sc#L30824s=">24s1>15569 href};spanD1_PE"L27tring">"gmi_cs2_n_pk3", 92472p15n c924s="15n class="s6code=_G824s=">2472>15569 href};spanD1_PE"L27tring">"gmi_cs3_n_pk4", 92473p15n c924s="15s6code=_GPI6" clas824s=">2473>15569 href};spanD1_PE"L27tring">"gmi_cs4_n_pk2", 92474p15n c924s="15="s6code=_GPI6" cl824s=">2474>15569 href};spanD1_PE"L27tring">"gmi_cs6_n_pi3", 92475p15n c924s="15d5_/a>sc#L306" id=824s=">24s5>15569 href};spanD1_PE"L27tring">"gmi_cs7_n_pi6", 92476p15n c924s="15ode=_GPI6" class="824s=">2476>15569 href};spanD1_PE"L27tring">"gmi_dqs_pi2", 92477p15n c92467 href};f">TEGRA_PIN>))2467 >2477>15569 href};spanD1_PE"L27tring">"gmi_iordy_pi5", 92478p15n c924s="14="s6">/* All 6on-G824s=">2478>15569 href};spanD1_PE"L27tring">"gmi_oe_n_pi1", 92479p15n c924s="14c_/d6_/a>sc#L306" 824s=">24st>15569 href};spanD1_PE"L27tring">"gmi_rst_n_pi4", 9248sp15n c924s="14s="s67" class=6sre824s=">24s=>15569 href};spanD1_PE"L27tring">"gmi_wait_pi7", 92481p15n c924s="14e=off6et" class="s824s=">24s1>15569 href};spanD1_PE"L27tring">"gmi_wp_n_pc7", 92482p15n c924s="14="s6ss="comme6t">/824s=">24s2>15569 href};spanD1_PE"L27tring">"gmi_wr_n_pi0", 92483p15n c924s="14c_/d7_/a>sc#L306" 824s=">2483>15569 href};spanD1_PE"L27tring">"kb_col0_pq0", 92484p15n c924s="14s="s67ode=_GPI6PIN824s=">2484>15569 href};spanD1_PE"L27tring">"kb_col1_pq1", 92485p15n c924s="14=_GPI6PIN" class="824s=">2485>15569 href};spanD1_PE"L27tring">"kb_col2_pq2", 92486p15n c924s="14="s6"8ing">&q6PIN"824s=">24s6>15569 href};spanD1_PE"L27tring">"kb_col3_pq3", 92487p15n c924s="14pe0_/a>sc#L306" id824s=">24s7>15569 href};spanD1_PE"L27tring">"kb_col4_pq4", 92488p15n c924s="14679ing">&q6PIN" cl824s=">24s8>15569 href};spanD1_PE"L27tring">"kb_col5_pq5", 92489p15n c924s="14=6PIN" class="sref824s=">24st>15569 href};spanD1_PE"L27tring">"kb_col6_pq6", 9249sp15n c924s="14="s6f="+code=6PIN"824s=">24s=>15569 href};spanD1_PE"L27tring">"kb_col7_pq7", 92491p15n c924s="14/e1_/a>sc#L306" id824s=">24s1>15569 href};spanD1_PE"L27tring">"kb_row0_pr0", 92492p15n c924s="146f="+code=6PIN" cl824s=">24s2>15569 href};spanD1_PE"L27tring">"kb_row1_pr1", 92493p15n c924s="14e6PIN" class="sref824s=">24s3>15569 href};spanD1_PE"L27tring">"kb_row10_ps2", 92494p15n c924s="14="s6="+code=_6IN" 824s=">24s4>15569 href};spanD1_PE"L27tring">"kb_row11_ps3", 92495p15n c924s="14/e2_/a>sc#L306" id824s=">24s5>15569 href};spanD1_PE"L27tring">"kb_row12_ps4", 92496p15n c924s="146fode=_GPI6s="line824s=">24s6>15569 href};spanD1_PE"L27tring">"kb_row13_ps5", 92497p15n c924s="14q6"sref">tegra30_p824s=">24s7>15569 href};spanD1_PE"L27tring">"kb_row14_ps6", 92498p15n c924s="14="s7g">"7ART3824s=">24s8>15569 href};spanD1_PE"L27tring">"kb_row15_ps7", 92499p15n c924s="14/e3_/a>sc#L306" id824s=">24st>15569 href};spanD1_PE"L27tring">"kb_row2_pr2", 925sc#L306" id825250=>15569 href};spanD1_PE"L27tring">"kb_row3_pr3", 925<1p15n c925<="14/e1_/a>sc#L306" id825<=">2501>15569 href};spanD1_PE"L27tring">"kb_row4_pr4", 925<2p15n c925<="146f="+code=6PIN" cl825<=">2502>15569 href};spanD1_PE"L27tring">"kb_row5_pr5", 925<3p15n c925<="14e6PIN" class="sref825<=">2503>15569 href};spanD1_PE"L27tring">"kb_row6_pr6", 925<4p15n c925<="14="s6="+code=_6IN" 825<=">2504>15569 href};spanD1_PE"L27tring">"kb_row7_pr7", 925<5p15n c925<="14/e2_/a>sc#L306" id825<=">2505>15569 href};spanD1_PE"L27tring">"kb_row8_ps0", 925<6p15n c925<="146fode=_GPI6s="line825<=">2506>15569 href};spanD1_PE"L27tring">"kb_row9_ps1", 925<7p15n c925<="14q6"sref">tegra30_p825<=">2507>15569 href};spanD1_PE"L27tring">"sdmmc4_clk_pcc4", 925<8p15n c925<="14="s7g">"7ART3825<=">2508>15569 href};spanD1_PE"L27tring">"sdmmc4_cmd_pt7", 925<9p15n c925<="14/e3_/a>sc#L306" id825<=">2509>15nt;),
70 hrefstatic const unsignedrs/pin8251sp15n c925s="15="s6g">"6DMMC925s=">251=>157),
70 hrefstatic const unsignedrs/pin82511p15n c925s="15dat2_/b5_/a>sc#L30925s=">2511>15=a(4)
68 hchar *4)
68 href};f">TEGRA_Pnand_alt_groupIND1_PE"L271" clnand_alt_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2512p15n c925s="15n class="s6g">&quo925s=">2512>15569 href};spanD1_PE"L27tring">"gmi_cs6_n_pi3", 92513p15n c925s="15s6rng">&quo6DMMC3_925s=">2513>15569 href};spanD1_PE"L27tring">"gmi_cs7_n_pi6", 92514p15n c925s="15="s6gg">"6t;LC925s=">2514>15569 href};spanD1_PE"L27tring">"gmi_rst_n_pi4", 92515p15n c925s="15dat1_/b6_/a>sc#L30925s=">2512>15nt;),
70 hrefstatic const unsignedrs/pin82516p15n c925s="15n class="s6g7">&qu925s=">251e>157),
70 hrefstatic const unsignedrs/pin82517p15n c925s="15] = {f">TEGRA_PIN_V25s=">251=>15=a(4)
68 hchar *4)
68 href};f">TEGRA_Powr_groupIND1_PE"L271" clowr_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2518p15n c925s="15="s6">"G6N1_I825s=">2518>15569 href};spanD1_PE"L27tring">"pu0", 92519p15n c925s="15dat0_/b7_/a>sc#L30825s=">25st>15569 href};spanD1_PE"L27tring">"pv2", 9252sp15n c925s="15n class="s6ring">&825s=">252=>15569 href};spanD1_PE"L27tring">"kb_row5_pr5", 92521p15n c925s="15s6ring">&qu6t;GMI_825s=">2521>15569 href};spanD1_PE"L27tring">"owr", 92522p15n c925s="15="s6r">"6DMMC825s=">2522>155t;),
70 hrefstatic const unsignedrs/pin82523p15n c925s="15ts_n_pc0_/a>sc#L30825s=">2523>155),
70 hrefstatic const unsignedrs/pin82524p15n c925s="15n class="s6rg">&qu825s=">2524>155a(4)
68 hchar *4)
68 href};f">TEGRA_Ppcie_groupIND1_PE"L271" clpcie_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2525p15n c925s="15s6rg">"6DMMC3_825s=">2525>15569 href};spanD1_PE"L27tring">"pex_l0_clkreq_n_pdd2", 92526p15n c925s="15="s6"8">"6quot825s=">2526>15569 href};spanD1_PE"L27tring">"pex_l0_prsnt_n_pdd0", 92527p15n c925s="151_/c1_/a>sc#L306" 825s=">2527>15569 href};spanD1_PE"L27tring">"pex_l0_rst_n_pdd1", 92528p15n c925s="15s="s6r9">"6t;V825s=">25s8>15569 href};spanD1_PE"L27tring">"pex_l1_clkreq_n_pdd6", 92529p15n c925s="15">&qu6t;VI_HSYNC P825s=">252t>15569 href};spanD1_PE"L27tring">"pex_l1_prsnt_n_pdd4", 9253sp15n c925s="15="s6ring">&qu6" cl825s=">253=>15569 href};spanD1_PE"L27tring">"pex_l1_rst_n_pdd5", 92531p15n c925s="15xdCpc2_/a>sc#L306"825s=">2531>15569 href};spanD1_PE"L27tring">"pex_l2_clkreq_n_pcc7", 92532p15n c925s="15ass="s6r">"6"825s=">25s2>15569 href};spanD1_PE"L27tring">"pex_l2_prsnt_n_pdd7", 92533p15n c925s="15>"6" class="s825s=">2533>15569 href};spanD1_PE"L27tring">"pex_l2_rst_n_pcc6", 925s4p15n c925s="15="s6code=_GPI6" cl825s=">2534>15569 href};spanD1_PE"L27tring">"pex_wake_n_pdd3", 925s5p15n c925s="15xdCpc3_/a>sc#L306"825s=">2532>15nt;),
70 hrefstatic const unsignedrs/pin82536p15n c925s="15ass="s6rng">&quo6"825s=">253e>157),
70 hrefstatic const unsignedrs/pin825s7p15n c925s="15">"6" class="s825s=">253=>15=a(4)
68 hchar *4)
68 href};f">TEGRA_Ppwm0_groupIND1_PE"L271" clpwm0_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2538p15n c925s="15="s6code=_GPI6" cl825s=">2538>15569 href};spanD1_PE"L27tring">"gmi_ad8_ph0", 925s9p15n c925s="15c_sclCpc4_/a>sc#L3825s=">253t>15569 href};spanD1_PE"L27tring">"pu3", 9254sp15n c925s="15pan class="s6code=825s=">25s=>15569 href};spanD1_PE"L27tring">"sdmmc3_dat3_pb4", 92541p15n c925s="15="s6code=_GPI6" cl825s=">2541>15569 href};spanD1_PE"L27tring">"sdmmc3_dat5_pd0", 925s2p15n c925s="15="s6code=_GPI6" cl825s=">2542>15569 href};spanD1_PE"L27tring">"uart3_rts_n_pc0", 925s3p15n c925s="15c_sdaCpc5_/a>sc#L3825s=">254P>14=t;),
70 hrefstatic const unsignedrs/pin82544p15n c925s="15pan class="s6cring825s=">254s>14=),
70 hrefstatic const unsignedrs/pin82545p15n c925s="15="s6code=_GPI6" cl825s=">2542>14=a(4)
68 hchar *4)
68 href};f">TEGRA_Ppwm1_groupIND1_PE"L271" clpwm1_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2546p15n c925s="15="s6c8">"6" cl825s=">2546>15569 href};spanD1_PE"L27tring">"gmi_ad9_ph1", 92547p15n c925s="152_/c6_/a>sc#L306" 825s=">2547>15569 href};spanD1_PE"L27tring">"pu4", 92548p15n c925s="15s="s6c9">"6" c825s=">2548>15569 href};spanD1_PE"L27tring">"sdmmc3_dat2_pb5", 92549p15n c925s="15=_GPI6" class="sre825s=">25st>15569 href};spanD1_PE"L27tring">"sdmmc3_dat4_pd1", 9255sp15n c925s="15="s6code=_GPI6" cl825s=">255=>155t;),
70 hrefstatic const unsignedrs/pin82551p15n c925s="15n_pc7_/a>sc#L306" 825s=">2551>155),
70 hrefstatic const unsignedrs/pin82552p15n c925s="15s="s6code=_GPI6" c825s=">2552>155a(4)
68 hchar *4)
68 href};f">TEGRA_Ppwm2_groupIND1_PE"L271" clpwm2_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2553p15n c925s="15=_GPI6" class="sre825s=">2553>15569 href};spanD1_PE"L27tring">"gmi_ad10_ph2", 92554p15n c925s="15="s6code=_GPI6" cl825s=">25s4>15569 href};spanD1_PE"L27tring">"pu5", 92555p15n c925s="15dat5_/d0_/a>sc#L30825s=">25s5>15569 href};spanD1_PE"L27tring">"sdmmc3_clk_pa6", 92556p15n c925s="15n class="s6code=_G825s=">2556>155t;),
70 hrefstatic const unsignedrs/pin82557p15n c925s="15s6c8">"6" clas825s=">2557>155),
70 hrefstatic const unsignedrs/pin82558p15n c925s="15="s6code=_GPI6" cl825s=">2558>155a(4)
68 hchar *4)
68 href};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2559p15n c925s="15dat4_/d1_/a>sc#L30825s=">25st>15569 href};spanD1_PE"L27tring">"gmi_ad11_ph3", 9256sp15n c925s="15n class="s6code=_G825s=">25s=>15569 href};spanD1_PE"L27tring">"pu6", 92561p15n c925s="15s6code=_GPI6" clas825s=">25s1>15569 href};spanD1_PE"L27tring">"sdmmc3_cmd_pa7", 92562p15n c925s="15="s6code=_GPI6" cl825s=">2562>155t;),
70 hrefstatic const unsignedrs/pin82563p15n c925s="15_/d2_/a>sc#L306" i825s=">2563>155),
70 hrefstatic const unsignedrs/pin82564p15n c925s="15"s6code=_GPI6" cla825s=">2564>155a(4)
68 hchar *4)
68 href};f">TEGRA_Ppwr_int_n_groupIND1_PE"L271" clpwr_int_n_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2565p15n c925s="15GPI6" class="sref"825s=">25s5>15569 href};spanD1_PE"L27tring">"pwr_int_n", 92566p15n c925s="15="s6c8">"6" cl825s=">2566>155t;),
70 hrefstatic const unsignedrs/pin82567p15n c925s="15dat6_/d3_/a>sc#L30825s=">2567>155),
70 hrefstatic const unsignedrs/pin82568p15n c925s="15n class="s6c9">&qu825s=">2568>155a(4)
68 hchar *4)
68 href};f">TEGRA_Prsvd1_groupIND1_PE"L271" clrsvd1_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2569p15n c925s="15s6code=_GPI6" clas825s=">256t>15569 href};spanD1_PE"L27tring">"gmi_ad0_pg0", 9257sp15n c925s="15="s6code=_GPI6" cl825s=">257=>15569 href};spanD1_PE"L27tring">"gmi_ad1_pg1", 92571p15n c925s="15dat7_/d4_/a>sc#L30825s=">25s1>15569 href};spanD1_PE"L27tring">"gmi_ad12_ph4", 92572p15n c925s="15n class="s6code=_G825s=">2572>15569 href};spanD1_PE"L27tring">"gmi_ad13_ph5", 92573p15n c925s="15s6code=_GPI6" clas825s=">2573>15569 href};spanD1_PE"L27tring">"gmi_ad14_ph6", 92574p15n c925s="15="s6code=_GPI6" cl825s=">2574>15569 href};spanD1_PE"L27tring">"gmi_ad15_ph7", 92575p15n c925s="15d5_/a>sc#L306" id=825s=">25s5>15569 href};spanD1_PE"L27tring">"gmi_ad2_pg2", 92576p15n c925s="15ode=_GPI6" class="825s=">2576>15569 href};spanD1_PE"L27tring">"gmi_ad3_pg3", 92577p15n c92567 href};f">TEGRA_PIN>))2567 >2577>15569 href};spanD1_PE"L27tring">"gmi_ad4_pg4", 92578p15n c925s="14="s6">/* All 6on-G825s=">2578>15569 href};spanD1_PE"L27tring">"gmi_ad5_pg5", 92579p15n c925s="14c_/d6_/a>sc#L306" 825s=">25st>15569 href};spanD1_PE"L27tring">"gmi_ad6_pg6", 9258sp15n c925s="14s="s67" class=6sre825s=">25s=>15569 href};spanD1_PE"L27tring">"gmi_ad7_pg7", 92581p15n c925s="14e=off6et" class="s825s=">25s1>15569 href};spanD1_PE"L27tring">"gmi_adv_n_pk0", 92582p15n c925s="14="s6ss="comme6t">/825s=">25s2>15569 href};spanD1_PE"L27tring">"gmi_clk_pk1", 92583p15n c925s="14c_/d7_/a>sc#L306" 825s=">2583>15569 href};spanD1_PE"L27tring">"gmi_cs0_n_pj0", 92584p15n c925s="14s="s67ode=_GPI6PIN825s=">2584>15569 href};spanD1_PE"L27tring">"gmi_cs1_n_pj2", 92585p15n c925s="14=_GPI6PIN" class="825s=">2585>15569 href};spanD1_PE"L27tring">"gmi_cs2_n_pk3", 92586p15n c925s="14="s6"8ing">&q6PIN"825s=">25s6>15569 href};spanD1_PE"L27tring">"gmi_cs3_n_pk4", 92587p15n c925s="14pe0_/a>sc#L306" id825s=">25s7>15569 href};spanD1_PE"L27tring">"gmi_cs4_n_pk2", 92588p15n c925s="14679ing">&q6PIN" cl825s=">25s8>15569 href};spanD1_PE"L27tring">"gmi_dqs_pi2", 92589p15n c925s="14=6PIN" class="sref825s=">25st>15569 href};spanD1_PE"L27tring">"gmi_iordy_pi5", 9259sp15n c925s="14="s6f="+code=6PIN"825s=">25s=>15569 href};spanD1_PE"L27tring">"gmi_oe_n_pi1", 92591p15n c925s="14/e1_/a>sc#L306" id825s=">25s1>15569 href};spanD1_PE"L27tring">"gmi_wait_pi7", 92592p15n c925s="146f="+code=6PIN" cl825s=">25s2>15569 href};spanD1_PE"L27tring">"gmi_wp_n_pc7", 92593p15n c925s="14e6PIN" class="sref825s=">25s3>15569 href};spanD1_PE"L27tring">"gmi_wr_n_pi0", 92594p15n c925s="14="s6="+code=_6IN" 825s=">25s4>15569 href};spanD1_PE"L27tring">"pu1", 92595p15n c925s="14/e2_/a>sc#L306" id825s=">25s5>15569 href};spanD1_PE"L27tring">"pu2", 92596p15n c925s="146fode=_GPI6s="line825s=">25s6>15569 href};spanD1_PE"L27tring">"pv0", 92597p15n c925s="14q6"sref">tegra30_p825s=">25s7>15569 href};spanD1_PE"L27tring">"pv1", 92598p15n c925s="14="s7g">"7ART3825s=">25s8>15569 href};spanD1_PE"L27tring">"sdmmc3_dat0_pb7", 92599p15n c925s="14/e3_/a>sc#L306" id825s=">25st>15569 href};spanD1_PE"L27tring">"sdmmc3_dat1_pb6", 926sc#L306" id826260=>15569 href};spanD1_PE"L27tring">"sdmmc3_dat2_pb5", 926<1p15n c926<="14/e1_/a>sc#L306" id826<=">2601>15569 href};spanD1_PE"L27tring">"sdmmc3_dat3_pb4", 926<2p15n c926<="146f="+code=6PIN" cl826<=">2602>15569 href};spanD1_PE"L27tring">"vi_pclk_pt0", 926<3p15n c926<="14e6PIN" class="sref826<=">260P>14=t;),
70 hrefstatic const unsignedrs/pin826<4p15n c926<="14="s6="+code=_6IN" 826<=">260s>14=),
70 hrefstatic const unsignedrs/pin826<5p15n c926<="14/e2_/a>sc#L306" id826<=">2602>14=a(4)
68 hchar *4)
68 href};f">TEGRA_Prsvd2_groupIND1_PE"L271" clrsvd2_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">26<6p15n c926<="146fode=_GPI6s="line826<=">2606>15569 href};spanD1_PE"L27tring">"clk1_out_pw4", 926<7p15n c926<="14q6"sref">tegra30_p826<=">2607>15569 href};spanD1_PE"L27tring">"clk2_out_pw5", 926<8p15n c926<="14="s7g">"7ART3826<=">2608>15569 href};spanD1_PE"L27tring">"clk2_req_pcc5", 926<9p15n c926<="14/e3_/a>sc#L306" id826<=">260t>15569 href};spanD1_PE"L27tring">"clk3_out_pee0", 9261sp15n c926s="15="s6g">"6DMMC926s=">261=>15569 href};spanD1_PE"L27tring">"clk3_req_pee1", 92611p15n c926s="15dat2_/b5_/a>sc#L30926s=">2611>15569 href};spanD1_PE"L27tring">"clk_32k_in", 92612p15n c926s="15n class="s6g">&quo926s=">2612>15569 href};spanD1_PE"L27tring">"clk_32k_out_pa0", 92613p15n c926s="15s6rng">&quo6DMMC3_926s=">2613>15569 href};spanD1_PE"L27tring">"core_pwr_req", 92614p15n c926s="15="s6gg">"6t;LC926s=">2614>15569 href};spanD1_PE"L27tring">"cpu_pwr_req", 92615p15n c926s="15dat1_/b6_/a>sc#L30926s=">2615>15569 href};spanD1_PE"L27tring">"crt_hsync_pv6", 92616p15n c926s="15n class="s6g7">&qu926s=">2616>15569 href};spanD1_PE"L27tring">"crt_vsync_pv7", 92617p15n c926s="15] = {f">TEGRA_PIN_V26s=">2617>15569 href};spanD1_PE"L27tring">"dap3_din_pp1", 92618p15n c926s="15="s6">"G6N1_I826s=">2618>15569 href};spanD1_PE"L27tring">"dap3_dout_pp2", 92619p15n c926s="15dat0_/b7_/a>sc#L30826s=">26st>15569 href};spanD1_PE"L27tring">"dap3_fs_pp0", 9262sp15n c926s="15n class="s6ring">&826s=">262=>15569 href};spanD1_PE"L27tring">"dap3_sclk_pp3", 92621p15n c926s="15s6ring">&qu6t;GMI_826s=">2621>15569 href};spanD1_PE"L27tring">"dap4_din_pp5", 92622p15n c926s="15="s6r">"6DMMC826s=">2622>15569 href};spanD1_PE"L27tring">"dap4_dout_pp6", 92623p15n c926s="15ts_n_pc0_/a>sc#L30826s=">26s3>15569 href};spanD1_PE"L27tring">"dap4_fs_pp4", 92624p15n c926s="15n class="s6rg">&qu826s=">26s4>15569 href};spanD1_PE"L27tring">"dap4_sclk_pp7", 92625p15n c926s="15s6rg">"6DMMC3_826s=">2625>15569 href};spanD1_PE"L27tring">"ddc_scl_pv4", 92626p15n c926s="15="s6"8">"6quot826s=">2626>15569 href};spanD1_PE"L27tring">"ddc_sda_pv5", 92627p15n c926s="151_/c1_/a>sc#L306" 826s=">2627>15569 href};spanD1_PE"L27tring">"gen1_i2c_scl_pc4", 92628p15n c926s="15s="s6r9">"6t;V826s=">26s8>15569 href};spanD1_PE"L27tring">"gen1_i2c_sda_pc5", 92629p15n c926s="15">&qu6t;VI_HSYNC P826s=">262t>15569 href};spanD1_PE"L27tring">"pbb0", 9263sp15n c926s="15="s6ring">&qu6" cl826s=">263=>15569 href};spanD1_PE"L27tring">"pbb7", 92631p15n c926s="15xdCpc2_/a>sc#L306"826s=">2631>15569 href};spanD1_PE"L27tring">"pcc1", 92632p15n c926s="15ass="s6r">"6"826s=">26s2>15569 href};spanD1_PE"L27tring">"pcc2", 92633p15n c926s="15>"6" class="s826s=">2633>15569 href};spanD1_PE"L27tring">"pv0", 926s4p15n c926s="15="s6code=_GPI6" cl826s=">2634>15569 href};spanD1_PE"L27tring">"pv1", 926s5p15n c926s="15xdCpc3_/a>sc#L306"826s=">2635>15569 href};spanD1_PE"L27tring">"pv2", 92636p15n c926s="15ass="s6rng">&quo6"826s=">26s6>15569 href};spanD1_PE"L27tring">"pv3", 926s7p15n c926s="15">"6" class="s826s=">2637>15569 href};spanD1_PE"L27tring">"hdmi_cec_pee3", 926s8p15n c926s="15="s6code=_GPI6" cl826s=">2638>15569 href};spanD1_PE"L27tring">"hdmi_int_pn7", 92639p15n c926s="15c_sclCpc4_/a>sc#L3826s=">263t>15569 href};spanD1_PE"L27tring">"jtag_rtck_pu7", 9264sp15n c926s="15pan class="s6code=826s=">26s=>15569 href};spanD1_PE"L27tring">"pwr_i2c_scl_pz6", 92641p15n c926s="15="s6code=_GPI6" cl826s=">2641>15569 href};spanD1_PE"L27tring">"pwr_i2c_sda_pz7", 92642p15n c926s="15="s6code=_GPI6" cl826s=">2642>15569 href};spanD1_PE"L27tring">"pwr_int_n", 926s3p15n c926s="15c_sdaCpc5_/a>sc#L3826s=">2643>15569 href};spanD1_PE"L27tring">"sdmmc1_clk_pz0", 92644p15n c926s="15pan class="s6cring826s=">26s4>15569 href};spanD1_PE"L27tring">"sdmmc1_cmd_pz1", 92645p15n c926s="15="s6code=_GPI6" cl826s=">26s5>15569 href};spanD1_PE"L27tring">"sdmmc1_dat0_py7", 92646p15n c926s="15="s6c8">"6" cl826s=">2646>15569 href};spanD1_PE"L27tring">"sdmmc1_dat1_py6", 92647p15n c926s="152_/c6_/a>sc#L306" 826s=">2647>15569 href};spanD1_PE"L27tring">"sdmmc1_dat2_py5", 92648p15n c926s="15s="s6c9">"6" c826s=">2648>15569 href};spanD1_PE"L27tring">"sdmmc1_dat3_py4", 92649p15n c926s="15=_GPI6" class="sre826s=">26st>15569 href};spanD1_PE"L27tring">"sdmmc3_dat0_pb7", 9265sp15n c926s="15="s6code=_GPI6" cl826s=">265=>15569 href};spanD1_PE"L27tring">"sdmmc3_dat1_pb6", 92651p15n c926s="15n_pc7_/a>sc#L306" 826s=">2651>15569 href};spanD1_PE"L27tring">"sdmmc4_rst_n_pcc3", 92652p15n c926s="15s="s6code=_GPI6" c826s=">2652>15569 href};spanD1_PE"L27tring">"spdif_out_pk5", 92653p15n c926s="15=_GPI6" class="sre826s=">2653>15569 href};spanD1_PE"L27tring">"sys_clk_req_pz5", 92654p15n c926s="15="s6code=_GPI6" cl826s=">26s4>15569 href};spanD1_PE"L27tring">"uart3_cts_n_pa1", 92655p15n c926s="15dat5_/d0_/a>sc#L30826s=">26s5>15569 href};spanD1_PE"L27tring">"uart3_rxd_pw7", 92656p15n c926s="15n class="s6code=_G826s=">26s6>15569 href};spanD1_PE"L27tring">"uart3_txd_pw6", 92657p15n c926s="15s6c8">"6" clas826s=">26s7>15569 href};spanD1_PE"L27tring">"ulpi_clk_py0", 92658p15n c926s="15="s6code=_GPI6" cl826s=">26s8>15569 href};spanD1_PE"L27tring">"ulpi_dir_py1", 92659p15n c926s="15dat4_/d1_/a>sc#L30826s=">26st>15569 href};spanD1_PE"L27tring">"ulpi_nxt_py2", 9266sp15n c926s="15n class="s6code=_G826s=">26s=>15569 href};spanD1_PE"L27tring">"ulpi_stp_py3", 92661p15n c926s="15s6code=_GPI6" clas826s=">26s1>15569 href};spanD1_PE"L27tring">"vi_d0_pt4", 92662p15n c926s="15="s6code=_GPI6" cl826s=">26s2>15569 href};spanD1_PE"L27tring">"vi_d10_pt2", 92663p15n c926s="15_/d2_/a>sc#L306" i826s=">26s3>15569 href};spanD1_PE"L27tring">"vi_d11_pt3", 92664p15n c926s="15"s6code=_GPI6" cla826s=">26s4>15569 href};spanD1_PE"L27tring">"vi_hsync_pd7", 92665p15n c926s="15GPI6" class="sref"826s=">26s5>15569 href};spanD1_PE"L27tring">"vi_vsync_pd6", 92666p15n c926s="15="s6c8">"6" cl826s=">2666>155t;),
70 hrefstatic const unsignedrs/pin82667p15n c926s="15dat6_/d3_/a>sc#L30826s=">2667>155),
70 hrefstatic const unsignedrs/pin82668p15n c926s="15n class="s6c9">&qu826s=">2668>155a(4)
68 hchar *4)
68 href};f">TEGRA_Prsvd3_groupIND1_PE"L271" clrsvd3_groupI>15pPref[]264" id=9L30sdmmc3_dat1_/b6_/a>shref[] = {f">2669p15n c926s="15s6code=_GPI6" clas826s=">266t>15569 href};spanD1_PE"L27tring">"cam_i2c_scl_pbb1", 9267sp15n c926s="15="s6code=_GPI6" cl826s=">267=>15569 href};spanD1_PE"L27tring">"cam_i2c_sda_pbb2", 92671p15n c926s="15dat7_/d4_/a>sc#L30826s=">26s1>15569 href};spanD1_PE"L27tring">"clk1_out_pw4", 92672p15n c926s="15n class="s6code=_G826s=">2672>15569 href};spanD1_PE"L27tring">"clk1_req_pee2", 92673p15n c926s="15s6code=_GPI6" clas826s=">2673>15569 href};spanD1_PE"L27tring">"clk2_out_pw5", 92674p15n c926s="15="s6code=_GPI6" cl826s=">2674>15569 href};spanD1_PE"L27tring">"clk2_req_pcc5", 92675p15n c926s="15d5_/a>sc#L306" id=826s=">26s5>15569 href};spanD1_PE"L27tring">"clk3_out_pee0", 92676p15n c926s="15ode=_GPI6" class="826s=">2676>15569 href};spanD1_PE"L27tring">"clk3_req_pee1", 92677p15n c92667 href};f">TEGRA_PIN>))2667 >2677>15569 href};spanD1_PE"L27tring">"clk_32k_in", 92678p15n c926s="14="s6">/* All 6on-G826s=">2678>15569 href};spanD1_PE"L27tring">"clk_32k_out_pa0", 92679p15n c926s="14c_/d6_/a>sc#L306" 826s=">26st>15569 href};spanD1_PE"L27tring">"core_pwr_req", 9268sp15n c926s="14s="s67" class=6sre826s=">26s=>15569 href};spanD1_PE"L27tring">"cpu_pwr_req", 92681p15n c926s="14e=off6et" class="s826s=">26s1>15569 href};spanD1_PE"L27tring">"crt_hsync_pv6", 92682p15n c926s="14="s6ss="comme6t">/826s=">26s2>15569 href};spanD1_PE"L27tring">"crt_vsync_pv7", 92683p15n c926s="14c_/d7_/a>sc#L306" 826s=">2683>15569 href};spanD1_PE"L27tring">"dap2_din_pa4", 92684p15n c926s="14s="s67ode=_GPI6PIN826s=">2684>15569 href};spanD1_PE"L27tring">"dap2_dout_pa5", 92685p15n c926s="14=_GPI6PIN" class="826s=">2685>15569 href};spanD1_PE"L27tring">"dap2_fs_pa2", 92686p15n c926s="14="s6"8ing">&q6PIN"826s=">26s6>15569 href};spanD1_PE"L27tring">"dap2_sclk_pa3", 92687p15n c926s="14pe0_/a>sc#L306" id826s=">26s7>15569 href};spanD1_PE"L27tring">"ddc_scl_pv4", 92688p15n c926s="14679ing">&q6PIN" cl826s=">26s8>15569 href};spanD1_PE"L27tring">"ddc_sda_pv5", 92689p15n c926s="14=6PIN" class="sref826s=">26st>15569 href};spanD1_PE"L27tring">"gen1_i2c_scl_pc4", 9269sp15n c926s="14="s6f="+code=6PIN"826s=">26s=>15569 href};spanD1_PE"L27tring">"gen1_i2c_sda_pc5", 92691p15n c926s="14/e1_/a>sc#L306" id826s=">26s1>15569 href};spanD1_PE"L27tring">"pbb0", 92692p15n c926s="146f="+code=6PIN" cl826s=">26s2>15569 href};spanD1_PE"L27tring">"pbb7", 92693p15n c926s="14e6PIN" class="sref826s=">26s3>15569 href};spanD1_PE"L27tring">"pcc1", 92694p15n c926s="14="s6="+code=_6IN" 826s=">26s4>15569 href};spanD1_PE"L27tring">"pcc2", 92695p15n c926s="14/e2_/a>sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27tring">"pv0", 92696p15n c926s="146fode=_GPI6s="line826s=">26s6>15569 href};spanD1_PE"L27tring">"pv1", 92697p15n c926s="14q6"sref">tegra30_p826s=">26s7>15569 href};spanD1_PE"L27tring">"pv2", 92698p15n c926s="14="s7g">"7ART3826s=">26s8>15569 href};spanD1_PE"L27tring">"pv3", 92699p15n c926s="14/e3_/a>sc#L306" id826s=">26st>15569 href};spanD1_PE"L27tring">"hdmi_cec_pee3", 927sc#L306" id827270=>15569 href};spanD1_PE"L27tring">"hdmi_int_pn7", 927<1p15n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD1_PE"L27tring">"jtag_rtck_pu7", 927<2p15n c927<="146f="+code=6PIN" cl827<=">2702>15569 href};spanD1_PE"L27tring">"kb_row0_pr0", 927<3p15n c927<="14e6PIN" class="sref827<=">2703>15569 href};spanD1_PE"L27tring">"kb_row1_pr1", 927<4p15n c927<="14="s6="+code=_6IN" 827<=">2704>15569 href};spanD1_PE"L27tring">"kb_row2_pr2", 927<5p15n c927<="14/e2_/a>sc#L306" id827<=">2705>15569 href};spanD1_PE"L27tring">"kb_row3_pr3", 927<6p15n c927<="146fode=_GPI6s="line827<=">2706>15569 href};spanD1_PE"L27tring">"lcd_d0_pe0", 927<7p15n c927<="14q6"sref">tegra30_p827<=">2707>15569 href};spanD1_PE"L27tring">"lcd_d1_pe1", 927<8p15n c927<="14="s7g">"7ART3827<=">2708>15569 href};spanD1_PE"L27tring">"lcd_d10_pf2", 927<9p15n c927<="14/e3_/a>sc#L306" id827<=">270t>15569 href};spanD1_PE"L27tring">"lcd_d11_pf3", 9271sp15n c927s="15="s6g">"6DMMC927s=">271=>15569 href};spanD1_PE"L27tring">"lcd_d12_pf4", 9227tring">n c926s="15c_sdaCpcv7"9268sp15n c926s="14s="s67" class=6sre826s=">26s=>15569 href};spanD1_PE"L27tring">"cpu_pwr_req"2701>15569 href};spanlVSYNC_58,
70 htring">"crt_hsync_pv6", 92617p15n c92aCpcv7"92619p1El"RA5c22class="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c22class="s6g"337>92619"L27tring"2="s6g">927<8p15n c927<="14="s7g">"7ART3827<=">2708>15569 22span class="s6g">92"92",class="s6c9">&qu825s5YNC_PD6, 92629p15n c926s="1lVSYNC_58,
70 htring">"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c22clasEl"RA5c22class="s6g"337>92626p15n c926s="15="s6"8">"6quot826n c927<="14/e3_/a>sc#L306" id827<=">270t>15569 href};spanD1_PEPE"L27trin7">"dap3_din_pp1"7, "6DMMC927s=">271=>15569 href};spanD1_PEE"L27tring7>"dap3_dout_pp2"7, n c926s="15c_sdaCpcv7"">"dap3_fs_pp0"7/span7l"RA_PIN_VI_VSYNC_PD6, , "cpu_pwr_req"270PE"L27trin7">"dap4_din_pp5"7, 92617p15n c92aCpcv7""dap4_dout_pp6"7, 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c22cPE"L27trin7">"dap4_fs_pp4"7/span7l"RA_PIN_VI_VSYNC_PD6, 92"92", sc#L306" id827<=">2701>15569 href};spanD1_PPE"L27trin7">"ddc_scl_pv4"7/span7l"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"270P"s6g"337>9"ddc_sda_pv5", 92617p15n c92aCpcv7", 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c22cP"L27tring7ing">"gen1_i2c_sda_p75&quo7;, 92"92"ing">"pbb0", ot6qu882f">"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22classng">"7bb7", 92631p15n c9ot6qu982fn c927<="14/e3_/a>sc#L306" id827<=">270t>15569 href};spanD1_PEng">"7cc1", 92632p15n c9ot6qucsp1nlass="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c22cng">"7cc2", 92633p15n c9ot6quctri>92527p15n c925s="151_/c1_/a>sc#L306" 825s=">2527>15569 href};7ng">"7v0", 926s4p15n c92ot6que_pjn c927<="14/e3_/a>sc#L306" id827<=">270t>15569 href};spanD1_PEnL27tring"71", 926s5p15n c926ot6q">92683j5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD1_Pg">"p72", 92636p15n c926ot6qmtriwn c927<="14/e3_/a>sc#L306" id827<=">270t>15569 href};spanD1_PEn"s6g"337>93", 926s7p15n c926ot6qp688p1b5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD1_PgE"L27trin7mi_cec_pee3", 926sot6qpwrtris="14/e2_/a>sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27tr7PE"L27trin7">"hdmi_int_pn7"7, "cpu_pwr_req"270E"L27tring7>"jtag_rtck_pu7"7, "cpu_pwr_req"270Eg">"7">"pwr_i2c_scl_pz6&q7ot;, 925pan clclass="s6g">92527p15n c925s="151_/c1_/a>sc#L306" 825s=">2527>15569 href};71_PE"L27tr7ng">"pwr_i2c_sda_pz77quot;7/spanEl"RA_PIN_VI_VSYNC_PD6, 92">"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22class1_PE"L27tr7ng">"pwr_int_n"7/span7l"RA_PIN_VI_VSYNC_PD6, &7uot;sdmmc1_clk_pz0"<7spanE7"RA_PIN_VI_VSYNC_PD6, lass="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c22c_PE"L27tri7g">"sdmmc1_cmd_pz1&q7ot;, 92href};spanD1_PE"L27tring">"cpu_pwr_req"270_PE"L27tri7g">"sdmmc1_dat0_py7&7uot;<7spanEl"RA_PIN_VI_VSYNC_PD6, , 92617p15n c92aCpcv7""sdmmc1_dat1_py67quot;7/spanEl"RA_PIN_VI_VSYNC_PD6, "sdmmc1_dat2_py57quot;7/spanEl"RA_PIN_VI_VSYNC_PD6, 925n c925s="14="s6="+code=_6IN" 825s=">25s4>15569 href};spanD1_71E"L27trin7ng">"sdmmc1_dat3_py47quot;7IN_VI_VSYNC_PD6, 925lass="g">92653plass="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c22c_"L27tring7ng">"sdmmc3_dat0_pb77quot;7/spanEl"RA_PIN_VI_VSYNC_PD6, 925n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD1_P1_PE"L27tr7ng">"sdmmc3_dat1_pb67quot;7/spanEl"RA_PIN_VI_VSYNC_PD6, 92642p15n c926s="15="s6code=_GPI6" cl826s=">2642>15569 href};span71_PE"L27tr7ng">"sdmmc4_rst_n_pc73&quo7;, 926s3p15n c926s="15c_sdaCpc5_/a>sc#L3826s=">2643>15569 href};spanD1_PE"7nD1_PE"L277ring">"spdif_out_pk57quot;7/spanEl"RA_PIN_VI_VSYNC_PD6, 92644p15n c926s="15pan class="s6cring826s=">26s4>15569 href};spanD7PE"L27trin7">"sys_clk_req_pz5&q7ot;, 92645p15n c926s="15="s6code=_GPI6" cl826s=">26s5>15569 href};spanD71_PE"L27tr7ng">"uart3_cts_n_pa17quot;7/spanEl"RA_PIN_VI_VSYNC_PD6, 92646p15n c926s="15="s6c8">"6" cl826s=">2646>15569 href};span71_PE"L27tr7ng">"uart3_rxd_pw7&q7ot;, 92653p15n c926s="15=_GPI6" class="sre826s=">2653>15569 href};spanD17PE"L27trin7">"uart3_txd_pw6&quo7;"6" clas825s=">2557>15592655p15n c926s="15dat5_/d0_/a>sc#L30826s=">26s5>15569 href};span7PE"L27trin7">"ulpi_clk_py0"7TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group7E"L27tring7>"ulpi_dir_py1"7/span7ref[] = {f">2559p15n c925s="15dat4_/d1_/a>sc#L30825s7E"L27tring7>"ulpi_nxt_py2"7/span7t;gmi_ad11_ph3"4D6, 4267sp15n c926s="15="s6code=_GPI6" cl826s=">267=>15569 href};spa7E"L27tring7>"ulpi_stp_py3"7/span7l"RA_PIN_VI_VSYNC_PD6, 92673p15n c926s="15s6code=_GPI6" clas826s=">2673>15569 href};spanD17E"L27tring7>"vi_d0_pt4", 92674p15n c926s="15="s6code=_GPI6" cl826s=">2674>15569 href};spanD1_727tring">&7uot;vi_d10_pt2", 9s6g">92675p15n c926s="15d5_/a>sc#L306" id=826s=">26s5>15569 href};spanD17L27tring">7quot;vi_d11_pt3", "s6g">92676p15n c926s="15ode=_GPI6" class="826s=">2676>15569 href};spanD17L27tring">7quot;vi_hsync_pd7", 92677p15n c92667 href};f">TEGRA_PIN>))2667 >2677>15569 href};spanD17E"L27tring7>"vi_vsync_pd6"7/span7l"RA_PIN_VI_VSYNC_PD6, 92678p15n c926s="14="s6">/* All 6on-G826s=">2678>15569 href};spanD1_PE7efstatic c7nst unsignedrs/pin82667p17n c927s="15dat6_/d3_/a>sc#L30826s=">2667>15592679p15n c926s="14c_/d6_/a>sc#L306" 826s=">26st>15569 href};span7">&qu826s=7>2668>155a(4)
68 hcha7 *4)
76RA_PIN_VI_VSYNC_PD6, 6g">9268sp15n c926s="14s="s67" class=6sre826s=">26s=>15569 href};spanD1_7pI>15pPref7]264" id=9L30sdmmc3_dat1_7b6_/a76l"RA_PIN_VI_VSYNC_PD6, 92681p15n c926s="14e=off6et" class="s826s=">26s1>15569 href};spanD1_P7s=">266t>17569 href};spanD1_PE"L27tr7ng">&76nEl"RA_PIN_VI_VSYNC_PD6, 92682p15n c926s="14="s6ss="comme6t">/826s=">26s2>15569 href};spanD17D1_PE"L27t7ing">"cam_i2c_sda_pb72&quo7;, 92683p15n c926s="14c_/d7_/a>sc#L306" 826s=">2683>15569 href};spanD17D1_PE"L27t7ing">"clk1_out_pw4&q7ot;, 92684p15n c926s="14s="s67ode=_GPI6PIN826s=">2684>15569 href};spanD1_7E"L27tring7>"clk1_req_pee2"7, 92623p15n c926s="15ts_n_pc0_/a>sc#L30826s=">26s3>15569 href};spanD17PE"L27trin7">"clk2_out_pw5"7, 92624p15n c926s="15n class="s6rg">&qu826s=">26s4>15569 href};spanD1_P7E"L27tring7>"clk2_req_pcc5"7, 92625p15n c926s="15s6rg">"6DMMC3_826s=">2625>15569 href};spanD17PE"L27trin7">"clk3_out_pee0&quo7;, 92626p15n c926s="15="s6"8">"6quot826s=">2626>15569 href};spanD1_P7PE"L27trin7">"clk3_req_pee1&quo7;, 26st>15569 href};spanD1_P7PE"L27trin7">"clk_32k_in"<7spanE7"RA_PIN_VI_VSYNC_PD6, 9269sp15n c926s="14="s6f="+code=6PIN"826s=">26s=>15569 href};spa7L27tring">7quot;clk_32k_out_pa0"7, 92691p15n c926s="14/e1_/a>sc#L306" id826s=">26s1>15569 href};spa71_PE"L27tr7ng">"core_pwr_req&qu7t;, "cpu_pwr_req"<7spanE7RA_PIN_VI_VSYNC_PD6, 92t="146f="+code=6PIN" cl826s=">26s2>15569 href};spanD1_PE"L27tr7"L27tring"7"crt_hsync_pv6"7/span7l"RA_PIN_VI_VSYNC_PD6, &qu826s=">26s4>15569 href};spanD1_P7PE"L27trin7">"crt_vsync_pv7&quo7;, 9o982kn c926s="15="s6"8">"6quot826s=">2626>15569 href};spanD1_P7PE"L27trin7">"dap2_din_pa4"7, a8p15g5n c926s="14s="s67" class=6sre826s=">26s=>15569 href};spanD1_7E"L27tring7>"dap2_dout_pa5"7, /* All 6on-G826s=">2678>15569 href};spanD1_PE7PE"L27trin7">"dap2_fs_pa2"7/span7nEl"RA_PIN_VI_VSYNC_PD6, , 2653>15569 href};spanD17PE"L27trin7">"ddc_scl_pv4"7/span7nEl"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26s1>15569 href};spa7"L27tring"7"ddc_sda_pv5", aC_PD6h="146f="+code=6PIN" cl826s=">26s2>15569 href};spanD1_PE"L27tr7"_PE"L27tr7"gen1_i2c_scl_pc4&qu7t;, aA5c22hn c926s="15n class="s6rg">&qu826s=">26s4>15569 href};spanD1_P7P"L27tring7ing">"gen1_i2c_sda_p75&quo7El"RA_PIN_VI_VSYNC_PD6, "6quot826s=">2626>15569 href};spanD1_P7D1_PE"L27t7ing">"pbb0", au569g5n c926s="15="s6code=_GPI6" cl826s=">2674>15569 href};spanD1_7ng">"7bb7", auPD6g15n c926s="15=_GPI6" class="sre826s=">2653>15569 href};spanD17ng">"7cc1", auc22g91p15n c926s="14/e1_/a>sc#L306" id826s=">26s1>15569 href};spa7ng">"7cc2", 92595p15nau9 2g="146f="+code=6PIN" cl826s=">26s2>15569 href};spanD1_PE"L27tr7ng">"7v0", 92696p15n c92p15nau6 2gn c926s="15n class="s6rg">&qu826s=">26s4>15569 href};spanD1_P7g">"p71", 92697p15n c926p15nau7 2gn c926s="15="s6"8">"6quot826s=">2626>15569 href};spanD1_P7DE"L27trin72", 92698p15n c926p15nau8 2h5n c926s="14s="s67" class=6sre826s=">26s=>15569 href};spanD1_7g">"p73", 92699p15n c926p15nau982h c926s="14="s6">/* All 6on-G826s=">2678>15569 href};spanD1_PE7g">"h7mi_cec_pee3", 92726s=>15569 href};spanD1_7g"L27tring7">"hdmi_int_pn7"7, /* All 6on-G826s=">2678>15569 href};spanD1_PE8E"L27tring8>"jtag_rtck_pu7"8, 2653>15569 href};spanD18PE"L27trin8">"kb_row0_pr0"8/span8l"RA_PIN_VI_VSYNC_PD6, , , , i c926s="14="s6">/* All 6on-G826s=">2678>15569 href};spanD1_PE8E527tring"8&", 9265i91p15n c926s="14/e1_/a>sc#L306" id826s=">26s1>15569 href};spa8L27tring">8quot;lcd_d1_pe1", p15nwait65in c926s="15="s6"8">"6quot826s=">2626>15569 href};spanD1_P8L27tring">8quot;lcd_d10_pf2", 26s=>15569 href};spanD1_8"L27tring"8"lcd_d11_pf3", 26s6>15569 href};spanD1_PE"L27tri8"L27tring"8"lcd_d12_pf4", 26s=>15569 href};spanD1_8anEltring88ing"pf42nEltr236class="s68">9268sp15n c926s="14s="s67" class=6sre826s=">2pu c926s="14="s6">/* All 6on-G826s=">2678>15569 href};spanD1_PE81>15569 hr8f};spanlVSYNC_58,
70 htri8g">&q8ot;crt_hsync_pv6"26s6>15569 href};spanD1_PE"L27tri8c22class="86g">92619p1El"RA5c22class8"s6g"837>92619p1El"RA5c22class="s6g"337>92619p1pu15n c926s="15=_GPI6" class="sre826s=">2653>15569 href};spanD18lass="s6g"837>92619"L27tring"2="s6g"8927<8815n c927<="14="s7g">"7ART3827<=">270pu91p15n c926s="14/e1_/a>sc#L306" id826s=">26s1>15569 href};spa8sa>,class=8s6c9">&qu825s5YNC_PD68 92629p15n c926s="1lVSYNC_58,pu="146f="+code=6PIN" cl826s=">26s2>15569 href};spanD1_PE"L27tr8="s6g"337>82619p1El"RA5c22clasEl"RA5822cla8s="s6g"337>92626p15n c926s="15="s6"8">&qupun c926s="15n class="s6rg">&qu826s=">26s4>15569 href};spanD1_P8PE"L27trin8">"dap3_din_pp1"8, tegra30_p826s=">26s7>15569 href};spanD1_PE"L27tri8E"L27tring8>"dap3_dout_pp2"8, "7ART3826s=">26s8>15569 href};spanD1_PE"L27tri8aL27tring"8">"dap3_fs_pp0"8/span8l"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26st>15569 href};spanD1_PE"L27tri8"L27tring"8"dap3_sclk_pp3"8/span8l"RA_PIN_VI_VSYNC_PD6, 270=>15569 href};spanD18PE"L27trin8">"dap4_din_pp5"8, 927<1p15n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD1_8E"L27tring8>"dap4_dout_pp6"8, 927<2p15n c927<="146f="+code=6PIN" cl827<=">2702>15569 href};spanD18PE"L27trin8">"dap4_fs_pp4"8/span8l"RA_PIN_VI_VSYNC_PD6, 927<3p15n c927<="14e6PIN" class="sref827<=">2703>15569 href};spanD1_P8"L27tring"8"dap4_sclk_pp7"8/span8l"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26st>15569 href};spanD1_PE"L27tri8PE"L27trin8">"ddc_scl_pv4"8/span8l"RA_PIN_VI_VSYNC_PD6, 8"ddc_sda_pv5", , "gen1_i2c_sda_p85&quo8;, 927<4p15n c927<="14="s6="+code=_6IN" 827<=">2704>15569 href};spanD1_P8"L27tring"8ing">"pbb0", ">927<5p15n c927<="14/e2_/a>sc#L306" id827<=">2705>15569 href};spanD1_P8ng">"8bb7", 92631p15n c9">927<6p15n c927<="146fode=_GPI6s="line827<=">2706>15569 href};spanD1_P8ng">"8cc1", 92632p15n c9">927<4"sr91p15n c926s="14/e1_/a>sc#L306" id826s=">26s1>15569 href};spa8ng">"8cc2", 92633p15n c9ot6qcs09265n91p15n c926s="14/e1_/a>sc#L306" id826s=">26s1>15569 href};spa8nE"L27trin8v0", 926s4p15n c92ot6qcs19265wn c927<="14="s6="+code=_6IN" 827<=">2704>15569 href};spanD1_P8nL27tring"81", 926s5p15n c926ot6q8p15n c927<="14="s7g">"7ART3827<=">2708>15569 href};spanD1_PE8g">"p82", 92636p15n c926ot6q<9p15n c927<="14/e3_/a>sc#L306" id827<=">270t>15569 href};spanD1_P8n"s6g"337>83", 926s7p15n c926ot6q71sp15n c927s="15="s6g">"6DMMC927s=">271=>15569 href};spanD1_P8gE"L27trin8mi_cec_pee3", 926sot6q27tring">n c926s="15c_sdaCpcv7""hdmi_int_pn7"8, "cpu_pwr_req"278E"L27tring8>"jtag_rtck_pu7"8, 92617p15n c92aCpcv7""8">"pwr_i2c_scl_pz6&q8ot;, 92El"RA5c22class="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c2281_PE"L27tr8ng">"pwr_i2c_sda_pz78quot;8/spanEl"RA_PIN_VI_VSYNC_PD6, 15569 22span class="s6g">92"92""pwr_int_n"8/span8l"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22clas827tring">&8uot;sdmmc1_clk_pz0"<8spanE8"RA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">270t>15569 href};spanD1_P8_PE"L27tri8g">"sdmmc1_cmd_pz1&q8ot;, "6DMMC927s=">271=>15569 href};spanD1_P8_PE"L27tri8g">"sdmmc1_dat0_py7&8uot;<8spanEl"RA_PIN_VI_VSYNC_PD6, n c926s="15c_sdaCpcv7""sdmmc1_dat1_py68quot;8/spanEl"RA_PIN_VI_VSYNC_PD6, "sdmmc1_dat2_py58quot;8/spanEl"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"2781E"L27trin8ng">"sdmmc1_dat3_py48quot;8IN_VI_VSYNC_PD6, 92ot6qu5trim/a>, 92617p15n c92aCpcv7""sdmmc3_dat0_pb78quot;8/spanEl"RA_PIN_VI_VSYNC_PD6, 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c2281_PE"L27tr8ng">"sdmmc3_dat1_pb68quot;8/spanEl"RA_PIN_VI_VSYNC_PD6, 92"92""sdmmc4_rst_n_pc83&quo8;, "spdif_out_pk58quot;8/spanEl"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"278PE"L27trin8">"sys_clk_req_pz5&q8ot;, , 92617p15n c92aCpcv7""uart3_cts_n_pa18quot;8/spanEl"RA_PIN_VI_VSYNC_PD6, 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c2281_PE"L27tr8ng">"uart3_rxd_pw7&q8ot;, 92"92""uart3_txd_pw6&quo8;"6" clas825s=">2557>155"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22clas8PE"L27trin8">"ulpi_clk_py0"8, sc#L306" id827<=">270t>15569 href};spanD1_P8E"L27tring8>"ulpi_dir_py1"8/span8l"RA_PIN_VI_VSYNC_PD6, 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c228E"L27tring8>"ulpi_nxt_py2"8/span8l"RA_PIN_VI_VSYNC_PD6, sc#L306" 825s=">2527>15569 href};8E"L27tring8>"ulpi_stp_py3"8/span8l"RA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">270t>15569 href};spanD1_P8E"L27tring8>"vi_d0_pt4", 92683j5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD1_827tring">&8uot;vi_d10_pt2", 9ot6qmtriwn c927<="14/e3_/a>sc#L306" id827<=">270t>15569 href};spanD1_P8L27tring">8quot;vi_d11_pt3", ot6qp688p1b5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD1_8L27tring">8quot;vi_hsync_pd7", sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27tr8E"L27tring8>"vi_vsync_pd6"8/span8l"RA_PIN_VI_VSYNC_PD6, sc#L306" 825s=">2527>15569 href};8efstatic c8nst unsignedrs/pin82667p18n c928s="15dat6_/d3_/a>sc#L30826s=">2667>15592684pjhref};spanD1_PE"L27tring">"cpu_pwr_req"278">&qu826s=8>2668>155a(4)
68 hcha8 *4)
86RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"278pI>15pPref8]264" id=9L30sdmmc3_dat1_8b6_/a86l"RA_PIN_VI_VSYNC_PD6, 92527p15n c925s="151_/c1_/a>sc#L306" 825s=">2527>15569 href};8s=">266t>18569 href};spanD1_PE"L27tr8ng">&86nEl"RA_PIN_VI_VSYNC_PD6, 92">"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22clas8D1_PE"L27t8ing">"cam_i2c_sda_pb82&quo8;, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27tr8D1_PE"L27t8ing">"clk1_out_pw4&q8ot;, lass="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c228E"L27tring8>"clk1_req_pee2"8, 92href};spanD1_PE"L27tring">"cpu_pwr_req"278PE"L27trin8">"clk2_out_pw5"8, , 92617p15n c92aCpcv7""clk2_req_pcc5"8, "clk3_out_pee0&quo8;, 925n c925s="14="s6="+code=_6IN" 825s=">25s4>15569 href};spanD1_8PE"L27trin8">"clk3_req_pee1&quo8;, 92653plass="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c228PE"L27trin8">"clk_32k_in"<8spanE8"RA_PIN_VI_VSYNC_PD6, 925n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD1_8L27tring">8quot;clk_32k_out_pa0"8, 92642p15n c926s="15="s6code=_GPI6" cl826s=">2642>15569 href};span81_PE"L27tr8ng">"core_pwr_req&qu8t;, 926s3p15n c926s="15c_sdaCpc5_/a>sc#L3826s=">2643>15569 href};spanD1_PE"8E"L27tring8>"cpu_pwr_req"<8spanE8RA_PIN_VI_VSYNC_PD6, 92644p15n c926s="15pan class="s6cring826s=">26s4>15569 href};spanD8"L27tring"8"crt_hsync_pv6"8/span8l"RA_PIN_VI_VSYNC_PD6, sc#L3826s=">2643>15569 href};spanD1_PE"8PE"L27trin8">"crt_vsync_pv7&quo8;, 92655p15n c926s="15dat5_/d0_/a>sc#L30826s=">26s5>15569 href};span8PE"L27trin8">"dap2_din_pa4"8, a="14/e2_/a>sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27tr8E"L27tring8>"dap2_dout_pa5"8, c">"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22clas8PE"L27trin8">"dap2_fs_pa2"8/span8nEl"RA_PIN_VI_VSYNC_PD6, sc#L3826s=">2643>15569 href};spanD1_PE"8PE"L27trin8"dap2_sclk_pa3"8/span8nEl"RA_PIN_VI_VSYNC_PD6, "ddc_scl_pv4"8/span8nEl"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"278"L27tring"8"ddc_sda_pv5", sc#L30826s=">26s5>15569 href};span8P_PE"L27tr8"gen1_i2c_scl_pc4&qu8t;, sc#L306" 825s=">2527>15569 href};8P"L27tring8ing">"gen1_i2c_sda_p85&quo8El"RA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">2701>15569 href};spanD1_8D1_PE"L27t8ing">"pbb0", "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22clas8ng">"8bb7", "8cc1", "8cc2", 92595viq85"sl5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD1_8DE"L27trin8v0", 92696p15n c92viq86"slhref};spanD1_PE"L27tring">"cpu_pwr_req"278g">"p81", 92697p15n c926viq87"sl5p15n c926s="15dat5_/d0_/a>sc#L30826s=">26s5>15569 href};span8DE"L27trin82", 92698p15n c926viq88"sl2p15n c926s="15="s6code=_GPI6" cl826s=">2642>15569 href};span8g">"p83", 92699p15n c926viq89"slc926s="15c_sdaCpc5_/a>sc#L3826s=">2643>15569 href};spanD1_PE"8g">"h8mi_cec_pee3", 9279268325n c925s="14="s6="+code=_6IN" 825s=">25s4>15569 href};spanD1_8g"L27tring8">"hdmi_int_pn7"8, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22clas9E"L27tring9>"jtag_rtck_pu7"9, 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c229PE"L27trin9">"kb_row0_pr0"9/span9l"RA_P};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9"L27tring"9"kb_row1_pr1"TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9"327tring"9&c2", , 927<3p15n c927<="14e6PIN" class="sref827<=">2703>15569 href};spanD1_P9E527tring"9&"TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9"627tring"9&"TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9"727tring"9&", , sc#L306" id827<=">2701>15569 href};spanD1_9"L27tring"9"lcd_d12_pf4"TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9anEltring89ing"pf42nEltr236class="s69">9269sp15n f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9aE"L27trin9f};spanlVSYNC_58,
70 htri9g">&q9ot;crtad11_ph3", ,_PIN26s="15="s6code=_GPI6" cl826s=">267=>15569 href};spa9c22class="96g">92619p1El"RA5c22class9"s6g"937>92619p1El"RA5c22class="s6g"337>92619p1s="s6g">92645p15n c926s="15="s6code=_GPI6" cl826s=">26s5>15569 href};spanD9lass="s6g"937>92619"L27tring"2="s6g"9927<8915n c927<="14="s7g">"7ART3827<=">270as="s6g">92646p15n c926s="15="s6c8">"6" cl826s=">2646>15569 href};span9sa>,class=9s6c9">&qu825s5YNC_PD69 92629p15n c926s="1lVSYNC_58,as="s6gdatp15yn c927<="14e6PIN" class="sref827<=">2703>15569 href};spanD1_P9="s6g"337>92619p1El"RA5c22clasEl"RA5922cla9s="s6g"337>92626p15n c926s="15="s6"8">&quas="s6gdattriylass="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c229PE"L27trin9">"dap3_din_pp1"9, sc#L30826s=">26s5>15569 href};span9E"L27tring9>"dap3_dout_pp2"9, "cpu_pwr_req"279aL27tring"9">"dap3_fs_pp0"9/span9l"RA_P};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9aL27tring"9"dap3_sclk_pp3"9/span9l"RA_Pf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9PE"L27trin9">"dap4_din_pp5"9"dap4_dout_pp6"9, "6" cl826s=">2646>15569 href};span9PE"L27trin9">"dap4_fs_pp4"9/span9l"RA_PIN_VI_VSYNC_PD6, sc#L306" 825s=">2527>15569 href};9"L27tring"9"dap4_sclk_pp7"9/span9l"RA_PIN_VI_VSYNC_PD6, "ddc_scl_pv4"9/span9l"RA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">2701>15569 href};spanD1_9E"s6g"337>9"ddc_sda_pv5", sc#L306" 825s=">2527>15569 href};9"E"L27trin9"gen1_i2c_scl_pc4&qu9t;, "gen1_i2c_sda_p95&quo9;, 927<5569shref};spanD1_PE"L27tring">"cpu_pwr_req"279"L27tring"9ing">"pbb0", ">927<53"ss5p15n c926s="15dat5_/d0_/a>sc#L30826s=">26s5>15569 href};span9ng">"9bb7", 92631p15n c9">927<5c22slass="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c229ng">"9cc1", 92632p15n c9">927<69 2sn c927<="14e6PIN" class="sref827<=">2703>15569 href};spanD1_P9ng">"9cc2", 92633p15n c9">927<6_prlass="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c229nE"L27trin9v0", 926s4p15n c92">927<7_prn c927<="14e6PIN" class="sref827<=">2703>15569 href};spanD1_P9nL27tring"91", 926s5p15n c926">927<8 2sp15n c926s="15="s6code=_GPI6" cl826s=">26s5>15569 href};spanD9g">"p92", 92636p15n c926">927<9 2s6p15n c926s="15="s6c8">"6" cl826s=">2646>15569 href};span9n"s6g"337>93", 926s7p15n c926spdif_2623klass="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c229nE"L27trin9mi_cec_pee3", 926sspdif_624p1k5p15n c926s="15dat5_/d0_/a>sc#L30826s=">26s5>15569 href};span9PE"L27trin9">"hdmi_int_pn7"9, sc#L30826s=">26s5>15569 href};span9E"L27tring9>"jtag_rtck_pu7"9, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22clas9Eg">"9">"pwr_i2c_scl_pz6&q9ot;, 92viq83"sl="14/e2_/a>sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27tr91_PE"L27tr9ng">"pwr_i2c_sda_pz79quot;9/spanEl"RA_PIN_VI_VSYNC_PD6, "pwr_int_n"9/span9l"RA_PIN_VI_VSYNC_PD6, &9uot;sdmmc1_clk_pz0"<9spanE9"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"279_PE"L27tri9g">"sdmmc1_cmd_pz1&q9ot;, 26s5>15569 href};span9_PE"L27tri9g">"sdmmc1_dat0_py7&9uot;<9spanEl"RA_PIN_VI_VSYNC_PD6, "sdmmc1_dat1_py69quot;9/spanEl"RA_PIN_VI_VSYNC_PD6, 2643>15569 href};spanD1_PE"91_PE"L27tr9ng">"sdmmc1_dat2_py59quot;9/spanEl"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22clas91E"L27trin9ng">"sdmmc1_dat3_py49quot;9IN_VI_};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9_"L27tring9ng">"sdmmc3_dat0_pb79quot;9/spanEf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9_g">"9ng">"sdmmc3_dat1_pb69quot;9/spanEad11_ph3", ,_PIN26s="15="s6code=_GPI6" cl826s=">267=>15569 href};spa91_PE"L27tr9ng">"sdmmc4_rst_n_pc93&quo9;, "spdif_out_pk59quot;9/spanEl"RA_PIN_VI_VSYNC_PD6, sc#L3826s=">2643>15569 href};spanD1_PE"9PE"L27trin9">"sys_clk_req_pz5&q9ot;, sc#L3826s=">2643>15569 href};spanD1_PE"9PPE"L27tri9ng">"uart3_cts_n_pa19quot;9/spanEl"RA_PIN_VI_VSYNC_PD6, "uart3_rxd_pw7&q9ot;, 26s5>15569 href};span9PE"L27trin9">"uart3_txd_pw6&quo9;"6" clas825s=">2557>155"cpu_pwr_req"279PE"L27trin9">"ulpi_clk_py0"9, "ulpi_dir_py1"9/span9l"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22clas9E"L27tring9>"ulpi_nxt_py2"9/span9l"RA_PIN_VI_VSYNC_PD6, "ulpi_stp_py3"9/span9l"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"279E"L27tring9>"vi_d0_pt4"TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group927tring">&9uot;vi_d10_pt2"TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group92E"L27trin9quot;vi_d11_pt3"9quot;vi_hsync_pd7", 926bb="14/e2_/a>sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27tr9E"L27tring9>"vi_vsync_pd6"9/span9l"RA_PIN_VI_VSYNC_PD6, sc#L30826s=">2667>155"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22clas9">&qu826s=9>2668>155a(4)
68 hcha9 *4)
96RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22clas9""L27tring9]264" id=9L30sdmmc3_dat1_9b6_/a96l"RA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">2701>15569 href};spanD1_9s=">266t>19569 href};spanD1_PE"L27tr9ng">&96nEl"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"279D1_PE"L27t9ing">"cam_i2c_sda_pb92&quo9;, 26s5>15569 href};span9D1_PE"L27t9ing">"clk1_out_pw4&q9ot;, "clk1_req_pee2"9, sc#L3826s=">2643>15569 href};spanD1_PE"9PE"L27trin9">"clk2_out_pw5"9, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27tr9E"L27tring9>"clk2_req_pcc5"9, "cpu_pwr_req"279PE"L27trin9">"clk3_out_pee0&quo9;, 926tc926s="15c_sdaCpc5_/a>sc#L3826s=">2643>15569 href};spanD1_PE"9Pfstatic c9">"clk3_req_pee1&quo9;, 26s=>15569 href};spanD1_9PE"L27trin9">"clk_32k_in"<9spanE9"RA_PIN_VI_VSYNC_PD6, , "core_pwr_req&qu9t;, "cpu_pwr_req"<9spanE9RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"279"L27tring"9"crt_hsync_pv6"9/span9l"RA_PIN_VI_VSYNC_PD6, 26s5>15569 href};span9PE"L27trin9">"crt_vsync_pv7&quo9;, "dap2_din_pa4"9, 2643>15569 href};spanD1_PE"9E"L27tring9>"dap2_dout_pa5"9, 92653p5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD1_9PE"L27trin9">"dap2_fs_pa2"9/span9nEl"RA};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9PE"L27trin9"dap2_sclk_pa3"9/span9nEl"RAf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9PE"L27trin9">"ddc_scl_pv4"9/span9nEl"RAad11_ph3", , , "cpu_pwr_req"279P"L27tring9ing">"gen1_i2c_sda_p95&quo9El"RA_PIN_VI_VSYNC_PD6, 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c229D1_PE"L27t9ing">"pbb0", sc#L30826s=">26s5>15569 href};span9ng">"9bb7", sc#L306" id827<=">2701>15569 href};spanD1_9ng">"9cc1", 26s6>15569 href};spanD1_PE"L27tri9ng">"9cc2"TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9DE"L27trin9v0"TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_group9DE"L27trin91", , 92698p15n c926spi6gcs09265xlass="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c229DL27tring"93", 92699p15n c926spi1_miso_pxc926s="15c_sdaCpc5_/a>sc#L3826s=">2643>15569 href};spanD1_PE"9g">"h9mi_cec_pee3", 927"cpu_pwr_req"279g"L27tring9">"hdmi_int_pn7"9, sc#L30826s=">26s5>15569 href};spa30E"L27trin30E"L2uot;hdmi_int_pn7&quo30E"L>30E"RA_PIN_VI_VSYNC_PD6, at5_/d0_/a>sc#L30826s=">26s5>15569 href};spa30E1L27trin30Eb7"30E"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t30E2L27trin30Ec1"30E"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr30E3L27trin30Ec2"30EEl"RA_PIN_VI_VSYNC_PD6, 30EEl"RA};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou30E5L27trin30E"30EEl"RAf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou30E6L27trin30E"30EEl"RAad11_ph3", 30E"RA_PIN_VI_VSYNC_PD6, 926ac926s="15c_sdaCpc5_/a>sc#L3826s=">2643>15569 href};spanD1_PE30E8L27trin30Ei_cec_pee3"30E"RA_PIN_VI_VSYNC_PD6, "hdmi_int_pn7&quo30E>&>30E"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla301"L27trin30ing"pf42nEltr236class="s30ing>30inRA_PIN_VI_VSYNC_PD6, , "cpu_pwr_req"230i2L27trin306g">92619p1El"RA5c22clas306g">30i"RA_PIN_VI_VSYNC_PD6, 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c230i3L27trin3037>92619"L27tring"2="s6g3037>>30iEl"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"230i4L27trin30s6c9">&qu825s5YNC_PD630iEl"RA_PIN_VI_VSYNC_PD6, 26s5>15569 href};spa3015L27trin302619p1El"RA5c22clasEl"RA30261>30iD6, 926s7p15n c926spi2gcs09265x5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD130i6L27trin30">"dap3_din_pp1&quo30">&>30iD6, 92698p15n c926spi2qcs19265w"146fode=_GPI6s="line826s=">26s6>15569 href};spanD1_PE"L27tr3017L27trin30>"dap3_dout_pp2&quo30>&q>30iD6, 92699p15n c926spi2qcs29265w5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD130i8L27trin30">"dap3_fs_pp0"30">&>30iVI_VSYNC_PD6, 927sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3019L27trin30"dap3_sclk_pp3"30&qu>30il"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla302"L27trin30">"dap4_din_pp5&quo30">&>30">"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr3021L27trin30>"dap4_dout_pp6&quo30>&q>30""RA_PIN_VI_VSYNC_PD6, 26s5>15569 href};spa3022L27trin30">"dap4_fs_pp4"30">&>30""RA_PIN_VI_VSYNC_PD6, 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c23023L27trin30"dap4_sclk_pp7"30&qu>30"El"RA_PIN_VI_VSYNC_PD6, sc#L3826s=">2643>15569 href};spanD1_PE3024L27trin30">"ddc_scl_pv4"30">&>30"El"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla3025L27trin30"ddc_sda_pv5"<30&qu>30"_PIN_};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou30"6L27trin30"gen1_i2c_scl_pc4&q30&qu>30"PIN_Vf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou30"7L27trin30ing">"gen1_i2c_sda_30ing>30"_PIN_ad11_ph3", "pbb0"30"VI_VSYNC_PD6, 92792619p1El"RA5c22class="s6g"337>92619p1El"RA5c23029L27trin30bb7"30"l"RA_PIN_VI_VSYNC_PD6, sc#L3826s=">2643>15569 href};spanD1_PE303"L27trin30cc1"30ccl"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"23031L27trin30cc2"30cspanEl"RA_PIN_VI_VSYNC_PD6, 26s5>15569 href};spa3032L27trin30v0"30c"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr3033L27trin301"30cEl"RA_PIN_VI_VSYNC_PD6, 30cEl"RA};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3035L27trin303"30cEl"RAf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3036L27trin30mi_cec_pee3"30cEl"RAad11_ph3", "hdmi_int_pn7&quo30">&>30c"RA_PIN_VI_VSYNC_PD6, , 2643>15569 href};spanD1_PE30c9L27trin30">"pwr_i2c_scl_pz6&30">&>30c"RA_PIN_VI_VSYNC_PD6, "pwr_i2c_sda_pz30ng">30ngnEl"RA_PIN_VI_VSYNC_PD6, 26s5>15569 href};spa30n1L27trin30ng">"pwr_int_n"30ng">30nspanEl"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"230n2L27trin30uot;sdmmc1_clk_pz0"30uot>30n"RA_PIN_VI_VSYNC_PD6, 26s=>15569 href};spanD130n3L27trin30g">"sdmmc1_cmd_pz1&30g">>30nEl"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t30n4L27trin30g">"sdmmc1_dat0_py730g">>30nEl"RA_PIN_VI_VSYNC_PD6, "sdmmc1_dat1_py30ng">30nEl"RA_PIN_VI_VSYNC_PD6, "sdmmc1_dat2_py30ng">30nD6, 92698p15n c926spi6gmiso_pxc926s="15c_sdaCpc5_/a>sc#L3826s=">2643>15569 href};spanD1_PE3047L27trin30ng">"sdmmc1_dat3_py30ng">30nD6, 92699p15n c926spi2qcs09265x5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD13048L27trin30ng">"sdmmc3_dat0_pb30ng">30nVI_VSYNC_PD6, 92726s6>15569 href};spanD1_PE"L27tr3049L27trin30ng">"sdmmc3_dat1_pb30ng">30nl"RA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">2701>15569 href};spanD1305"L27trin30ng">"sdmmc4_rst_n_p30ng">30ngI_VSYNC_PD6, 927sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3051L27trin30ring">"spdif_out_pk30rin>30nspanEl"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla3052L27trin30">"sys_clk_req_pz5&30">&>30n"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr3053L27trin30ng">"uart3_cts_n_pa30ng">30nEl"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3054L27trin30ng">"uart3_rxd_pw7&30ng">30nEl"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr3055L27trin30">"uart3_txd_pw6&qu30">&>30nEl"RA_PIN_VI_VSYNC_PD6, "ulpi_clk_py0&quo30">&>30nD6, 92698p15n c926ulp5ndata315ohref};spanD1_PE"L27tring">"cpu_pwr_req"23057L27trin30>"ulpi_dir_py1"30>&q>30nN_VI_};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou30n8L27trin30>"ulpi_nxt_py2"30>&q>30nspanEf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou30n9L27trin30>"ulpi_stp_py3"30>&q>30nspanEad11_ph3", "vi_d0_pt4"&q>30>&6, 92698p15n c926p15na16_pjc926s="15c_sdaCpc5_/a>sc#L3826s=">2643>15569 href};spanD1_PE3061L27trin30uot;vi_d10_pt2"30>spanEl"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla3062L27trin30quot;vi_d11_pt3"30>"RA_PIN_VI_VSYNC_PD6, 30>El"RA_PIN_VI_VSYNC_PD6, sc#L3826s=">2643>15569 href};spanD1_PE3064L27trin30>"vi_vsync_pd6"30>&q>30>anEl"RA_PIN_VI_VSYNC_PD6, 30>5s="15s6c8">"6" clas825s=">2557>155"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla3066L27trin30>2668>155a(4)
68 hch30>26>30>l"RA_PIN_VI_VSYNC_PD6, 30>"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"23068L27trin30569 href};spanD1_PE"L27t30569>30>VI_VSYNC_PD6, 927j5p15n c926s="15dat5_/d0_/a>sc#L30826s=">26s5>15569 href};spa3069L27trin30ing">"cam_i2c_sda_p30ing>30>l"RA_PIN_VI_VSYNC_PD6, j2p15n c926s="15="s6code=_GPI6" cl826s=">2642>15569 href};spa307"L27trin30ing">"clk1_out_pw4&30ing>30inRA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">2701>15569 href};spanD130i1L27trin30>"clk1_req_pee2&quo30>&q>30i"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr30i2L27trin30">"clk2_out_pw5&quo30">&>30i2_VI_};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3073L27trin30>"clk2_req_pcc5&quo30>&q>30i3panEf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3074L27trin30">"clk3_out_pee0&qu30">&>30i4panEad11_ph3", "clk3_req_pee1&qu30">&>30i="15dat6_/d3_/a>sc#L30826s=">2667>155"cpu_pwr_req"23076L27trin30">"clk_32k_in"30">&>30il"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla3077L27trin30quot;clk_32k_out_pa0&quo30quo>30i"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr30i8L27trin30ng">"core_pwr_req&q30ng">30iVI_VSYNC_PD6, 92792619p1El"RA5c22class="s6g"337>92619p1El"RA5c230i9L27trin30>"cpu_pwr_req"30>&q>30il"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"2308"L27trin30"crt_hsync_pv6"30&qu>30&q"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr3081L27trin30">"crt_vsync_pv7&qu30">&>30&"RA_PIN_VI_VSYNC_PD6, sc#L30826s=">26s5>15569 href};spa3082L27trin30">"dap2_din_pa4&quo30">&>30&"RA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">2701>15569 href};spanD13083L27trin30>"dap2_dout_pa5&quo30>&q>30&I_VSY};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou30&4L27trin30">"dap2_fs_pa2"30">&>30&PD6TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou30&5L27trin30"dap2_sclk_pa3"30&qu>30&D6, "ddc_scl_pv4"30">&>30&D6, 92698p15n c926spi2qcs09265x5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD13087L27trin30"ddc_sda_pv5"<30&qu>30&D6, 92699p15n c926spi2qmiso_px="14/e2_/a>sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3088L27trin30"gen1_i2c_scl_pc4&q30&qu>30&VI_VSYNC_PD6, 927"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla3089L27trin30ing">"gen1_i2c_sda_30ing>30&l"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr309"L27trin30ing">"pbb0"30in_VSY};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3091L27trin30bb7"30iIN_VIf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou30i2L27trin30cc1"30iPIN_Vad11_ph3", 30iEl"RA_PIN_VI_VSYNC_PD6, 92655p15n c926s="15dat5_/d0_/a>sc#L30826s=">26s5>15569 href};spa30i4L27trin30v0"30iEl"RA};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3095L27trin301"30iEl"RAf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3096L27trin302"30iEl"RAad11_ph3", 30i, 9colp15q">"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla3098L27trin30mi_cec_pee3"30iPIN_VI_VSYNC_PD6, ">9col115q="14/e2_/a>sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3099L27trin30">"hdmi_int_pn7&quo30">&>30iA_PIN};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou31E"L27trin31E"L2uot;hdmi_int_pn7&quo31E"L>310p15n f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3101L27trin31Eb7"310t;crtad11_ph3", 31E"RA_PIN_VI_VSYNC_PD6, 9colp15q">"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla31E3L27trin31Ec2"31EEl"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t31E4L27trin31E0"31RA_PIN_VI_VSYNC_PD6, 9col215q"146fode=_GPI6s="line826s=">26s6>15569 href};spanD1_PE"L27tr31E5L27trin31E"310A_PIN_VI_VSYNC_PD6, sc#L306" id827<=">2701>15569 href};spanD131E6L27trin31E"310nEl"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"231E7L27trin31E"31E"RA_PIN_VI_VSYNC_PD6, sc#L30826s=">26s5>15569 href};spa31E8L27trin31Ei_cec_pee3"31E"RA_PIN_VI_VSYNC_PD6, 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c231E9L27trin31E>"hdmi_int_pn7&quo31E>&>31E"RA_PIN_VI_VSYNC_PD6, sc#L3826s=">2643>15569 href};spanD1_PE311"L27trin31ing"pf42nEltr236class="s31ing>31inRA_PIN_VI_VSYNC_PD6, 927<415rhref};spanD1_PE"L27tring">"cpu_pwr_req"231i1L27trin31f};spanlVSYNC_58,
70 htr31f};>31ispanEl"RA_PIN_VI_VSYNC_PD6, 927<515r5p15n c926s="15dat5_/d0_/a>sc#L30826s=">26s5>15569 href};spa31i2L27trin316g">92619p1El"RA5c22clas316g">3112_VI_};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou31i3L27trin3137>92619"L27tring"2="s6g3137>>3113panEf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou31i4L27trin31s6c9">&qu825s5YNC_PD63114panEad11_ph3", 31iD6, 926s7p15n c926pu">"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla31i6L27trin31">"dap3_din_pp1&quo31">&>31iD6, 92698p15n c926pu="14/e2_/a>sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3117L27trin31>"dap3_dout_pp2&quo31>&q>31iD6, 92699p15n c926pu"146fode=_GPI6s="line826s=">26s6>15569 href};spanD1_PE"L27tr31i8L27trin31">"dap3_fs_pp0"31">&>31iVI_VSYNC_PD6, 927, "cpu_pwr_req"2312"L27trin31">"dap4_din_pp5&quo31">&>31">"RA_PIN_VI_VSYNC_PD6, sc#L30826s=">26s5>15569 href};spa3121L27trin31>"dap4_dout_pp6&quo31>&q>31""RA_PIN_VI_VSYNC_PD6, 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c23122L27trin31">"dap4_fs_pp4"31">&>31""RA_PIN_VI_VSYNC_PD6, 92645p15n c926s="15="s6code=_GPI6" cl826s=">26s5>15569 href};span31"3L27trin31"dap4_sclk_pp7"31&qu>31"El"RA_PIN_VI_VSYNC_PD6, 92646p15n c926s="15="s6c8">"6" cl826s=">2646>15569 href};spa31"4L27trin31">"ddc_scl_pv4"31">&>31"El"RA_PIN_VI_VSYNC_PD6, 2703>15569 href};spanD1_31"5L27trin31"ddc_sda_pv5"<31&qu>31RA_PIN_VI_VSYNC_PD6, 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c231R6L27trin31"gen1_i2c_scl_pc4&q31&qu>31anEl"RA_PIN_VI_VSYNC_PD6, 26s5>15569 href};spa31a7L27trin31ing">"gen1_i2c_sda_31ing>31;, "cpu_pwr_req"231;8L27trin31ing">"pbb0"31"VI_VSYNC_PD6, 92731"l"RA_PIN_VI_VSYNC_PD6, 926ac926s="15c_sdaCpc5_/a>sc#L3826s=">2643>15569 href};spanD1_PE313"L27trin31cc1"31ccl"RA_PIN_VI_VSYNC_PD6, j5p15n c926s="15dat5_/d0_/a>sc#L30826s=">26s5>15569 href};spa3131L27trin31cc2"31cspanEl"RA_PIN_VI_VSYNC_PD6, j2p15n c926s="15="s6code=_GPI6" cl826s=">2642>15569 href};spa3132L27trin31v0"31c"RA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">2701>15569 href};spanD13133L27trin311"31cEl"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr3134L27trin312"31PD6, 92636p15n c926ulp5ndatap15o="14/e2_/a>sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3135L27trin313"31PD6, 926s7p15n c926ulp5ndata115o"146fode=_GPI6s="line826s=">26s6>15569 href};spanD1_PE"L27tr3136L27trin31mi_cec_pee3"31_VI_VSYNC_PD6, 926sulp5ndata215o5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD13137L27trin31">"hdmi_int_pn7&quo31">&>31c"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"231c8L27trin31>"jtag_rtck_pu7&quo31>&q>31c"RA_PIN_VI_VSYNC_PD6, 26s5>15569 href};spa31c9L27trin31">"pwr_i2c_scl_pz6&31">&>31c"RA_PIN_VI_VSYNC_PD6, 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c2314"L27trin31ng">"pwr_i2c_sda_pz31ng">31ngnEl"RA_PIN_VI_VSYNC_PD6, 2643>15569 href};spanD1_PE31n1L27trin31ng">"pwr_int_n"31ng">31nspanEl"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla31n2L27trin31uot;sdmmc1_clk_pz0"31uot>3142_VI_};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou31n3L27trin31g">"sdmmc1_cmd_pz1&31g">>3143panEf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou31n4L27trin31g">"sdmmc1_dat0_py731g">>3144panEad11_ph3", "sdmmc1_dat1_py31ng">31nEl"RA_PIN_VI_VSYNC_PD6, j5p15n c926s="15dat5_/d0_/a>sc#L30826s=">26s5>15569 href};spa31n6L27trin31ng">"sdmmc1_dat2_py31ng">31nD6, 92698p15n c926uart2_rts6g">j2p15n c926s="15="s6code=_GPI6" cl826s=">2642>15569 href};spa3147L27trin31ng">"sdmmc1_dat3_py31ng">31nD6, 92699p15n c926uart2_rx6qpp5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD13148L27trin31ng">"sdmmc3_dat0_pb31ng">31nVI_VSYNC_PD6, 92726s6>15569 href};spanD1_PE"L27tr3149L27trin31ng">"sdmmc3_dat1_pb31ng">314A_PIN};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou315"L27trin31ng">"sdmmc4_rst_n_p31ng">315p15n f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3151L27trin31ring">"spdif_out_pk31rin>315t;crtad11_ph3", "sys_clk_req_pz5&31">&>31n"RA_PIN_VI_VSYNC_PD6, 1="14/e2_/a>sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3153L27trin31ng">"uart3_cts_n_pa31ng">31nEl"RA_PIN_VI_VSYNC_PD6, c">"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla31n4L27trin31ng">"uart3_rxd_pw7&31ng">31nEl"RA_PIN_VI_VSYNC_PD6, sc#L3826s=">2643>15569 href};spanD1_PE3155L27trin31">"uart3_txd_pw6&qu31">&>31nEl"RA_PIN_VI_VSYNC_PD6, "ulpi_clk_py0&quo31">&>31nD6TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3157L27trin31>"ulpi_dir_py1"31>&q>31nN_VI_f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3158L27trin31>"ulpi_nxt_py2"31>&q>31nspanEad11_ph3", , sc#L3826s=">2643>15569 href};spanD1_PE316"L27trin31>"vi_d0_pt4"&q>31>&6, 92698p15n c926p15na17"sb">"crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla3161L27trin31uot;vi_d10_pt2"31>spanEl"RA_PIN_VI_VSYNC_PD6, 31>"RA_PIN_VI_VSYNC_PD6, sc#L3826s=">2643>15569 href};spanD1_PE3163L27trin31quot;vi_hsync_pd7"<31quo>31>El"RA_PIN_VI_VSYNC_PD6, sc#L3826s=">2643>15569 href};spanD1_PE3164L27trin31>"vi_vsync_pd6"31>&q>31>anEl"RA_PIN_VI_VSYNC_PD6, 31>5s="15s6c8">"6" clas825s=">2557>15526s6>15569 href};spanD1_PE"L27tr3166L27trin31>2668>155a(4)
68 hch31>26>31>l"RA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">2701>15569 href};spanD13167L27trin31]264" id=9L30sdmmc3_dat131]26>316N_VI_};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3168L27trin31569 href};spanD1_PE"L27t31569>316spanEf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3169L27trin31ing">"cam_i2c_sda_p31ing>316spanEad11_ph3", "clk1_out_pw4&31ing>31inRA_PIN_VI_VSYNC_PD6, 2703>15569 href};spanD1_31i1L27trin31>"clk1_req_pee2&quo31>&q>31i"RA_PIN_VI_VSYNC_PD6, 92619p1El"RA5c22class="s6g"337>92619p1El"RA5c231i2L27trin31">"clk2_out_pw5&quo31">&>31El"RA_PIN_VI_VSYNC_PD6, sc#L30826s=">26s5>15569 href};spa3173L27trin31>"clk2_req_pcc5&quo31>&q>31El"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"23174L27trin31">"clk3_out_pee0&qu31">&>31nEl"RA_PIN_VI_VSYNC_PD6, 26s=>15569 href};spanD13175L27trin31">"clk3_req_pee1&qu31">&>31nEl"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3176L27trin31">"clk_32k_in"31">&>31"RA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">2701>15569 href};spanD131i8L27trin31ng">"core_pwr_req&q31ng">31iVI_VS};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou31i9L27trin31>"cpu_pwr_req"31>&q>31il"RA_f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou318"L27trin31"crt_hsync_pv6"31&qu>31&q"RA_ad11_ph3", "crt_vsync_pv7&qu31">&>31&"RA_PIN_VI_VSYNC_PD6, 2643>15569 href};spanD1_PE3182L27trin31">"dap2_din_pa4&quo31">&>31&"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3183L27trin31>"dap2_dout_pa5&quo31>&q>31nEl"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr31&4L27trin31">"dap2_fs_pa2"31">&>318D6, 92636p15n c926ulp5ndata215o5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD131&5L27trin31"dap2_sclk_pa3"31&qu>318D6, 926s7p15n c926ulp5ndata315ohref};spanD1_PE"L27tring">"cpu_pwr_req"23186L27trin31">"ddc_scl_pv4"31">&>31&D6, 92698p15n c926ulp5ndata4"so5p15n c926s="15dat5_/d0_/a>sc#L30826s=">26s5>15569 href};spa3187L27trin31"ddc_sda_pv5"<31&qu>31&D6, 92699p15n c926ulp5ndata5"solass="s6g"337>92619p1El"RA5c22class="s6g"337>92619p1El"RA5c23188L27trin31"gen1_i2c_scl_pc4&q31&qu>31&VI_VSYNC_PD6, 927sc#L3826s=">2643>15569 href};spanD1_PE3189L27trin31ing">"gen1_i2c_sda_31ing>31&l"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla319"L27trin31ing">"pbb0"31l"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3191L27trin31bb7"31l"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr31i2L27trin31cc1"31l"RA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">2701>15569 href};spanD13193L27trin31cc2"31VI_VSY};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou31V4L27trin31v0"31_PD6TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou31_5L27trin311"31PD6, 31PD6, 92698p15n c926cam_i2c_scl_pbb="14/e2_/a>sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3197L27trin313"319N_VI_};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3198L27trin31mi_cec_pee3"319spanEf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3199L27trin31">"hdmi_int_pn7&quo31">&>319spanEad11_ph3", 32E"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr3201L27trin32Eb7"320t;crt};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou32E2L27trin32Ec1"32E"RA_Pf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou32E3L27trin32Ec2"32EEl"RAad11_ph3", 32RA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">2701>15569 href};spanD132E5L27trin32E"320A_PIN_VI_VSYNC_PD6, 26s5>15569 href};spa32E6L27trin32E"320D6TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou32E7L27trin32E"320N_VI_f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou32E8L27trin32Ei_cec_pee3"320spanEad11_ph3", , "cpu_pwr_req"2321"L27trin32ing"pf42nEltr236class="s32ing>32inRA_PIN_VI_VSYNC_PD6, TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou32i2L27trin326g">92619p1El"RA5c22clas326g">321"RA_Pf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou32i3L27trin3237>92619"L27tring"2="s6g3237>>321El"RAad11_ph3", &qu825s5YNC_PD632iEl"RA_PIN_VI_VSYNC_PD6, 26s5>15569 href};spa3215L27trin322619p1El"RA5c22clasEl"RA32261>32iD6, 926s7p15n c926sss="4gdat7"saac926s="15c_sdaCpc5_/a>sc#L3826s=">2643>15569 href};spanD1_PE32i6L27trin32">"dap3_din_pp1&quo32">&>321D6TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3217L27trin32>"dap3_dout_pp2&quo32>&q>321N_VI_f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou32i8L27trin32">"dap3_fs_pp0"32">&>321spanEad11_ph3", , "dap4_din_pp5&quo32">&>32">"RA_PIN_VI_VSYNC_PD6, cp5n c927<="14/e1_/a>sc#L306" id827<=">2701>15569 href};spanD13221L27trin32>"dap4_dout_pp6&quo32>&q>322t;crt};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3222L27trin32">"dap4_fs_pp4"32">&>322"RA_Pf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou32"3L27trin32"dap4_sclk_pp7"32&qu>322El"RAad11_ph3", "ddc_scl_pv4"32">&>32"El"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla32"5L27trin32"ddc_sda_pv5"<32&qu>32RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"232R6L27trin32"gen1_i2c_scl_pc4&q32&qu>32anEl"RA_PIN_VI_VSYNC_PD6, 26s5>15569 href};spa32a7L27trin32ing">"gen1_i2c_sda_32ing>32;, 26s6>15569 href};spanD1_PE"L27tr32;8L27trin32ing">"pbb0"32"VI_VSYNC_PD6, 92732"l"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla323"L27trin32cc1"32ccl"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3231L27trin32cc2"32cspanEl"RA_PIN_VI_VSYNC_PD6, 26s6>15569 href};spanD1_PE"L27tr3232L27trin32v0"32c"RA_PIN_VI_VSYNC_PD6, sc#L306" id827<=">2701>15569 href};spanD13233L27trin321"32cEl"RA_PIN_VI_VSYNC_PD6, "cpu_pwr_req"23234L27trin322"32PD6, 92636p15n c926v5nd7"sl5p15n c926s="15dat5_/d0_/a>sc#L30826s=">26s5>15569 href};spa3235L27trin323"32PD6, 926s7p15n c926v5nd8"sl2p15n c926s="15="s6code=_GPI6" cl826s=">2642>15569 href};spa3236L27trin32mi_cec_pee3"32_VI_VSYNC_PD6, 926sv5nd9"slc926s="15c_sdaCpc5_/a>sc#L3826s=">2643>15569 href};spanD1_PE3237L27trin32">"hdmi_int_pn7&quo32">&>32c"RA_PIN_VI_VSYNC_PD6, sc#L3826s=">2643>15569 href};spanD1_PE3238L27trin32>"jtag_rtck_pu7&quo32>&q>32c"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3239L27trin32">"pwr_i2c_scl_pz6&32">&>32c"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla324"L27trin32ng">"pwr_i2c_sda_pz32ng">32ngnEl"RA_PIN_VI_VSYNC_PD6, "pwr_int_n"32ng">324t;crt};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou32n2L27trin32uot;sdmmc1_clk_pz0"32uot>324"RA_Pf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou32n3L27trin32g">"sdmmc1_cmd_pz1&32g">>324El"RAad11_ph3", "sdmmc1_dat0_py732g">>32nEl"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla32n5L27trin32ng">"sdmmc1_dat1_py32ng">32nEl"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t32n6L27trin32ng">"sdmmc1_dat2_py32ng">324D6TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3247L27trin32ng">"sdmmc1_dat3_py32ng">324N_VI_f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3248L27trin32ng">"sdmmc3_dat0_pb32ng">324spanEad11_ph3", "sdmmc3_dat1_pb32ng">32nl"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t325"L27trin32ng">"sdmmc4_rst_n_p32ng">325n_VSY};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3251L27trin32ring">"spdif_out_pk32rin>325IN_VIf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3252L27trin32">"sys_clk_req_pz5&32">&>325PIN_Vad11_ph3", "uart3_cts_n_pa32ng">32nEl"RA_PIN_VI_VSYNC_PD6, "crt_hsync_pv6ode=k_outs="s6g"337>92619p1El"RA5c22cla32n4L27trin32ng">"uart3_rxd_pw7&32ng">32nEl"RA_PIN_VI_VSYNC_PD6, sc#L306" id826s=">26s5>15569 href};spanD1_PE"L27t3255L27trin32">"uart3_txd_pw6&qu32">&>32nEl"RA};f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3256L27trin32">"ulpi_clk_py0&quo32">&>32nD6TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3257L27trin32>"ulpi_dir_py1"32>&q>32nN_VI_#defdir_PIN_VI_VSYNC_PDFUNCTION TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3258L27trin32>"ulpi_nxt_py2"32>&q>325"RA_PIN_VI_VS{                                               \f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3259L27trin32>"ulpi_stp_py3"32>&q>32l"RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDy1&q TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou326"L27trin32>"vi_d0_pt4"&q>32>&6, , TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3261L27trin32uot;vi_d10_pt2"32>spanEl"RA_PINSSSSSSSS.PIN_VI_VSYNC_PDy6, ,),  \f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3262L27trin32quot;vi_d11_pt3"32>"RA_PIN_VI_VS}f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3263L27trin32quot;vi_hsync_pd7"<32quo>3263panEf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3264L27trin32>"vi_vsync_pd6"32>&q>3264panEad11_ph3", &qIN_VI_VSYNC_PDFUNCTION 2668>155a(4)
68 hch32>26>32>l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 32>"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION 32>VI_VSYNC_PD6"cam_i2c_sda_p32ing>32>l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 9 9_VI_)L306" id826s=">26s5>15569 href};spanD1_PE"L27t327"L27trin32ing">"clk1_out_pw4&32ing>32inRA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION 9 9_VI_)L306" id826s=">26s5>15569 href};spanD1_PE"L27t3271L27trin32>"clk1_req_pee2&quo32>&q>32i"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION "clk2_out_pw5&quo32">&>32El"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION "clk2_req_pcc5&quo32>&q>32El"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION "clk3_out_pee0&qu32">&>32nEl"RA_PIN_VI_VIN_VI_VSYNC_PDFUNCTION "clk3_req_pee1&qu32">&>3275s="15s6c8">&qIN_VI_VSYNC_PDFUNCTION "clk_32k_in"32">&>327l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 327"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION "core_pwr_req&q32ng">327VI_VSYNC_PD6"cpu_pwr_req"32>&q>327l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 328nRA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION "crt_vsync_pv7&qu32">&>328"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION "dap2_din_pa4&quo32">&>328l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION "dap2_dout_pa5&quo32>&q>328l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION "dap2_fs_pa2"32">&>328El"RA_PIN_VI_VIN_VI_VSYNC_PDFUNCTION 3285s="15s6c8">&qIN_VI_VSYNC_PDFUNCTION "ddc_scl_pv4"32">&>328l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 328"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION 328VI_VSYNC_PD6"gen1_i2c_sda_32ing>328l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION "pbb0"329nRA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION 329"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION 329l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 329l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 329El"RA_PIN_VI_VIN_VI_VSYNC_PDFUNCTION 3295s="15s6c8">&qIN_VI_VSYNC_PDFUNCTION 329l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 329"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION 329VI_VSYNC_PD6"hdmi_int_pn7&quo32">&>329l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 330nRA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION 330"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION 330l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 330l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 330El"RA_PIN_VI_VIN_VI_VSYNC_PDFUNCTION 3305s="15s6c8">&qIN_VI_VSYNC_PDFUNCTION 330l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 330"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION 330VI_VSYNC_PD6"hdmi_int_pn7&quo33E>&>330l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 331"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION 92619p1El"RA5c22clas336g">331l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 92619"L27tring"2="s6g3337>>331l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION &qu825s5YNC_PD6331El"RA_PIN_VI_VIN_VI_VSYNC_PDFUNCTION 3315s="15s6c8">&qIN_VI_VSYNC_PDFUNCTION "dap3_din_pp1&quo33">&>331l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION "dap3_dout_pp2&quo33>&q>331"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION "dap3_fs_pp0"33">&>331VI_VSYNC_PD6331l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION "dap4_din_pp5&quo33">&>332nRA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION "dap4_dout_pp6&quo33>&q>332"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION "dap4_fs_pp4"33">&>332l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 332l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION "ddc_scl_pv4"33">&>332El"RA_PIN_VI_VIN_VI_VSYNC_PDFUNCTION 3325s="15s6c8">&qIN_VI_VSYNC_PDFUNCTION 332l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION "gen1_i2c_sda_33ing>332"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION "pbb0"332VI_VSYNC_PD6332l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 333nRA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION 333"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION 333l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 333l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION 333El"RA_PIN_VI_VIN_VI_VSYNC_PDFUNCTION 3335s="15s6c8">&qIN_VI_VSYNC_PDFUNCTION 333l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION "hdmi_int_pn7&quo33">&>333"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION "jtag_rtck_pu7&quo33>&q>333VI_VSYNC_PD6"pwr_i2c_scl_pz6&33">&>333l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION "pwr_i2c_sda_pz33ng">334nRA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION "pwr_int_n"33ng">334"RA_PIN_VI_VSYIN_VI_VSYNC_PDFUNCTION 334l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION "sdmmc1_cmd_pz1&33g">>334l"RA_PIN_VI_VSIN_VI_VSYNC_PDFUNCTION "sdmmc1_dat0_py733g">>334El"RA_PIN_VI_VIN_VI_VSYNC_PDFUNCTION "sdmmc1_dat1_py33ng">3345s="15s6c8">&qIN_VI_VSYNC_PDFUNCTION "sdmmc1_dat2_py33ng">334D6TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3347L27trin33ng">"sdmmc1_dat3_py33ng">334N_VI_f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3348L27trin33ng">"sdmmc3_dat0_pb33ng">334spanE#defdir_PIN_VI_VSYNC_PDDRV_PINGROUP_REG_A comment">/* bank 0 */_/a>sc#f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3349L27trin33ng">"sdmmc3_dat1_pb33ng">33nl"RA_#defdir_PIN_VI_VSYNC_PDPINGROUP_REG_A comment">/* bank 1 */_/a>sc#f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou335"L27trin33ng">"sdmmc4_rst_n_p33ng">335n_VSYf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3351L27trin33ring">"spdif_out_pk33rin>335IN_VI#defdir_PIN_VI_VSYNC_PDPINGROUP_REG_Y TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3352L27trin33">"sys_clk_req_pz5&33">&>335PIN_V#defdir_PIN_VI_VSYNC_PDPINGROUP_REG_N TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3353L27trin33ng">"uart3_cts_n_pa33ng">3353panEf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou33n4L27trin33ng">"uart3_rxd_pw7&33ng">33nEl"RA#defdir_PIN_VI_VSYNC_PDPINGROUP TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3355L27trin33">"uart3_txd_pw6&qu33">&>3355s="15s6c8">&{                                                       \f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3356L27trin33">"ulpi_clk_py0&quo33">&>3356s="15s6c8"6c8""""""".PIN_VI_VSYNC_PDy1&q TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3357L27trin33>"ulpi_dir_py1"33>&q>3357s="15s6c8"6c8""""""".PIN_VI_VSYNC_PDE"L, TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3358L27trin33>"ulpi_nxt_py2"33>&q>335"RA_PIN_VI_VS8""""""".PIN_VI_VSYNC_PDyE"L, TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3359L27trin33>"ulpi_stp_py3"33>&q>33l"RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDfuL2, TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou336"L27trin33>"vi_d0_pt4"&q>33>&6, TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3361L27trin33uot;vi_d10_pt2"33>spanEl"RA_PINSSSSSSSSSSSSSSSSPIN_VI_VSYNC_PDTEGRA_MUX_ TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3362L27trin33quot;vi_d11_pt3"33>"RA_PIN_VI_VSSSSSSSSSSSSSSSSSPIN_VI_VSYNC_PDTEGRA_MUX_ TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3363L27trin33quot;vi_hsync_pd7"<33quo>3363RA_PIN_VI_VSSSSSSSSSSSSSSSSSPIN_VI_VSYNC_PDTEGRA_MUX_ TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3364L27trin33>"vi_vsync_pd6"33>&q>3364RA_PIN_VI_VSSSSSSSSS},                                              \f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3365L27trin33nst unsignedrs/pin82667p33nst>33>5s="15s6c8">&&&&&&&&&.PIN_VI_VSYNC_PDfuL2_safq TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3366L27trin33>2668>155a(4)
68 hch33>26>3366s="15s6c8"6c8""""""".PIN_VI_VSYNC_PDmux_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3367L27trin33]264" id=9L30sdmmc3_dat133]26>3367s="15s6c8"6c8""""""".PIN_VI_VSYNC_PDmux_bank TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3368L27trin33569 href};spanD1_PE"L27t33569>336"RA_PIN_VI_VS8""""""".PIN_VI_VSYNC_PDmux_bit TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3369L27trin33ing">"cam_i2c_sda_p33ing>336"RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDpupd_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou337"L27trin33ing">"clk1_out_pw4&33ing>337&6, TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3371L27trin33>"clk1_req_pee2&quo33>&q>337spanEl"RA_PINSSSSSSSS.PIN_VI_VSYNC_PDpupd_bit TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou33i2L27trin33">"clk2_out_pw5&quo33">&>337"RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDtri_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou33i3L27trin33>"clk2_req_pcc5&quo33>&q>3373RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDtri_bank TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou33i4L27trin33">"clk3_out_pee0&qu33">&>3374RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDtri_bit TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou33i5L27trin33">"clk3_req_pee1&qu33">&>3375s="15s6c8">&&&&&&&&&.PIN_VI_VSYNC_PDeinput_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou33i6L27trin33">"clk_32k_in"33">&>3376s="15s6c8"6c8""""""".PIN_VI_VSYNC_PDeinput_bank TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou33i7L27trin33quot;clk_32k_out_pa0&quo33quo>3377s="15s6c8"6c8""""""".PIN_VI_VSYNC_PDeinput_bit TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou33i8L27trin33ng">"core_pwr_req&q33ng">337"RA_PIN_VI_VS8""""""".PIN_VI_VSYNC_PDodrain_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou33i9L27trin33>"cpu_pwr_req"33>&q>337"RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDodrain_bank TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou338"L27trin33"crt_hsync_pv6"33&qu>338&6, TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3381L27trin33">"crt_vsync_pv7&qu33">&>338spanEl"RA_PINSSSSSSSS.PIN_VI_VSYNC_PDlock_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3382L27trin33">"dap2_din_pa4&quo33">&>338"RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDlock_bank TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3383L27trin33>"dap2_dout_pa5&quo33>&q>3383RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDlock_bit TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3384L27trin33">"dap2_fs_pa2"33">&>3384RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDioreset_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3385L27trin33"dap2_sclk_pa3"33&qu>3385s="15s6c8">&&&&&&&&&.PIN_VI_VSYNC_PDioreset_bank TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3386L27trin33">"ddc_scl_pv4"33">&>3386s="15s6c8"6c8""""""".PIN_VI_VSYNC_PDioreset_bit TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3387L27trin33"ddc_sda_pv5"<33&qu>3387s="15s6c8"6c8""""""".PIN_VI_VSYNC_PDdrv_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3388L27trin33"gen1_i2c_scl_pc4&q33&qu>338VI_VSYNC_PD6<}f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3389L27trin33ing">"gen1_i2c_sda_33ing>338l"RA_f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou339"L27trin33ing">"pbb0"339nRA_P#defdir_PIN_VI_VSYNC_PDDRV_PINGROUP TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3391L27trin33bb7"339spanEl"RA_PINSSSSSSSSSSSSSPIN_VI_VSYNC_PDdrvdn_b TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3392L27trin33cc1"339"RA_PIN_VI_VSSSSSSSSSSSSSSPIN_VI_VSYNC_PDslwr_b TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3393L27trin33cc2"339l"RA_PIN_VI_V{                                                       \f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou33V4L27trin33v0"3394RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDy1&q , sc#"#pg_y1&q,                      \f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou33V5L27trin331"3395s="15s6c8">&&&&&&&&&.PIN_VI_VSYNC_PDE"L, TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou33V6L27trin332"3396s="15s6c8"6c8""""""".PIN_VI_VSYNC_PDyE"L, TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou33V7L27trin333"3397s="15s6c8"6c8""""""".PIN_VI_VSYNC_PDmux_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3398L27trin33mi_cec_pee3"339"RA_PIN_VI_VS8""""""".PIN_VI_VSYNC_PDpupd_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3399L27trin33">"hdmi_int_pn7&quo33">&>339"RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDtri_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou34E"L27trin34E"L2uot;hdmi_int_pn7&quo34E"L>340&6, TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou34E1L27trin34Eb7"340spanEl"RA_PINSSSSSSSS.PIN_VI_VSYNC_PDodrain_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou34E2L27trin34Ec1"340"RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDlock_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou34E3L27trin34Ec2"3403RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDioreset_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou34E4L27trin34E0"3404RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDdrv_reg TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou34E5L27trin34E"3405s="15s6c8">&&&&&&&&&.PIN_VI_VSYNC_PDdrv_bank TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou34E6L27trin34E"3406s="15s6c8"6c8""""""".PIN_VI_VSYNC_PDhsm_bit TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou34E7L27trin34E"3407s="15s6c8"6c8""""""".PIN_VI_VSYNC_PDschmitt_bit TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou34E8L27trin34Ei_cec_pee3"340"RA_PIN_VI_VS8""""""".PIN_VI_VSYNC_PDlpmd_bit TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou34E9L27trin34E>"hdmi_int_pn7&quo34E>&>340"RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDdrvdn_bit TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou341"L27trin34ing"pf42nEltr236class="s34ing>341&6, TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3411L27trin34f};spanlVSYNC_58,
70 htr34f};>341spanEl"RA_PINSSSSSSSS.PIN_VI_VSYNC_PDdrvup_bit TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3412L27trin346g">92619p1El"RA5c22clas346g">341"RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDdrvup_width TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3413L27trin3437>92619"L27tring"2="s6g3437>>3413RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDslwr_bit TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3414L27trin34s6c9">&qu825s5YNC_PD63414RA_PIN_VI_VSSSSSSSSS.PIN_VI_VSYNC_PDslwr_width TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3415L27trin342619p1El"RA5c22clasEl"RA34261>3415s="15s6c8">&&&&&&&&&.PIN_VI_VSYNC_PDslwf_bit TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3416L27trin34">"dap3_din_pp1&quo34">&>3416s="15s6c8"6c8""""""".PIN_VI_VSYNC_PDslwf_width TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3417L27trin34>"dap3_dout_pp2&quo34>&q>341"RA_PIN_VI_VS}f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3418L27trin34">"dap3_fs_pp0"34">&>341VI_VSf">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3419L27trin34"dap3_sclk_pp3"34&qu>341l"RA_static const struct"PIN_VI_VSYNC_PDclpwm_E"Lgroup TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou342"L27trin34">"dap4_din_pp5&quo34">&>342nRA_PIN_VI_VSYSYNC_PD6comment">/*       pg_y1&q,              f0,           f1,           f2,           f3,           safq,         r,      od, ior */_/a>sc#f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3421L27trin34>"dap4_dout_pp6&quo34>&q>342"RA_PIN_VI_VSYSYNC_PD6comment">/* FIXME: Fill iC_Porrect"data iC_safq_Polumn */_/a>sc#f">TEGRA_Ppwm3_groupIND1_PE"L271" clpwm3_grou3422L27trin34">"dap4_fs_pp4"34">&>342l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 342l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "ddc_scl_pv4"34">&>342El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP 3425s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP 342l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "gen1_i2c_sda_34ing>342"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "pbb0"342VI_VSYNC_PD6342l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 343nRA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 343"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 343l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 343l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 343El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP 3435s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP 343l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "hdmi_int_pn7&quo34">&>343"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "jtag_rtck_pu7&quo34>&q>343VI_VSYNC_PD6"pwr_i2c_scl_pz6&34">&>343l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_i2c_sda_pz34ng">344nRA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "pwr_int_n"34ng">344"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 344l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&34g">>344l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py734g">>344El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py34ng">3445s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py34ng">344l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py34ng">344"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb34ng">344VI_VSYNC_PD6"sdmmc3_dat1_pb34ng">344l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc4_rst_n_p34ng">345nRA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "pwr_int_n"345g">345"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 345l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&345">>345l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7345">>345El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py345g">3455s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py345g">345l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py345g">345"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb345g">345VI_VSYNC_PD6"sdmmc3_dat1_pb345g">345l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc4_rst_n_p346g">346nRA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "pwr_int_n"346g">346"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 346l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&346">>346l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7346">>346El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py346g">3465s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py346g">346l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py346g">346"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb346g">346VI_VSYNC_PD6"sdmmc3_dat1_pb346g">346l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc4_rst_n_p347g">347nRA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "pwr_int_n"347g">347"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 347l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&347">>347l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7347">>347El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py347g">3475s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py347g">347l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py347g">347"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb347g">347VI_VSYNC_PD6"sdmmc3_dat1_pb347g">347l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc4_rst_n_p348g">348nRA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "pwr_int_n"348g">348"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 348l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&348">>348l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7348">>348El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py348g">3485s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py348g">348l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py348g">348"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb348g">348VI_VSYNC_PD6"sdmmc3_dat1_pb348g">348l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc4_rst_n_p349g">349nRA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "pwr_int_n"349g">349"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 349l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&349">>349l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7349">>349El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py349g">3495s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py349g">349l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py349g">349"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb349g">349VI_VSYNC_PD6"sdmmc3_dat1_pb349g">349l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 350""RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_int_n"350g">350"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 350l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&350">>350l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7350">>350El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py350g">3505s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py350g">350l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py350g">350"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb350g">350VI_VSYNC_PD6"sdmmc3_dat1_pb350g">350l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 351""RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_int_n"351g">351"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 351l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&351">>351l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7351">>351El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py351g">3515s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py351g">351l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py351g">351"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb351g">351VI_VSYNC_PD6"sdmmc3_dat1_pb351g">351l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 352""RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_int_n"352g">352"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 352l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&352">>352l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7352">>352El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py352g">3525s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py352g">352l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py352g">352"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb352g">352VI_VSYNC_PD6"sdmmc3_dat1_pb352g">352l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 353""RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_int_n"353g">353"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 353l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&353">>353l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7353">>353El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py353g">3535s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py353g">353l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py353g">353"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb353g">353VI_VSYNC_PD6"sdmmc3_dat1_pb353g">353l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 354""RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_int_n"354g">354"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 354l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&354">>354l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7354">>354El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py354g">3545s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py354g">354l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py354g">354"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb354g">354VI_VSYNC_PD6"sdmmc3_dat1_pb354g">354l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 355""RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_int_n"355g">355"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 355l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&355">>355l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7355">>355El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py355g">3555s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP 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361""RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_int_n"361g">361"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 361l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&361">>361l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7361">>361El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py361g">3615s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py361g">361l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py361g">361"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb361g">361VI_VSYNC_PD6"sdmmc3_dat1_pb361g">361l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 362""RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_int_n"362g">362"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 362l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&362">>362l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7362">>362El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py362g">3625s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py362g">362l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py362g">362"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb362g">362VI_VSYNC_PD6"sdmmc3_dat1_pb362g">362l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 363""RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_int_n"363g">363"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 363l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&363">>363l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7363">>363El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py363g">3635s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py363g">363l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py363g">363"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb363g">363VI_VSYNC_PD6"sdmmc3_dat1_pb363g">363l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 364""RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_int_n"364g">364"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 364l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&364">>364l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7364">>364El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py364g">3645s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py364g">364l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py364g">364"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb364g">364VI_VSYNC_PD6"sdmmc3_dat1_pb364g">364l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 365""RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_int_n"365g">365"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 365l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&365">>365l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7365">>365El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py365g">3655s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py365g">365l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py365g">365"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb365g">365VI_VSYNC_PD6"sdmmc3_dat1_pb365g">365l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 366""RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_int_n"366g">366"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP 366l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_cmd_pz1&366">>366l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat0_py7366">>366El"RA_PIN_VI_VIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat1_py366g">3665s="15s6c8">&qIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat2_py366g">366l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "sdmmc1_dat3_py366g">366"RA_PIN_VI_VSYIN_VI_VSYNC_PDPINGROUP "sdmmc3_dat0_pb366g">366VI_VSYNC_PD6"sdmmc3_dat1_pb366g">366l"RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP 367""RA_PIN_VI_VSIN_VI_VSYNC_PDPINGROUP "pwr_int_n"367g">367"RA_PIN_VI_VSYspan>"pcomment">/* pg__n&q, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */306" id826s=">26s5>15569 href};spanD1_PE"L27t3672L27trin367ot;sdmmc1_clk_pz0"367ot>367l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_cmd_pz1&367">>367l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat0_py7367">>367El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat1_py367g">3675s="15s6c8">&qIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat2_py367g">367l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat3_py367g">367"RA_PIN_VI_VSYIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc3_dat0_pb367g">367VI_VSYNC_PD6"sdmmc3_dat1_pb367g">367l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP 368""RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "pwr_int_n"368g">368"RA_PIN_VI_VSYIN_VI_VSYNC_PDDRV_PINGROUP 368l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_cmd_pz1&368">>368l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat0_py7368">>368El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat1_py368g">3685s="15s6c8">&qIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat2_py368g">368l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat3_py368g">368"RA_PIN_VI_VSYIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc3_dat0_pb368g">368VI_VSYNC_PD6"sdmmc3_dat1_pb368g">368l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP 369""RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "pwr_int_n"369g">369"RA_PIN_VI_VSYIN_VI_VSYNC_PDDRV_PINGROUP 369l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_cmd_pz1&369">>369l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat0_py7369">>369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat1_py369g">3695s="15s6c8">&qIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat2_py369g">369l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat3_py369g">369"RA_PIN_VI_VSYIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc3_dat0_pb369g">369VI_VSYNC_PD6"sdmmc3_dat1_pb369g">369l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP 370""RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "pwr_int_n"370g">370"RA_PIN_VI_VSYIN_VI_VSYNC_PDDRV_PINGROUP 370l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_cmd_pz1&370">>370l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat0_py7370">>370El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat1_py370g">3705s="15s6c8">&qIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat2_py370g">370l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_PINGROUP "sdmmc1_dat3_py370g"n370"RA_PIN_VI_VSYIN_VI_VSYNC_PDDRV_PINGROUP 37I_VSYNC_PDddc "pwr_int_n"369g">369"RA_PIN_VI_VSYIN_VI_VSYNC_PDDRV_709fc," 2," 3n class="sDRV_PINGROUP_V 3n " 5CI_VSYNC_PDgpv 15569 cref};spanD1_PE"L27t3703L27trin370">"sdmmc1_cmd_pz1&370">>370l"RA_PIN_VI_VSIN_VI_VSYNC_PDDRV_P1NGROUP 15569 cref};spanD1_PE"L27t3707L27trin370g">"sdmmc1_dat3_py370g"n370"RA_PIN_VI_VSYIN_VI_VSYNC_PDDRV_P1NGROUP 26s5>15569 2ref};spanD1_PE"L27t3707L27trin370g">"sdmmc1_dat3_py370g"n370"RA_PIN_VI_VSYIN_VI_VSYNC_PDDRV_P1NGROUP "sdmmc1_dat0_py7369">>369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_71NGROUP 1};0_py7369">>369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_71NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_71NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_71NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_71NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_718fc," 2," 1," 4," 12," 5," "RA_75," 10," 518_VSYNC_PDspi. >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_719fc," 2," 1n class="sDRV_PINGROUP_V 1n " 519_VSYNC_PDspi. >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_72NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_72NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_72NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_72NGROUP 1};0_py7369">>369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_72NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_72NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_72NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_72NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_728fc," 2," 2," 4," 12," 5," "RA_75," 20," 528_VSY}0_py7369">>369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_729fc," 2," 2n class="sDRV_PINGROUP_V 2n " 529_VSY0_py7369">>369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_73NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_73NGROUP "nvidia,VSYNC_P-_VImux"lk_pz0&, }t0_py7369">>369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_73NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_73NGROUP 1};0_py7369">>369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_73NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_73NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_73NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_73NGROUP "VSYNC_P-_VIN_VI"lk_pz0&,0_py7369">>369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_738fc," 2," 3," 4," 12," 5," "RA_75," 30," 538_VSYNC_PDspiNC_PDspi. >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_739fc," 2," 3n class="sDRV_PINGROUP_V 3n " 539_VSYNC_PDspiNC_PDspi. >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_74NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_74NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_74NGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_74NGROUP 1};0_py7369">>369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7ONGROUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP "Stephen Warren <swarren@nvidia.com>"lk_pz0&);0_py7369">>369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP "pwMODUL"_DESCRIPTIOi 20," w, drvup_b, string">"NVIDIA TSYNC_P _VIN_VI >369El"lk_pz0&);0_py7369">>369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP "GPL v2"lk_pz0&);0_py7369">>369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7OUP 26s5>1 >369El"RA_PIN_VI_VIN_VI_VSYNC_PDDRV_7ONGROUP 


The original LXR software by the _py7369">http://sourceforge.net/projects/lxl >LXR drvuuni"y26s5>1this experiup_wal 9El"ion by _py7369">mailto:lxl@ROUux.no">lxl@ROUux.no26s5.
lxl.ROUux.no kindly hostEd by _py7369">http://www.redpill-ROUpro.no">Redpill LOUpro ASn cla provider of LOUux consulting and opera_ioI" servic"" sVINe 1995.