linux/drivers/ide/siimage.c
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   1/*
   2 * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   3 * Copyright (C) 2003           Red Hat
   4 * Copyright (C) 2007-2008      MontaVista Software, Inc.
   5 * Copyright (C) 2007-2008      Bartlomiej Zolnierkiewicz
   6 *
   7 *  May be copied or modified under the terms of the GNU General Public License
   8 *
   9 *  Documentation for CMD680:
  10 *  http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
  11 *
  12 *  Documentation for SiI 3112:
  13 *  http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
  14 *
  15 *  Errata and other documentation only available under NDA.
  16 *
  17 *
  18 *  FAQ Items:
  19 *      If you are using Marvell SATA-IDE adapters with Maxtor drives
  20 *      ensure the system is set up for ATA100/UDMA5, not UDMA6.
  21 *
  22 *      If you are using WD drives with SATA bridges you must set the
  23 *      drive to "Single". "Master" will hang.
  24 *
  25 *      If you have strange problems with nVidia chipset systems please
  26 *      see the SI support documentation and update your system BIOS
  27 *      if necessary
  28 *
  29 *  The Dell DRAC4 has some interesting features including effectively hot
  30 *  unplugging/replugging the virtual CD interface when the DRAC is reset.
  31 *  This often causes drivers/ide/siimage to panic but is ok with the rather
  32 *  smarter code in libata.
  33 *
  34 * TODO:
  35 * - VDMA support
  36 */
  37
  38#include <linux/types.h>
  39#include <linux/module.h>
  40#include <linux/pci.h>
  41#include <linux/ide.h>
  42#include <linux/init.h>
  43#include <linux/io.h>
  44
  45#define DRV_NAME "siimage"
  46
  47/**
  48 *      pdev_is_sata            -       check if device is SATA
  49 *      @pdev:  PCI device to check
  50 *
  51 *      Returns true if this is a SATA controller
  52 */
  53
  54static int pdev_is_sata(struct pci_dev *pdev)
  55{
  56#ifdef CONFIG_BLK_DEV_IDE_SATA
  57        switch (pdev->device) {
  58        case PCI_DEVICE_ID_SII_3112:
  59        case PCI_DEVICE_ID_SII_1210SA:
  60                return 1;
  61        case PCI_DEVICE_ID_SII_680:
  62                return 0;
  63        }
  64        BUG();
  65#endif
  66        return 0;
  67}
  68
  69/**
  70 *      is_sata                 -       check if hwif is SATA
  71 *      @hwif:  interface to check
  72 *
  73 *      Returns true if this is a SATA controller
  74 */
  75
  76static inline int is_sata(ide_hwif_t *hwif)
  77{
  78        return pdev_is_sata(to_pci_dev(hwif->dev));
  79}
  80
  81/**
  82 *      siimage_selreg          -       return register base
  83 *      @hwif: interface
  84 *      @r: config offset
  85 *
  86 *      Turn a config register offset into the right address in either
  87 *      PCI space or MMIO space to access the control register in question
  88 *      Thankfully this is a configuration operation, so isn't performance
  89 *      critical.
  90 */
  91
  92static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
  93{
  94        unsigned long base = (unsigned long)hwif->hwif_data;
  95
  96        base += 0xA0 + r;
  97        if (hwif->host_flags & IDE_HFLAG_MMIO)
  98                base += hwif->channel << 6;
  99        else
 100                base += hwif->channel << 4;
 101        return base;
 102}
 103
 104/**
 105 *      siimage_seldev          -       return register base
 106 *      @hwif: interface
 107 *      @r: config offset
 108 *
 109 *      Turn a config register offset into the right address in either
 110 *      PCI space or MMIO space to access the control register in question
 111 *      including accounting for the unit shift.
 112 */
 113
 114static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
 115{
 116        ide_hwif_t *hwif        = drive->hwif;
 117        unsigned long base      = (unsigned long)hwif->hwif_data;
 118        u8 unit                 = drive->dn & 1;
 119
 120        base += 0xA0 + r;
 121        if (hwif->host_flags & IDE_HFLAG_MMIO)
 122                base += hwif->channel << 6;
 123        else
 124                base += hwif->channel << 4;
 125        base |= unit << unit;
 126        return base;
 127}
 128
 129static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
 130{
 131        struct ide_host *host = pci_get_drvdata(dev);
 132        u8 tmp = 0;
 133
 134        if (host->host_priv)
 135                tmp = readb((void __iomem *)addr);
 136        else
 137                pci_read_config_byte(dev, addr, &tmp);
 138
 139        return tmp;
 140}
 141
 142static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
 143{
 144        struct ide_host *host = pci_get_drvdata(dev);
 145        u16 tmp = 0;
 146
 147        if (host->host_priv)
 148                tmp = readw((void __iomem *)addr);
 149        else
 150                pci_read_config_word(dev, addr, &tmp);
 151
 152        return tmp;
 153}
 154
 155static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
 156{
 157        struct ide_host *host = pci_get_drvdata(dev);
 158
 159        if (host->host_priv)
 160                writeb(val, (void __iomem *)addr);
 161        else
 162                pci_write_config_byte(dev, addr, val);
 163}
 164
 165static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
 166{
 167        struct ide_host *host = pci_get_drvdata(dev);
 168
 169        if (host->host_priv)
 170                writew(val, (void __iomem *)addr);
 171        else
 172                pci_write_config_word(dev, addr, val);
 173}
 174
 175static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
 176{
 177        struct ide_host *host = pci_get_drvdata(dev);
 178
 179        if (host->host_priv)
 180                writel(val, (void __iomem *)addr);
 181        else
 182                pci_write_config_dword(dev, addr, val);
 183}
 184
 185/**
 186 *      sil_udma_filter         -       compute UDMA mask
 187 *      @drive: IDE device
 188 *
 189 *      Compute the available UDMA speeds for the device on the interface.
 190 *
 191 *      For the CMD680 this depends on the clocking mode (scsc), for the
 192 *      SI3112 SATA controller life is a bit simpler.
 193 */
 194
 195static u8 sil_pata_udma_filter(ide_drive_t *drive)
 196{
 197        ide_hwif_t *hwif        = drive->hwif;
 198        struct pci_dev *dev     = to_pci_dev(hwif->dev);
 199        unsigned long base      = (unsigned long)hwif->hwif_data;
 200        u8 scsc, mask           = 0;
 201
 202        base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A;
 203
 204        scsc = sil_ioread8(dev, base);
 205
 206        switch (scsc & 0x30) {
 207        case 0x10:      /* 133 */
 208                mask = ATA_UDMA6;
 209                break;
 210        case 0x20:      /* 2xPCI */
 211                mask = ATA_UDMA6;
 212                break;
 213        case 0x00:      /* 100 */
 214                mask = ATA_UDMA5;
 215                break;
 216        default:        /* Disabled ? */
 217                BUG();
 218        }
 219
 220        return mask;
 221}
 222
 223static u8 sil_sata_udma_filter(ide_drive_t *drive)
 224{
 225        char *m = (char *)&drive->id[ATA_ID_PROD];
 226
 227        return strstr(m, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6;
 228}
 229
 230/**
 231 *      sil_set_pio_mode        -       set host controller for PIO mode
 232 *      @hwif: port
 233 *      @drive: drive
 234 *
 235 *      Load the timing settings for this device mode into the
 236 *      controller.
 237 */
 238
 239static void sil_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 240{
 241        static const u16 tf_speed[]   = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
 242        static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
 243
 244        struct pci_dev *dev     = to_pci_dev(hwif->dev);
 245        ide_drive_t *pair       = ide_get_pair_dev(drive);
 246        u32 speedt              = 0;
 247        u16 speedp              = 0;
 248        unsigned long addr      = siimage_seldev(drive, 0x04);
 249        unsigned long tfaddr    = siimage_selreg(hwif,  0x02);
 250        unsigned long base      = (unsigned long)hwif->hwif_data;
 251        const u8 pio            = drive->pio_mode - XFER_PIO_0;
 252        u8 tf_pio               = pio;
 253        u8 mmio                 = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
 254        u8 addr_mask            = hwif->channel ? (mmio ? 0xF4 : 0x84)
 255                                                : (mmio ? 0xB4 : 0x80);
 256        u8 mode                 = 0;
 257        u8 unit                 = drive->dn & 1;
 258
 259        /* trim *taskfile* PIO to the slowest of the master/slave */
 260        if (pair) {
 261                u8 pair_pio = pair->pio_mode - XFER_PIO_0;
 262
 263                if (pair_pio < tf_pio)
 264                        tf_pio = pair_pio;
 265        }
 266
 267        /* cheat for now and use the docs */
 268        speedp = data_speed[pio];
 269        speedt = tf_speed[tf_pio];
 270
 271        sil_iowrite16(dev, speedp, addr);
 272        sil_iowrite16(dev, speedt, tfaddr);
 273
 274        /* now set up IORDY */
 275        speedp = sil_ioread16(dev, tfaddr - 2);
 276        speedp &= ~0x200;
 277
 278        mode = sil_ioread8(dev, base + addr_mask);
 279        mode &= ~(unit ? 0x30 : 0x03);
 280
 281        if (ide_pio_need_iordy(drive, pio)) {
 282                speedp |= 0x200;
 283                mode |= unit ? 0x10 : 0x01;
 284        }
 285
 286        sil_iowrite16(dev, speedp, tfaddr - 2);
 287        sil_iowrite8(dev, mode, base + addr_mask);
 288}
 289
 290/**
 291 *      sil_set_dma_mode        -       set host controller for DMA mode
 292 *      @hwif: port
 293 *      @drive: drive
 294 *
 295 *      Tune the SiI chipset for the desired DMA mode.
 296 */
 297
 298static void sil_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 299{
 300        static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
 301        static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
 302        static const u16 dma[]   = { 0x2208, 0x10C2, 0x10C1 };
 303
 304        struct pci_dev *dev     = to_pci_dev(hwif->dev);
 305        unsigned long base      = (unsigned long)hwif->hwif_data;
 306        u16 ultra = 0, multi    = 0;
 307        u8 mode = 0, unit       = drive->dn & 1;
 308        u8 mmio                 = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
 309        u8 scsc = 0, addr_mask  = hwif->channel ? (mmio ? 0xF4 : 0x84)
 310                                                : (mmio ? 0xB4 : 0x80);
 311        unsigned long ma        = siimage_seldev(drive, 0x08);
 312        unsigned long ua        = siimage_seldev(drive, 0x0C);
 313        const u8 speed          = drive->dma_mode;
 314
 315        scsc  = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A));
 316        mode  = sil_ioread8 (dev, base + addr_mask);
 317        multi = sil_ioread16(dev, ma);
 318        ultra = sil_ioread16(dev, ua);
 319
 320        mode  &= ~(unit ? 0x30 : 0x03);
 321        ultra &= ~0x3F;
 322        scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
 323
 324        scsc = is_sata(hwif) ? 1 : scsc;
 325
 326        if (speed >= XFER_UDMA_0) {
 327                multi  = dma[2];
 328                ultra |= scsc ? ultra6[speed - XFER_UDMA_0] :
 329                                ultra5[speed - XFER_UDMA_0];
 330                mode  |= unit ? 0x30 : 0x03;
 331        } else {
 332                multi = dma[speed - XFER_MW_DMA_0];
 333                mode |= unit ? 0x20 : 0x02;
 334        }
 335
 336        sil_iowrite8 (dev, mode, base + addr_mask);
 337        sil_iowrite16(dev, multi, ma);
 338        sil_iowrite16(dev, ultra, ua);
 339}
 340
 341static int sil_test_irq(ide_hwif_t *hwif)
 342{
 343        struct pci_dev *dev     = to_pci_dev(hwif->dev);
 344        unsigned long addr      = siimage_selreg(hwif, 1);
 345        u8 val                  = sil_ioread8(dev, addr);
 346
 347        /* Return 1 if INTRQ asserted */
 348        return (val & 8) ? 1 : 0;
 349}
 350
 351/**
 352 *      siimage_mmio_dma_test_irq       -       check we caused an IRQ
 353 *      @drive: drive we are testing
 354 *
 355 *      Check if we caused an IDE DMA interrupt. We may also have caused
 356 *      SATA status interrupts, if so we clean them up and continue.
 357 */
 358
 359static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
 360{
 361        ide_hwif_t *hwif        = drive->hwif;
 362        void __iomem *sata_error_addr
 363                = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
 364
 365        if (sata_error_addr) {
 366                unsigned long base      = (unsigned long)hwif->hwif_data;
 367                u32 ext_stat            = readl((void __iomem *)(base + 0x10));
 368                u8 watchdog             = 0;
 369
 370                if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
 371                        u32 sata_error = readl(sata_error_addr);
 372
 373                        writel(sata_error, sata_error_addr);
 374                        watchdog = (sata_error & 0x00680000) ? 1 : 0;
 375                        printk(KERN_WARNING "%s: sata_error = 0x%08x, "
 376                                "watchdog = %d, %s\n",
 377                                drive->name, sata_error, watchdog, __func__);
 378                } else
 379                        watchdog = (ext_stat & 0x8000) ? 1 : 0;
 380
 381                ext_stat >>= 16;
 382                if (!(ext_stat & 0x0404) && !watchdog)
 383                        return 0;
 384        }
 385
 386        /* return 1 if INTR asserted */
 387        if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4)
 388                return 1;
 389
 390        return 0;
 391}
 392
 393static int siimage_dma_test_irq(ide_drive_t *drive)
 394{
 395        if (drive->hwif->host_flags & IDE_HFLAG_MMIO)
 396                return siimage_mmio_dma_test_irq(drive);
 397        else
 398                return ide_dma_test_irq(drive);
 399}
 400
 401/**
 402 *      sil_sata_reset_poll     -       wait for SATA reset
 403 *      @drive: drive we are resetting
 404 *
 405 *      Poll the SATA phy and see whether it has come back from the dead
 406 *      yet.
 407 */
 408
 409static int sil_sata_reset_poll(ide_drive_t *drive)
 410{
 411        ide_hwif_t *hwif = drive->hwif;
 412        void __iomem *sata_status_addr
 413                = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET];
 414
 415        if (sata_status_addr) {
 416                /* SATA Status is available only when in MMIO mode */
 417                u32 sata_stat = readl(sata_status_addr);
 418
 419                if ((sata_stat & 0x03) != 0x03) {
 420                        printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
 421                                            hwif->name, sata_stat);
 422                        return -ENXIO;
 423                }
 424        }
 425
 426        return 0;
 427}
 428
 429/**
 430 *      sil_sata_pre_reset      -       reset hook
 431 *      @drive: IDE device being reset
 432 *
 433 *      For the SATA devices we need to handle recalibration/geometry
 434 *      differently
 435 */
 436
 437static void sil_sata_pre_reset(ide_drive_t *drive)
 438{
 439        if (drive->media == ide_disk) {
 440                drive->special_flags &=
 441                        ~(IDE_SFLAG_SET_GEOMETRY | IDE_SFLAG_RECALIBRATE);
 442        }
 443}
 444
 445/**
 446 *      init_chipset_siimage    -       set up an SI device
 447 *      @dev: PCI device
 448 *
 449 *      Perform the initial PCI set up for this device. Attempt to switch
 450 *      to 133 MHz clocking if the system isn't already set up to do it.
 451 */
 452
 453static int init_chipset_siimage(struct pci_dev *dev)
 454{
 455        struct ide_host *host = pci_get_drvdata(dev);
 456        void __iomem *ioaddr = host->host_priv;
 457        unsigned long base, scsc_addr;
 458        u8 rev = dev->revision, tmp;
 459
 460        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
 461
 462        if (ioaddr)
 463                pci_set_master(dev);
 464
 465        base = (unsigned long)ioaddr;
 466
 467        if (ioaddr && pdev_is_sata(dev)) {
 468                u32 tmp32, irq_mask;
 469
 470                /* make sure IDE0/1 interrupts are not masked */
 471                irq_mask = (1 << 22) | (1 << 23);
 472                tmp32 = readl(ioaddr + 0x48);
 473                if (tmp32 & irq_mask) {
 474                        tmp32 &= ~irq_mask;
 475                        writel(tmp32, ioaddr + 0x48);
 476                        readl(ioaddr + 0x48); /* flush */
 477                }
 478                writel(0, ioaddr + 0x148);
 479                writel(0, ioaddr + 0x1C8);
 480        }
 481
 482        sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
 483        sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
 484
 485        scsc_addr = base ? (base + 0x4A) : 0x8A;
 486        tmp = sil_ioread8(dev, scsc_addr);
 487
 488        switch (tmp & 0x30) {
 489        case 0x00:
 490                /* On 100 MHz clocking, try and switch to 133 MHz */
 491                sil_iowrite8(dev, tmp | 0x10, scsc_addr);
 492                break;
 493        case 0x30:
 494                /* Clocking is disabled, attempt to force 133MHz clocking. */
 495                sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
 496        case 0x10:
 497                /* On 133Mhz clocking. */
 498                break;
 499        case 0x20:
 500                /* On PCIx2 clocking. */
 501                break;
 502        }
 503
 504        tmp = sil_ioread8(dev, scsc_addr);
 505
 506        sil_iowrite8 (dev,       0x72, base + 0xA1);
 507        sil_iowrite16(dev,     0x328A, base + 0xA2);
 508        sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
 509        sil_iowrite32(dev, 0x43924392, base + 0xA8);
 510        sil_iowrite32(dev, 0x40094009, base + 0xAC);
 511        sil_iowrite8 (dev,       0x72, base ? (base + 0xE1) : 0xB1);
 512        sil_iowrite16(dev,     0x328A, base ? (base + 0xE2) : 0xB2);
 513        sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
 514        sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
 515        sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
 516
 517        if (base && pdev_is_sata(dev)) {
 518                writel(0xFFFF0000, ioaddr + 0x108);
 519                writel(0xFFFF0000, ioaddr + 0x188);
 520                writel(0x00680000, ioaddr + 0x148);
 521                writel(0x00680000, ioaddr + 0x1C8);
 522        }
 523
 524        /* report the clocking mode of the controller */
 525        if (!pdev_is_sata(dev)) {
 526                static const char *clk_str[] =
 527                        { "== 100", "== 133", "== 2X PCI", "DISABLED!" };
 528
 529                tmp >>= 4;
 530                printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n",
 531                        pci_name(dev), clk_str[tmp & 3]);
 532        }
 533
 534        return 0;
 535}
 536
 537/**
 538 *      init_mmio_iops_siimage  -       set up the iops for MMIO
 539 *      @hwif: interface to set up
 540 *
 541 *      The basic setup here is fairly simple, we can use standard MMIO
 542 *      operations. However we do have to set the taskfile register offsets
 543 *      by hand as there isn't a standard defined layout for them this time.
 544 *
 545 *      The hardware supports buffered taskfiles and also some rather nice
 546 *      extended PRD tables. For better SI3112 support use the libata driver
 547 */
 548
 549static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
 550{
 551        struct pci_dev *dev     = to_pci_dev(hwif->dev);
 552        struct ide_host *host   = pci_get_drvdata(dev);
 553        void *addr              = host->host_priv;
 554        u8 ch                   = hwif->channel;
 555        struct ide_io_ports *io_ports = &hwif->io_ports;
 556        unsigned long base;
 557
 558        /*
 559         *      Fill in the basic hwif bits
 560         */
 561        hwif->host_flags |= IDE_HFLAG_MMIO;
 562
 563        hwif->hwif_data = addr;
 564
 565        /*
 566         *      Now set up the hw. We have to do this ourselves as the
 567         *      MMIO layout isn't the same as the standard port based I/O.
 568         */
 569        memset(io_ports, 0, sizeof(*io_ports));
 570
 571        base = (unsigned long)addr;
 572        if (ch)
 573                base += 0xC0;
 574        else
 575                base += 0x80;
 576
 577        /*
 578         *      The buffered task file doesn't have status/control, so we
 579         *      can't currently use it sanely since we want to use LBA48 mode.
 580         */
 581        io_ports->data_addr     = base;
 582        io_ports->error_addr    = base + 1;
 583        io_ports->nsect_addr    = base + 2;
 584        io_ports->lbal_addr     = base + 3;
 585        io_ports->lbam_addr     = base + 4;
 586        io_ports->lbah_addr     = base + 5;
 587        io_ports->device_addr   = base + 6;
 588        io_ports->status_addr   = base + 7;
 589        io_ports->ctl_addr      = base + 10;
 590
 591        if (pdev_is_sata(dev)) {
 592                base = (unsigned long)addr;
 593                if (ch)
 594                        base += 0x80;
 595                hwif->sata_scr[SATA_STATUS_OFFSET]      = base + 0x104;
 596                hwif->sata_scr[SATA_ERROR_OFFSET]       = base + 0x108;
 597                hwif->sata_scr[SATA_CONTROL_OFFSET]     = base + 0x100;
 598        }
 599
 600        hwif->irq = dev->irq;
 601
 602        hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
 603}
 604
 605static int is_dev_seagate_sata(ide_drive_t *drive)
 606{
 607        const char *s   = (const char *)&drive->id[ATA_ID_PROD];
 608        unsigned len    = strnlen(s, ATA_ID_PROD_LEN);
 609
 610        if ((len > 4) && (!memcmp(s, "ST", 2)))
 611                if ((!memcmp(s + len - 2, "AS", 2)) ||
 612                    (!memcmp(s + len - 3, "ASL", 3))) {
 613                        printk(KERN_INFO "%s: applying pessimistic Seagate "
 614                                         "errata fix\n", drive->name);
 615                        return 1;
 616                }
 617
 618        return 0;
 619}
 620
 621/**
 622 *      sil_quirkproc           -       post probe fixups
 623 *      @drive: drive
 624 *
 625 *      Called after drive probe we use this to decide whether the
 626 *      Seagate fixup must be applied. This used to be in init_iops but
 627 *      that can occur before we know what drives are present.
 628 */
 629
 630static void sil_quirkproc(ide_drive_t *drive)
 631{
 632        ide_hwif_t *hwif = drive->hwif;
 633
 634        /* Try and rise the rqsize */
 635        if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
 636                hwif->rqsize = 128;
 637}
 638
 639/**
 640 *      init_iops_siimage       -       set up iops
 641 *      @hwif: interface to set up
 642 *
 643 *      Do the basic setup for the SIIMAGE hardware interface
 644 *      and then do the MMIO setup if we can. This is the first
 645 *      look in we get for setting up the hwif so that we
 646 *      can get the iops right before using them.
 647 */
 648
 649static void __devinit init_iops_siimage(ide_hwif_t *hwif)
 650{
 651        struct pci_dev *dev = to_pci_dev(hwif->dev);
 652        struct ide_host *host = pci_get_drvdata(dev);
 653
 654        hwif->hwif_data = NULL;
 655
 656        /* Pessimal until we finish probing */
 657        hwif->rqsize = 15;
 658
 659        if (host->host_priv)
 660                init_mmio_iops_siimage(hwif);
 661}
 662
 663/**
 664 *      sil_cable_detect        -       cable detection
 665 *      @hwif: interface to check
 666 *
 667 *      Check for the presence of an ATA66 capable cable on the interface.
 668 */
 669
 670static u8 sil_cable_detect(ide_hwif_t *hwif)
 671{
 672        struct pci_dev *dev     = to_pci_dev(hwif->dev);
 673        unsigned long addr      = siimage_selreg(hwif, 0);
 674        u8 ata66                = sil_ioread8(dev, addr);
 675
 676        return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 677}
 678
 679static const struct ide_port_ops sil_pata_port_ops = {
 680        .set_pio_mode           = sil_set_pio_mode,
 681        .set_dma_mode           = sil_set_dma_mode,
 682        .quirkproc              = sil_quirkproc,
 683        .test_irq               = sil_test_irq,
 684        .udma_filter            = sil_pata_udma_filter,
 685        .cable_detect           = sil_cable_detect,
 686};
 687
 688static const struct ide_port_ops sil_sata_port_ops = {
 689        .set_pio_mode           = sil_set_pio_mode,
 690        .set_dma_mode           = sil_set_dma_mode,
 691        .reset_poll             = sil_sata_reset_poll,
 692        .pre_reset              = sil_sata_pre_reset,
 693        .quirkproc              = sil_quirkproc,
 694        .test_irq               = sil_test_irq,
 695        .udma_filter            = sil_sata_udma_filter,
 696        .cable_detect           = sil_cable_detect,
 697};
 698
 699static const struct ide_dma_ops sil_dma_ops = {
 700        .dma_host_set           = ide_dma_host_set,
 701        .dma_setup              = ide_dma_setup,
 702        .dma_start              = ide_dma_start,
 703        .dma_end                = ide_dma_end,
 704        .dma_test_irq           = siimage_dma_test_irq,
 705        .dma_timer_expiry       = ide_dma_sff_timer_expiry,
 706        .dma_lost_irq           = ide_dma_lost_irq,
 707        .dma_sff_read_status    = ide_dma_sff_read_status,
 708};
 709
 710#define DECLARE_SII_DEV(p_ops)                          \
 711        {                                               \
 712                .name           = DRV_NAME,             \
 713                .init_chipset   = init_chipset_siimage, \
 714                .init_iops      = init_iops_siimage,    \
 715                .port_ops       = p_ops,                \
 716                .dma_ops        = &sil_dma_ops,         \
 717                .pio_mask       = ATA_PIO4,             \
 718                .mwdma_mask     = ATA_MWDMA2,           \
 719                .udma_mask      = ATA_UDMA6,            \
 720        }
 721
 722static const struct ide_port_info siimage_chipsets[] __devinitconst = {
 723        /* 0: SiI680 */  DECLARE_SII_DEV(&sil_pata_port_ops),
 724        /* 1: SiI3112 */ DECLARE_SII_DEV(&sil_sata_port_ops)
 725};
 726
 727/**
 728 *      siimage_init_one        -       PCI layer discovery entry
 729 *      @dev: PCI device
 730 *      @id: ident table entry
 731 *
 732 *      Called by the PCI code when it finds an SiI680 or SiI3112 controller.
 733 *      We then use the IDE PCI generic helper to do most of the work.
 734 */
 735
 736static int __devinit siimage_init_one(struct pci_dev *dev,
 737                                      const struct pci_device_id *id)
 738{
 739        void __iomem *ioaddr = NULL;
 740        resource_size_t bar5 = pci_resource_start(dev, 5);
 741        unsigned long barsize = pci_resource_len(dev, 5);
 742        int rc;
 743        struct ide_port_info d;
 744        u8 idx = id->driver_data;
 745        u8 BA5_EN;
 746
 747        d = siimage_chipsets[idx];
 748
 749        if (idx) {
 750                static int first = 1;
 751
 752                if (first) {
 753                        printk(KERN_INFO DRV_NAME ": For full SATA support you "
 754                                "should use the libata sata_sil module.\n");
 755                        first = 0;
 756                }
 757
 758                d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
 759        }
 760
 761        rc = pci_enable_device(dev);
 762        if (rc)
 763                return rc;
 764
 765        pci_read_config_byte(dev, 0x8A, &BA5_EN);
 766        if ((BA5_EN & 0x01) || bar5) {
 767                /*
 768                * Drop back to PIO if we can't map the MMIO. Some systems
 769                * seem to get terminally confused in the PCI spaces.
 770                */
 771                if (!request_mem_region(bar5, barsize, d.name)) {
 772                        printk(KERN_WARNING DRV_NAME " %s: MMIO ports not "
 773                                "available\n", pci_name(dev));
 774                } else {
 775                        ioaddr = pci_ioremap_bar(dev, 5);
 776                        if (ioaddr == NULL)
 777                                release_mem_region(bar5, barsize);
 778                }
 779        }
 780
 781        rc = ide_pci_init_one(dev, &d, ioaddr);
 782        if (rc) {
 783                if (ioaddr) {
 784                        iounmap(ioaddr);
 785                        release_mem_region(bar5, barsize);
 786                }
 787                pci_disable_device(dev);
 788        }
 789
 790        return rc;
 791}
 792
 793static void __devexit siimage_remove(struct pci_dev *dev)
 794{
 795        struct ide_host *host = pci_get_drvdata(dev);
 796        void __iomem *ioaddr = host->host_priv;
 797
 798        ide_pci_remove(dev);
 799
 800        if (ioaddr) {
 801                resource_size_t bar5 = pci_resource_start(dev, 5);
 802                unsigned long barsize = pci_resource_len(dev, 5);
 803
 804                iounmap(ioaddr);
 805                release_mem_region(bar5, barsize);
 806        }
 807
 808        pci_disable_device(dev);
 809}
 810
 811static const struct pci_device_id siimage_pci_tbl[] = {
 812        { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680),    0 },
 813#ifdef CONFIG_BLK_DEV_IDE_SATA
 814        { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112),   1 },
 815        { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 1 },
 816#endif
 817        { 0, },
 818};
 819MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
 820
 821static struct pci_driver siimage_pci_driver = {
 822        .name           = "SiI_IDE",
 823        .id_table       = siimage_pci_tbl,
 824        .probe          = siimage_init_one,
 825        .remove         = __devexit_p(siimage_remove),
 826        .suspend        = ide_pci_suspend,
 827        .resume         = ide_pci_resume,
 828};
 829
 830static int __init siimage_ide_init(void)
 831{
 832        return ide_pci_register_driver(&siimage_pci_driver);
 833}
 834
 835static void __exit siimage_ide_exit(void)
 836{
 837        pci_unregister_driver(&siimage_pci_driver);
 838}
 839
 840module_init(siimage_ide_init);
 841module_exit(siimage_ide_exit);
 842
 843MODULE_AUTHOR("Andre Hedrick, Alan Cox");
 844MODULE_DESCRIPTION("PCI driver module for SiI IDE");
 845MODULE_LICENSE("GPL");
 846
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