linux/drivers/clk/clk-highbank.c
<<
>>
Prefs
   1/*
   2 * Copyright 2011-2012 Calxeda, Inc.
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms and conditions of the GNU General Public License,
   6 * version 2, as published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope it will be useful, but WITHOUT
   9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11 * more details.
  12 *
  13 * You should have received a copy of the GNU General Public License along with
  14 * this program.  If not, see <http://www.gnu.org/licenses/>.
  15 */
  16
  17#include <linux/kernel.h>
  18#include <linux/slab.h>
  19#include <linux/err.h>
  20#include <linux/clk-provider.h>
  21#include <linux/io.h>
  22#include <linux/of.h>
  23
  24extern void __iomem *sregs_base;
  25
  26#define HB_PLL_LOCK_500         0x20000000
  27#define HB_PLL_LOCK             0x10000000
  28#define HB_PLL_DIVF_SHIFT       20
  29#define HB_PLL_DIVF_MASK        0x0ff00000
  30#define HB_PLL_DIVQ_SHIFT       16
  31#define HB_PLL_DIVQ_MASK        0x00070000
  32#define HB_PLL_DIVR_SHIFT       8
  33#define HB_PLL_DIVR_MASK        0x00001f00
  34#define HB_PLL_RANGE_SHIFT      4
  35#define HB_PLL_RANGE_MASK       0x00000070
  36#define HB_PLL_BYPASS           0x00000008
  37#define HB_PLL_RESET            0x00000004
  38#define HB_PLL_EXT_BYPASS       0x00000002
  39#define HB_PLL_EXT_ENA          0x00000001
  40
  41#define HB_PLL_VCO_MIN_FREQ     2133000000
  42#define HB_PLL_MAX_FREQ         HB_PLL_VCO_MIN_FREQ
  43#define HB_PLL_MIN_FREQ         (HB_PLL_VCO_MIN_FREQ / 64)
  44
  45#define HB_A9_BCLK_DIV_MASK     0x00000006
  46#define HB_A9_BCLK_DIV_SHIFT    1
  47#define HB_A9_PCLK_DIV          0x00000001
  48
  49struct hb_clk {
  50        struct clk_hw   hw;
  51        void __iomem    *reg;
  52        char *parent_name;
  53};
  54#define to_hb_clk(p) container_of(p, struct hb_clk, hw)
  55
  56static int clk_pll_prepare(struct clk_hw *hwclk)
  57        {
  58        struct hb_clk *hbclk = to_hb_clk(hwclk);
  59        u32 reg;
  60
  61        reg = readl(hbclk->reg);
  62        reg &= ~HB_PLL_RESET;
  63        writel(reg, hbclk->reg);
  64
  65        while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
  66                ;
  67        while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
  68                ;
  69
  70        return 0;
  71}
  72
  73static void clk_pll_unprepare(struct clk_hw *hwclk)
  74{
  75        struct hb_clk *hbclk = to_hb_clk(hwclk);
  76        u32 reg;
  77
  78        reg = readl(hbclk->reg);
  79        reg |= HB_PLL_RESET;
  80        writel(reg, hbclk->reg);
  81}
  82
  83static int clk_pll_enable(struct clk_hw *hwclk)
  84{
  85        struct hb_clk *hbclk = to_hb_clk(hwclk);
  86        u32 reg;
  87
  88        reg = readl(hbclk->reg);
  89        reg |= HB_PLL_EXT_ENA;
  90        writel(reg, hbclk->reg);
  91
  92        return 0;
  93}
  94
  95static void clk_pll_disable(struct clk_hw *hwclk)
  96{
  97        struct hb_clk *hbclk = to_hb_clk(hwclk);
  98        u32 reg;
  99
 100        reg = readl(hbclk->reg);
 101        reg &= ~HB_PLL_EXT_ENA;
 102        writel(reg, hbclk->reg);
 103}
 104
 105static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
 106                                         unsigned long parent_rate)
 107{
 108        struct hb_clk *hbclk = to_hb_clk(hwclk);
 109        unsigned long divf, divq, vco_freq, reg;
 110
 111        reg = readl(hbclk->reg);
 112        if (reg & HB_PLL_EXT_BYPASS)
 113                return parent_rate;
 114
 115        divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
 116        divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
 117        vco_freq = parent_rate * (divf + 1);
 118
 119        return vco_freq / (1 << divq);
 120}
 121
 122static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
 123                        u32 *pdivq, u32 *pdivf)
 124{
 125        u32 divq, divf;
 126        unsigned long vco_freq;
 127
 128        if (rate < HB_PLL_MIN_FREQ)
 129                rate = HB_PLL_MIN_FREQ;
 130        if (rate > HB_PLL_MAX_FREQ)
 131                rate = HB_PLL_MAX_FREQ;
 132
 133        for (divq = 1; divq <= 6; divq++) {
 134                if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
 135                        break;
 136        }
 137
 138        vco_freq = rate * (1 << divq);
 139        divf = (vco_freq + (ref_freq / 2)) / ref_freq;
 140        divf--;
 141
 142        *pdivq = divq;
 143        *pdivf = divf;
 144}
 145
 146static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate,
 147                               unsigned long *parent_rate)
 148{
 149        u32 divq, divf;
 150        unsigned long ref_freq = *parent_rate;
 151
 152        clk_pll_calc(rate, ref_freq, &divq, &divf);
 153
 154        return (ref_freq * (divf + 1)) / (1 << divq);
 155}
 156
 157static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
 158                            unsigned long parent_rate)
 159{
 160        struct hb_clk *hbclk = to_hb_clk(hwclk);
 161        u32 divq, divf;
 162        u32 reg;
 163
 164        clk_pll_calc(rate, parent_rate, &divq, &divf);
 165
 166        reg = readl(hbclk->reg);
 167        if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
 168                /* Need to re-lock PLL, so put it into bypass mode */
 169                reg |= HB_PLL_EXT_BYPASS;
 170                writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
 171
 172                writel(reg | HB_PLL_RESET, hbclk->reg);
 173                reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
 174                reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
 175                writel(reg | HB_PLL_RESET, hbclk->reg);
 176                writel(reg, hbclk->reg);
 177
 178                while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
 179                        ;
 180                while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
 181                        ;
 182                reg |= HB_PLL_EXT_ENA;
 183                reg &= ~HB_PLL_EXT_BYPASS;
 184        } else {
 185                reg &= ~HB_PLL_DIVQ_MASK;
 186                reg |= divq << HB_PLL_DIVQ_SHIFT;
 187        }
 188        writel(reg, hbclk->reg);
 189
 190        return 0;
 191}
 192
 193static const struct clk_ops clk_pll_ops = {
 194        .prepare = clk_pll_prepare,
 195        .unprepare = clk_pll_unprepare,
 196        .enable = clk_pll_enable,
 197        .disable = clk_pll_disable,
 198        .recalc_rate = clk_pll_recalc_rate,
 199        .round_rate = clk_pll_round_rate,
 200        .set_rate = clk_pll_set_rate,
 201};
 202
 203static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *hwclk,
 204                                                   unsigned long parent_rate)
 205{
 206        struct hb_clk *hbclk = to_hb_clk(hwclk);
 207        u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;
 208        return parent_rate / div;
 209}
 210
 211static const struct clk_ops a9periphclk_ops = {
 212        .recalc_rate = clk_cpu_periphclk_recalc_rate,
 213};
 214
 215static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *hwclk,
 216                                                unsigned long parent_rate)
 217{
 218        struct hb_clk *hbclk = to_hb_clk(hwclk);
 219        u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;
 220
 221        return parent_rate / (div + 2);
 222}
 223
 224static const struct clk_ops a9bclk_ops = {
 225        .recalc_rate = clk_cpu_a9bclk_recalc_rate,
 226};
 227
 228static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
 229                                             unsigned long parent_rate)
 230{
 231        struct hb_clk *hbclk = to_hb_clk(hwclk);
 232        u32 div;
 233
 234        div = readl(hbclk->reg) & 0x1f;
 235        div++;
 236        div *= 2;
 237
 238        return parent_rate / div;
 239}
 240
 241static long clk_periclk_round_rate(struct clk_hw *hwclk, unsigned long rate,
 242                                   unsigned long *parent_rate)
 243{
 244        u32 div;
 245
 246        div = *parent_rate / rate;
 247        div++;
 248        div &= ~0x1;
 249
 250        return *parent_rate / div;
 251}
 252
 253static int clk_periclk_set_rate(struct clk_hw *hwclk, unsigned long rate,
 254                                unsigned long parent_rate)
 255{
 256        struct hb_clk *hbclk = to_hb_clk(hwclk);
 257        u32 div;
 258
 259        div = parent_rate / rate;
 260        if (div & 0x1)
 261                return -EINVAL;
 262
 263        writel(div >> 1, hbclk->reg);
 264        return 0;
 265}
 266
 267static const struct clk_ops periclk_ops = {
 268        .recalc_rate = clk_periclk_recalc_rate,
 269        .round_rate = clk_periclk_round_rate,
 270        .set_rate = clk_periclk_set_rate,
 271};
 272
 273static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops)
 274{
 275        u32 reg;
 276        struct clk *clk;
 277        struct hb_clk *hb_clk;
 278        const char *clk_name = node->name;
 279        const char *parent_name;
 280        struct clk_init_data init;
 281        int rc;
 282
 283        rc = of_property_read_u32(node, "reg", &reg);
 284        if (WARN_ON(rc))
 285                return NULL;
 286
 287        hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
 288        if (WARN_ON(!hb_clk))
 289                return NULL;
 290
 291        hb_clk->reg = sregs_base + reg;
 292
 293        of_property_read_string(node, "clock-output-names", &clk_name);
 294
 295        init.name = clk_name;
 296        init.ops = ops;
 297        init.flags = 0;
 298        parent_name = of_clk_get_parent_name(node, 0);
 299        init.parent_names = &parent_name;
 300        init.num_parents = 1;
 301
 302        hb_clk->hw.init = &init;
 303
 304        clk = clk_register(NULL, &hb_clk->hw);
 305        if (WARN_ON(IS_ERR(clk))) {
 306                kfree(hb_clk);
 307                return NULL;
 308        }
 309        rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
 310        return clk;
 311}
 312
 313static void __init hb_pll_init(struct device_node *node)
 314{
 315        hb_clk_init(node, &clk_pll_ops);
 316}
 317
 318static void __init hb_a9periph_init(struct device_node *node)
 319{
 320        hb_clk_init(node, &a9periphclk_ops);
 321}
 322
 323static void __init hb_a9bus_init(struct device_node *node)
 324{
 325        struct clk *clk = hb_clk_init(node, &a9bclk_ops);
 326        clk_prepare_enable(clk);
 327}
 328
 329static void __init hb_emmc_init(struct device_node *node)
 330{
 331        hb_clk_init(node, &periclk_ops);
 332}
 333
 334static const __initconst struct of_device_id clk_match[] = {
 335        { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
 336        { .compatible = "calxeda,hb-pll-clock", .data = hb_pll_init, },
 337        { .compatible = "calxeda,hb-a9periph-clock", .data = hb_a9periph_init, },
 338        { .compatible = "calxeda,hb-a9bus-clock", .data = hb_a9bus_init, },
 339        { .compatible = "calxeda,hb-emmc-clock", .data = hb_emmc_init, },
 340        {}
 341};
 342
 343void __init highbank_clocks_init(void)
 344{
 345        of_clk_init(clk_match);
 346}
 347
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.