linux/arch/blackfin/Kconfig
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   1config SYMBOL_PREFIX
   2        string
   3        default "_"
   4
   5config MMU
   6        def_bool n
   7
   8config FPU
   9        def_bool n
  10
  11config RWSEM_GENERIC_SPINLOCK
  12        def_bool y
  13
  14config RWSEM_XCHGADD_ALGORITHM
  15        def_bool n
  16
  17config BLACKFIN
  18        def_bool y
  19        select HAVE_ARCH_KGDB
  20        select HAVE_ARCH_TRACEHOOK
  21        select HAVE_DYNAMIC_FTRACE
  22        select HAVE_FTRACE_MCOUNT_RECORD
  23        select HAVE_FUNCTION_GRAPH_TRACER
  24        select HAVE_FUNCTION_TRACER
  25        select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  26        select HAVE_IDE
  27        select HAVE_IRQ_WORK
  28        select HAVE_KERNEL_GZIP if RAMKERNEL
  29        select HAVE_KERNEL_BZIP2 if RAMKERNEL
  30        select HAVE_KERNEL_LZMA if RAMKERNEL
  31        select HAVE_KERNEL_LZO if RAMKERNEL
  32        select HAVE_OPROFILE
  33        select HAVE_PERF_EVENTS
  34        select ARCH_HAVE_CUSTOM_GPIO_H
  35        select ARCH_WANT_OPTIONAL_GPIOLIB
  36        select HAVE_UID16
  37        select ARCH_WANT_IPC_PARSE_VERSION
  38        select HAVE_GENERIC_HARDIRQS
  39        select GENERIC_ATOMIC64
  40        select GENERIC_IRQ_PROBE
  41        select IRQ_PER_CPU if SMP
  42        select USE_GENERIC_SMP_HELPERS if SMP
  43        select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
  44        select GENERIC_SMP_IDLE_THREAD
  45        select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
  46        select HAVE_MOD_ARCH_SPECIFIC
  47        select MODULES_USE_ELF_RELA
  48
  49config GENERIC_CSUM
  50        def_bool y
  51
  52config GENERIC_BUG
  53        def_bool y
  54        depends on BUG
  55
  56config ZONE_DMA
  57        def_bool y
  58
  59config GENERIC_GPIO
  60        def_bool y
  61
  62config FORCE_MAX_ZONEORDER
  63        int
  64        default "14"
  65
  66config GENERIC_CALIBRATE_DELAY
  67        def_bool y
  68
  69config LOCKDEP_SUPPORT
  70        def_bool y
  71
  72config STACKTRACE_SUPPORT
  73        def_bool y
  74
  75config TRACE_IRQFLAGS_SUPPORT
  76        def_bool y
  77
  78source "init/Kconfig"
  79
  80source "kernel/Kconfig.preempt"
  81
  82source "kernel/Kconfig.freezer"
  83
  84menu "Blackfin Processor Options"
  85
  86comment "Processor and Board Settings"
  87
  88choice
  89        prompt "CPU"
  90        default BF533
  91
  92config BF512
  93        bool "BF512"
  94        help
  95          BF512 Processor Support.
  96
  97config BF514
  98        bool "BF514"
  99        help
 100          BF514 Processor Support.
 101
 102config BF516
 103        bool "BF516"
 104        help
 105          BF516 Processor Support.
 106
 107config BF518
 108        bool "BF518"
 109        help
 110          BF518 Processor Support.
 111
 112config BF522
 113        bool "BF522"
 114        help
 115          BF522 Processor Support.
 116
 117config BF523
 118        bool "BF523"
 119        help
 120          BF523 Processor Support.
 121
 122config BF524
 123        bool "BF524"
 124        help
 125          BF524 Processor Support.
 126
 127config BF525
 128        bool "BF525"
 129        help
 130          BF525 Processor Support.
 131
 132config BF526
 133        bool "BF526"
 134        help
 135          BF526 Processor Support.
 136
 137config BF527
 138        bool "BF527"
 139        help
 140          BF527 Processor Support.
 141
 142config BF531
 143        bool "BF531"
 144        help
 145          BF531 Processor Support.
 146
 147config BF532
 148        bool "BF532"
 149        help
 150          BF532 Processor Support.
 151
 152config BF533
 153        bool "BF533"
 154        help
 155          BF533 Processor Support.
 156
 157config BF534
 158        bool "BF534"
 159        help
 160          BF534 Processor Support.
 161
 162config BF536
 163        bool "BF536"
 164        help
 165          BF536 Processor Support.
 166
 167config BF537
 168        bool "BF537"
 169        help
 170          BF537 Processor Support.
 171
 172config BF538
 173        bool "BF538"
 174        help
 175          BF538 Processor Support.
 176
 177config BF539
 178        bool "BF539"
 179        help
 180          BF539 Processor Support.
 181
 182config BF542_std
 183        bool "BF542"
 184        help
 185          BF542 Processor Support.
 186
 187config BF542M
 188        bool "BF542m"
 189        help
 190          BF542 Processor Support.
 191
 192config BF544_std
 193        bool "BF544"
 194        help
 195          BF544 Processor Support.
 196
 197config BF544M
 198        bool "BF544m"
 199        help
 200          BF544 Processor Support.
 201
 202config BF547_std
 203        bool "BF547"
 204        help
 205          BF547 Processor Support.
 206
 207config BF547M
 208        bool "BF547m"
 209        help
 210          BF547 Processor Support.
 211
 212config BF548_std
 213        bool "BF548"
 214        help
 215          BF548 Processor Support.
 216
 217config BF548M
 218        bool "BF548m"
 219        help
 220          BF548 Processor Support.
 221
 222config BF549_std
 223        bool "BF549"
 224        help
 225          BF549 Processor Support.
 226
 227config BF549M
 228        bool "BF549m"
 229        help
 230          BF549 Processor Support.
 231
 232config BF561
 233        bool "BF561"
 234        help
 235          BF561 Processor Support.
 236
 237config BF609
 238        bool "BF609"
 239        select CLKDEV_LOOKUP
 240        help
 241          BF609 Processor Support.
 242
 243endchoice
 244
 245config SMP
 246        depends on BF561
 247        select TICKSOURCE_CORETMR
 248        bool "Symmetric multi-processing support"
 249        ---help---
 250          This enables support for systems with more than one CPU,
 251          like the dual core BF561. If you have a system with only one
 252          CPU, say N. If you have a system with more than one CPU, say Y.
 253
 254          If you don't know what to do here, say N.
 255
 256config NR_CPUS
 257        int
 258        depends on SMP
 259        default 2 if BF561
 260
 261config HOTPLUG_CPU
 262        bool "Support for hot-pluggable CPUs"
 263        depends on SMP && HOTPLUG
 264        default y
 265
 266config BF_REV_MIN
 267        int
 268        default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 269        default 2 if (BF537 || BF536 || BF534)
 270        default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 271        default 4 if (BF538 || BF539)
 272
 273config BF_REV_MAX
 274        int
 275        default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 276        default 3 if (BF537 || BF536 || BF534 || BF54xM)
 277        default 5 if (BF561 || BF538 || BF539)
 278        default 6 if (BF533 || BF532 || BF531)
 279
 280choice
 281        prompt "Silicon Rev"
 282        default BF_REV_0_0 if (BF51x || BF52x || BF60x)
 283        default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 284        default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 285
 286config BF_REV_0_0
 287        bool "0.0"
 288        depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
 289
 290config BF_REV_0_1
 291        bool "0.1"
 292        depends on (BF51x || BF52x || (BF54x && !BF54xM))
 293
 294config BF_REV_0_2
 295        bool "0.2"
 296        depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 297
 298config BF_REV_0_3
 299        bool "0.3"
 300        depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 301
 302config BF_REV_0_4
 303        bool "0.4"
 304        depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
 305
 306config BF_REV_0_5
 307        bool "0.5"
 308        depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 309
 310config BF_REV_0_6
 311        bool "0.6"
 312        depends on (BF533 || BF532 || BF531)
 313
 314config BF_REV_ANY
 315        bool "any"
 316
 317config BF_REV_NONE
 318        bool "none"
 319
 320endchoice
 321
 322config BF53x
 323        bool
 324        depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 325        default y
 326
 327config MEM_MT48LC64M4A2FB_7E
 328        bool
 329        depends on (BFIN533_STAMP)
 330        default y
 331
 332config MEM_MT48LC16M16A2TG_75
 333        bool
 334        depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 335                || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 336                || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 337                || BFIN527_BLUETECHNIX_CM)
 338        default y
 339
 340config MEM_MT48LC32M8A2_75
 341        bool
 342        depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 343        default y
 344
 345config MEM_MT48LC8M32B2B5_7
 346        bool
 347        depends on (BFIN561_BLUETECHNIX_CM)
 348        default y
 349
 350config MEM_MT48LC32M16A2TG_75
 351        bool
 352        depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
 353        default y
 354
 355config MEM_MT48H32M16LFCJ_75
 356        bool
 357        depends on (BFIN526_EZBRD)
 358        default y
 359
 360config MEM_MT47H64M16
 361        bool
 362        depends on (BFIN609_EZKIT)
 363        default y
 364
 365source "arch/blackfin/mach-bf518/Kconfig"
 366source "arch/blackfin/mach-bf527/Kconfig"
 367source "arch/blackfin/mach-bf533/Kconfig"
 368source "arch/blackfin/mach-bf561/Kconfig"
 369source "arch/blackfin/mach-bf537/Kconfig"
 370source "arch/blackfin/mach-bf538/Kconfig"
 371source "arch/blackfin/mach-bf548/Kconfig"
 372source "arch/blackfin/mach-bf609/Kconfig"
 373
 374menu "Board customizations"
 375
 376config CMDLINE_BOOL
 377        bool "Default bootloader kernel arguments"
 378
 379config CMDLINE
 380        string "Initial kernel command string"
 381        depends on CMDLINE_BOOL
 382        default "console=ttyBF0,57600"
 383        help
 384          If you don't have a boot loader capable of passing a command line string
 385          to the kernel, you may specify one here. As a minimum, you should specify
 386          the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 387
 388config BOOT_LOAD
 389        hex "Kernel load address for booting"
 390        default "0x1000"
 391        range 0x1000 0x20000000
 392        help
 393          This option allows you to set the load address of the kernel.
 394          This can be useful if you are on a board which has a small amount
 395          of memory or you wish to reserve some memory at the beginning of
 396          the address space.
 397
 398          Note that you need to keep this value above 4k (0x1000) as this
 399          memory region is used to capture NULL pointer references as well
 400          as some core kernel functions.
 401
 402config PHY_RAM_BASE_ADDRESS
 403        hex "Physical RAM Base"
 404        default 0x0
 405        help
 406          set BF609 FPGA physical SRAM base address
 407
 408config ROM_BASE
 409        hex "Kernel ROM Base"
 410        depends on ROMKERNEL
 411        default "0x20040040"
 412        range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
 413        range 0x20000000 0x30000000 if (BF54x || BF561)
 414        range 0xB0000000 0xC0000000 if (BF60x)
 415        help
 416          Make sure your ROM base does not include any file-header
 417          information that is prepended to the kernel.
 418
 419          For example, the bootable U-Boot format (created with
 420          mkimage) has a 64 byte header (0x40).  So while the image
 421          you write to flash might start at say 0x20080000, you have
 422          to add 0x40 to get the kernel's ROM base as it will come
 423          after the header.
 424
 425comment "Clock/PLL Setup"
 426
 427config CLKIN_HZ
 428        int "Frequency of the crystal on the board in Hz"
 429        default "10000000" if BFIN532_IP0X
 430        default "11059200" if BFIN533_STAMP
 431        default "24576000" if PNAV10
 432        default "25000000" # most people use this
 433        default "27000000" if BFIN533_EZKIT
 434        default "30000000" if BFIN561_EZKIT
 435        default "24000000" if BFIN527_AD7160EVAL
 436        help
 437          The frequency of CLKIN crystal oscillator on the board in Hz.
 438          Warning: This value should match the crystal on the board. Otherwise,
 439          peripherals won't work properly.
 440
 441config BFIN_KERNEL_CLOCK
 442        bool "Re-program Clocks while Kernel boots?"
 443        default n
 444        help
 445          This option decides if kernel clocks are re-programed from the
 446          bootloader settings. If the clocks are not set, the SDRAM settings
 447          are also not changed, and the Bootloader does 100% of the hardware
 448          configuration.
 449
 450config PLL_BYPASS
 451        bool "Bypass PLL"
 452        depends on BFIN_KERNEL_CLOCK && (!BF60x)
 453        default n
 454
 455config CLKIN_HALF
 456        bool "Half Clock In"
 457        depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 458        default n
 459        help
 460          If this is set the clock will be divided by 2, before it goes to the PLL.
 461
 462config VCO_MULT
 463        int "VCO Multiplier"
 464        depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 465        range 1 64
 466        default "22" if BFIN533_EZKIT
 467        default "45" if BFIN533_STAMP
 468        default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 469        default "22" if BFIN533_BLUETECHNIX_CM
 470        default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 471        default "20" if (BFIN561_EZKIT || BF609)
 472        default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 473        default "25" if BFIN527_AD7160EVAL
 474        help
 475          This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 476          PLL Frequency = (Crystal Frequency) * (this setting)
 477
 478choice
 479        prompt "Core Clock Divider"
 480        depends on BFIN_KERNEL_CLOCK
 481        default CCLK_DIV_1
 482        help
 483          This sets the frequency of the core. It can be 1, 2, 4 or 8
 484          Core Frequency = (PLL frequency) / (this setting)
 485
 486config CCLK_DIV_1
 487        bool "1"
 488
 489config CCLK_DIV_2
 490        bool "2"
 491
 492config CCLK_DIV_4
 493        bool "4"
 494
 495config CCLK_DIV_8
 496        bool "8"
 497endchoice
 498
 499config SCLK_DIV
 500        int "System Clock Divider"
 501        depends on BFIN_KERNEL_CLOCK
 502        range 1 15
 503        default 4
 504        help
 505          This sets the frequency of the system clock (including SDRAM or DDR) on
 506          !BF60x else it set the clock for system buses and provides the
 507          source from which SCLK0 and SCLK1 are derived.
 508          This can be between 1 and 15
 509          System Clock = (PLL frequency) / (this setting)
 510
 511config SCLK0_DIV
 512        int "System Clock0 Divider"
 513        depends on BFIN_KERNEL_CLOCK && BF60x
 514        range 1 15
 515        default 1
 516        help
 517          This sets the frequency of the system clock0 for PVP and all other
 518          peripherals not clocked by SCLK1.
 519          This can be between 1 and 15
 520          System Clock0 = (System Clock) / (this setting)
 521
 522config SCLK1_DIV
 523        int "System Clock1 Divider"
 524        depends on BFIN_KERNEL_CLOCK && BF60x
 525        range 1 15
 526        default 1
 527        help
 528          This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
 529          This can be between 1 and 15
 530          System Clock1 = (System Clock) / (this setting)
 531
 532config DCLK_DIV
 533        int "DDR Clock Divider"
 534        depends on BFIN_KERNEL_CLOCK && BF60x
 535        range 1 15
 536        default 2
 537        help
 538          This sets the frequency of the DDR memory.
 539          This can be between 1 and 15
 540          DDR Clock = (PLL frequency) / (this setting)
 541
 542choice
 543        prompt "DDR SDRAM Chip Type"
 544        depends on BFIN_KERNEL_CLOCK
 545        depends on BF54x
 546        default MEM_MT46V32M16_5B
 547
 548config MEM_MT46V32M16_6T
 549        bool "MT46V32M16_6T"
 550
 551config MEM_MT46V32M16_5B
 552        bool "MT46V32M16_5B"
 553endchoice
 554
 555choice
 556        prompt "DDR/SDRAM Timing"
 557        depends on BFIN_KERNEL_CLOCK && !BF60x
 558        default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 559        help
 560          This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 561          The calculated SDRAM timing parameters may not be 100%
 562          accurate - This option is therefore marked experimental.
 563
 564config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 565        bool "Calculate Timings (EXPERIMENTAL)"
 566        depends on EXPERIMENTAL
 567
 568config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 569        bool "Provide accurate Timings based on target SCLK"
 570        help
 571          Please consult the Blackfin Hardware Reference Manuals as well
 572          as the memory device datasheet.
 573          http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 574endchoice
 575
 576menu "Memory Init Control"
 577        depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 578
 579config MEM_DDRCTL0
 580        depends on BF54x
 581        hex "DDRCTL0"
 582        default 0x0
 583
 584config MEM_DDRCTL1
 585        depends on BF54x
 586        hex "DDRCTL1"
 587        default 0x0
 588
 589config MEM_DDRCTL2
 590        depends on BF54x
 591        hex "DDRCTL2"
 592        default 0x0
 593
 594config MEM_EBIU_DDRQUE
 595        depends on BF54x
 596        hex "DDRQUE"
 597        default 0x0
 598
 599config MEM_SDRRC
 600        depends on !BF54x
 601        hex "SDRRC"
 602        default 0x0
 603
 604config MEM_SDGCTL
 605        depends on !BF54x
 606        hex "SDGCTL"
 607        default 0x0
 608endmenu
 609
 610#
 611# Max & Min Speeds for various Chips
 612#
 613config MAX_VCO_HZ
 614        int
 615        default 400000000 if BF512
 616        default 400000000 if BF514
 617        default 400000000 if BF516
 618        default 400000000 if BF518
 619        default 400000000 if BF522
 620        default 600000000 if BF523
 621        default 400000000 if BF524
 622        default 600000000 if BF525
 623        default 400000000 if BF526
 624        default 600000000 if BF527
 625        default 400000000 if BF531
 626        default 400000000 if BF532
 627        default 750000000 if BF533
 628        default 500000000 if BF534
 629        default 400000000 if BF536
 630        default 600000000 if BF537
 631        default 533333333 if BF538
 632        default 533333333 if BF539
 633        default 600000000 if BF542
 634        default 533333333 if BF544
 635        default 600000000 if BF547
 636        default 600000000 if BF548
 637        default 533333333 if BF549
 638        default 600000000 if BF561
 639        default 800000000 if BF609
 640
 641config MIN_VCO_HZ
 642        int
 643        default 50000000
 644
 645config MAX_SCLK_HZ
 646        int
 647        default 200000000 if BF609
 648        default 133333333
 649
 650config MIN_SCLK_HZ
 651        int
 652        default 27000000
 653
 654comment "Kernel Timer/Scheduler"
 655
 656source kernel/Kconfig.hz
 657
 658config SET_GENERIC_CLOCKEVENTS
 659        bool "Generic clock events"
 660        default y
 661        select GENERIC_CLOCKEVENTS
 662
 663menu "Clock event device"
 664        depends on GENERIC_CLOCKEVENTS
 665config TICKSOURCE_GPTMR0
 666        bool "GPTimer0"
 667        depends on !SMP
 668        select BFIN_GPTIMERS
 669
 670config TICKSOURCE_CORETMR
 671        bool "Core timer"
 672        default y
 673endmenu
 674
 675menu "Clock souce"
 676        depends on GENERIC_CLOCKEVENTS
 677config CYCLES_CLOCKSOURCE
 678        bool "CYCLES"
 679        default y
 680        depends on !BFIN_SCRATCH_REG_CYCLES
 681        depends on !SMP
 682        help
 683          If you say Y here, you will enable support for using the 'cycles'
 684          registers as a clock source.  Doing so means you will be unable to
 685          safely write to the 'cycles' register during runtime.  You will
 686          still be able to read it (such as for performance monitoring), but
 687          writing the registers will most likely crash the kernel.
 688
 689config GPTMR0_CLOCKSOURCE
 690        bool "GPTimer0"
 691        select BFIN_GPTIMERS
 692        depends on !TICKSOURCE_GPTMR0
 693endmenu
 694
 695comment "Misc"
 696
 697choice
 698        prompt "Blackfin Exception Scratch Register"
 699        default BFIN_SCRATCH_REG_RETN
 700        help
 701          Select the resource to reserve for the Exception handler:
 702            - RETN: Non-Maskable Interrupt (NMI)
 703            - RETE: Exception Return (JTAG/ICE)
 704            - CYCLES: Performance counter
 705
 706          If you are unsure, please select "RETN".
 707
 708config BFIN_SCRATCH_REG_RETN
 709        bool "RETN"
 710        help
 711          Use the RETN register in the Blackfin exception handler
 712          as a stack scratch register.  This means you cannot
 713          safely use NMI on the Blackfin while running Linux, but
 714          you can debug the system with a JTAG ICE and use the
 715          CYCLES performance registers.
 716
 717          If you are unsure, please select "RETN".
 718
 719config BFIN_SCRATCH_REG_RETE
 720        bool "RETE"
 721        help
 722          Use the RETE register in the Blackfin exception handler
 723          as a stack scratch register.  This means you cannot
 724          safely use a JTAG ICE while debugging a Blackfin board,
 725          but you can safely use the CYCLES performance registers
 726          and the NMI.
 727
 728          If you are unsure, please select "RETN".
 729
 730config BFIN_SCRATCH_REG_CYCLES
 731        bool "CYCLES"
 732        help
 733          Use the CYCLES register in the Blackfin exception handler
 734          as a stack scratch register.  This means you cannot
 735          safely use the CYCLES performance registers on a Blackfin
 736          board at anytime, but you can debug the system with a JTAG
 737          ICE and use the NMI.
 738
 739          If you are unsure, please select "RETN".
 740
 741endchoice
 742
 743endmenu
 744
 745
 746menu "Blackfin Kernel Optimizations"
 747
 748comment "Memory Optimizations"
 749
 750config I_ENTRY_L1
 751        bool "Locate interrupt entry code in L1 Memory"
 752        default y
 753        depends on !SMP
 754        help
 755          If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 756          into L1 instruction memory. (less latency)
 757
 758config EXCPT_IRQ_SYSC_L1
 759        bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 760        default y
 761        depends on !SMP
 762        help
 763          If enabled, the entire ASM lowlevel exception and interrupt entry code
 764          (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 765          (less latency)
 766
 767config DO_IRQ_L1
 768        bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 769        default y
 770        depends on !SMP
 771        help
 772          If enabled, the frequently called do_irq dispatcher function is linked
 773          into L1 instruction memory. (less latency)
 774
 775config CORE_TIMER_IRQ_L1
 776        bool "Locate frequently called timer_interrupt() function in L1 Memory"
 777        default y
 778        depends on !SMP
 779        help
 780          If enabled, the frequently called timer_interrupt() function is linked
 781          into L1 instruction memory. (less latency)
 782
 783config IDLE_L1
 784        bool "Locate frequently idle function in L1 Memory"
 785        default y
 786        depends on !SMP
 787        help
 788          If enabled, the frequently called idle function is linked
 789          into L1 instruction memory. (less latency)
 790
 791config SCHEDULE_L1
 792        bool "Locate kernel schedule function in L1 Memory"
 793        default y
 794        depends on !SMP
 795        help
 796          If enabled, the frequently called kernel schedule is linked
 797          into L1 instruction memory. (less latency)
 798
 799config ARITHMETIC_OPS_L1
 800        bool "Locate kernel owned arithmetic functions in L1 Memory"
 801        default y
 802        depends on !SMP
 803        help
 804          If enabled, arithmetic functions are linked
 805          into L1 instruction memory. (less latency)
 806
 807config ACCESS_OK_L1
 808        bool "Locate access_ok function in L1 Memory"
 809        default y
 810        depends on !SMP
 811        help
 812          If enabled, the access_ok function is linked
 813          into L1 instruction memory. (less latency)
 814
 815config MEMSET_L1
 816        bool "Locate memset function in L1 Memory"
 817        default y
 818        depends on !SMP
 819        help
 820          If enabled, the memset function is linked
 821          into L1 instruction memory. (less latency)
 822
 823config MEMCPY_L1
 824        bool "Locate memcpy function in L1 Memory"
 825        default y
 826        depends on !SMP
 827        help
 828          If enabled, the memcpy function is linked
 829          into L1 instruction memory. (less latency)
 830
 831config STRCMP_L1
 832        bool "locate strcmp function in L1 Memory"
 833        default y
 834        depends on !SMP
 835        help
 836          If enabled, the strcmp function is linked
 837          into L1 instruction memory (less latency).
 838
 839config STRNCMP_L1
 840        bool "locate strncmp function in L1 Memory"
 841        default y
 842        depends on !SMP
 843        help
 844          If enabled, the strncmp function is linked
 845          into L1 instruction memory (less latency).
 846
 847config STRCPY_L1
 848        bool "locate strcpy function in L1 Memory"
 849        default y
 850        depends on !SMP
 851        help
 852          If enabled, the strcpy function is linked
 853          into L1 instruction memory (less latency).
 854
 855config STRNCPY_L1
 856        bool "locate strncpy function in L1 Memory"
 857        default y
 858        depends on !SMP
 859        help
 860          If enabled, the strncpy function is linked
 861          into L1 instruction memory (less latency).
 862
 863config SYS_BFIN_SPINLOCK_L1
 864        bool "Locate sys_bfin_spinlock function in L1 Memory"
 865        default y
 866        depends on !SMP
 867        help
 868          If enabled, sys_bfin_spinlock function is linked
 869          into L1 instruction memory. (less latency)
 870
 871config IP_CHECKSUM_L1
 872        bool "Locate IP Checksum function in L1 Memory"
 873        default n
 874        depends on !SMP
 875        help
 876          If enabled, the IP Checksum function is linked
 877          into L1 instruction memory. (less latency)
 878
 879config CACHELINE_ALIGNED_L1
 880        bool "Locate cacheline_aligned data to L1 Data Memory"
 881        default y if !BF54x
 882        default n if BF54x
 883        depends on !SMP && !BF531 && !CRC32
 884        help
 885          If enabled, cacheline_aligned data is linked
 886          into L1 data memory. (less latency)
 887
 888config SYSCALL_TAB_L1
 889        bool "Locate Syscall Table L1 Data Memory"
 890        default n
 891        depends on !SMP && !BF531
 892        help
 893          If enabled, the Syscall LUT is linked
 894          into L1 data memory. (less latency)
 895
 896config CPLB_SWITCH_TAB_L1
 897        bool "Locate CPLB Switch Tables L1 Data Memory"
 898        default n
 899        depends on !SMP && !BF531
 900        help
 901          If enabled, the CPLB Switch Tables are linked
 902          into L1 data memory. (less latency)
 903
 904config ICACHE_FLUSH_L1
 905        bool "Locate icache flush funcs in L1 Inst Memory"
 906        default y
 907        help
 908          If enabled, the Blackfin icache flushing functions are linked
 909          into L1 instruction memory.
 910
 911          Note that this might be required to address anomalies, but
 912          these functions are pretty small, so it shouldn't be too bad.
 913          If you are using a processor affected by an anomaly, the build
 914          system will double check for you and prevent it.
 915
 916config DCACHE_FLUSH_L1
 917        bool "Locate dcache flush funcs in L1 Inst Memory"
 918        default y
 919        depends on !SMP
 920        help
 921          If enabled, the Blackfin dcache flushing functions are linked
 922          into L1 instruction memory.
 923
 924config APP_STACK_L1
 925        bool "Support locating application stack in L1 Scratch Memory"
 926        default y
 927        depends on !SMP
 928        help
 929          If enabled the application stack can be located in L1
 930          scratch memory (less latency).
 931
 932          Currently only works with FLAT binaries.
 933
 934config EXCEPTION_L1_SCRATCH
 935        bool "Locate exception stack in L1 Scratch Memory"
 936        default n
 937        depends on !SMP && !APP_STACK_L1
 938        help
 939          Whenever an exception occurs, use the L1 Scratch memory for
 940          stack storage.  You cannot place the stacks of FLAT binaries
 941          in L1 when using this option.
 942
 943          If you don't use L1 Scratch, then you should say Y here.
 944
 945comment "Speed Optimizations"
 946config BFIN_INS_LOWOVERHEAD
 947        bool "ins[bwl] low overhead, higher interrupt latency"
 948        default y
 949        depends on !SMP
 950        help
 951          Reads on the Blackfin are speculative. In Blackfin terms, this means
 952          they can be interrupted at any time (even after they have been issued
 953          on to the external bus), and re-issued after the interrupt occurs.
 954          For memory - this is not a big deal, since memory does not change if
 955          it sees a read.
 956
 957          If a FIFO is sitting on the end of the read, it will see two reads,
 958          when the core only sees one since the FIFO receives both the read
 959          which is cancelled (and not delivered to the core) and the one which
 960          is re-issued (which is delivered to the core).
 961
 962          To solve this, interrupts are turned off before reads occur to
 963          I/O space. This option controls which the overhead/latency of
 964          controlling interrupts during this time
 965           "n" turns interrupts off every read
 966                (higher overhead, but lower interrupt latency)
 967           "y" turns interrupts off every loop
 968                (low overhead, but longer interrupt latency)
 969
 970          default behavior is to leave this set to on (type "Y"). If you are experiencing
 971          interrupt latency issues, it is safe and OK to turn this off.
 972
 973endmenu
 974
 975choice
 976        prompt "Kernel executes from"
 977        help
 978          Choose the memory type that the kernel will be running in.
 979
 980config RAMKERNEL
 981        bool "RAM"
 982        help
 983          The kernel will be resident in RAM when running.
 984
 985config ROMKERNEL
 986        bool "ROM"
 987        help
 988          The kernel will be resident in FLASH/ROM when running.
 989
 990endchoice
 991
 992# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
 993config XIP_KERNEL
 994        bool
 995        default y
 996        depends on ROMKERNEL
 997
 998source "mm/Kconfig"
 999
1000config BFIN_GPTIMERS
1001        tristate "Enable Blackfin General Purpose Timers API"
1002        default n
1003        help
1004          Enable support for the General Purpose Timers API.  If you
1005          are unsure, say N.
1006
1007          To compile this driver as a module, choose M here: the module
1008          will be called gptimers.
1009
1010choice
1011        prompt "Uncached DMA region"
1012        default DMA_UNCACHED_1M
1013config DMA_UNCACHED_32M
1014        bool "Enable 32M DMA region"
1015config DMA_UNCACHED_16M
1016        bool "Enable 16M DMA region"
1017config DMA_UNCACHED_8M
1018        bool "Enable 8M DMA region"
1019config DMA_UNCACHED_4M
1020        bool "Enable 4M DMA region"
1021config DMA_UNCACHED_2M
1022        bool "Enable 2M DMA region"
1023config DMA_UNCACHED_1M
1024        bool "Enable 1M DMA region"
1025config DMA_UNCACHED_512K
1026        bool "Enable 512K DMA region"
1027config DMA_UNCACHED_256K
1028        bool "Enable 256K DMA region"
1029config DMA_UNCACHED_128K
1030        bool "Enable 128K DMA region"
1031config DMA_UNCACHED_NONE
1032        bool "Disable DMA region"
1033endchoice
1034
1035
1036comment "Cache Support"
1037
1038config BFIN_ICACHE
1039        bool "Enable ICACHE"
1040        default y
1041config BFIN_EXTMEM_ICACHEABLE
1042        bool "Enable ICACHE for external memory"
1043        depends on BFIN_ICACHE
1044        default y
1045config BFIN_L2_ICACHEABLE
1046        bool "Enable ICACHE for L2 SRAM"
1047        depends on BFIN_ICACHE
1048        depends on (BF54x || BF561 || BF60x) && !SMP
1049        default n
1050
1051config BFIN_DCACHE
1052        bool "Enable DCACHE"
1053        default y
1054config BFIN_DCACHE_BANKA
1055        bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1056        depends on BFIN_DCACHE && !BF531
1057        default n
1058config BFIN_EXTMEM_DCACHEABLE
1059        bool "Enable DCACHE for external memory"
1060        depends on BFIN_DCACHE
1061        default y
1062choice
1063        prompt "External memory DCACHE policy"
1064        depends on BFIN_EXTMEM_DCACHEABLE
1065        default BFIN_EXTMEM_WRITEBACK if !SMP
1066        default BFIN_EXTMEM_WRITETHROUGH if SMP
1067config BFIN_EXTMEM_WRITEBACK
1068        bool "Write back"
1069        depends on !SMP
1070        help
1071          Write Back Policy:
1072            Cached data will be written back to SDRAM only when needed.
1073            This can give a nice increase in performance, but beware of
1074            broken drivers that do not properly invalidate/flush their
1075            cache.
1076
1077          Write Through Policy:
1078            Cached data will always be written back to SDRAM when the
1079            cache is updated.  This is a completely safe setting, but
1080            performance is worse than Write Back.
1081
1082          If you are unsure of the options and you want to be safe,
1083          then go with Write Through.
1084
1085config BFIN_EXTMEM_WRITETHROUGH
1086        bool "Write through"
1087        help
1088          Write Back Policy:
1089            Cached data will be written back to SDRAM only when needed.
1090            This can give a nice increase in performance, but beware of
1091            broken drivers that do not properly invalidate/flush their
1092            cache.
1093
1094          Write Through Policy:
1095            Cached data will always be written back to SDRAM when the
1096            cache is updated.  This is a completely safe setting, but
1097            performance is worse than Write Back.
1098
1099          If you are unsure of the options and you want to be safe,
1100          then go with Write Through.
1101
1102endchoice
1103
1104config BFIN_L2_DCACHEABLE
1105        bool "Enable DCACHE for L2 SRAM"
1106        depends on BFIN_DCACHE
1107        depends on (BF54x || BF561 || BF60x) && !SMP
1108        default n
1109choice
1110        prompt "L2 SRAM DCACHE policy"
1111        depends on BFIN_L2_DCACHEABLE
1112        default BFIN_L2_WRITEBACK
1113config BFIN_L2_WRITEBACK
1114        bool "Write back"
1115
1116config BFIN_L2_WRITETHROUGH
1117        bool "Write through"
1118endchoice
1119
1120
1121comment "Memory Protection Unit"
1122config MPU
1123        bool "Enable the memory protection unit (EXPERIMENTAL)"
1124        default n
1125        help
1126          Use the processor's MPU to protect applications from accessing
1127          memory they do not own.  This comes at a performance penalty
1128          and is recommended only for debugging.
1129
1130comment "Asynchronous Memory Configuration"
1131
1132menu "EBIU_AMGCTL Global Control"
1133        depends on !BF60x
1134config C_AMCKEN
1135        bool "Enable CLKOUT"
1136        default y
1137
1138config C_CDPRIO
1139        bool "DMA has priority over core for ext. accesses"
1140        default n
1141
1142config C_B0PEN
1143        depends on BF561
1144        bool "Bank 0 16 bit packing enable"
1145        default y
1146
1147config C_B1PEN
1148        depends on BF561
1149        bool "Bank 1 16 bit packing enable"
1150        default y
1151
1152config C_B2PEN
1153        depends on BF561
1154        bool "Bank 2 16 bit packing enable"
1155        default y
1156
1157config C_B3PEN
1158        depends on BF561
1159        bool "Bank 3 16 bit packing enable"
1160        default n
1161
1162choice
1163        prompt "Enable Asynchronous Memory Banks"
1164        default C_AMBEN_ALL
1165
1166config C_AMBEN
1167        bool "Disable All Banks"
1168
1169config C_AMBEN_B0
1170        bool "Enable Bank 0"
1171
1172config C_AMBEN_B0_B1
1173        bool "Enable Bank 0 & 1"
1174
1175config C_AMBEN_B0_B1_B2
1176        bool "Enable Bank 0 & 1 & 2"
1177
1178config C_AMBEN_ALL
1179        bool "Enable All Banks"
1180endchoice
1181endmenu
1182
1183menu "EBIU_AMBCTL Control"
1184        depends on !BF60x
1185config BANK_0
1186        hex "Bank 0 (AMBCTL0.L)"
1187        default 0x7BB0
1188        help
1189          These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1190          used to control the Asynchronous Memory Bank 0 settings.
1191
1192config BANK_1
1193        hex "Bank 1 (AMBCTL0.H)"
1194        default 0x7BB0
1195        default 0x5558 if BF54x
1196        help
1197          These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1198          used to control the Asynchronous Memory Bank 1 settings.
1199
1200config BANK_2
1201        hex "Bank 2 (AMBCTL1.L)"
1202        default 0x7BB0
1203        help
1204          These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1205          used to control the Asynchronous Memory Bank 2 settings.
1206
1207config BANK_3
1208        hex "Bank 3 (AMBCTL1.H)"
1209        default 0x99B3
1210        help
1211          These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1212          used to control the Asynchronous Memory Bank 3 settings.
1213
1214endmenu
1215
1216config EBIU_MBSCTLVAL
1217        hex "EBIU Bank Select Control Register"
1218        depends on BF54x
1219        default 0
1220
1221config EBIU_MODEVAL
1222        hex "Flash Memory Mode Control Register"
1223        depends on BF54x
1224        default 1
1225
1226config EBIU_FCTLVAL
1227        hex "Flash Memory Bank Control Register"
1228        depends on BF54x
1229        default 6
1230endmenu
1231
1232#############################################################################
1233menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1234
1235config PCI
1236        bool "PCI support"
1237        depends on BROKEN
1238        help
1239          Support for PCI bus.
1240
1241source "drivers/pci/Kconfig"
1242
1243source "drivers/pcmcia/Kconfig"
1244
1245source "drivers/pci/hotplug/Kconfig"
1246
1247endmenu
1248
1249menu "Executable file formats"
1250
1251source "fs/Kconfig.binfmt"
1252
1253endmenu
1254
1255menu "Power management options"
1256
1257source "kernel/power/Kconfig"
1258
1259config ARCH_SUSPEND_POSSIBLE
1260        def_bool y
1261
1262choice
1263        prompt "Standby Power Saving Mode"
1264        depends on PM && !BF60x
1265        default PM_BFIN_SLEEP_DEEPER
1266config  PM_BFIN_SLEEP_DEEPER
1267        bool "Sleep Deeper"
1268        help
1269          Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1270          power dissipation by disabling the clock to the processor core (CCLK).
1271          Furthermore, Standby sets the internal power supply voltage (VDDINT)
1272          to 0.85 V to provide the greatest power savings, while preserving the
1273          processor state.
1274          The PLL and system clock (SCLK) continue to operate at a very low
1275          frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1276          the SDRAM is put into Self Refresh Mode. Typically an external event
1277          such as GPIO interrupt or RTC activity wakes up the processor.
1278          Various Peripherals such as UART, SPORT, PPI may not function as
1279          normal during Sleep Deeper, due to the reduced SCLK frequency.
1280          When in the sleep mode, system DMA access to L1 memory is not supported.
1281
1282          If unsure, select "Sleep Deeper".
1283
1284config  PM_BFIN_SLEEP
1285        bool "Sleep"
1286        help
1287          Sleep Mode (High Power Savings) - The sleep mode reduces power
1288          dissipation by disabling the clock to the processor core (CCLK).
1289          The PLL and system clock (SCLK), however, continue to operate in
1290          this mode. Typically an external event or RTC activity will wake
1291          up the processor. When in the sleep mode, system DMA access to L1
1292          memory is not supported.
1293
1294          If unsure, select "Sleep Deeper".
1295endchoice
1296
1297comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1298        depends on PM
1299
1300config PM_BFIN_WAKE_PH6
1301        bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1302        depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1303        default n
1304        help
1305          Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1306
1307config PM_BFIN_WAKE_GP
1308        bool "Allow Wake-Up from GPIOs"
1309        depends on PM && BF54x
1310        default n
1311        help
1312          Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1313          (all processors, except ADSP-BF549). This option sets
1314          the general-purpose wake-up enable (GPWE) control bit to enable
1315          wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1316          On ADSP-BF549 this option enables the same functionality on the
1317          /MRXON pin also PH7.
1318
1319config PM_BFIN_WAKE_PA15
1320        bool "Allow Wake-Up from PA15"
1321        depends on PM && BF60x
1322        default n
1323        help
1324          Enable PA15 Wake-Up
1325
1326config PM_BFIN_WAKE_PA15_POL
1327        int "Wake-up priority"
1328        depends on PM_BFIN_WAKE_PA15
1329        default 0
1330        help
1331          Wake-Up priority 0(low) 1(high)
1332
1333config PM_BFIN_WAKE_PB15
1334        bool "Allow Wake-Up from PB15"
1335        depends on PM && BF60x
1336        default n
1337        help
1338          Enable PB15 Wake-Up
1339
1340config PM_BFIN_WAKE_PB15_POL
1341        int "Wake-up priority"
1342        depends on PM_BFIN_WAKE_PB15
1343        default 0
1344        help
1345          Wake-Up priority 0(low) 1(high)
1346
1347config PM_BFIN_WAKE_PC15
1348        bool "Allow Wake-Up from PC15"
1349        depends on PM && BF60x
1350        default n
1351        help
1352          Enable PC15 Wake-Up
1353
1354config PM_BFIN_WAKE_PC15_POL
1355        int "Wake-up priority"
1356        depends on PM_BFIN_WAKE_PC15
1357        default 0
1358        help
1359          Wake-Up priority 0(low) 1(high)
1360
1361config PM_BFIN_WAKE_PD06
1362        bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1363        depends on PM && BF60x
1364        default n
1365        help
1366          Enable PD06(ETH0_PHYINT) Wake-up
1367
1368config PM_BFIN_WAKE_PD06_POL
1369        int "Wake-up priority"
1370        depends on PM_BFIN_WAKE_PD06
1371        default 0
1372        help
1373          Wake-Up priority 0(low) 1(high)
1374
1375config PM_BFIN_WAKE_PE12
1376        bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1377        depends on PM && BF60x
1378        default n
1379        help
1380          Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1381
1382config PM_BFIN_WAKE_PE12_POL
1383        int "Wake-up priority"
1384        depends on PM_BFIN_WAKE_PE12
1385        default 0
1386        help
1387          Wake-Up priority 0(low) 1(high)
1388
1389config PM_BFIN_WAKE_PG04
1390        bool "Allow Wake-Up from PG04(CAN0_RX)"
1391        depends on PM && BF60x
1392        default n
1393        help
1394          Enable PG04(CAN0_RX) Wake-up
1395
1396config PM_BFIN_WAKE_PG04_POL
1397        int "Wake-up priority"
1398        depends on PM_BFIN_WAKE_PG04
1399        default 0
1400        help
1401          Wake-Up priority 0(low) 1(high)
1402
1403config PM_BFIN_WAKE_PG13
1404        bool "Allow Wake-Up from PG13"
1405        depends on PM && BF60x
1406        default n
1407        help
1408          Enable PG13 Wake-Up
1409
1410config PM_BFIN_WAKE_PG13_POL
1411        int "Wake-up priority"
1412        depends on PM_BFIN_WAKE_PG13
1413        default 0
1414        help
1415          Wake-Up priority 0(low) 1(high)
1416
1417config PM_BFIN_WAKE_USB
1418        bool "Allow Wake-Up from (USB)"
1419        depends on PM && BF60x
1420        default n
1421        help
1422          Enable (USB) Wake-up
1423
1424config PM_BFIN_WAKE_USB_POL
1425        int "Wake-up priority"
1426        depends on PM_BFIN_WAKE_USB
1427        default 0
1428        help
1429          Wake-Up priority 0(low) 1(high)
1430
1431endmenu
1432
1433menu "CPU Frequency scaling"
1434
1435source "drivers/cpufreq/Kconfig"
1436
1437config BFIN_CPU_FREQ
1438        bool
1439        depends on CPU_FREQ
1440        select CPU_FREQ_TABLE
1441        default y
1442
1443config CPU_VOLTAGE
1444        bool "CPU Voltage scaling"
1445        depends on EXPERIMENTAL
1446        depends on CPU_FREQ
1447        default n
1448        help
1449          Say Y here if you want CPU voltage scaling according to the CPU frequency.
1450          This option violates the PLL BYPASS recommendation in the Blackfin Processor
1451          manuals. There is a theoretical risk that during VDDINT transitions
1452          the PLL may unlock.
1453
1454endmenu
1455
1456source "net/Kconfig"
1457
1458source "drivers/Kconfig"
1459
1460source "drivers/firmware/Kconfig"
1461
1462source "fs/Kconfig"
1463
1464source "arch/blackfin/Kconfig.debug"
1465
1466source "security/Kconfig"
1467
1468source "crypto/Kconfig"
1469
1470source "lib/Kconfig"
1471
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