linux/include/linux/pci.h
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   1/*
   2 *      pci.h
   3 *
   4 *      PCI defines and function prototypes
   5 *      Copyright 1994, Drew Eckhardt
   6 *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
   7 *
   8 *      For more information, please consult the following manuals (look at
   9 *      http://www.pcisig.com/ for how to get them):
  10 *
  11 *      PCI BIOS Specification
  12 *      PCI Local Bus Specification
  13 *      PCI to PCI Bridge Specification
  14 *      PCI System Design Guide
  15 */
  16#ifndef LINUX_PCI_H
  17#define LINUX_PCI_H
  18
  19
  20#include <linux/mod_devicetable.h>
  21
  22#include <linux/types.h>
  23#include <linux/init.h>
  24#include <linux/ioport.h>
  25#include <linux/list.h>
  26#include <linux/compiler.h>
  27#include <linux/errno.h>
  28#include <linux/kobject.h>
  29#include <linux/atomic.h>
  30#include <linux/device.h>
  31#include <linux/io.h>
  32#include <linux/irqreturn.h>
  33#include <uapi/linux/pci.h>
  34
  35/* Include the ID list */
  36#include <linux/pci_ids.h>
  37
  38/* pci_slot represents a physical slot */
  39struct pci_slot {
  40        struct pci_bus *bus;            /* The bus this slot is on */
  41        struct list_head list;          /* node in list of slots on this bus */
  42        struct hotplug_slot *hotplug;   /* Hotplug info (migrate over time) */
  43        unsigned char number;           /* PCI_SLOT(pci_dev->devfn) */
  44        struct kobject kobj;
  45};
  46
  47static inline const char *pci_slot_name(const struct pci_slot *slot)
  48{
  49        return kobject_name(&slot->kobj);
  50}
  51
  52/* File state for mmap()s on /proc/bus/pci/X/Y */
  53enum pci_mmap_state {
  54        pci_mmap_io,
  55        pci_mmap_mem
  56};
  57
  58/* This defines the direction arg to the DMA mapping routines. */
  59#define PCI_DMA_BIDIRECTIONAL   0
  60#define PCI_DMA_TODEVICE        1
  61#define PCI_DMA_FROMDEVICE      2
  62#define PCI_DMA_NONE            3
  63
  64/*
  65 *  For PCI devices, the region numbers are assigned this way:
  66 */
  67enum {
  68        /* #0-5: standard PCI resources */
  69        PCI_STD_RESOURCES,
  70        PCI_STD_RESOURCE_END = 5,
  71
  72        /* #6: expansion ROM resource */
  73        PCI_ROM_RESOURCE,
  74
  75        /* device specific resources */
  76#ifdef CONFIG_PCI_IOV
  77        PCI_IOV_RESOURCES,
  78        PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
  79#endif
  80
  81        /* resources assigned to buses behind the bridge */
  82#define PCI_BRIDGE_RESOURCE_NUM 4
  83
  84        PCI_BRIDGE_RESOURCES,
  85        PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
  86                                  PCI_BRIDGE_RESOURCE_NUM - 1,
  87
  88        /* total resources associated with a PCI device */
  89        PCI_NUM_RESOURCES,
  90
  91        /* preserve this for compatibility */
  92        DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
  93};
  94
  95typedef int __bitwise pci_power_t;
  96
  97#define PCI_D0          ((pci_power_t __force) 0)
  98#define PCI_D1          ((pci_power_t __force) 1)
  99#define PCI_D2          ((pci_power_t __force) 2)
 100#define PCI_D3hot       ((pci_power_t __force) 3)
 101#define PCI_D3cold      ((pci_power_t __force) 4)
 102#define PCI_UNKNOWN     ((pci_power_t __force) 5)
 103#define PCI_POWER_ERROR ((pci_power_t __force) -1)
 104
 105/* Remember to update this when the list above changes! */
 106extern const char *pci_power_names[];
 107
 108static inline const char *pci_power_name(pci_power_t state)
 109{
 110        return pci_power_names[1 + (int) state];
 111}
 112
 113#define PCI_PM_D2_DELAY         200
 114#define PCI_PM_D3_WAIT          10
 115#define PCI_PM_D3COLD_WAIT      100
 116#define PCI_PM_BUS_WAIT         50
 117
 118/** The pci_channel state describes connectivity between the CPU and
 119 *  the pci device.  If some PCI bus between here and the pci device
 120 *  has crashed or locked up, this info is reflected here.
 121 */
 122typedef unsigned int __bitwise pci_channel_state_t;
 123
 124enum pci_channel_state {
 125        /* I/O channel is in normal state */
 126        pci_channel_io_normal = (__force pci_channel_state_t) 1,
 127
 128        /* I/O to channel is blocked */
 129        pci_channel_io_frozen = (__force pci_channel_state_t) 2,
 130
 131        /* PCI card is dead */
 132        pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
 133};
 134
 135typedef unsigned int __bitwise pcie_reset_state_t;
 136
 137enum pcie_reset_state {
 138        /* Reset is NOT asserted (Use to deassert reset) */
 139        pcie_deassert_reset = (__force pcie_reset_state_t) 1,
 140
 141        /* Use #PERST to reset PCI-E device */
 142        pcie_warm_reset = (__force pcie_reset_state_t) 2,
 143
 144        /* Use PCI-E Hot Reset to reset device */
 145        pcie_hot_reset = (__force pcie_reset_state_t) 3
 146};
 147
 148typedef unsigned short __bitwise pci_dev_flags_t;
 149enum pci_dev_flags {
 150        /* INTX_DISABLE in PCI_COMMAND register disables MSI
 151         * generation too.
 152         */
 153        PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
 154        /* Device configuration is irrevocably lost if disabled into D3 */
 155        PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
 156        /* Provide indication device is assigned by a Virtual Machine Manager */
 157        PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
 158};
 159
 160enum pci_irq_reroute_variant {
 161        INTEL_IRQ_REROUTE_VARIANT = 1,
 162        MAX_IRQ_REROUTE_VARIANTS = 3
 163};
 164
 165typedef unsigned short __bitwise pci_bus_flags_t;
 166enum pci_bus_flags {
 167        PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
 168        PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
 169};
 170
 171/* Based on the PCI Hotplug Spec, but some values are made up by us */
 172enum pci_bus_speed {
 173        PCI_SPEED_33MHz                 = 0x00,
 174        PCI_SPEED_66MHz                 = 0x01,
 175        PCI_SPEED_66MHz_PCIX            = 0x02,
 176        PCI_SPEED_100MHz_PCIX           = 0x03,
 177        PCI_SPEED_133MHz_PCIX           = 0x04,
 178        PCI_SPEED_66MHz_PCIX_ECC        = 0x05,
 179        PCI_SPEED_100MHz_PCIX_ECC       = 0x06,
 180        PCI_SPEED_133MHz_PCIX_ECC       = 0x07,
 181        PCI_SPEED_66MHz_PCIX_266        = 0x09,
 182        PCI_SPEED_100MHz_PCIX_266       = 0x0a,
 183        PCI_SPEED_133MHz_PCIX_266       = 0x0b,
 184        AGP_UNKNOWN                     = 0x0c,
 185        AGP_1X                          = 0x0d,
 186        AGP_2X                          = 0x0e,
 187        AGP_4X                          = 0x0f,
 188        AGP_8X                          = 0x10,
 189        PCI_SPEED_66MHz_PCIX_533        = 0x11,
 190        PCI_SPEED_100MHz_PCIX_533       = 0x12,
 191        PCI_SPEED_133MHz_PCIX_533       = 0x13,
 192        PCIE_SPEED_2_5GT                = 0x14,
 193        PCIE_SPEED_5_0GT                = 0x15,
 194        PCIE_SPEED_8_0GT                = 0x16,
 195        PCI_SPEED_UNKNOWN               = 0xff,
 196};
 197
 198struct pci_cap_saved_data {
 199        char cap_nr;
 200        unsigned int size;
 201        u32 data[0];
 202};
 203
 204struct pci_cap_saved_state {
 205        struct hlist_node next;
 206        struct pci_cap_saved_data cap;
 207};
 208
 209struct pcie_link_state;
 210struct pci_vpd;
 211struct pci_sriov;
 212struct pci_ats;
 213
 214/*
 215 * The pci_dev structure is used to describe PCI devices.
 216 */
 217struct pci_dev {
 218        struct list_head bus_list;      /* node in per-bus list */
 219        struct pci_bus  *bus;           /* bus this device is on */
 220        struct pci_bus  *subordinate;   /* bus this device bridges to */
 221
 222        void            *sysdata;       /* hook for sys-specific extension */
 223        struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
 224        struct pci_slot *slot;          /* Physical slot this device is in */
 225
 226        unsigned int    devfn;          /* encoded device & function index */
 227        unsigned short  vendor;
 228        unsigned short  device;
 229        unsigned short  subsystem_vendor;
 230        unsigned short  subsystem_device;
 231        unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
 232        u8              revision;       /* PCI revision, low byte of class word */
 233        u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
 234        u8              pcie_cap;       /* PCI-E capability offset */
 235        u8              pcie_mpss:3;    /* PCI-E Max Payload Size Supported */
 236        u8              rom_base_reg;   /* which config register controls the ROM */
 237        u8              pin;            /* which interrupt pin this device uses */
 238        u16             pcie_flags_reg; /* cached PCI-E Capabilities Register */
 239
 240        struct pci_driver *driver;      /* which driver has allocated this device */
 241        u64             dma_mask;       /* Mask of the bits of bus address this
 242                                           device implements.  Normally this is
 243                                           0xffffffff.  You only need to change
 244                                           this if your device has broken DMA
 245                                           or supports 64-bit transfers.  */
 246
 247        struct device_dma_parameters dma_parms;
 248
 249        pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
 250                                           this is D0-D3, D0 being fully functional,
 251                                           and D3 being off. */
 252        int             pm_cap;         /* PM capability offset in the
 253                                           configuration space */
 254        unsigned int    pme_support:5;  /* Bitmask of states from which PME#
 255                                           can be generated */
 256        unsigned int    pme_interrupt:1;
 257        unsigned int    pme_poll:1;     /* Poll device's PME status bit */
 258        unsigned int    d1_support:1;   /* Low power state D1 is supported */
 259        unsigned int    d2_support:1;   /* Low power state D2 is supported */
 260        unsigned int    no_d1d2:1;      /* D1 and D2 are forbidden */
 261        unsigned int    no_d3cold:1;    /* D3cold is forbidden */
 262        unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
 263        unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
 264                                                   decoding during bar sizing */
 265        unsigned int    wakeup_prepared:1;
 266        unsigned int    runtime_d3cold:1;       /* whether go through runtime
 267                                                   D3cold, not set for devices
 268                                                   powered on/off by the
 269                                                   corresponding bridge */
 270        unsigned int    d3_delay;       /* D3->D0 transition time in ms */
 271        unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
 272
 273#ifdef CONFIG_PCIEASPM
 274        struct pcie_link_state  *link_state;    /* ASPM link state. */
 275#endif
 276
 277        pci_channel_state_t error_state;        /* current connectivity state */
 278        struct  device  dev;            /* Generic device interface */
 279
 280        int             cfg_size;       /* Size of configuration space */
 281
 282        /*
 283         * Instead of touching interrupt line and base address registers
 284         * directly, use the values stored here. They might be different!
 285         */
 286        unsigned int    irq;
 287        struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
 288
 289        /* These fields are used by common fixups */
 290        unsigned int    transparent:1;  /* Transparent PCI bridge */
 291        unsigned int    multifunction:1;/* Part of multi-function device */
 292        /* keep track of device state */
 293        unsigned int    is_added:1;
 294        unsigned int    is_busmaster:1; /* device is busmaster */
 295        unsigned int    no_msi:1;       /* device may not use msi */
 296        unsigned int    block_cfg_access:1;     /* config space access is blocked */
 297        unsigned int    broken_parity_status:1; /* Device generates false positive parity */
 298        unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
 299        unsigned int    msi_enabled:1;
 300        unsigned int    msix_enabled:1;
 301        unsigned int    ari_enabled:1;  /* ARI forwarding */
 302        unsigned int    is_managed:1;
 303        unsigned int    is_pcie:1;      /* Obsolete. Will be removed.
 304                                           Use pci_is_pcie() instead */
 305        unsigned int    needs_freset:1; /* Dev requires fundamental reset */
 306        unsigned int    state_saved:1;
 307        unsigned int    is_physfn:1;
 308        unsigned int    is_virtfn:1;
 309        unsigned int    reset_fn:1;
 310        unsigned int    is_hotplug_bridge:1;
 311        unsigned int    __aer_firmware_first_valid:1;
 312        unsigned int    __aer_firmware_first:1;
 313        unsigned int    broken_intx_masking:1;
 314        unsigned int    io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
 315        pci_dev_flags_t dev_flags;
 316        atomic_t        enable_cnt;     /* pci_enable_device has been called */
 317
 318        u32             saved_config_space[16]; /* config space saved at suspend time */
 319        struct hlist_head saved_cap_space;
 320        struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
 321        int rom_attr_enabled;           /* has display of the rom attribute been enabled? */
 322        struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
 323        struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
 324#ifdef CONFIG_PCI_MSI
 325        struct list_head msi_list;
 326        struct kset *msi_kset;
 327#endif
 328        struct pci_vpd *vpd;
 329#ifdef CONFIG_PCI_ATS
 330        union {
 331                struct pci_sriov *sriov;        /* SR-IOV capability related */
 332                struct pci_dev *physfn; /* the PF this VF is associated with */
 333        };
 334        struct pci_ats  *ats;   /* Address Translation Service */
 335#endif
 336};
 337
 338static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
 339{
 340#ifdef CONFIG_PCI_IOV
 341        if (dev->is_virtfn)
 342                dev = dev->physfn;
 343#endif
 344
 345        return dev;
 346}
 347
 348extern struct pci_dev *alloc_pci_dev(void);
 349
 350#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
 351#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
 352
 353static inline int pci_channel_offline(struct pci_dev *pdev)
 354{
 355        return (pdev->error_state != pci_channel_io_normal);
 356}
 357
 358extern struct resource busn_resource;
 359
 360struct pci_host_bridge_window {
 361        struct list_head list;
 362        struct resource *res;           /* host bridge aperture (CPU address) */
 363        resource_size_t offset;         /* bus address + offset = CPU address */
 364};
 365
 366struct pci_host_bridge {
 367        struct device dev;
 368        struct pci_bus *bus;            /* root bus */
 369        struct list_head windows;       /* pci_host_bridge_windows */
 370        void (*release_fn)(struct pci_host_bridge *);
 371        void *release_data;
 372};
 373
 374#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
 375void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
 376                     void (*release_fn)(struct pci_host_bridge *),
 377                     void *release_data);
 378
 379/*
 380 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
 381 * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
 382 * buses below host bridges or subtractive decode bridges) go in the list.
 383 * Use pci_bus_for_each_resource() to iterate through all the resources.
 384 */
 385
 386/*
 387 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
 388 * and there's no way to program the bridge with the details of the window.
 389 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
 390 * decode bit set, because they are explicit and can be programmed with _SRS.
 391 */
 392#define PCI_SUBTRACTIVE_DECODE  0x1
 393
 394struct pci_bus_resource {
 395        struct list_head list;
 396        struct resource *res;
 397        unsigned int flags;
 398};
 399
 400#define PCI_REGION_FLAG_MASK    0x0fU   /* These bits of resource flags tell us the PCI region flags */
 401
 402struct pci_bus {
 403        struct list_head node;          /* node in list of buses */
 404        struct pci_bus  *parent;        /* parent bus this bridge is on */
 405        struct list_head children;      /* list of child buses */
 406        struct list_head devices;       /* list of devices on this bus */
 407        struct pci_dev  *self;          /* bridge device as seen by parent */
 408        struct list_head slots;         /* list of slots on this bus */
 409        struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
 410        struct list_head resources;     /* address space routed to this bus */
 411        struct resource busn_res;       /* bus numbers routed to this bus */
 412
 413        struct pci_ops  *ops;           /* configuration access functions */
 414        void            *sysdata;       /* hook for sys-specific extension */
 415        struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
 416
 417        unsigned char   number;         /* bus number */
 418        unsigned char   primary;        /* number of primary bridge */
 419        unsigned char   max_bus_speed;  /* enum pci_bus_speed */
 420        unsigned char   cur_bus_speed;  /* enum pci_bus_speed */
 421
 422        char            name[48];
 423
 424        unsigned short  bridge_ctl;     /* manage NO_ISA/FBB/et al behaviors */
 425        pci_bus_flags_t bus_flags;      /* Inherited by child busses */
 426        struct device           *bridge;
 427        struct device           dev;
 428        struct bin_attribute    *legacy_io; /* legacy I/O for this bus */
 429        struct bin_attribute    *legacy_mem; /* legacy mem */
 430        unsigned int            is_added:1;
 431};
 432
 433#define pci_bus_b(n)    list_entry(n, struct pci_bus, node)
 434#define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
 435
 436/*
 437 * Returns true if the pci bus is root (behind host-pci bridge),
 438 * false otherwise
 439 */
 440static inline bool pci_is_root_bus(struct pci_bus *pbus)
 441{
 442        return !(pbus->parent);
 443}
 444
 445#ifdef CONFIG_PCI_MSI
 446static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
 447{
 448        return pci_dev->msi_enabled || pci_dev->msix_enabled;
 449}
 450#else
 451static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
 452#endif
 453
 454/*
 455 * Error values that may be returned by PCI functions.
 456 */
 457#define PCIBIOS_SUCCESSFUL              0x00
 458#define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
 459#define PCIBIOS_BAD_VENDOR_ID           0x83
 460#define PCIBIOS_DEVICE_NOT_FOUND        0x86
 461#define PCIBIOS_BAD_REGISTER_NUMBER     0x87
 462#define PCIBIOS_SET_FAILED              0x88
 463#define PCIBIOS_BUFFER_TOO_SMALL        0x89
 464
 465/*
 466 * Translate above to generic errno for passing back through non-pci.
 467 */
 468static inline int pcibios_err_to_errno(int err)
 469{
 470        if (err <= PCIBIOS_SUCCESSFUL)
 471                return err; /* Assume already errno */
 472
 473        switch (err) {
 474        case PCIBIOS_FUNC_NOT_SUPPORTED:
 475                return -ENOENT;
 476        case PCIBIOS_BAD_VENDOR_ID:
 477                return -EINVAL;
 478        case PCIBIOS_DEVICE_NOT_FOUND:
 479                return -ENODEV;
 480        case PCIBIOS_BAD_REGISTER_NUMBER:
 481                return -EFAULT;
 482        case PCIBIOS_SET_FAILED:
 483                return -EIO;
 484        case PCIBIOS_BUFFER_TOO_SMALL:
 485                return -ENOSPC;
 486        }
 487
 488        return -ENOTTY;
 489}
 490
 491/* Low-level architecture-dependent routines */
 492
 493struct pci_ops {
 494        int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
 495        int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
 496};
 497
 498/*
 499 * ACPI needs to be able to access PCI config space before we've done a
 500 * PCI bus scan and created pci_bus structures.
 501 */
 502extern int raw_pci_read(unsigned int domain, unsigned int bus,
 503                        unsigned int devfn, int reg, int len, u32 *val);
 504extern int raw_pci_write(unsigned int domain, unsigned int bus,
 505                        unsigned int devfn, int reg, int len, u32 val);
 506
 507struct pci_bus_region {
 508        resource_size_t start;
 509        resource_size_t end;
 510};
 511
 512struct pci_dynids {
 513        spinlock_t lock;            /* protects list, index */
 514        struct list_head list;      /* for IDs added at runtime */
 515};
 516
 517/* ---------------------------------------------------------------- */
 518/** PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
 519 *  a set of callbacks in struct pci_error_handlers, then that device driver
 520 *  will be notified of PCI bus errors, and will be driven to recovery
 521 *  when an error occurs.
 522 */
 523
 524typedef unsigned int __bitwise pci_ers_result_t;
 525
 526enum pci_ers_result {
 527        /* no result/none/not supported in device driver */
 528        PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
 529
 530        /* Device driver can recover without slot reset */
 531        PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
 532
 533        /* Device driver wants slot to be reset. */
 534        PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
 535
 536        /* Device has completely failed, is unrecoverable */
 537        PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
 538
 539        /* Device driver is fully recovered and operational */
 540        PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
 541};
 542
 543/* PCI bus error event callbacks */
 544struct pci_error_handlers {
 545        /* PCI bus error detected on this device */
 546        pci_ers_result_t (*error_detected)(struct pci_dev *dev,
 547                                           enum pci_channel_state error);
 548
 549        /* MMIO has been re-enabled, but not DMA */
 550        pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
 551
 552        /* PCI Express link has been reset */
 553        pci_ers_result_t (*link_reset)(struct pci_dev *dev);
 554
 555        /* PCI slot has been reset */
 556        pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
 557
 558        /* Device driver may resume normal operations */
 559        void (*resume)(struct pci_dev *dev);
 560};
 561
 562/* ---------------------------------------------------------------- */
 563
 564struct module;
 565struct pci_driver {
 566        struct list_head node;
 567        const char *name;
 568        const struct pci_device_id *id_table;   /* must be non-NULL for probe to be called */
 569        int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);   /* New device inserted */
 570        void (*remove) (struct pci_dev *dev);   /* Device removed (NULL if not a hot-plug capable driver) */
 571        int  (*suspend) (struct pci_dev *dev, pm_message_t state);      /* Device suspended */
 572        int  (*suspend_late) (struct pci_dev *dev, pm_message_t state);
 573        int  (*resume_early) (struct pci_dev *dev);
 574        int  (*resume) (struct pci_dev *dev);                   /* Device woken up */
 575        void (*shutdown) (struct pci_dev *dev);
 576        const struct pci_error_handlers *err_handler;
 577        struct device_driver    driver;
 578        struct pci_dynids dynids;
 579};
 580
 581#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
 582
 583/**
 584 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
 585 * @_table: device table name
 586 *
 587 * This macro is used to create a struct pci_device_id array (a device table)
 588 * in a generic manner.
 589 */
 590#define DEFINE_PCI_DEVICE_TABLE(_table) \
 591        const struct pci_device_id _table[] __devinitconst
 592
 593/**
 594 * PCI_DEVICE - macro used to describe a specific pci device
 595 * @vend: the 16 bit PCI Vendor ID
 596 * @dev: the 16 bit PCI Device ID
 597 *
 598 * This macro is used to create a struct pci_device_id that matches a
 599 * specific device.  The subvendor and subdevice fields will be set to
 600 * PCI_ANY_ID.
 601 */
 602#define PCI_DEVICE(vend,dev) \
 603        .vendor = (vend), .device = (dev), \
 604        .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
 605
 606/**
 607 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
 608 * @dev_class: the class, subclass, prog-if triple for this device
 609 * @dev_class_mask: the class mask for this device
 610 *
 611 * This macro is used to create a struct pci_device_id that matches a
 612 * specific PCI class.  The vendor, device, subvendor, and subdevice
 613 * fields will be set to PCI_ANY_ID.
 614 */
 615#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
 616        .class = (dev_class), .class_mask = (dev_class_mask), \
 617        .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
 618        .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
 619
 620/**
 621 * PCI_VDEVICE - macro used to describe a specific pci device in short form
 622 * @vendor: the vendor name
 623 * @device: the 16 bit PCI Device ID
 624 *
 625 * This macro is used to create a struct pci_device_id that matches a
 626 * specific PCI device.  The subvendor, and subdevice fields will be set
 627 * to PCI_ANY_ID. The macro allows the next field to follow as the device
 628 * private data.
 629 */
 630
 631#define PCI_VDEVICE(vendor, device)             \
 632        PCI_VENDOR_ID_##vendor, (device),       \
 633        PCI_ANY_ID, PCI_ANY_ID, 0, 0
 634
 635/* these external functions are only available when PCI support is enabled */
 636#ifdef CONFIG_PCI
 637
 638extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
 639
 640enum pcie_bus_config_types {
 641        PCIE_BUS_TUNE_OFF,
 642        PCIE_BUS_SAFE,
 643        PCIE_BUS_PERFORMANCE,
 644        PCIE_BUS_PEER2PEER,
 645};
 646
 647extern enum pcie_bus_config_types pcie_bus_config;
 648
 649extern struct bus_type pci_bus_type;
 650
 651/* Do NOT directly access these two variables, unless you are arch specific pci
 652 * code, or pci core code. */
 653extern struct list_head pci_root_buses; /* list of all known PCI buses */
 654/* Some device drivers need know if pci is initiated */
 655extern int no_pci_devices(void);
 656
 657void pcibios_fixup_bus(struct pci_bus *);
 658int __must_check pcibios_enable_device(struct pci_dev *, int mask);
 659/* Architecture specific versions may override this (weak) */
 660char *pcibios_setup(char *str);
 661
 662/* Used only when drivers/pci/setup.c is used */
 663resource_size_t pcibios_align_resource(void *, const struct resource *,
 664                                resource_size_t,
 665                                resource_size_t);
 666void pcibios_update_irq(struct pci_dev *, int irq);
 667
 668/* Weak but can be overriden by arch */
 669void pci_fixup_cardbus(struct pci_bus *);
 670
 671/* Generic PCI functions used internally */
 672
 673void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 674                             struct resource *res);
 675void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 676                             struct pci_bus_region *region);
 677void pcibios_scan_specific_bus(int busn);
 678extern struct pci_bus *pci_find_bus(int domain, int busnr);
 679void pci_bus_add_devices(const struct pci_bus *bus);
 680struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
 681                                      struct pci_ops *ops, void *sysdata);
 682struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
 683struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
 684                                    struct pci_ops *ops, void *sysdata,
 685                                    struct list_head *resources);
 686int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
 687int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
 688void pci_bus_release_busn_res(struct pci_bus *b);
 689struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
 690                                             struct pci_ops *ops, void *sysdata,
 691                                             struct list_head *resources);
 692struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
 693                                int busnr);
 694void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
 695struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
 696                                 const char *name,
 697                                 struct hotplug_slot *hotplug);
 698void pci_destroy_slot(struct pci_slot *slot);
 699void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
 700int pci_scan_slot(struct pci_bus *bus, int devfn);
 701struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
 702void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
 703unsigned int pci_scan_child_bus(struct pci_bus *bus);
 704int __must_check pci_bus_add_device(struct pci_dev *dev);
 705void pci_read_bridge_bases(struct pci_bus *child);
 706struct resource *pci_find_parent_resource(const struct pci_dev *dev,
 707                                          struct resource *res);
 708u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
 709int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
 710u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
 711extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
 712extern void pci_dev_put(struct pci_dev *dev);
 713extern void pci_remove_bus(struct pci_bus *b);
 714extern void pci_stop_and_remove_bus_device(struct pci_dev *dev);
 715void pci_setup_cardbus(struct pci_bus *bus);
 716extern void pci_sort_breadthfirst(void);
 717#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
 718#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
 719#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
 720
 721/* Generic PCI functions exported to card drivers */
 722
 723enum pci_lost_interrupt_reason {
 724        PCI_LOST_IRQ_NO_INFORMATION = 0,
 725        PCI_LOST_IRQ_DISABLE_MSI,
 726        PCI_LOST_IRQ_DISABLE_MSIX,
 727        PCI_LOST_IRQ_DISABLE_ACPI,
 728};
 729enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
 730int pci_find_capability(struct pci_dev *dev, int cap);
 731int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
 732int pci_find_ext_capability(struct pci_dev *dev, int cap);
 733int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
 734int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
 735int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
 736struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
 737
 738struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
 739                                struct pci_dev *from);
 740struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
 741                                unsigned int ss_vendor, unsigned int ss_device,
 742                                struct pci_dev *from);
 743struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
 744struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
 745                                            unsigned int devfn);
 746static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
 747                                                   unsigned int devfn)
 748{
 749        return pci_get_domain_bus_and_slot(0, bus, devfn);
 750}
 751struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
 752int pci_dev_present(const struct pci_device_id *ids);
 753
 754int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
 755                             int where, u8 *val);
 756int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
 757                             int where, u16 *val);
 758int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
 759                              int where, u32 *val);
 760int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
 761                              int where, u8 val);
 762int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
 763                              int where, u16 val);
 764int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
 765                               int where, u32 val);
 766struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
 767
 768static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
 769{
 770        return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
 771}
 772static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
 773{
 774        return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
 775}
 776static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
 777                                        u32 *val)
 778{
 779        return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
 780}
 781static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
 782{
 783        return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
 784}
 785static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
 786{
 787        return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
 788}
 789static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
 790                                         u32 val)
 791{
 792        return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
 793}
 794
 795int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
 796int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
 797int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
 798int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
 799int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
 800                                       u16 clear, u16 set);
 801int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
 802                                        u32 clear, u32 set);
 803
 804static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
 805                                           u16 set)
 806{
 807        return pcie_capability_clear_and_set_word(dev, pos, 0, set);
 808}
 809
 810static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
 811                                            u32 set)
 812{
 813        return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
 814}
 815
 816static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
 817                                             u16 clear)
 818{
 819        return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
 820}
 821
 822static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
 823                                              u32 clear)
 824{
 825        return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
 826}
 827
 828/* user-space driven config access */
 829int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
 830int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
 831int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
 832int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
 833int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
 834int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
 835
 836int __must_check pci_enable_device(struct pci_dev *dev);
 837int __must_check pci_enable_device_io(struct pci_dev *dev);
 838int __must_check pci_enable_device_mem(struct pci_dev *dev);
 839int __must_check pci_reenable_device(struct pci_dev *);
 840int __must_check pcim_enable_device(struct pci_dev *pdev);
 841void pcim_pin_device(struct pci_dev *pdev);
 842
 843static inline int pci_is_enabled(struct pci_dev *pdev)
 844{
 845        return (atomic_read(&pdev->enable_cnt) > 0);
 846}
 847
 848static inline int pci_is_managed(struct pci_dev *pdev)
 849{
 850        return pdev->is_managed;
 851}
 852
 853void pci_disable_device(struct pci_dev *dev);
 854
 855extern unsigned int pcibios_max_latency;
 856void pci_set_master(struct pci_dev *dev);
 857void pci_clear_master(struct pci_dev *dev);
 858
 859int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
 860int pci_set_cacheline_size(struct pci_dev *dev);
 861#define HAVE_PCI_SET_MWI
 862int __must_check pci_set_mwi(struct pci_dev *dev);
 863int pci_try_set_mwi(struct pci_dev *dev);
 864void pci_clear_mwi(struct pci_dev *dev);
 865void pci_intx(struct pci_dev *dev, int enable);
 866bool pci_intx_mask_supported(struct pci_dev *dev);
 867bool pci_check_and_mask_intx(struct pci_dev *dev);
 868bool pci_check_and_unmask_intx(struct pci_dev *dev);
 869void pci_msi_off(struct pci_dev *dev);
 870int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
 871int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
 872int pcix_get_max_mmrbc(struct pci_dev *dev);
 873int pcix_get_mmrbc(struct pci_dev *dev);
 874int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
 875int pcie_get_readrq(struct pci_dev *dev);
 876int pcie_set_readrq(struct pci_dev *dev, int rq);
 877int pcie_get_mps(struct pci_dev *dev);
 878int pcie_set_mps(struct pci_dev *dev, int mps);
 879int __pci_reset_function(struct pci_dev *dev);
 880int __pci_reset_function_locked(struct pci_dev *dev);
 881int pci_reset_function(struct pci_dev *dev);
 882void pci_update_resource(struct pci_dev *dev, int resno);
 883int __must_check pci_assign_resource(struct pci_dev *dev, int i);
 884int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
 885int pci_select_bars(struct pci_dev *dev, unsigned long flags);
 886
 887/* ROM control related routines */
 888int pci_enable_rom(struct pci_dev *pdev);
 889void pci_disable_rom(struct pci_dev *pdev);
 890void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
 891void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
 892size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
 893
 894/* Power management related routines */
 895int pci_save_state(struct pci_dev *dev);
 896void pci_restore_state(struct pci_dev *dev);
 897struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
 898int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
 899int pci_load_and_free_saved_state(struct pci_dev *dev,
 900                                  struct pci_saved_state **state);
 901int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
 902int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
 903pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
 904bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
 905void pci_pme_active(struct pci_dev *dev, bool enable);
 906int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
 907                      bool runtime, bool enable);
 908int pci_wake_from_d3(struct pci_dev *dev, bool enable);
 909pci_power_t pci_target_state(struct pci_dev *dev);
 910int pci_prepare_to_sleep(struct pci_dev *dev);
 911int pci_back_from_sleep(struct pci_dev *dev);
 912bool pci_dev_run_wake(struct pci_dev *dev);
 913bool pci_check_pme_status(struct pci_dev *dev);
 914void pci_pme_wakeup_bus(struct pci_bus *bus);
 915
 916static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
 917                                  bool enable)
 918{
 919        return __pci_enable_wake(dev, state, false, enable);
 920}
 921
 922#define PCI_EXP_IDO_REQUEST     (1<<0)
 923#define PCI_EXP_IDO_COMPLETION  (1<<1)
 924void pci_enable_ido(struct pci_dev *dev, unsigned long type);
 925void pci_disable_ido(struct pci_dev *dev, unsigned long type);
 926
 927enum pci_obff_signal_type {
 928        PCI_EXP_OBFF_SIGNAL_L0 = 0,
 929        PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
 930};
 931int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
 932void pci_disable_obff(struct pci_dev *dev);
 933
 934int pci_enable_ltr(struct pci_dev *dev);
 935void pci_disable_ltr(struct pci_dev *dev);
 936int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
 937
 938/* For use by arch with custom probe code */
 939void set_pcie_port_type(struct pci_dev *pdev);
 940void set_pcie_hotplug_bridge(struct pci_dev *pdev);
 941
 942/* Functions for PCI Hotplug drivers to use */
 943int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
 944#ifdef CONFIG_HOTPLUG
 945unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
 946unsigned int pci_rescan_bus(struct pci_bus *bus);
 947#endif
 948
 949/* Vital product data routines */
 950ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
 951ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
 952int pci_vpd_truncate(struct pci_dev *dev, size_t size);
 953
 954/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
 955resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
 956void pci_bus_assign_resources(const struct pci_bus *bus);
 957void pci_bus_size_bridges(struct pci_bus *bus);
 958int pci_claim_resource(struct pci_dev *, int);
 959void pci_assign_unassigned_resources(void);
 960void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
 961void pdev_enable_device(struct pci_dev *);
 962int pci_enable_resources(struct pci_dev *, int mask);
 963void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
 964                    int (*)(const struct pci_dev *, u8, u8));
 965#define HAVE_PCI_REQ_REGIONS    2
 966int __must_check pci_request_regions(struct pci_dev *, const char *);
 967int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
 968void pci_release_regions(struct pci_dev *);
 969int __must_check pci_request_region(struct pci_dev *, int, const char *);
 970int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
 971void pci_release_region(struct pci_dev *, int);
 972int pci_request_selected_regions(struct pci_dev *, int, const char *);
 973int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
 974void pci_release_selected_regions(struct pci_dev *, int);
 975
 976/* drivers/pci/bus.c */
 977void pci_add_resource(struct list_head *resources, struct resource *res);
 978void pci_add_resource_offset(struct list_head *resources, struct resource *res,
 979                             resource_size_t offset);
 980void pci_free_resource_list(struct list_head *resources);
 981void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
 982struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
 983void pci_bus_remove_resources(struct pci_bus *bus);
 984
 985#define pci_bus_for_each_resource(bus, res, i)                          \
 986        for (i = 0;                                                     \
 987            (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
 988             i++)
 989
 990int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
 991                        struct resource *res, resource_size_t size,
 992                        resource_size_t align, resource_size_t min,
 993                        unsigned int type_mask,
 994                        resource_size_t (*alignf)(void *,
 995                                                  const struct resource *,
 996                                                  resource_size_t,
 997                                                  resource_size_t),
 998                        void *alignf_data);
 999void pci_enable_bridges(struct pci_bus *bus);
1000
1001/* Proper probing supporting hot-pluggable devices */
1002int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1003                                       const char *mod_name);
1004
1005/*
1006 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1007 */
1008#define pci_register_driver(driver)             \
1009        __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1010
1011void pci_unregister_driver(struct pci_driver *dev);
1012
1013/**
1014 * module_pci_driver() - Helper macro for registering a PCI driver
1015 * @__pci_driver: pci_driver struct
1016 *
1017 * Helper macro for PCI drivers which do not do anything special in module
1018 * init/exit. This eliminates a lot of boilerplate. Each module may only
1019 * use this macro once, and calling it replaces module_init() and module_exit()
1020 */
1021#define module_pci_driver(__pci_driver) \
1022        module_driver(__pci_driver, pci_register_driver, \
1023                       pci_unregister_driver)
1024
1025struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1026int pci_add_dynid(struct pci_driver *drv,
1027                  unsigned int vendor, unsigned int device,
1028                  unsigned int subvendor, unsigned int subdevice,
1029                  unsigned int class, unsigned int class_mask,
1030                  unsigned long driver_data);
1031const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1032                                         struct pci_dev *dev);
1033int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1034                    int pass);
1035
1036void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1037                  void *userdata);
1038int pci_cfg_space_size_ext(struct pci_dev *dev);
1039int pci_cfg_space_size(struct pci_dev *dev);
1040unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1041void pci_setup_bridge(struct pci_bus *bus);
1042resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1043                                         unsigned long type);
1044
1045#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1046#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1047
1048int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1049                      unsigned int command_bits, u32 flags);
1050/* kmem_cache style wrapper around pci_alloc_consistent() */
1051
1052#include <linux/pci-dma.h>
1053#include <linux/dmapool.h>
1054
1055#define pci_pool dma_pool
1056#define pci_pool_create(name, pdev, size, align, allocation) \
1057                dma_pool_create(name, &pdev->dev, size, align, allocation)
1058#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1059#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1060#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1061
1062enum pci_dma_burst_strategy {
1063        PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1064                                   strategy_parameter is N/A */
1065        PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1066                                   byte boundaries */
1067        PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1068                                   strategy_parameter byte boundaries */
1069};
1070
1071struct msix_entry {
1072        u32     vector; /* kernel uses to write allocated vector */
1073        u16     entry;  /* driver uses to specify entry, OS writes */
1074};
1075
1076
1077#ifndef CONFIG_PCI_MSI
1078static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1079{
1080        return -1;
1081}
1082
1083static inline void pci_msi_shutdown(struct pci_dev *dev)
1084{ }
1085static inline void pci_disable_msi(struct pci_dev *dev)
1086{ }
1087
1088static inline int pci_msix_table_size(struct pci_dev *dev)
1089{
1090        return 0;
1091}
1092static inline int pci_enable_msix(struct pci_dev *dev,
1093                                  struct msix_entry *entries, int nvec)
1094{
1095        return -1;
1096}
1097
1098static inline void pci_msix_shutdown(struct pci_dev *dev)
1099{ }
1100static inline void pci_disable_msix(struct pci_dev *dev)
1101{ }
1102
1103static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1104{ }
1105
1106static inline void pci_restore_msi_state(struct pci_dev *dev)
1107{ }
1108static inline int pci_msi_enabled(void)
1109{
1110        return 0;
1111}
1112#else
1113extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1114extern void pci_msi_shutdown(struct pci_dev *dev);
1115extern void pci_disable_msi(struct pci_dev *dev);
1116extern int pci_msix_table_size(struct pci_dev *dev);
1117extern int pci_enable_msix(struct pci_dev *dev,
1118        struct msix_entry *entries, int nvec);
1119extern void pci_msix_shutdown(struct pci_dev *dev);
1120extern void pci_disable_msix(struct pci_dev *dev);
1121extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1122extern void pci_restore_msi_state(struct pci_dev *dev);
1123extern int pci_msi_enabled(void);
1124#endif
1125
1126#ifdef CONFIG_PCIEPORTBUS
1127extern bool pcie_ports_disabled;
1128extern bool pcie_ports_auto;
1129#else
1130#define pcie_ports_disabled     true
1131#define pcie_ports_auto         false
1132#endif
1133
1134#ifndef CONFIG_PCIEASPM
1135static inline int pcie_aspm_enabled(void) { return 0; }
1136static inline bool pcie_aspm_support_enabled(void) { return false; }
1137#else
1138extern int pcie_aspm_enabled(void);
1139extern bool pcie_aspm_support_enabled(void);
1140#endif
1141
1142#ifdef CONFIG_PCIEAER
1143void pci_no_aer(void);
1144bool pci_aer_available(void);
1145#else
1146static inline void pci_no_aer(void) { }
1147static inline bool pci_aer_available(void) { return false; }
1148#endif
1149
1150#ifndef CONFIG_PCIE_ECRC
1151static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1152{
1153        return;
1154}
1155static inline void pcie_ecrc_get_policy(char *str) {};
1156#else
1157extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1158extern void pcie_ecrc_get_policy(char *str);
1159#endif
1160
1161#define pci_enable_msi(pdev)    pci_enable_msi_block(pdev, 1)
1162
1163#ifdef CONFIG_HT_IRQ
1164/* The functions a driver should call */
1165int  ht_create_irq(struct pci_dev *dev, int idx);
1166void ht_destroy_irq(unsigned int irq);
1167#endif /* CONFIG_HT_IRQ */
1168
1169extern void pci_cfg_access_lock(struct pci_dev *dev);
1170extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1171extern void pci_cfg_access_unlock(struct pci_dev *dev);
1172
1173/*
1174 * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
1175 * a PCI domain is defined to be a set of PCI busses which share
1176 * configuration space.
1177 */
1178#ifdef CONFIG_PCI_DOMAINS
1179extern int pci_domains_supported;
1180#else
1181enum { pci_domains_supported = 0 };
1182static inline int pci_domain_nr(struct pci_bus *bus)
1183{
1184        return 0;
1185}
1186
1187static inline int pci_proc_domain(struct pci_bus *bus)
1188{
1189        return 0;
1190}
1191#endif /* CONFIG_PCI_DOMAINS */
1192
1193/* some architectures require additional setup to direct VGA traffic */
1194typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1195                      unsigned int command_bits, u32 flags);
1196extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1197
1198#else /* CONFIG_PCI is not enabled */
1199
1200/*
1201 *  If the system does not have PCI, clearly these return errors.  Define
1202 *  these as simple inline functions to avoid hair in drivers.
1203 */
1204
1205#define _PCI_NOP(o, s, t) \
1206        static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1207                                                int where, t val) \
1208                { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1209
1210#define _PCI_NOP_ALL(o, x)      _PCI_NOP(o, byte, u8 x) \
1211                                _PCI_NOP(o, word, u16 x) \
1212                                _PCI_NOP(o, dword, u32 x)
1213_PCI_NOP_ALL(read, *)
1214_PCI_NOP_ALL(write,)
1215
1216static inline struct pci_dev *pci_get_device(unsigned int vendor,
1217                                             unsigned int device,
1218                                             struct pci_dev *from)
1219{
1220        return NULL;
1221}
1222
1223static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1224                                             unsigned int device,
1225                                             unsigned int ss_vendor,
1226                                             unsigned int ss_device,
1227                                             struct pci_dev *from)
1228{
1229        return NULL;
1230}
1231
1232static inline struct pci_dev *pci_get_class(unsigned int class,
1233                                            struct pci_dev *from)
1234{
1235        return NULL;
1236}
1237
1238#define pci_dev_present(ids)    (0)
1239#define no_pci_devices()        (1)
1240#define pci_dev_put(dev)        do { } while (0)
1241
1242static inline void pci_set_master(struct pci_dev *dev)
1243{ }
1244
1245static inline int pci_enable_device(struct pci_dev *dev)
1246{
1247        return -EIO;
1248}
1249
1250static inline void pci_disable_device(struct pci_dev *dev)
1251{ }
1252
1253static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1254{
1255        return -EIO;
1256}
1257
1258static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1259{
1260        return -EIO;
1261}
1262
1263static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1264                                        unsigned int size)
1265{
1266        return -EIO;
1267}
1268
1269static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1270                                        unsigned long mask)
1271{
1272        return -EIO;
1273}
1274
1275static inline int pci_assign_resource(struct pci_dev *dev, int i)
1276{
1277        return -EBUSY;
1278}
1279
1280static inline int __pci_register_driver(struct pci_driver *drv,
1281                                        struct module *owner)
1282{
1283        return 0;
1284}
1285
1286static inline int pci_register_driver(struct pci_driver *drv)
1287{
1288        return 0;
1289}
1290
1291static inline void pci_unregister_driver(struct pci_driver *drv)
1292{ }
1293
1294static inline int pci_find_capability(struct pci_dev *dev, int cap)
1295{
1296        return 0;
1297}
1298
1299static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1300                                           int cap)
1301{
1302        return 0;
1303}
1304
1305static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1306{
1307        return 0;
1308}
1309
1310/* Power management related routines */
1311static inline int pci_save_state(struct pci_dev *dev)
1312{
1313        return 0;
1314}
1315
1316static inline void pci_restore_state(struct pci_dev *dev)
1317{ }
1318
1319static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1320{
1321        return 0;
1322}
1323
1324static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1325{
1326        return 0;
1327}
1328
1329static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1330                                           pm_message_t state)
1331{
1332        return PCI_D0;
1333}
1334
1335static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1336                                  int enable)
1337{
1338        return 0;
1339}
1340
1341static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1342{
1343}
1344
1345static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1346{
1347}
1348
1349static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1350{
1351        return 0;
1352}
1353
1354static inline void pci_disable_obff(struct pci_dev *dev)
1355{
1356}
1357
1358static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1359{
1360        return -EIO;
1361}
1362
1363static inline void pci_release_regions(struct pci_dev *dev)
1364{ }
1365
1366#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1367
1368static inline void pci_block_cfg_access(struct pci_dev *dev)
1369{ }
1370
1371static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1372{ return 0; }
1373
1374static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1375{ }
1376
1377static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1378{ return NULL; }
1379
1380static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1381                                                unsigned int devfn)
1382{ return NULL; }
1383
1384static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1385                                                unsigned int devfn)
1386{ return NULL; }
1387
1388static inline int pci_domain_nr(struct pci_bus *bus)
1389{ return 0; }
1390
1391static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1392{ return NULL; }
1393
1394#define dev_is_pci(d) (false)
1395#define dev_is_pf(d) (false)
1396#define dev_num_vf(d) (0)
1397#endif /* CONFIG_PCI */
1398
1399/* Include architecture-dependent settings and functions */
1400
1401#include <asm/pci.h>
1402
1403#ifndef PCIBIOS_MAX_MEM_32
1404#define PCIBIOS_MAX_MEM_32 (-1)
1405#endif
1406
1407/* these helpers provide future and backwards compatibility
1408 * for accessing popular PCI BAR info */
1409#define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
1410#define pci_resource_end(dev, bar)      ((dev)->resource[(bar)].end)
1411#define pci_resource_flags(dev, bar)    ((dev)->resource[(bar)].flags)
1412#define pci_resource_len(dev,bar) \
1413        ((pci_resource_start((dev), (bar)) == 0 &&      \
1414          pci_resource_end((dev), (bar)) ==             \
1415          pci_resource_start((dev), (bar))) ? 0 :       \
1416                                                        \
1417         (pci_resource_end((dev), (bar)) -              \
1418          pci_resource_start((dev), (bar)) + 1))
1419
1420/* Similar to the helpers above, these manipulate per-pci_dev
1421 * driver-specific data.  They are really just a wrapper around
1422 * the generic device structure functions of these calls.
1423 */
1424static inline void *pci_get_drvdata(struct pci_dev *pdev)
1425{
1426        return dev_get_drvdata(&pdev->dev);
1427}
1428
1429static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1430{
1431        dev_set_drvdata(&pdev->dev, data);
1432}
1433
1434/* If you want to know what to call your pci_dev, ask this function.
1435 * Again, it's a wrapper around the generic device.
1436 */
1437static inline const char *pci_name(const struct pci_dev *pdev)
1438{
1439        return dev_name(&pdev->dev);
1440}
1441
1442
1443/* Some archs don't want to expose struct resource to userland as-is
1444 * in sysfs and /proc
1445 */
1446#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1447static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1448                const struct resource *rsrc, resource_size_t *start,
1449                resource_size_t *end)
1450{
1451        *start = rsrc->start;
1452        *end = rsrc->end;
1453}
1454#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1455
1456
1457/*
1458 *  The world is not perfect and supplies us with broken PCI devices.
1459 *  For at least a part of these bugs we need a work-around, so both
1460 *  generic (drivers/pci/quirks.c) and per-architecture code can define
1461 *  fixup hooks to be called for particular buggy devices.
1462 */
1463
1464struct pci_fixup {
1465        u16 vendor;             /* You can use PCI_ANY_ID here of course */
1466        u16 device;             /* You can use PCI_ANY_ID here of course */
1467        u32 class;              /* You can use PCI_ANY_ID here too */
1468        unsigned int class_shift;       /* should be 0, 8, 16 */
1469        void (*hook)(struct pci_dev *dev);
1470};
1471
1472enum pci_fixup_pass {
1473        pci_fixup_early,        /* Before probing BARs */
1474        pci_fixup_header,       /* After reading configuration header */
1475        pci_fixup_final,        /* Final phase of device fixups */
1476        pci_fixup_enable,       /* pci_enable_device() time */
1477        pci_fixup_resume,       /* pci_device_resume() */
1478        pci_fixup_suspend,      /* pci_device_suspend */
1479        pci_fixup_resume_early, /* pci_device_resume_early() */
1480};
1481
1482/* Anonymous variables would be nice... */
1483#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1484                                  class_shift, hook)                    \
1485        static const struct pci_fixup __pci_fixup_##name __used         \
1486        __attribute__((__section__(#section), aligned((sizeof(void *)))))    \
1487                = { vendor, device, class, class_shift, hook };
1488
1489#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,            \
1490                                         class_shift, hook)             \
1491        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1492                vendor##device##hook, vendor, device, class, class_shift, hook)
1493#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,           \
1494                                         class_shift, hook)             \
1495        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1496                vendor##device##hook, vendor, device, class, class_shift, hook)
1497#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,            \
1498                                         class_shift, hook)             \
1499        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1500                vendor##device##hook, vendor, device, class, class_shift, hook)
1501#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,           \
1502                                         class_shift, hook)             \
1503        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1504                vendor##device##hook, vendor, device, class, class_shift, hook)
1505#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,           \
1506                                         class_shift, hook)             \
1507        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1508                resume##vendor##device##hook, vendor, device, class,    \
1509                class_shift, hook)
1510#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,     \
1511                                         class_shift, hook)             \
1512        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1513                resume_early##vendor##device##hook, vendor, device,     \
1514                class, class_shift, hook)
1515#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,          \
1516                                         class_shift, hook)             \
1517        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1518                suspend##vendor##device##hook, vendor, device, class,   \
1519                class_shift, hook)
1520
1521#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)                   \
1522        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1523                vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1524#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)                  \
1525        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1526                vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1527#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)                   \
1528        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1529                vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1530#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)                  \
1531        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1532                vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1533#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)                  \
1534        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1535                resume##vendor##device##hook, vendor, device,           \
1536                PCI_ANY_ID, 0, hook)
1537#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)            \
1538        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1539                resume_early##vendor##device##hook, vendor, device,     \
1540                PCI_ANY_ID, 0, hook)
1541#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)                 \
1542        DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1543                suspend##vendor##device##hook, vendor, device,          \
1544                PCI_ANY_ID, 0, hook)
1545
1546#ifdef CONFIG_PCI_QUIRKS
1547void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1548struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1549int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1550#else
1551static inline void pci_fixup_device(enum pci_fixup_pass pass,
1552                                    struct pci_dev *dev) {}
1553static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1554{
1555        return pci_dev_get(dev);
1556}
1557static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1558                                               u16 acs_flags)
1559{
1560        return -ENOTTY;
1561}
1562#endif
1563
1564void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1565void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1566void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1567int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1568int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1569                                   const char *name);
1570void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1571
1572extern int pci_pci_problems;
1573#define PCIPCI_FAIL             1       /* No PCI PCI DMA */
1574#define PCIPCI_TRITON           2
1575#define PCIPCI_NATOMA           4
1576#define PCIPCI_VIAETBF          8
1577#define PCIPCI_VSFX             16
1578#define PCIPCI_ALIMAGIK         32      /* Need low latency setting */
1579#define PCIAGP_FAIL             64      /* No PCI to AGP DMA */
1580
1581extern unsigned long pci_cardbus_io_size;
1582extern unsigned long pci_cardbus_mem_size;
1583extern u8 __devinitdata pci_dfl_cache_line_size;
1584extern u8 pci_cache_line_size;
1585
1586extern unsigned long pci_hotplug_io_size;
1587extern unsigned long pci_hotplug_mem_size;
1588
1589/* Architecture specific versions may override these (weak) */
1590int pcibios_add_platform_entries(struct pci_dev *dev);
1591void pcibios_disable_device(struct pci_dev *dev);
1592void pcibios_set_master(struct pci_dev *dev);
1593int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1594                                 enum pcie_reset_state state);
1595
1596#ifdef CONFIG_PCI_MMCONFIG
1597extern void __init pci_mmcfg_early_init(void);
1598extern void __init pci_mmcfg_late_init(void);
1599#else
1600static inline void pci_mmcfg_early_init(void) { }
1601static inline void pci_mmcfg_late_init(void) { }
1602#endif
1603
1604int pci_ext_cfg_avail(struct pci_dev *dev);
1605
1606void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1607
1608#ifdef CONFIG_PCI_IOV
1609extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1610extern void pci_disable_sriov(struct pci_dev *dev);
1611extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1612extern int pci_num_vf(struct pci_dev *dev);
1613#else
1614static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1615{
1616        return -ENODEV;
1617}
1618static inline void pci_disable_sriov(struct pci_dev *dev)
1619{
1620}
1621static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1622{
1623        return IRQ_NONE;
1624}
1625static inline int pci_num_vf(struct pci_dev *dev)
1626{
1627        return 0;
1628}
1629#endif
1630
1631#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1632extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1633extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1634#endif
1635
1636/**
1637 * pci_pcie_cap - get the saved PCIe capability offset
1638 * @dev: PCI device
1639 *
1640 * PCIe capability offset is calculated at PCI device initialization
1641 * time and saved in the data structure. This function returns saved
1642 * PCIe capability offset. Using this instead of pci_find_capability()
1643 * reduces unnecessary search in the PCI configuration space. If you
1644 * need to calculate PCIe capability offset from raw device for some
1645 * reasons, please use pci_find_capability() instead.
1646 */
1647static inline int pci_pcie_cap(struct pci_dev *dev)
1648{
1649        return dev->pcie_cap;
1650}
1651
1652/**
1653 * pci_is_pcie - check if the PCI device is PCI Express capable
1654 * @dev: PCI device
1655 *
1656 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1657 */
1658static inline bool pci_is_pcie(struct pci_dev *dev)
1659{
1660        return !!pci_pcie_cap(dev);
1661}
1662
1663/**
1664 * pci_pcie_type - get the PCIe device/port type
1665 * @dev: PCI device
1666 */
1667static inline int pci_pcie_type(const struct pci_dev *dev)
1668{
1669        return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4;
1670}
1671
1672void pci_request_acs(void);
1673bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1674bool pci_acs_path_enabled(struct pci_dev *start,
1675                          struct pci_dev *end, u16 acs_flags);
1676
1677#define PCI_VPD_LRDT                    0x80    /* Large Resource Data Type */
1678#define PCI_VPD_LRDT_ID(x)              (x | PCI_VPD_LRDT)
1679
1680/* Large Resource Data Type Tag Item Names */
1681#define PCI_VPD_LTIN_ID_STRING          0x02    /* Identifier String */
1682#define PCI_VPD_LTIN_RO_DATA            0x10    /* Read-Only Data */
1683#define PCI_VPD_LTIN_RW_DATA            0x11    /* Read-Write Data */
1684
1685#define PCI_VPD_LRDT_ID_STRING          PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1686#define PCI_VPD_LRDT_RO_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1687#define PCI_VPD_LRDT_RW_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1688
1689/* Small Resource Data Type Tag Item Names */
1690#define PCI_VPD_STIN_END                0x78    /* End */
1691
1692#define PCI_VPD_SRDT_END                PCI_VPD_STIN_END
1693
1694#define PCI_VPD_SRDT_TIN_MASK           0x78
1695#define PCI_VPD_SRDT_LEN_MASK           0x07
1696
1697#define PCI_VPD_LRDT_TAG_SIZE           3
1698#define PCI_VPD_SRDT_TAG_SIZE           1
1699
1700#define PCI_VPD_INFO_FLD_HDR_SIZE       3
1701
1702#define PCI_VPD_RO_KEYWORD_PARTNO       "PN"
1703#define PCI_VPD_RO_KEYWORD_MFR_ID       "MN"
1704#define PCI_VPD_RO_KEYWORD_VENDOR0      "V0"
1705#define PCI_VPD_RO_KEYWORD_CHKSUM       "RV"
1706
1707/**
1708 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1709 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1710 *
1711 * Returns the extracted Large Resource Data Type length.
1712 */
1713static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1714{
1715        return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1716}
1717
1718/**
1719 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1720 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1721 *
1722 * Returns the extracted Small Resource Data Type length.
1723 */
1724static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1725{
1726        return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1727}
1728
1729/**
1730 * pci_vpd_info_field_size - Extracts the information field length
1731 * @lrdt: Pointer to the beginning of an information field header
1732 *
1733 * Returns the extracted information field length.
1734 */
1735static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1736{
1737        return info_field[2];
1738}
1739
1740/**
1741 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1742 * @buf: Pointer to buffered vpd data
1743 * @off: The offset into the buffer at which to begin the search
1744 * @len: The length of the vpd buffer
1745 * @rdt: The Resource Data Type to search for
1746 *
1747 * Returns the index where the Resource Data Type was found or
1748 * -ENOENT otherwise.
1749 */
1750int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1751
1752/**
1753 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1754 * @buf: Pointer to buffered vpd data
1755 * @off: The offset into the buffer at which to begin the search
1756 * @len: The length of the buffer area, relative to off, in which to search
1757 * @kw: The keyword to search for
1758 *
1759 * Returns the index where the information field keyword was found or
1760 * -ENOENT otherwise.
1761 */
1762int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1763                              unsigned int len, const char *kw);
1764
1765/* PCI <-> OF binding helpers */
1766#ifdef CONFIG_OF
1767struct device_node;
1768extern void pci_set_of_node(struct pci_dev *dev);
1769extern void pci_release_of_node(struct pci_dev *dev);
1770extern void pci_set_bus_of_node(struct pci_bus *bus);
1771extern void pci_release_bus_of_node(struct pci_bus *bus);
1772
1773/* Arch may override this (weak) */
1774extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1775
1776static inline struct device_node *
1777pci_device_to_OF_node(const struct pci_dev *pdev)
1778{
1779        return pdev ? pdev->dev.of_node : NULL;
1780}
1781
1782static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1783{
1784        return bus ? bus->dev.of_node : NULL;
1785}
1786
1787#else /* CONFIG_OF */
1788static inline void pci_set_of_node(struct pci_dev *dev) { }
1789static inline void pci_release_of_node(struct pci_dev *dev) { }
1790static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1791static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1792#endif  /* CONFIG_OF */
1793
1794#ifdef CONFIG_EEH
1795static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1796{
1797        return pdev->dev.archdata.edev;
1798}
1799#endif
1800
1801/**
1802 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1803 * @pdev: the PCI device
1804 *
1805 * if the device is PCIE, return NULL
1806 * if the device isn't connected to a PCIe bridge (that is its parent is a
1807 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1808 * parent
1809 */
1810struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1811
1812#endif /* LINUX_PCI_H */
1813
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