linux/include/drm/drm_dp_helper.h
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   1/*
   2 * Copyright © 2008 Keith Packard
   3 *
   4 * Permission to use, copy, modify, distribute, and sell this software and its
   5 * documentation for any purpose is hereby granted without fee, provided that
   6 * the above copyright notice appear in all copies and that both that copyright
   7 * notice and this permission notice appear in supporting documentation, and
   8 * that the name of the copyright holders not be used in advertising or
   9 * publicity pertaining to distribution of the software without specific,
  10 * written prior permission.  The copyright holders make no representations
  11 * about the suitability of this software for any purpose.  It is provided "as
  12 * is" without express or implied warranty.
  13 *
  14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20 * OF THIS SOFTWARE.
  21 */
  22
  23#ifndef _DRM_DP_HELPER_H_
  24#define _DRM_DP_HELPER_H_
  25
  26#include <linux/types.h>
  27#include <linux/i2c.h>
  28
  29/*
  30 * Unless otherwise noted, all values are from the DP 1.1a spec.  Note that
  31 * DP and DPCD versions are independent.  Differences from 1.0 are not noted,
  32 * 1.0 devices basically don't exist in the wild.
  33 *
  34 * Abbreviations, in chronological order:
  35 *
  36 * eDP: Embedded DisplayPort version 1
  37 * DPI: DisplayPort Interoperability Guideline v1.1a
  38 * 1.2: DisplayPort 1.2
  39 *
  40 * 1.2 formally includes both eDP and DPI definitions.
  41 */
  42
  43#define AUX_NATIVE_WRITE        0x8
  44#define AUX_NATIVE_READ         0x9
  45#define AUX_I2C_WRITE           0x0
  46#define AUX_I2C_READ            0x1
  47#define AUX_I2C_STATUS          0x2
  48#define AUX_I2C_MOT             0x4
  49
  50#define AUX_NATIVE_REPLY_ACK    (0x0 << 4)
  51#define AUX_NATIVE_REPLY_NACK   (0x1 << 4)
  52#define AUX_NATIVE_REPLY_DEFER  (0x2 << 4)
  53#define AUX_NATIVE_REPLY_MASK   (0x3 << 4)
  54
  55#define AUX_I2C_REPLY_ACK       (0x0 << 6)
  56#define AUX_I2C_REPLY_NACK      (0x1 << 6)
  57#define AUX_I2C_REPLY_DEFER     (0x2 << 6)
  58#define AUX_I2C_REPLY_MASK      (0x3 << 6)
  59
  60/* AUX CH addresses */
  61/* DPCD */
  62#define DP_DPCD_REV                         0x000
  63
  64#define DP_MAX_LINK_RATE                    0x001
  65
  66#define DP_MAX_LANE_COUNT                   0x002
  67# define DP_MAX_LANE_COUNT_MASK             0x1f
  68# define DP_TPS3_SUPPORTED                  (1 << 6) /* 1.2 */
  69# define DP_ENHANCED_FRAME_CAP              (1 << 7)
  70
  71#define DP_MAX_DOWNSPREAD                   0x003
  72# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING  (1 << 6)
  73
  74#define DP_NORP                             0x004
  75
  76#define DP_DOWNSTREAMPORT_PRESENT           0x005
  77# define DP_DWN_STRM_PORT_PRESENT           (1 << 0)
  78# define DP_DWN_STRM_PORT_TYPE_MASK         0x06
  79/* 00b = DisplayPort */
  80/* 01b = Analog */
  81/* 10b = TMDS or HDMI */
  82/* 11b = Other */
  83# define DP_FORMAT_CONVERSION               (1 << 3)
  84# define DP_DETAILED_CAP_INFO_AVAILABLE     (1 << 4) /* DPI */
  85
  86#define DP_MAIN_LINK_CHANNEL_CODING         0x006
  87
  88#define DP_DOWN_STREAM_PORT_COUNT           0x007
  89# define DP_PORT_COUNT_MASK                 0x0f
  90# define DP_MSA_TIMING_PAR_IGNORED          (1 << 6) /* eDP */
  91# define DP_OUI_SUPPORT                     (1 << 7)
  92
  93#define DP_I2C_SPEED_CAP                    0x00c    /* DPI */
  94# define DP_I2C_SPEED_1K                    0x01
  95# define DP_I2C_SPEED_5K                    0x02
  96# define DP_I2C_SPEED_10K                   0x04
  97# define DP_I2C_SPEED_100K                  0x08
  98# define DP_I2C_SPEED_400K                  0x10
  99# define DP_I2C_SPEED_1M                    0x20
 100
 101#define DP_EDP_CONFIGURATION_CAP            0x00d   /* XXX 1.2? */
 102#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
 103
 104/* Multiple stream transport */
 105#define DP_MSTM_CAP                         0x021   /* 1.2 */
 106# define DP_MST_CAP                         (1 << 0)
 107
 108#define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
 109# define DP_PSR_IS_SUPPORTED                1
 110#define DP_PSR_CAPS                         0x071   /* XXX 1.2? */
 111# define DP_PSR_NO_TRAIN_ON_EXIT            1
 112# define DP_PSR_SETUP_TIME_330              (0 << 1)
 113# define DP_PSR_SETUP_TIME_275              (1 << 1)
 114# define DP_PSR_SETUP_TIME_220              (2 << 1)
 115# define DP_PSR_SETUP_TIME_165              (3 << 1)
 116# define DP_PSR_SETUP_TIME_110              (4 << 1)
 117# define DP_PSR_SETUP_TIME_55               (5 << 1)
 118# define DP_PSR_SETUP_TIME_0                (6 << 1)
 119# define DP_PSR_SETUP_TIME_MASK             (7 << 1)
 120# define DP_PSR_SETUP_TIME_SHIFT            1
 121
 122/*
 123 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
 124 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set.  If it was not,
 125 * each port's descriptor is one byte wide.  If it was set, each port's is
 126 * four bytes wide, starting with the one byte from the base info.  As of
 127 * DP interop v1.1a only VGA defines additional detail.
 128 */
 129
 130/* offset 0 */
 131#define DP_DOWNSTREAM_PORT_0                0x80
 132# define DP_DS_PORT_TYPE_MASK               (7 << 0)
 133# define DP_DS_PORT_TYPE_DP                 0
 134# define DP_DS_PORT_TYPE_VGA                1
 135# define DP_DS_PORT_TYPE_DVI                2
 136# define DP_DS_PORT_TYPE_HDMI               3
 137# define DP_DS_PORT_TYPE_NON_EDID           4
 138# define DP_DS_PORT_HPD                     (1 << 3)
 139/* offset 1 for VGA is maximum megapixels per second / 8 */
 140/* offset 2 */
 141# define DP_DS_VGA_MAX_BPC_MASK             (3 << 0)
 142# define DP_DS_VGA_8BPC                     0
 143# define DP_DS_VGA_10BPC                    1
 144# define DP_DS_VGA_12BPC                    2
 145# define DP_DS_VGA_16BPC                    3
 146
 147/* link configuration */
 148#define DP_LINK_BW_SET                      0x100
 149# define DP_LINK_BW_1_62                    0x06
 150# define DP_LINK_BW_2_7                     0x0a
 151# define DP_LINK_BW_5_4                     0x14    /* 1.2 */
 152
 153#define DP_LANE_COUNT_SET                   0x101
 154# define DP_LANE_COUNT_MASK                 0x0f
 155# define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
 156
 157#define DP_TRAINING_PATTERN_SET             0x102
 158# define DP_TRAINING_PATTERN_DISABLE        0
 159# define DP_TRAINING_PATTERN_1              1
 160# define DP_TRAINING_PATTERN_2              2
 161# define DP_TRAINING_PATTERN_3              3       /* 1.2 */
 162# define DP_TRAINING_PATTERN_MASK           0x3
 163
 164# define DP_LINK_QUAL_PATTERN_DISABLE       (0 << 2)
 165# define DP_LINK_QUAL_PATTERN_D10_2         (1 << 2)
 166# define DP_LINK_QUAL_PATTERN_ERROR_RATE    (2 << 2)
 167# define DP_LINK_QUAL_PATTERN_PRBS7         (3 << 2)
 168# define DP_LINK_QUAL_PATTERN_MASK          (3 << 2)
 169
 170# define DP_RECOVERED_CLOCK_OUT_EN          (1 << 4)
 171# define DP_LINK_SCRAMBLING_DISABLE         (1 << 5)
 172
 173# define DP_SYMBOL_ERROR_COUNT_BOTH         (0 << 6)
 174# define DP_SYMBOL_ERROR_COUNT_DISPARITY    (1 << 6)
 175# define DP_SYMBOL_ERROR_COUNT_SYMBOL       (2 << 6)
 176# define DP_SYMBOL_ERROR_COUNT_MASK         (3 << 6)
 177
 178#define DP_TRAINING_LANE0_SET               0x103
 179#define DP_TRAINING_LANE1_SET               0x104
 180#define DP_TRAINING_LANE2_SET               0x105
 181#define DP_TRAINING_LANE3_SET               0x106
 182
 183# define DP_TRAIN_VOLTAGE_SWING_MASK        0x3
 184# define DP_TRAIN_VOLTAGE_SWING_SHIFT       0
 185# define DP_TRAIN_MAX_SWING_REACHED         (1 << 2)
 186# define DP_TRAIN_VOLTAGE_SWING_400         (0 << 0)
 187# define DP_TRAIN_VOLTAGE_SWING_600         (1 << 0)
 188# define DP_TRAIN_VOLTAGE_SWING_800         (2 << 0)
 189# define DP_TRAIN_VOLTAGE_SWING_1200        (3 << 0)
 190
 191# define DP_TRAIN_PRE_EMPHASIS_MASK         (3 << 3)
 192# define DP_TRAIN_PRE_EMPHASIS_0            (0 << 3)
 193# define DP_TRAIN_PRE_EMPHASIS_3_5          (1 << 3)
 194# define DP_TRAIN_PRE_EMPHASIS_6            (2 << 3)
 195# define DP_TRAIN_PRE_EMPHASIS_9_5          (3 << 3)
 196
 197# define DP_TRAIN_PRE_EMPHASIS_SHIFT        3
 198# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
 199
 200#define DP_DOWNSPREAD_CTRL                  0x107
 201# define DP_SPREAD_AMP_0_5                  (1 << 4)
 202# define DP_MSA_TIMING_PAR_IGNORE_EN        (1 << 7) /* eDP */
 203
 204#define DP_MAIN_LINK_CHANNEL_CODING_SET     0x108
 205# define DP_SET_ANSI_8B10B                  (1 << 0)
 206
 207#define DP_I2C_SPEED_CONTROL_STATUS         0x109   /* DPI */
 208/* bitmask as for DP_I2C_SPEED_CAP */
 209
 210#define DP_EDP_CONFIGURATION_SET            0x10a   /* XXX 1.2? */
 211
 212#define DP_MSTM_CTRL                        0x111   /* 1.2 */
 213# define DP_MST_EN                          (1 << 0)
 214# define DP_UP_REQ_EN                       (1 << 1)
 215# define DP_UPSTREAM_IS_SRC                 (1 << 2)
 216
 217#define DP_PSR_EN_CFG                       0x170   /* XXX 1.2? */
 218# define DP_PSR_ENABLE                      (1 << 0)
 219# define DP_PSR_MAIN_LINK_ACTIVE            (1 << 1)
 220# define DP_PSR_CRC_VERIFICATION            (1 << 2)
 221# define DP_PSR_FRAME_CAPTURE               (1 << 3)
 222
 223#define DP_SINK_COUNT                       0x200
 224/* prior to 1.2 bit 7 was reserved mbz */
 225# define DP_GET_SINK_COUNT(x)               ((((x) & 0x80) >> 1) | ((x) & 0x3f))
 226# define DP_SINK_CP_READY                   (1 << 6)
 227
 228#define DP_DEVICE_SERVICE_IRQ_VECTOR        0x201
 229# define DP_REMOTE_CONTROL_COMMAND_PENDING  (1 << 0)
 230# define DP_AUTOMATED_TEST_REQUEST          (1 << 1)
 231# define DP_CP_IRQ                          (1 << 2)
 232# define DP_SINK_SPECIFIC_IRQ               (1 << 6)
 233
 234#define DP_LANE0_1_STATUS                   0x202
 235#define DP_LANE2_3_STATUS                   0x203
 236# define DP_LANE_CR_DONE                    (1 << 0)
 237# define DP_LANE_CHANNEL_EQ_DONE            (1 << 1)
 238# define DP_LANE_SYMBOL_LOCKED              (1 << 2)
 239
 240#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |           \
 241                            DP_LANE_CHANNEL_EQ_DONE |   \
 242                            DP_LANE_SYMBOL_LOCKED)
 243
 244#define DP_LANE_ALIGN_STATUS_UPDATED        0x204
 245
 246#define DP_INTERLANE_ALIGN_DONE             (1 << 0)
 247#define DP_DOWNSTREAM_PORT_STATUS_CHANGED   (1 << 6)
 248#define DP_LINK_STATUS_UPDATED              (1 << 7)
 249
 250#define DP_SINK_STATUS                      0x205
 251
 252#define DP_RECEIVE_PORT_0_STATUS            (1 << 0)
 253#define DP_RECEIVE_PORT_1_STATUS            (1 << 1)
 254
 255#define DP_ADJUST_REQUEST_LANE0_1           0x206
 256#define DP_ADJUST_REQUEST_LANE2_3           0x207
 257# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK  0x03
 258# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
 259# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK   0x0c
 260# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT  2
 261# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK  0x30
 262# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
 263# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
 264# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
 265
 266#define DP_TEST_REQUEST                     0x218
 267# define DP_TEST_LINK_TRAINING              (1 << 0)
 268# define DP_TEST_LINK_PATTERN               (1 << 1)
 269# define DP_TEST_LINK_EDID_READ             (1 << 2)
 270# define DP_TEST_LINK_PHY_TEST_PATTERN      (1 << 3) /* DPCD >= 1.1 */
 271
 272#define DP_TEST_LINK_RATE                   0x219
 273# define DP_LINK_RATE_162                   (0x6)
 274# define DP_LINK_RATE_27                    (0xa)
 275
 276#define DP_TEST_LANE_COUNT                  0x220
 277
 278#define DP_TEST_PATTERN                     0x221
 279
 280#define DP_TEST_RESPONSE                    0x260
 281# define DP_TEST_ACK                        (1 << 0)
 282# define DP_TEST_NAK                        (1 << 1)
 283# define DP_TEST_EDID_CHECKSUM_WRITE        (1 << 2)
 284
 285#define DP_SOURCE_OUI                       0x300
 286#define DP_SINK_OUI                         0x400
 287#define DP_BRANCH_OUI                       0x500
 288
 289#define DP_SET_POWER                        0x600
 290# define DP_SET_POWER_D0                    0x1
 291# define DP_SET_POWER_D3                    0x2
 292
 293#define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
 294# define DP_PSR_LINK_CRC_ERROR              (1 << 0)
 295# define DP_PSR_RFB_STORAGE_ERROR           (1 << 1)
 296
 297#define DP_PSR_ESI                          0x2007  /* XXX 1.2? */
 298# define DP_PSR_CAPS_CHANGE                 (1 << 0)
 299
 300#define DP_PSR_STATUS                       0x2008  /* XXX 1.2? */
 301# define DP_PSR_SINK_INACTIVE               0
 302# define DP_PSR_SINK_ACTIVE_SRC_SYNCED      1
 303# define DP_PSR_SINK_ACTIVE_RFB             2
 304# define DP_PSR_SINK_ACTIVE_SINK_SYNCED     3
 305# define DP_PSR_SINK_ACTIVE_RESYNC          4
 306# define DP_PSR_SINK_INTERNAL_ERROR         7
 307# define DP_PSR_SINK_STATE_MASK             0x07
 308
 309#define MODE_I2C_START  1
 310#define MODE_I2C_WRITE  2
 311#define MODE_I2C_READ   4
 312#define MODE_I2C_STOP   8
 313
 314struct i2c_algo_dp_aux_data {
 315        bool running;
 316        u16 address;
 317        int (*aux_ch) (struct i2c_adapter *adapter,
 318                       int mode, uint8_t write_byte,
 319                       uint8_t *read_byte);
 320};
 321
 322int
 323i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
 324
 325#endif /* _DRM_DP_HELPER_H_ */
 326
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