linux/drivers/video/cirrusfb.c
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   1/*
   2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
   3 *
   4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
   5 *
   6 * Contributors (thanks, all!)
   7 *
   8 *      David Eger:
   9 *      Overhaul for Linux 2.6
  10 *
  11 *      Jeff Rugen:
  12 *      Major contributions;  Motorola PowerStack (PPC and PCI) support,
  13 *      GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
  14 *
  15 *      Geert Uytterhoeven:
  16 *      Excellent code review.
  17 *
  18 *      Lars Hecking:
  19 *      Amiga updates and testing.
  20 *
  21 * Original cirrusfb author:  Frank Neumann
  22 *
  23 * Based on retz3fb.c and cirrusfb.c:
  24 *      Copyright (C) 1997 Jes Sorensen
  25 *      Copyright (C) 1996 Frank Neumann
  26 *
  27 ***************************************************************
  28 *
  29 * Format this code with GNU indent '-kr -i8 -pcs' options.
  30 *
  31 * This file is subject to the terms and conditions of the GNU General Public
  32 * License.  See the file COPYING in the main directory of this archive
  33 * for more details.
  34 *
  35 */
  36
  37#include <linux/module.h>
  38#include <linux/kernel.h>
  39#include <linux/errno.h>
  40#include <linux/string.h>
  41#include <linux/mm.h>
  42#include <linux/delay.h>
  43#include <linux/fb.h>
  44#include <linux/init.h>
  45#include <asm/pgtable.h>
  46
  47#ifdef CONFIG_ZORRO
  48#include <linux/zorro.h>
  49#endif
  50#ifdef CONFIG_PCI
  51#include <linux/pci.h>
  52#endif
  53#ifdef CONFIG_AMIGA
  54#include <asm/amigahw.h>
  55#endif
  56#ifdef CONFIG_PPC_PREP
  57#include <asm/machdep.h>
  58#define isPReP machine_is(prep)
  59#else
  60#define isPReP 0
  61#endif
  62
  63#include <video/vga.h>
  64#include <video/cirrus.h>
  65
  66/*****************************************************************
  67 *
  68 * debugging and utility macros
  69 *
  70 */
  71
  72/* disable runtime assertions? */
  73/* #define CIRRUSFB_NDEBUG */
  74
  75/* debugging assertions */
  76#ifndef CIRRUSFB_NDEBUG
  77#define assert(expr) \
  78        if (!(expr)) { \
  79                printk("Assertion failed! %s,%s,%s,line=%d\n", \
  80                #expr, __FILE__, __func__, __LINE__); \
  81        }
  82#else
  83#define assert(expr)
  84#endif
  85
  86#define MB_ (1024 * 1024)
  87
  88/*****************************************************************
  89 *
  90 * chipset information
  91 *
  92 */
  93
  94/* board types */
  95enum cirrus_board {
  96        BT_NONE = 0,
  97        BT_SD64,        /* GD5434 */
  98        BT_PICCOLO,     /* GD5426 */
  99        BT_PICASSO,     /* GD5426 or GD5428 */
 100        BT_SPECTRUM,    /* GD5426 or GD5428 */
 101        BT_PICASSO4,    /* GD5446 */
 102        BT_ALPINE,      /* GD543x/4x */
 103        BT_GD5480,
 104        BT_LAGUNA,      /* GD5462/64 */
 105        BT_LAGUNAB,     /* GD5465 */
 106};
 107
 108/*
 109 * per-board-type information, used for enumerating and abstracting
 110 * chip-specific information
 111 * NOTE: MUST be in the same order as enum cirrus_board in order to
 112 * use direct indexing on this array
 113 * NOTE: '__initdata' cannot be used as some of this info
 114 * is required at runtime.  Maybe separate into an init-only and
 115 * a run-time table?
 116 */
 117static const struct cirrusfb_board_info_rec {
 118        char *name;             /* ASCII name of chipset */
 119        long maxclock[5];               /* maximum video clock */
 120        /* for  1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
 121        bool init_sr07 : 1; /* init SR07 during init_vgachip() */
 122        bool init_sr1f : 1; /* write SR1F during init_vgachip() */
 123        /* construct bit 19 of screen start address */
 124        bool scrn_start_bit19 : 1;
 125
 126        /* initial SR07 value, then for each mode */
 127        unsigned char sr07;
 128        unsigned char sr07_1bpp;
 129        unsigned char sr07_1bpp_mux;
 130        unsigned char sr07_8bpp;
 131        unsigned char sr07_8bpp_mux;
 132
 133        unsigned char sr1f;     /* SR1F VGA initial register value */
 134} cirrusfb_board_info[] = {
 135        [BT_SD64] = {
 136                .name                   = "CL SD64",
 137                .maxclock               = {
 138                        /* guess */
 139                        /* the SD64/P4 have a higher max. videoclock */
 140                        135100, 135100, 85500, 85500, 0
 141                },
 142                .init_sr07              = true,
 143                .init_sr1f              = true,
 144                .scrn_start_bit19       = true,
 145                .sr07                   = 0xF0,
 146                .sr07_1bpp              = 0xF0,
 147                .sr07_1bpp_mux          = 0xF6,
 148                .sr07_8bpp              = 0xF1,
 149                .sr07_8bpp_mux          = 0xF7,
 150                .sr1f                   = 0x1E
 151        },
 152        [BT_PICCOLO] = {
 153                .name                   = "CL Piccolo",
 154                .maxclock               = {
 155                        /* guess */
 156                        90000, 90000, 90000, 90000, 90000
 157                },
 158                .init_sr07              = true,
 159                .init_sr1f              = true,
 160                .scrn_start_bit19       = false,
 161                .sr07                   = 0x80,
 162                .sr07_1bpp              = 0x80,
 163                .sr07_8bpp              = 0x81,
 164                .sr1f                   = 0x22
 165        },
 166        [BT_PICASSO] = {
 167                .name                   = "CL Picasso",
 168                .maxclock               = {
 169                        /* guess */
 170                        90000, 90000, 90000, 90000, 90000
 171                },
 172                .init_sr07              = true,
 173                .init_sr1f              = true,
 174                .scrn_start_bit19       = false,
 175                .sr07                   = 0x20,
 176                .sr07_1bpp              = 0x20,
 177                .sr07_8bpp              = 0x21,
 178                .sr1f                   = 0x22
 179        },
 180        [BT_SPECTRUM] = {
 181                .name                   = "CL Spectrum",
 182                .maxclock               = {
 183                        /* guess */
 184                        90000, 90000, 90000, 90000, 90000
 185                },
 186                .init_sr07              = true,
 187                .init_sr1f              = true,
 188                .scrn_start_bit19       = false,
 189                .sr07                   = 0x80,
 190                .sr07_1bpp              = 0x80,
 191                .sr07_8bpp              = 0x81,
 192                .sr1f                   = 0x22
 193        },
 194        [BT_PICASSO4] = {
 195                .name                   = "CL Picasso4",
 196                .maxclock               = {
 197                        135100, 135100, 85500, 85500, 0
 198                },
 199                .init_sr07              = true,
 200                .init_sr1f              = false,
 201                .scrn_start_bit19       = true,
 202                .sr07                   = 0xA0,
 203                .sr07_1bpp              = 0xA0,
 204                .sr07_1bpp_mux          = 0xA6,
 205                .sr07_8bpp              = 0xA1,
 206                .sr07_8bpp_mux          = 0xA7,
 207                .sr1f                   = 0
 208        },
 209        [BT_ALPINE] = {
 210                .name                   = "CL Alpine",
 211                .maxclock               = {
 212                        /* for the GD5430.  GD5446 can do more... */
 213                        85500, 85500, 50000, 28500, 0
 214                },
 215                .init_sr07              = true,
 216                .init_sr1f              = true,
 217                .scrn_start_bit19       = true,
 218                .sr07                   = 0xA0,
 219                .sr07_1bpp              = 0xA0,
 220                .sr07_1bpp_mux          = 0xA6,
 221                .sr07_8bpp              = 0xA1,
 222                .sr07_8bpp_mux          = 0xA7,
 223                .sr1f                   = 0x1C
 224        },
 225        [BT_GD5480] = {
 226                .name                   = "CL GD5480",
 227                .maxclock               = {
 228                        135100, 200000, 200000, 135100, 135100
 229                },
 230                .init_sr07              = true,
 231                .init_sr1f              = true,
 232                .scrn_start_bit19       = true,
 233                .sr07                   = 0x10,
 234                .sr07_1bpp              = 0x11,
 235                .sr07_8bpp              = 0x11,
 236                .sr1f                   = 0x1C
 237        },
 238        [BT_LAGUNA] = {
 239                .name                   = "CL Laguna",
 240                .maxclock               = {
 241                        /* taken from X11 code */
 242                        170000, 170000, 170000, 170000, 135100,
 243                },
 244                .init_sr07              = false,
 245                .init_sr1f              = false,
 246                .scrn_start_bit19       = true,
 247        },
 248        [BT_LAGUNAB] = {
 249                .name                   = "CL Laguna AGP",
 250                .maxclock               = {
 251                        /* taken from X11 code */
 252                        170000, 250000, 170000, 170000, 135100,
 253                },
 254                .init_sr07              = false,
 255                .init_sr1f              = false,
 256                .scrn_start_bit19       = true,
 257        }
 258};
 259
 260#ifdef CONFIG_PCI
 261#define CHIP(id, btype) \
 262        { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
 263
 264static struct pci_device_id cirrusfb_pci_table[] = {
 265        CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
 266        CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_SD64),
 267        CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_SD64),
 268        CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
 269        CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
 270        CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
 271        CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
 272        CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
 273        CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
 274        CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
 275        CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/
 276        { 0, }
 277};
 278MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
 279#undef CHIP
 280#endif /* CONFIG_PCI */
 281
 282#ifdef CONFIG_ZORRO
 283struct zorrocl {
 284        enum cirrus_board type; /* Board type */
 285        u32 regoffset;          /* Offset of registers in first Zorro device */
 286        u32 ramsize;            /* Size of video RAM in first Zorro device */
 287                                /* If zero, use autoprobe on RAM device */
 288        u32 ramoffset;          /* Offset of video RAM in first Zorro device */
 289        zorro_id ramid;         /* Zorro ID of RAM device */
 290        zorro_id ramid2;        /* Zorro ID of optional second RAM device */
 291};
 292
 293static const struct zorrocl zcl_sd64 __devinitconst = {
 294        .type           = BT_SD64,
 295        .ramid          = ZORRO_PROD_HELFRICH_SD64_RAM,
 296};
 297
 298static const struct zorrocl zcl_piccolo __devinitconst = {
 299        .type           = BT_PICCOLO,
 300        .ramid          = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
 301};
 302
 303static const struct zorrocl zcl_picasso __devinitconst = {
 304        .type           = BT_PICASSO,
 305        .ramid          = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
 306};
 307
 308static const struct zorrocl zcl_spectrum __devinitconst = {
 309        .type           = BT_SPECTRUM,
 310        .ramid          = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
 311};
 312
 313static const struct zorrocl zcl_picasso4_z3 __devinitconst = {
 314        .type           = BT_PICASSO4,
 315        .regoffset      = 0x00600000,
 316        .ramsize        = 4 * MB_,
 317        .ramoffset      = 0x01000000,   /* 0x02000000 for 64 MiB boards */
 318};
 319
 320static const struct zorrocl zcl_picasso4_z2 __devinitconst = {
 321        .type           = BT_PICASSO4,
 322        .regoffset      = 0x10000,
 323        .ramid          = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM1,
 324        .ramid2         = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM2,
 325};
 326
 327
 328static const struct zorro_device_id cirrusfb_zorro_table[] __devinitconst = {
 329        {
 330                .id             = ZORRO_PROD_HELFRICH_SD64_REG,
 331                .driver_data    = (unsigned long)&zcl_sd64,
 332        }, {
 333                .id             = ZORRO_PROD_HELFRICH_PICCOLO_REG,
 334                .driver_data    = (unsigned long)&zcl_piccolo,
 335        }, {
 336                .id     = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
 337                .driver_data    = (unsigned long)&zcl_picasso,
 338        }, {
 339                .id             = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
 340                .driver_data    = (unsigned long)&zcl_spectrum,
 341        }, {
 342                .id             = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
 343                .driver_data    = (unsigned long)&zcl_picasso4_z3,
 344        }, {
 345                .id             = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_REG,
 346                .driver_data    = (unsigned long)&zcl_picasso4_z2,
 347        },
 348        { 0 }
 349};
 350MODULE_DEVICE_TABLE(zorro, cirrusfb_zorro_table);
 351#endif /* CONFIG_ZORRO */
 352
 353#ifdef CIRRUSFB_DEBUG
 354enum cirrusfb_dbg_reg_class {
 355        CRT,
 356        SEQ
 357};
 358#endif          /* CIRRUSFB_DEBUG */
 359
 360/* info about board */
 361struct cirrusfb_info {
 362        u8 __iomem *regbase;
 363        u8 __iomem *laguna_mmio;
 364        enum cirrus_board btype;
 365        unsigned char SFR;      /* Shadow of special function register */
 366
 367        int multiplexing;
 368        int doubleVCLK;
 369        int blank_mode;
 370        u32 pseudo_palette[16];
 371
 372        void (*unmap)(struct fb_info *info);
 373};
 374
 375static bool noaccel __devinitdata;
 376static char *mode_option __devinitdata = "640x480@60";
 377
 378/****************************************************************************/
 379/**** BEGIN PROTOTYPES ******************************************************/
 380
 381/*--- Interface used by the world ------------------------------------------*/
 382static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
 383                                struct fb_info *info);
 384
 385/*--- Internal routines ----------------------------------------------------*/
 386static void init_vgachip(struct fb_info *info);
 387static void switch_monitor(struct cirrusfb_info *cinfo, int on);
 388static void WGen(const struct cirrusfb_info *cinfo,
 389                 int regnum, unsigned char val);
 390static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
 391static void AttrOn(const struct cirrusfb_info *cinfo);
 392static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
 393static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
 394static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
 395static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
 396                  unsigned char red, unsigned char green, unsigned char blue);
 397#if 0
 398static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
 399                  unsigned char *red, unsigned char *green,
 400                  unsigned char *blue);
 401#endif
 402static void cirrusfb_WaitBLT(u8 __iomem *regbase);
 403static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
 404                            u_short curx, u_short cury,
 405                            u_short destx, u_short desty,
 406                            u_short width, u_short height,
 407                            u_short line_length);
 408static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
 409                              u_short x, u_short y,
 410                              u_short width, u_short height,
 411                              u32 fg_color, u32 bg_color,
 412                              u_short line_length, u_char blitmode);
 413
 414static void bestclock(long freq, int *nom, int *den, int *div);
 415
 416#ifdef CIRRUSFB_DEBUG
 417static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
 418static void cirrusfb_dbg_print_regs(struct fb_info *info,
 419                                    caddr_t regbase,
 420                                    enum cirrusfb_dbg_reg_class reg_class, ...);
 421#endif /* CIRRUSFB_DEBUG */
 422
 423/*** END   PROTOTYPES ********************************************************/
 424/*****************************************************************************/
 425/*** BEGIN Interface Used by the World ***************************************/
 426
 427static inline int is_laguna(const struct cirrusfb_info *cinfo)
 428{
 429        return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
 430}
 431
 432static int opencount;
 433
 434/*--- Open /dev/fbx ---------------------------------------------------------*/
 435static int cirrusfb_open(struct fb_info *info, int user)
 436{
 437        if (opencount++ == 0)
 438                switch_monitor(info->par, 1);
 439        return 0;
 440}
 441
 442/*--- Close /dev/fbx --------------------------------------------------------*/
 443static int cirrusfb_release(struct fb_info *info, int user)
 444{
 445        if (--opencount == 0)
 446                switch_monitor(info->par, 0);
 447        return 0;
 448}
 449
 450/**** END   Interface used by the World *************************************/
 451/****************************************************************************/
 452/**** BEGIN Hardware specific Routines **************************************/
 453
 454/* Check if the MCLK is not a better clock source */
 455static int cirrusfb_check_mclk(struct fb_info *info, long freq)
 456{
 457        struct cirrusfb_info *cinfo = info->par;
 458        long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
 459
 460        /* Read MCLK value */
 461        mclk = (14318 * mclk) >> 3;
 462        dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk);
 463
 464        /* Determine if we should use MCLK instead of VCLK, and if so, what we
 465         * should divide it by to get VCLK
 466         */
 467
 468        if (abs(freq - mclk) < 250) {
 469                dev_dbg(info->device, "Using VCLK = MCLK\n");
 470                return 1;
 471        } else if (abs(freq - (mclk / 2)) < 250) {
 472                dev_dbg(info->device, "Using VCLK = MCLK/2\n");
 473                return 2;
 474        }
 475
 476        return 0;
 477}
 478
 479static int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var,
 480                                   struct fb_info *info)
 481{
 482        long freq;
 483        long maxclock;
 484        struct cirrusfb_info *cinfo = info->par;
 485        unsigned maxclockidx = var->bits_per_pixel >> 3;
 486
 487        /* convert from ps to kHz */
 488        freq = PICOS2KHZ(var->pixclock);
 489
 490        dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
 491
 492        maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
 493        cinfo->multiplexing = 0;
 494
 495        /* If the frequency is greater than we can support, we might be able
 496         * to use multiplexing for the video mode */
 497        if (freq > maxclock) {
 498                dev_err(info->device,
 499                        "Frequency greater than maxclock (%ld kHz)\n",
 500                        maxclock);
 501                return -EINVAL;
 " class="f="drivers/video/cirrusfb.c#L408" f VCLK, and i1b.c#Lclass55ass="503e" name="L495"> 495        
 454
 465
 466         */
 497        > = var->== 8"sref">maxclock) {
 498 497        /a>[cinfo->maxclock) {
 409cinfo-BT_ALPINEa href="+code=bBT_ALPINEe" n:ef">maxclock) {
 410cinfo-BT_SDusfb.c#L464code=bBT_SDuse" n:ef">maxclock) {
 411cinfo-BT_ROD_VILsfb.c#L464code=bBT_ROD_VILse" n:ef">maxclock) {
 412     7"> 497        if (info)
 383             3"> 493        cinfo->            return 1;
 404     b">&k           return 1;
 405cinfo-BT_GD5rusfb.c#L480code=bBT_GD5ruse" n:ef">maxclock) {
 406     7"> 497        if (info)
 407             3"> 493        cinfo->            return 1;
 498     b">&k           return 1;
 489
 420maxclock) {
 411     b">&k           return 1;
 412<2"> " class="f="drivers/video/cirrusfbvideo/cir5usfb.c#L423" id="L423" c5ass="52ne" name="L382"> " class="f="drivers/video/cirrusfbvideo/cir5usfb.c#L424" id="L424" c5ass="52ne" name="L494"> 494
 495        
 496         */
 493        cinfo-int multiplexing = 0;
 468         || cinfo->btype ==SDusfb.c#L464code=bBT_SDuse" nref">Cef">CL"sref">dev_err(info-fif="+code=maxclocfif" cls="sref">btypebtypeMB_="+code=maxclocMB_e" nref">Cef">Cltiplexing = 0;
 497        > = var->== 16"sref">maxclock) {
 420<7"> 493        cinfo-int             return 1;
 " class="f="drivers/video/cirrusfbvideo/cir5usfb.c#L432" id="L432" c5ass="53ne" name="L422"> 422
 476        return 0;
 " class="f="drivers/video/cirrusfbvideo/cir5usfb.c#L435" id="L435" c5ass="53ne" name="L475"> 475
 479static int fb_var_screeninfo *var,
 407                              struct fb_info *info)
 428{
 369        yre (EINVAL;
 460                 */
 485        unsigss="ssref="+code=pixcloc"ss class="sref">cinfo = info-lass="_size="+code=maxclocsass="_sizelass=" 8 / 497        > = var->EINVAL;
 484        struct cirrusfb_info *cinfo = info->par;
 463
 497        > = var->maxclock) {
maxclock) {
 446            > = var-ar *btypemultiplexing = 0;
 407            > = var-ar *btype            return 1;
 498            > = var-ar *maxclockidx = var-ar * 469            > = var-&r *maxclockidx = var-ar * 420&k           return 1;
 491
maxclock) {
 383            > = var-ar *btypemultiplexing = 0;
 404            > = var-ar *btype8ultiplexing = 0;
 405            > = var-ar *maxclockidx = var-ar * 446            > = var-&r *maxclockidx = var-ar * 407&k           return 1;
 478
maxclock) {
 420<8"> 468        isPRePmaxclock) {
 411     /a>            > = var-ar *btype            return 2;
 412     /a>            > = var-ar *btype-pixel >> 3;
 383     /a>            > = var-&r *btype8ultiplexing = 0;
 404<1"> 471ref">maxclock) {
 405     /a>            > = var-ar *btype1            return 1;
 406     /a>            > = var-ar *btype5           return 1;
 407     /a>            > = var-&r *btypemultiplexing = 0;
 498<2"> " class="f="drivers/video/cirrusfbvideo/cir5usfb.c#L469" id="L469" c5ass="5ine" name="L469"> 469            > = var-ar *btype5           return 1;
 470            > = var-ar *btype6           return 1;
 411            > = var-&r *btype5           return 1;
 472&k           return 1;
 463
maxclock) {
 405<8"> 468        isPRePmaxclock) {
 406     /a>            > = var-ar *btypemultiplexing = 0;
 407     /a>            > = var-ar *btype8ultiplexing = 0;
 498     /a>            > = var-&r *btype16           return 1;
 469<1"> 471ref">maxclock) {
 480     /a>            > = var-ar *btype16           return 1;
 411     /a>            > = var-ar *btype8ultiplexing = 0;
 412     /a>            > = var-&r *btypemultiplexing = 0;
 383<2"> " class="f="drivers/video/cirrusfbvideo/cir5usfb.c#L484" id="L484" c5ass="58ne" name="L404"> 404            > = var-ar *btype8ultiplexing = 0;
 405            > = var-ar *btype8ultiplexing = 0;
 446            > = var-&r *btype8ultiplexing = 0;
 407&k           return 1;
 478
maxclock) {
 470                dev_dbg(info->maxclock) {
 411     /sref">device,  = var-> 412                return -EINVAL;
 " class="f="drivers/video/cirrusfbvideo/cir5usfb.c#L494" id="L494" c5ass="5ine" name="L494"> 494
 497        > = var-xres_virtua+code=bits_per_pxres_virtua+e" naef">m497        > = var-xrescode=bits_per_pxresref""ame="L494"> 494
 446            > = var-xres_virtua+code=bits_per_pxres_virtua+e" naf">maxclockidx = var-xrescode=bits_per_pxresref"s="sref">EINVAL;
 487                 */
 468        > = var-yres_virtua+code=bits_per_pyres_virtua+e" naf= -1"sref">maxclock) {
 499<468        > = var-yres_virtua+code=bits_per_pyres_virtua+e" naf/a>        unsigss="ssref="+code=pixcloc"ss clas/ 497        > = var-xres_virtua+code=bits_per_pxres_virtua+e" ns="sref">EINVAL;
EINVAL;
 501                /a>(dev_dbg(info->maxclock) {
 412      /sref">device, "dx;desidxclock: %ld ef">maxclock) {
 383      497        > = var-xres_virtua+code=bits_per_pxres_virtua+e" n kHz\n" = var-yres_virtua+code=bits_per_pyres_virtua+e" n"           return 1;
 474        }
 497        > = var-yres_virtua+code=bits_per_pyres_virtua+e" naef">m497        > = var-yre ( 494
 446            > = var-yres_virtua+code=bits_per_pyres_virtua+e" naf/a>        unsig> = var-yre ( 467
 468        > = var-xres_virtua+code=bits_per_pxres_virtua+e" na>mclk = (1431> = var-yres_virtua+code=bits_per_pyres_virtua+e" naes="sref">freq &ss="ssref="+code=pixcloc"ss cla"sref">maxclock) {
 409                dev_err(info->device, maxclock) {
 410<      /sref">device, oultiplexemory!xclock: %ld ef">maxclock) {
 411      497        > = var-xres_virtua+code=bits_per_pxres_virtua+e" n kHz\n" = var-yres_virtua+code=bits_per_pyres_virtua+e" n ef">maxclock) {
 412     Hz\n" = var-> 383                return -EINVAL;
 474        }
 475
 468        > = var-xoffseref="+code=opencxoffsers="sfef">mnass="sref">info)
 407<468        > = var-xoffseref="+code=opencxoffsers="sf">multiplexing = 0;
 468        > = var-yoffseref="+code=opencyoffsers="sfef">mnass="sref">info)
 499<468        > = var-yoffseref="+code=opencyoffsers="sf">multiplexing = 0;
EINVAL;
 487                 */
 468        > = var-xoffseref="+code=opencxoffsers="sfes="sref">freq &> = var-xres_virtua+code=bits_per_pxres_virtua+e" nass="sref">freq = var-xrescode=bits_per_pxresref""ame="L494"> 494
 383            > = var-xoffseref="+code=opencxoffsers="sf">ref">freq &> = var-xres_virtua+code=bits_per_pxres_virtua+e" nass="sref">freq = var-xrescode=bits_per_pxresref"ass            return 1;
 468        > = var-yoffseref="+code=opencyoffsers="sfes="sref">freq &> = var-yres_virtua+code=bits_per_pyres_virtua+e" nass="sref">freq = var-yre ( 494
 405            > = var-yoffseref="+code=opencyoffsers="sf">ref">freq &> = var-yres_virtua+code=bits_per_pyres_virtua+e" nass="sref">freq = var-yre ( 486
 493    > = var-ar *btype 486
 7"> 493    > = var-ar *btype 486
 497        > = var-&r *btype 486
 497        > = var-transp btype 486
 497        > = var-transp btype 486
 497        > = var-transp btypemultiplexing = 0;
 463
 493    yre (var-yre ( 497        > = var-vxing CL"sref">dev_err 494
 446            yre (            return 2;
var-vxing CL"sref">dev_err 494
 498            yre ( 489
 / 2)) < 250) {
 501                dev_err(info->device, maxclock) {
 412     Hsref">device, &q   < ss="="st! (TODOxclock (%ld "           return 1;
 383                return -EINVAL;
 474        }
 475
 468        int cirrusfb_        } else > =  * 494
 407                return -EINVAL;
 478
 !Hz\n" 494
 420<        } else > = var-accel_flag (EINVAL;
 491
 476        return 0;
 474        }
 494
fb_info * 369        div href="+code=devivclas"ame="L494"> 494
 / 2)) < 250) {
 484        struct cirrusfb_info *cinfo = info->par;
 485cinfopar;
 489
 490    #L4ert(cinfopar;
cinfo        unsig>ga_rs (var-argbasa href="+code=deargbasar" c kHz\n"CL~0x4        return 0;
 422
 468        div href="+code=devivclas"/a> / 2)) < 250) {
 404                dev_dbg(info->device, cirr sourmaxclock) {
 405      468        div href="+code=devivclasaf= 2) ? Hsref">device, device,  406<"sref">cinfo        return 0;
 407        unsig>ga_rs (var-argbasa href="+code=deargbasar" c kHz\n"CL~0x            return 1;
 498<8"> 468        div href="+code=devivclasaf= 2)          return 1;
 469<7"> 407            return 1;
EINVAL;
 411            >ga_ws (var-argbasa href="+code=deargbasar" c kHz\n" 474        }
ga_ws (usfb_        } else a> *var-argbasa href="+code=deargbasar" c kHz\n" " class="f="drivers/video/cirrusf6video/cir6usfb.c#L475" id="L475" c6ass="67ne" name="L475"> 475
 496maxclock) {
 496maxclock) {
 478
 496ouoheshardware,%ldef">maxclock) {
 496         */
 479static int fb_info *info)
 / 2)) < 250) {
 484        struct cirrusfb_info *cinfo = info->par;
fb_var_screeninfo *C"sref">cinfo = info-a> *par;
info-u8*info-__iomem*fb_var_screeninfocinfo *var-argbasa href="+code=deargbasar" class="sref">par;
 485cinfopar;
 479static por" ;par;
fb_var_screeninfopar;
 369        hdispen *par;
 369        yre (par;
par;
 369        nom*par;
 485 479static iontrol*par;
 494
info-    dev_dbg(info->device, maxclock) {
 446sref">info-a> *var-xrescode=bits_per_pxresref" kHz\n" = var-yres(var-> 467
 497        > = var->maxclock) {
maxclock) {
 420<        } else /a>(info-fix(btype        unsig> = var-xres_virtua+code=bits_per_pxres_virtua+e" na/>8ultiplexing = 0;
 501            /a>(info-fix(btype        unsigFB_VISUAL_MONOusfb.c#L410"+codeFB_VISUAL_MONOusclaslass="sref">par;
 412&k           return 1;
 463
maxclock) {
 405<        } else /a>(info-fix(btype        unsig> = var-xres_virtua+code=bits_per_pxres_virtua+e" n           return 1;
 446            /a>(info-fix(btype        unsigFB_VISUAL_PSEUDOCOLORfb.c#L410"+codeFB_VISUAL_PSEUDOCOLORe" n           return 1;
 407&k           return 1;
 478
maxclock) {
maxclock) {
 411<        } else /a>(info-fix(btype        unsig> = var-xres_virtua+code=bits_per_pxres_virtua+e" n *ef">maxclock) {
 412     ame="L411"> 411<        } else > = var-> >> 3;
 383            /a>(info-fix(btype        unsigFB_VISUAL_TRUECOLORfb.c#L410"+codeFB_VISUAL_TRUECOLORe" n           return 1;
 404&k           return 1;
 " class="f="drivers/video/cirrusf7v6deo/cir7usfb.c#L416" id="L416" c7ass="71ne" name="L40/a>            /a>(info-fix(btype        unsigFB_TYPE_PACKED_PIXELSfb.c#L410"+codeFB_TYPE_PACKED_PIXELSe" n           return 1;
 467
dev_dbg( 489
 490    bi+code=cirrusfb_bir" css=ef">C"sref">cinfocinfo *var-btypa href="+code=debtypar" c]           return 1;
 491
maxclockidx = var-xrescode=bits_per_pxresref" +87"> 493    > = var-ae ca_margimaxclockidx 493    > = var-hsync_a h( 493    htotal*        } else hsyncen * 493    > = var-lefa_margi8ultiplexing = 0;
info-hdispen *maxclockidx = var-xrescode=bits_per_pxresref" />8ultiplexing = 0;
maxclockidx 493    hsyncen *maxclockidx 478
        unsig> = var-yre ( 490    vsyncamert( 493    > = var-lowclamargicinfo 493    > = var-vsync_a h(        unsig>syncen * 493    > = var-uppclamargi 463
 497        > = var-vxing CL"sref">dev_errmaxclock) {
 405<        } else >dispen *            return 2;
 446            >syncamert(            return 2;
 407<468        >syncen *            return 2;
 498            vtotal*            return 2;
var-vxing CL"sref">dev_errmaxclock) {
 420<        } else >dispen * 501            vsyncamert( 412<"sref">cinfo 383        } else >total* 474        }
info-yre ( 468        yre (maxclock) {
 407<        } else >total*            return 2;
 498            vsyncamert(            return 2;
 499<468        >syncen *            return 2;
 420<        } else >dispen *            return 2;
 474        }
 422
            return 1;
 493    vsyncamert(            return 1;
info->syncen *            return 1;
            return 2;
 467
 468        a> *var-multiplex>, < href="+code=cmultiplex>, clas"sref">maxclock) {
 499<468        htotal*            return 2;
 420<        } else hsyncamert(            return 2;
 501            hsyncen *            return 2;
 412<"sref">cinfo            return 2;
 474        }
 494
info-htotal*5           return 2;
            return 1;
 493    hsyncamert(            return 1;
            return 1;
 489
 487                 */
cinfo        argbasa href="+code=deargbasar" c kHz\n" 487                 */
 422
 487        debugg>,  is enabled, all par473ters get output before writ>,  "comment">         */
 493        dev_dbg(info->device, info-htotal*info->ga_wcrt(        argbasa href="+code=deargbasar" c kHz\n" 486
 493        dev_dbg(info->device, info-hdispen *        argbasa href="+code=deargbasar" c kHz\n" 489
 490        dev_dbg(info->device, info-> = var-xrescode=bits_per_pxresref" />8"           return 1;
cinfo        argbasa href="+code=deargbasar" c kHz\n" = var-xrescode=bits_per_pxresref" />8"           return 1;
 422
 487                 */
 493        dev_dbg(info->device,         } else htotal*info-vga_wcrt(        argbasa href="+code=deargbasar" c kHz\n" 446<8128a+ (>        } else htotal* 467
dev_dbg(info->device, info-hsyncamert(        argbasa href="+code=deargbasar" c kHz\n"EINVAL;
cinfomaxclockidxCL32)          return 1;
 383 493        dev_dbg(info->device, info-tmp info->ga_wcrt(        argbasa href="+code=deargbasar" c kHz\n"info-tmp  486
 493        dev_dbg(info->device, info->total*CL0xff"           return 1;
        argbasa href="+code=deargbasar" c kHz\n"total*CL0xff"           return 1;
 489
 490    tmp  383 487                 */
CL256)          return 1;
 412<0"> 490    tmp             return 1;
 468        >dispen *CL256)          return 1;
 412<0"> 490    tmp 2           return 1;
 468        >syncamert(CL256)          return 1;
 446            tmp 4           return 1;
CL256)          return 1;
 498            tmp 8           return 1;
         } else >total*CL512)          return 1;
 420<        } else tmp 32           return 1;
CL512)          return 1;
 412<        } else tmp 64           return 1;
 468        >syncamert(CL512)          return 1;
 404<0"> 490    tmp  28           return 1;
info-    dev_dbg(info->device, info-tmp         argbasa href="+code=deargbasar" c kHz\n"info-tmp  467
 404<0"> 487                 */
 >        } else >dispen *CL512)          return 1;
 420<        } else tmp 0x20           return 1;
var-vxing CL"sref">dev_err 412<        } else tmp 0x80           return 1;
dev_dbg(info->device, info-tmp  493    >ga_wcrt(        argbasa href="+code=deargbasar" c kHz\n"info-tmp  475
dev_dbg(info->device, info->syncamert(CL0xff"           return 1;
 493    vga_wcrt(        argbasa href="+code=deargbasar" c kHz\n"syncamert(CL0xff"           return 1;
 478
dev_dbg(info->device, 64+32+"dxclock: %ld 0Hz\n"syncen * 490    vga_wcrt(        argbasa href="+code=deargbasar" c kHz\n"syncen * 491
dev_dbg(info->device, info->dispen *CL0xff"           return 1;
        argbasa href="+code=deargbasar" c kHz\n"dispen *CL0xff"           return 1;
 494
info-    dev_dbg(info->device,         } else >dispen *CL0xff"           return 1;
        argbasa href="+code=deargbasar" c kHz\n"        } else >dispen *CL0xff"           return 1;
 467
dev_dbg(info->device, info->total*CL0xff"           return 1;
        argbasa href="+code=deargbasar" c kHz\n"info->total*CL0xff"           return 1;
EINVAL;
cinfodev_dbg(info->device,         argbasa href="+code=deargbasar" c kHz\n" 463
 493    tmp  468        > = var-vxing CL"sref">dev_err 446            tmp             return 1;
CL64"          return 1;
 498            tmp  6           return 1;
 >        } else htotal*CL128"          return 1;
 420<        } else tmp 32           return 1;
CL256)          return 1;
 412<        } else tmp 64           return 1;
 468        >total*CL512)          return 1;
 404<0"> 490    tmp  28           return 1;
 475
dev_dbg(info->device, info-tmp  493    vga_wcrt(        argbasa href="+code=deargbasar" c kHz\n"info-tmp  478
        > = var-pixccirr  468        > = var-> 501<8"> 468        a> *var-btypa href="+code=debtypar" ca== "sref">var-BT_ALPINE href="+code=deBT_ALPINEr" ca|| "sref">var-a> *var-btypa href="+code=debtypar" ca== "sref">var-BT_SDusfb.c#L464ode=deBT_SDusclas"          return 1;
 412 >> 3;
 468        a> *var-multiplex>, < href="+code=cmultiplex>, clas"xel >> 3;
 404<0"> 490    freq             return 2;
 468        a> *var-doubleVCLK href="+code=devoubleVCLKclas"xel >> 3;
 446            freq  467
        freq C"sref">cinfoC"sref">cinfoC"sref">cinfo 489
 490        dev_dbg(info->device,  489
 501            freq cinfocinfocinfo 422
 487                 */
 487                 */
 487        OSC * N)ass(D * (1+P))t"comment">         */
 487        le: VClkaf/>14.31818 * 91)ass(23 * (1+1))t=s 8.325 MHz "comment">         */
 467
 468        a> *var-btypa href="+code=debtypar" ca== "sref">var-BT_ALPINE href="+code=deBT_ALPINEr" ca|| "sref">var-a> *var-btypa href="+code=debtypar" ca== "sref">var-BT_PICASSOsfb.c#L464ode=deBT_PICASSOsr" ca||ame="L467"> 467
 "sref">var-a> *var-btypa href="+code=debtypar" ca== "sref">var-BT_SDusfb.c#L464ode=deBT_SDusclas"sref">maxclock) {
 420< "> 487        freq is ccise to mclkaor mclk/2 select mclkomment">         */
 487         420< * as ccick sour" clment">         */
 487         420< *comment">         */
 383cinfodev_dbg(cinfo 404<8"> 468        divMCLK href="+code=devivMCLKr" c"xel >> 3;
 420< sref">cinfo 446dev_dbg(cinfo 474        }
 468        is_lagunadev_dbg *maxclock) {
 499cinfodev_dbg *var-laguna_mmi 420info-til a href="+code=ctil r" caf"Hz\n"dev_dbg *var-laguna_mmi 501cinfo 422
 383<8"> 468        a> *var-btypa href="+code=debtypar" ca== "sref">var-BT_LAGUNABfb.c#L464ode=deBT_LAGUNABclas"sref">maxclock) {
 404<6"> 446dev_dbg *var-laguna_mmi 420< sref">cinfoC= ~0x80           return 1;
 446<8"> 420< sref">cinfodev_dbgcinfo *var-laguna_mmi 474        }
 478
 499<468        ri_write+code=bits_per_pri_write+lass="sref">dev_dbgcinfo *var-laguna_mmi 420<        } else ri_writebcode=bits_per_pri_writeblass="sref">dev_dbgCL0x3f,="sref">cinfo *var-laguna_mmi 501            contro+code=bits_per_pcontro+e" naf"Hz\n"dev_dbg *var-laguna_mmi 412<0"> 490    t 49shol *dev_dbg *var-laguna_mmi 383C= ~0x6800           return 1;
 412<0"> 490    format( 490    t 49shol *C= 0xffc0a&f">CL0x3fbf           return 1;
 474        }
cinfomaxclock) {
 498            tmp             return 1;
 499<8"> 468        div( >> 3;
 420<8"> 498            tmp             return 1;
 501 487                 */
 412<8"> >        } else a> *var-btypa href="+code=debtypar" ca== "sref">var-BT_SDusfb.c#L464ode=deBT_SDusclas"s||ame="L467"> 467
 383<<<<< 468        a> *var-btypa href="+code=debtypar" ca== "sref">var-BT_ALPINE href="+code=deBT_ALPINEr" c"s||ame="L467"> 467
 404<<<<< 468        a> *var-btypa href="+code=debtypar" ca== "sref">var-BT_GD54usfb.c#L480ode=deBT_GD54us cla)"ame="L467"> 467
 420< sref">cinfo0x80           return 1;
 486
 487                 */
 498<8"> 468        is_lagunadev_dbg *maxclock) {
 499<0"> 420< sref">cinfodev_dbg 420<0"> 420< sref">cinfodev_dbg 501<} elsesref">maxclock) {
 412<0"> 420< sref">cinfodev_dbg 383<<<<<420< sref">cinfodev_dbg 404<4"> 474        }
 474        }
 486
cinfo 498 487                 */
 499<468        >ga_wcrt(        argbasa href="+code=deargbasar" c kHz\n" 501 487                 */
 487         420< * address wrap, no compat.t"comment">         */
 383ga_wcrt(        argbasa href="+code=deargbasar" c kHz\n" 494
 487                 */
 487                 */
cinfo = var-vxing CL"sref">dev_err 498            >ga_wcrt(        argbasa href="+code=deargbasar" c kHz\n" 420<        } else >ga_wcrt(        argbasa href="+code=deargbasar" c kHz\n" 487                 */
 491
 487                 */
 487        CLCRTC I/O address for color ming "comment">         */
 493    tmp  468        > = var-sync CL"sref">dev_err 446            tmp 0x4        > = var-sync CL"sref">dev_err 498            tmp 0x80           return 1;
dev_dbg *EINVAL;
 487                 */
        argbasa href="+code=deargbasar" c kHz\n" 487                 */
 493    vga_wcrt(        argbasa href="+code=deargbasar" c kHz\n" 475
 487                 */
 487                 */
 487                 */
 487                 */
 487                 */
 491
 487                 */
 468        > = var->maxclock) {
 404<0"> 490        dev_dbg(info->device,  490    vga_wgfx(        argbasa href="+code=deargbasar" c kHz\n" 487                 */
 486
 487                 */
 498        a> *var-btypa href="+code=debtypar" c"sref">maxclock) {
 499var-BT_SDusfb.c#L464ode=deBT_SDusclas:ef">maxclock) {
 420var-BT_PICCOLOfb.c#L464ode=deBT_PICCOLOclas:ef">maxclock) {
 501var-BT_PICASSOfb.c#L464ode=deBT_PICASSOclas:ef">maxclock) {
 412var-BT_SPECTRUMfb.c#L464ode=deBT_SPECTRUMclas:ef">maxclock) {
 383var-BT_PICASSOsfb.c#L464ode=deBT_PICASSOsr" c:ef">maxclock) {
 404var-BT_ALPINE href="+code=deBT_ALPINEr" c:ef">maxclock) {
var-BT_GD54usfb.c#L480ode=deBT_GD54us cla:ef">maxclock) {
 446<8"> 420< sref">cinfodev_dbgmaxclock) {
 446<8"> 420< sref">cinfo *var-multiplex>, < href="+code=cmultiplex>, clas ?ef">maxclock) {
 498<888888846"> 446<8"> 420< sref">cinfovar-sr07_1bpp_mux(cinfovar-sr07_1bpp(             break           return 1;
EINVAL;
 501var-BT_LAGUNAfb.c#L480ode=deBT_LAGUNA cla:ef">maxclock) {
 412var-BT_LAGUNABfb.c#L464ode=deBT_LAGUNABclas:ef">maxclock) {
 383<8"> 420< sref">cinfodev_dbgmaxclock) {
 404<3"> 383<8"> 420< sref">cinfodev_dbgCL~0x01"           return 1;
 420 486
maxclock) {
 498<888888840"> 490        warh(dev_dbg(info->device,  499<0"> 420 420<4"> 474        }
 491
 412<0"> 487                 */
 383        a> *var-btypa href="+code=debtypar" c"sref">maxclock) {
 494
var-BT_PICCOLOfb.c#L464ode=deBT_PICCOLOclas:ef">maxclock) {
 446var-BT_SPECTRUMfb.c#L464ode=deBT_SPECTRUMclas:ef">maxclock) {
 412<0"> 487                 */
 498<888888840"> 490    vga_wseq dev_dbg 499<<<<<<<<1000e" nam/pre>         return 1;
100ne" name="L501"> 501var-BT_PICASSOfb.c#L464ode=deBT_PICASSOclas:ef">maxclock) {
100ne" name="L412"> 412<0"> 420< "> 487                 */
100ne" name="L383"> 383<8"> 420< sref">cinfodev_dbg100ne" name="L404"> 404<3"> 383100ne" name="L475"> 475
100ne" name="L446"> 446var-BT_SDusfb.c#L464ode=deBT_SDusclas:ef">maxclock) {
100ne" name="L4888888888casa "sref">var-BT_PICASSOsfb.c#L464ode=deBT_PICASSOsr" c:ef">maxclock) {
100ne" name="L498"> 498var-BT_ALPINE href="+code=deBT_ALPINEr" c:ef">maxclock) {
100ne" name="L499"> 499var-BT_GD54usfb.c#L480ode=deBT_GD54us cla:ef">maxclock) {
10use" name="L501"> 501var-BT_LAGUNAfb.c#L480ode=deBT_LAGUNA cla:ef">maxclock) {
10une" name="L501"> 501var-BT_LAGUNABfb.c#L464ode=deBT_LAGUNABclas:ef">maxclock) {
10une" name="L412"> 412<0"> 420< "> 487                 */
10une" name="L383"> 383<8"> 42010une" name="L494"> 494
10une" name="L40ame="L42default:ef">maxclock) {
10une" name="L446"> 446<8"> 420< sref">cinfodev_dbg(info->device, 10une" name="L48888888882"> 41210une" name="L498"> 498<4"> 474        }
10une" name="L489"> 489
10use" name="L412"> 412<0"> 487                 */
10une" name="L501"> 501            WG h(dev_dbg *10une" name="L412"> 412<8">  sref">cinfo *var-multiplex>, < href="+code=cmultiplex>, clas"          return 1;
10une" name="L383"> 383<8"> 420< "> 487        
102ne" name="L404"> 404<1"> 501            WHDR(dev_dbg *102ne" name="L40ame="L42else          return 1;
102ne" name="L446"> 446<8"> 420< "> 487        
102ne" name="L48888888882"> 412<0a>            WHDR(dev_dbg *102ne" name="L498"> 498 487                 */
102ne" name="L499"> 499<468        >ga_wseq dev_dbg10use" name="L412"> 412<0"> 487                 */
10une" name="L501"> 501            >ga_wseq dev_dbg10une" name="L414"> 474        }
10u3e" name="L489"> 489
10u4e" name="L487"> 487                 */
10une" n "> 487                 */
10u6e" n "> 487                 */
10une" n "> 487                 */
10une" n "> 487                 */
10une" name="L489"> 489
10use" name="L48elses8"> 468        > = var->maxclock) {
10une" name="L501"> 501                dev_dbg(info->device, 10une" name="L412"> 412        a> *var-btypa href="+code=debtypar" c"sref">maxclock) {
10une" name="L383"> 383var-BT_SDusfb.c#L464ode=deBT_SDusclas:ef">maxclock) {
10une" name="L404"> 404var-BT_PICCOLOfb.c#L464ode=deBT_PICCOLOclas:ef">maxclock) {
10une" name="L40ame="L42casa "sref">var-BT_PICASSOfb.c#L464ode=deBT_PICASSOclas:ef">maxclock) {
10une" name="L446"> 446var-BT_SPECTRUMfb.c#L464ode=deBT_SPECTRUMclas:ef">maxclock) {
10une" name="L4888888888casa "sref">var-BT_PICASSOsfb.c#L464ode=deBT_PICASSOsr" c:ef">maxclock) {
10une" name="L498"> 498var-BT_ALPINE href="+code=deBT_ALPINEr" c:ef">maxclock) {
10une" name="L499"> 499var-BT_GD54usfb.c#L480ode=deBT_GD54us cla:ef">maxclock) {
10use" name="L383"> 383<8"> 420< sref">cinfodev_dbgmaxclock) {
10une" name="L501"> 501<383"> 383<8"> 420< sref">cinfo *var-multiplex>, < href="+code=cmultiplex>, clas ?ef">maxclock) {
10une" name="L412"> 412<0"> 420<3"> 383<8"> 420< sref">cinfovar-sr07_8bpp_mux(cinfovar-sr07_8bpp(10une" name="L383"> 383<8"> 42010une" name="L494"> 494
10une" name="L40ame="L42casa "sref">var-BT_LAGUNAfb.c#L480ode=deBT_LAGUNA cla:ef">maxclock) {
10une" name="L446"> 446var-BT_LAGUNABfb.c#L464ode=deBT_LAGUNABclas:ef">maxclock) {
10une" name="L48888888882"> 412<0a>            vga_wseq dev_dbgmaxclock) {
10une" name="L498"> 498<888888846"> 446<0a>            vga_rseq dev_dbg10une" name="L499"> 499<0"> 420< sref">cinfo0x10           return 1;
10use" name="L383"> 383<8"> 42010une" name="L491"> 491
10une" name="L412"> 412maxclock) {
10une" name="L383"> 383<8"> 420< sref">cinfodev_dbg(info->device, 10une" name="L404"> 404<3"> 38310une" name="L40ame="L424"> 474        }
10une" name="L486"> 486
10une" name="L4888888888switch< 468        a> *var-btypa href="+code=debtypar" c"sref">maxclock) {
10une" name="L498"> 498var-BT_PICCOLOfb.c#L464ode=deBT_PICCOLOclas:ef">maxclock) {
10une" name="L499"> 499var-BT_PICASSOfb.c#L464ode=deBT_PICASSOclas:ef">maxclock) {
10use" name="L446"> 446var-BT_SPECTRUMfb.c#L464ode=deBT_SPECTRUMclas:ef">maxclock) {
10une" name="L501"> 501<383"> 380"> 487                 */
10une" name="L412"> 412<0"> 420< sref">cinfodev_dbg10une" name="L383"> 383<8"> 42010une" name="L494"> 494
10une" name="L40ame="L42casa "sref">var-BT_PICASSOsfb.c#L464ode=deBT_PICASSOsr" c:ef">maxclock) {
10une" n#ifdefkHz\n" 494
10une" name="L48888888882"> 412<0"> 487                 */
10une" name="L498"> 498<888888840"> 490    vga_wseq dev_dbg10une" n#endif          return 1;
10use" name="L498"> 498var-BT_ALPINE href="+code=deBT_ALPINEr" c:ef">maxclock) {
10une" name="L501"> 501var-BT_SDusfb.c#L464ode=deBT_SDusclas:ef">maxclock) {
10une" name="L412"> 412var-BT_GD54usfb.c#L480ode=deBT_GD54us cla:ef">maxclock) {
10une" name="L383"> 383var-BT_LAGUNAfb.c#L480ode=deBT_LAGUNA cla:ef">maxclock) {
10une" name="L404"> 404var-BT_LAGUNABfb.c#L464ode=deBT_LAGUNABclas:ef">maxclock) {
10une" name="L40ame="L420"> 420< "> 487                 */
10une" name="L446"> 446<8"> 42010u7e" name="L494"> 494
10une" name="L498"> 498maxclock) {
10une" name="L499"> 499<0"> 420< sref">cinfodev_dbg(info->device, 10use" name="L446"> 446<8"> 42010une" name="L501"> 501<}          return 1;
10u2e" name="L494"> 494
10une" name="L383"> 383 487                 */
10une" name="L404"> 404<0"> 490    vga_wgfx(        argbasa href="+code=deargbasar" c kHz\n"10une" name="L40ame="L428">  sref">cinfo *var-multiplex>, < href="+code=cmultiplex>, clas"          return 1;
10une" name="L446"> 446<8"> 420< "> 487        
10une" name="L48888888882"> 412<0a>            WHDR(dev_dbg *10une" name="L498"> 49810une" name="L499"> 499<0"> 420< "> 487        
110se" name="L383"> 383<8"> 420< sref">cinfodev_dbg *110ne" name="L50}          return 1;
1102e" name="L494"> 494
1103e" name="L495"> 487                 */
110ne" n "> 487                 */
110ne" n "> 487                 */
1106e" n "> 487                 */
110ne" n "> 487                 */
110ne" n>         */
110ne" name="L40else88"> 468        > = var->maxclock) {
11use" name="L501"> 501< sref">cinfodev_dbg(info->device, 11une" name="L501"> 501        a> *var-btypa href="+code=debtypar" c"sref">maxclock) {
11une" name="L412"> 412var-BT_PICCOLOfb.c#L464ode=deBT_PICCOLOclas:ef">maxclock) {
11une" name="L383"> 383var-BT_SPECTRUMfb.c#L464ode=deBT_SPECTRUMclas:ef">maxclock) {
111ne" name="L404"> 404<1"> 501            vga_wseq dev_dbg0x87"           return 1;
11une" name="L40ame="L421"> 501 487                 */
11une" name="L446"> 446<8"> 420< sref">cinfodev_dbg11une" name="L48888888882"> 412111ne" n>         */
111ne" name="L499"> 499var-BT_PICASSOfb.c#L464ode=deBT_PICASSOclas:ef">maxclock) {
11use" name="L412"> 412<8"> 420< sref">cinfodev_dbg0x27"           return 1;
11une" name="L501"> 501<1"> 501 487                 */
11une" name="L412"> 412<8"> 420< sref">cinfodev_dbg11une" name="L383"> 383<8"> 420112ne" name="L494"> 494
112ne" name="L40ame="L42casa "sref">var-BT_SDusfb.c#L464ode=deBT_SDusclas:ef">maxclock) {
112ne" name="L446"> 446var-BT_PICASSOsfb.c#L464ode=deBT_PICASSOsr" c:ef">maxclock) {
112ne" name="L4888888888casa "sref">var-BT_ALPINE href="+code=deBT_ALPINEr" c:ef">maxclock) {
112ne" name="L498"> 498<1"> 501 487                 */
112ne" name="L499"> 499<8"> 420< sref">cinfodev_dbgmaxclock) {
11use" name="L412"> 412 499<8"> 420< sref">cinfo *var-doubleVCLK href="+code=devoubleVCLKe" na?k0xa3 :k0xa7"           return 1;
11une" name="L501"> 501<<<<<<<<1132e" name="L494"> 494
113ne" name="L383"> 383var-BT_GD54usfb.c#L480ode=deBT_GD54us cla:ef">maxclock) {
113ne" name="L404"> 404<1"> 501            vga_wseq dev_dbg0x17"           return 1;
113ne" name="L40ame="L421"> 501 487                 */
113ne" name="L446"> 446<8"> 4201137e" name="L494"> 494
113ne" name="L498"> 498var-BT_LAGUNAfb.c#L480ode=deBT_LAGUNA cla:ef">maxclock) {
113ne" name="L499"> 499var-BT_LAGUNABfb.c#L464ode=deBT_LAGUNABclas:ef">maxclock) {
114se" name="L412"> 412<8"> 420< sref">cinfodev_dbgmaxclock) {
11une" name="L501"> 501<2"> 412<8"> 420< sref">cinfodev_dbgCL~0x01"           return 1;
11une" name="L412"> 412<8"> 420< sref">cinfo0x2000           return 1;
11une" name="L383"> 383<8"> 420< sref">cinfo0x14s0           return 1;
11une" name="L404"> 404<8"> 420< sref">cinfo0x10           return 1;
11une" name="L40ame="L4222222222break           return 1;
114ne" name="L486"> 486
11une" name="L4888888888default:ef">maxclock) {
11une" name="L498"> 498<8"> 420< sref">cinfodev_dbg(info->device, 11une" name="L499"> 499<22222222break           return 1;
11use" name="L383"> 383<}          return 1;
115ne" name="L491"> 491
11une" name="L412"> 412 487                 */
11une" name="L383"> 383<0"> 490    vga_wgfx(        argbasa href="+code=deargbasar" c kHz\n"11une" n#ifdefkHz\n" 491
11une" name="L40ame="L42 sref">cinfodev_dbg *cinfo *var-doubleVCLK href="+code=devoubleVCLKe" na?k0xe1 :k0xc1"           return 1;
11une" n#elifkHz\n"dev_dbg11une" name="L4888888888/"> 487                 */
11une" name="L498"> 498<0a>            WHDR(dev_dbg * 487        
115ne" n#endif          return 1;
11use" name="L38}          return 1;
11une" name="L491"> 491
11une" name="L415"> 487                 */
11une" n "> 487                 */
116ne" n "> 487                 */
116ne" n "> 487                 */
1166e" n "> 487                 */
1167e" name="L494"> 494
11une" name="L49else88"> 468        > = var->maxclock) {
11une" name="L499"> 499< sref">cinfodev_dbg(info->device, 11use" name="L446"> 446        a> *var-btypa href="+code=debtypar" c"sref">maxclock) {
11une" name="L501"> 501var-BT_PICCOLOfb.c#L464ode=deBT_PICCOLOclas:ef">maxclock) {
11une" name="L412"> 412var-BT_SPECTRUMfb.c#L464ode=deBT_SPECTRUMclas:ef">maxclock) {
11une" name="L383"> 383<8"> 420< sref">cinfodev_dbg0x85"           return 1;
117ne" name="L404"> 404<8"> 420< "> 487                 */
11une" name="L40ame="L428"> 420< sref">cinfodev_dbg117ne" name="L446"> 446<8"> 4201177e" name="L494"> 494
11une" name="L498"> 498var-BT_PICASSOfb.c#L464ode=deBT_PICASSOclas:ef">maxclock) {
117ne" name="L499"> 499<8"> 420< sref">cinfodev_dbg0x25"           return 1;
11use" name="L498"> 498<8"> 420< "> 487                 */
11une" name="L501"> 501<8"> 420< sref">cinfodev_dbg11une" name="L412"> 412<8"> 4201183e" name="L489"> 489
11une" name="L404"> 404var-BT_SDusfb.c#L464ode=deBT_SDusclas:ef">maxclock) {
11une" name="L40ame="L42casa "sref">var-BT_PICASSOsfb.c#L464ode=deBT_PICASSOsr" c:ef">maxclock) {
11une" name="L446"> 446var-BT_ALPINE href="+code=deBT_ALPINEr" c:ef">maxclock) {
118ne" name="L48888888882"> 412<0"> 487                 */
11une" name="L498"> 498<8"> 420< sref">cinfodev_dbg0xa5"           return 1;
11une" name="L499"> 499<0"> 4201190e" name="L489"> 489
11une" name="L501"> 501var-BT_GD54usfb.c#L480ode=deBT_GD54us cla:ef">maxclock) {
119ne" name="L412"> 412<8"> 420< sref">cinfodev_dbg0x15"           return 1;
11une" name="L383"> 383<2"> 412<0"> 487                 */
11une" name="L404"> 404<0"> 420119ne" name="L475"> 475
11une" name="L446"> 446var-BT_LAGUNAfb.c#L480ode=deBT_LAGUNA cla:ef">maxclock) {
11une" name="L4888888888casa "sref">var-BT_LAGUNABfb.c#L464ode=deBT_LAGUNABclas:ef">maxclock) {
11une" name="L498"> 498<8"> 420< sref">cinfodev_dbgmaxclock) {
11une" name="L499"> 499<0"> 420<8"> 420< sref">cinfodev_dbgCL~0x01"           return 1;
120se" name="L383"> 383<8"> 420< sref">cinfo0x4000           return 1;
120ne" name="L501"> 501<8"> 420< sref">cinfo0x24s0           return 1;
120ne" name="L412"> 412<8"> 420< sref">cinfo0x20           return 1;
120ne" name="L383"> 383<8"> 420120ne" name="L494"> 494
120ne" name="L40ame="L42default:ef">maxclock) {
120ne" name="L446"> 446<8"> 420< sref">cinfodev_dbg(info->device, 120ne" name="L48888888882"> 412120ne" name="L498"> 498<4"> 474        }
120ne" name="L489"> 489
12use" name="L501"> 501< "> 487                 */
12une" name="L501"> 501<0"> 490    vga_wgfx(        argbasa href="+code=deargbasar" c kHz\n"12une" name="L412"> 412 487        
12une" name="L383"> 383<0a>            WHDR(dev_dbg *121ne" name="L404"> 474        }
121ne" name="L475"> 475
12une" name="L445"> 487                 */
121ne" n "> 487                 */
121ne" n "> 487                 */
121ne" n "> 487                 */
12use" n "> 487                 */
122ne" name="L491"> 491
12une" name="L41else          return 1;
12une" name="L383"> 383< sref">cinfodev_dbg(info->122ne" name="L404"> 404<8"> 420< "> 487  , 122ne" name="L40ame="L423"> 383< sref">cinfo = var->122ne" name="L486"> 486
122ne" name="L48"sref">var-pitchcode=bits_per_ppitchref"a=8"sref">var-/a>(info-fix(info-" id_lengthcode=bits_per_p" id_lengthref"ass="ss=" 3           return 1;
122ne" name="L490"> 490    vga_wcrt(        argbasa href="+code=deargbasar" c kHz\n"CL0xff"           return 1;
122ne" name="L49 sref">cinfo12use" name="L418"> 468        pitchcode=bits_per_ppitchref"a&f">CL0x100"          return 1;
12une" name="L501"> 501< sref">cinfo0x10 420< "> 487                 */
1232e" name="L494"> 494
1233e" name="L495"> 487                 */
123ne" name="L400"> 490    vga_wcrt(        argbasa href="+code=deargbasar" c kHz\n"123ne" name="L475"> 475
123ne" name="L445"> 487                 */
1237e" name="L418"> 468        ref="dri_board_> * *dev_dbg *var-btypa href="+code=debtypar" c].sref">info-scrn_start_bitusfb.c#L419ode=descrn_start_bitusref"">         */
123ne" name="L498"> 498<0"> 490    vga_wcrt(        argbasa href="+code=deargbasar" c kHz\n"        pitchcode=bits_per_ppitchref"a&s="ss=" 9) &f">CL1"           return 1;
123ne" name="L489"> 489
124se" name="L418"> 468        is_lagunadev_dbg *maxclock) {
12une" name="L501"> 501< sref">cinfo12une" name="L412"> 412<8"> ="sref">dev_dbgCL256">         */
12une" name="L383"> 383<8"> 420< sref">cinfo128           return 1;
12une" name="L404"> 404<8"> 468        hdispen *CL256">         */
12une" name="L40ame="L4222222222 sref">cinfo64           return 1;
124ne" name="L446"> 446<8"> 468        hsyncstart*CL256">         */
12une" name="L488888888822222222 sref">cinfo48           return 1;
12une" name="L498"> 498<8"> 468        >tota+code=bits_per_pvtota+e" na&f">CL1024">         */
12une" name="L499"> 499<22222222 sref">cinfo8           return 1;
12use" name="L383"> 383<8"> 468        >dispen *CL1024">         */
125ne" name="L501"> 501<8"> 420< sref">cinfo4           return 1;
12une" name="L412"> 412<8"> 468        >syncstart*CL1024">         */
12une" name="L383"> 383<8"> 420< sref">cinfo3           return 1;
125ne" name="L494"> 494
12une" name="L40ame="L42 sref">cinfo        argbasa href="+code=deargbasar" c kHz\n"125ne" name="L446"> 446< sref">cinfodev_dbg(info->device, 12une" name="L484"> 474        }
125ne" n>         */
125ne" name="L49 "> 487                 */
12use" name="L38 sref">cinfo        argbasa href="+code=deargbasar" c kHz\n"12une" name="L491"> 491
12une" name="L415"> 487                 */
1263e" name="L495"> 487                 */
126ne" name="L400"> 490    Att=Oh(dev_dbg *126ne" name="L475"> 475
126ne" name="L448"> 468        is_lagunadev_dbg *maxclock) {
126ne" name="L4888888888/"> 487                 */
126ne" name="L498"> 498<0"> 490    fb_writew(dev_dbgcinfo *var-laguna_mmi12une" name="L499"> 499< sref">cinfodev_dbgcinfo *var-laguna_mmi12use" name="L446"> 446< sref">cinfodev_dbgcinfo *var-laguna_mmi12une" name="L504"> 474        }
127ne" name="L415"> 487                 */
1273e" name="L495"> 487                 */
127ne" name="L400"> 490    tmp(127ne" name="L475"> 475
1276e" n "> 487                 */
127ne" n "> 487         varlass=vming &f">CLFB_VMODE_CLOCK_HALVE)omment">         */
127ne" n "> 487        0x08;omment">         */
127ne" n "> 487                 */
1280e" name="L489"> 489
12une" name="L50 sref">cinfodev_dbg12une" name="L41 sref">cinfodev_dbg(info->device, 1283e" name="L489"> 489
128ne" n#ifdefkHz\n" 489
12une" name="L40468        ref="dri_" c_arg_dump(dev_dbg(128ne" n#endif          return 1;
1287e" name="L494"> 494
12une" name="L49return 0           return 1;
12une" n4"> 474        }
1290e" name="L489"> 489
12une" n5"> 487                 */
129ne" n "> 487        , s to take..grr. -dtg "comment">         */
12une" nstatic int0468        ref="dri_set_p =         ri_/a>(dev_dbg(         */
12une" nref">maxclock) {
129ne" name="L40468        ref="dri_set_p =_fodev_dbg(12une" name="L44return 468        ref="dri_set_p =_fodev_dbg(12une" n4"> 474        }
129ne" n>         */
12une" nstatic int0468        ref="dri_setcolrega href="+code=cinf="dri_setcolreglass=unsigid  "sref">dev_dbgdev_dbgdev_dbg         */
130se" name="L383"> 383<8"> 420<<<<<<dev_dbgdev_dbg         */
130ne" name="L501"> 501<8"> 420<<<<<<<        ri_/a>(dev_dbg(         */
130ne" nref">maxclock) {
130ne" name="L38        inf="dri_> *(e" na*"sref">dev_dbg *var-/a>(info-p = 130ne" name="L494"> 494
130ne" name="L408"> 468        argn(         */
130ne" name="L446"> 446        EINVAL1307e" name="L494"> 494
130ne" name="L498"> 468        ia>(info-fix(info-visua+code=bits_per_pvisua+ claa==8"sref">var-FB_VISUAL_TRUECOLOR(maxclock) {
130ne" name="L499"> 499< sref">cinfocinfo13use" name="L501"> 501< sref">dev_dbgvar-/a>(info-> = info-ar *info-"engthcode=bits_per_p"engthref""           return 1;
13une" name="L501"> 501<0"> 490    green*var-/a>(info-> = info-green*info-"engthcode=bits_per_p"engthref""           return 1;
13une" name="L412"> 412dev_dbgvar-/a>(info-> = info-blua href="+code=deblua" cl.sref">info-"engthcode=bits_per_p"engthref""           return 1;
1313e" name="L489"> 489
131ne" name="L404"> 404<8"> 468        argn(         */
131ne" name="L40ame="L4222222222return 1           return 1;
131ne" name="L446"> 446< sref">cinfo        ar *var-/a>(info-> = info-ar *info-offset*131ne" name="L48888888882222 468        green*var-/a>(info-> = info-green*info-offset*131ne" name="L498"> 498<8">  468        blua href="+code=deblua" cla&l="sl="8"sref">var-/a>(info-> = info-blua href="+code=deblua" cl.sref">info-offset*131ne" name="L489"> 489
132se" name="L501"> 501< sref">dev_dbg *var-pseudo_paletta href="+code=depseudo_paletta cla["sref">dev_dbgvar-vcode=bits_per_pvlass           return 1;
132ne" name="L501"> 50113une" name="L414"> 474        }
1323e" name="L489"> 489
132ne" name="L408"> 468        ia>(info-> = info-bgt;         */
132ne" name="L40ame="L42sref">info-WClut*dev_dbg *cinfodev_dbgcinfocinfo132ne" name="L486"> 486
132ne" name="L48return 0           return 1;
132ne" n>         */
132ne" n4"> 474        }
1330e" name="L489"> 489
133ne" n5"> 487                 */
133ne" n "> 487         4_display()omment">         */
1333e" name="L489"> 489
133ne" n "> 487         4ning - pro>
         */
133ne" n "> 487                 */
133ne" nstatic int0468        ref="dri_> 4_displaya href="+code=cinf="dri_> 4_displaylass=        ri_=va_screen/a>(dev_dbg<> =          */
133ne" name="L48888888882222222222222222        ri_/a>(dev_dbg(         */
133ne" nref">maxclock) {
133ne" name="L49int0468        xoffset*134se" name="L41unsigid  long  sref">cinfo13une" name="L50unsigid  charkHz\n"cinfo13une" name="L41        inf="dri_> *(e" na*"sref">dev_dbg *var-/a>(info-p = 1343e" name="L489"> 489
13une" name="L40/"> 487                 */
13une" name="L405"> 487         4_display has already done this0ncomment">         */
134ne" name="L448"> 468        > = var-vming CL"sref">var-FB_VMODE_YWRAP(         */
13une" name="L4888888888return -468        EINVAL134ne" n>         */
134ne" name="L49 sref">cinfovar-v = var-xoffset*var-/a>(info-> = info-bgt;8           return 1;
1350e" name="L489"> 489
135ne" name="L50 sref">cinfovar-v = var-yoffset*var-/a>(info-fix(info-" id_lengthcode=bits_per_p" id_lengthref"a+0468        xoffset*1352e" name="L494"> 494
13une" name="L388"> 468        ia>(info-> = info-bgt;maxclock) {
135ne" name="L404"> 404<5"> 487                 */
13une" name="L40ame="L42 sref">cinfo 468        > = var-xoffset*135ne" name="L44}1elsesref">maxclock) {
135ne" name="L4888888888/sref">cinfo4           return 1;
135ne" name="L498"> 498<0"> 490    xpix(  468        xoffset*135ne" name="L494"> 474        }
1360e" name="L489"> 489
1361e" name="L388"> !468        is_lagunadev_dbg * 489
136ne" name="L412"> 412dev_dbgdev_dbg *var-argbasa href="+code=deargbasar" c)           return 1;
1363e" name="L489"> 489
136ne" name="L40/"> 487                 */
136ne" name="L40468        vga_wcrt(        a> *var-argbasa href="+code=deargbasar" c kHz\n"CL0xff"           return 1;
136ne" name="L44468        vga_wcrt(        a> *var-argbasa href="+code=deargbasar" c kHz\n"        basa href="+code=debasar" ca&s="ss=" 8)a&f">CL0xff"           return 1;
1367e" name="L494"> 494
136ne" name="L49/"> 487                 */
136ne" name="L49 sref">cinfo        vga_rcrt(        a> *var-argbasa href="+code=deargbasar" c kHz\n"CL0xf2           return 1;
13use" name="L44/"> 487                 */
1371e" name="L388"> Hz\n"CL0x10000"          return 1;
137ne" name="L412"> 412dev_dbg0x01           return 1;
137ne" name="L388"> 468        basa href="+code=debasar" ca&f">CL0x20000"          return 1;
137ne" name="L404"> 404<5sref">dev_dbg0x04           return 1;
137ne" name="L408"> 468        basa href="+code=debasar" ca&f">CL0x40000"          return 1;
137ne" name="L446"> 446< sref">cinfo0x08           return 1;
1377e" name="L494"> 494
137ne" name="L490"> 490    vga_wcrt(        a> *var-argbasa href="+code=deargbasar" c kHz\n"137ne" name="L489"> 489
138se" name="L44/"> 487                 */
1381e" name="L388"> Hz\n" * *dev_dbg *var-btypa href="+code=debtypar" c].sref">info-scrn_start_bitusfb.c#L419ode=descrn_start_bitusref""sref">maxclock) {
138ne" name="L412"> 412dev_dbg        vga_rcrt(        a> *var-argbasa href="+code=deargbasar" c kHz\n"138ne" name="L383"> 383<8"> 468        is_lagunadev_dbg *138ne" name="L404"> 404<8"> 420< sref">dev_dbgdev_dbgCL~0x18)a|>  468        basa href="+code=debasar" ca&s="ss=" 16)a&f">CL0x18"           return 1;
138ne" name="L40ame="L42else          return 1;
138ne" name="L446"> 446<8"> 420< sref">dev_dbgdev_dbgCL~0x80)a|>  468        basa href="+code=debasar" ca&s="ss=" 12)a&f">CL0x80"           return 1;
138ne" name="L4888888888/sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"13une" name="L494"> 474        }
138ne" name="L489"> 489
139se" name="L44/"> 487                 */
13une" n5"> 487                 */
139ne" n "> 487                 */
13une" n "> 487                 */
139ne" name="L408"> 468        ia>(info-> = info-bgt;139ne" name="L40ame="L42 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n" 490    xpix(139ne" name="L486"> 486
139ne" name="L48return 0           return 1;
139ne" n4"> 474        }
139ne" name="L489"> 489
140se" nstatic int0468        ref="dri_blanka href="+code=cinf="dri_blanke" n int0468        blank_ming (e" na*"sref">dev_dbg(         */
140ne" nref">maxclock) {
140ne" name="L415"> 487                 */
140ne" n "> 487        blank_ming != 0 kelsesunblank. I">blanka== NULLrement">         */
140ne" n "> 487        ,  thg CLUT (Color Look Up Table)omment">         */
140ne" n "> 487        blank>,  succeeded, != 0 8">un-/blank>, omment">         */
1406e" n "> 487        
         */
140ne" n "> 487                 */
140ne" n "> 487        ,  hsync/vsync:omment">         */
140ne" n "> 487        blank_ming == 2: suspen  vsyncomment">         */
14use" n "> 487        blank_ming == 3: suspen  hsyncomment">         */
141ne" n5"> 487        blank_ming == 4: powerdownomment">         */
141ne" n "> 487                 */
141ne" name="L38unsigid  charkHz\n"141ne" name="L40        inf="dri_> *(e" na*"sref">dev_dbg *var-/a>(info-p = 141ne" name="L40int0468        rurr  <_ming var-a> *var-blank_ming 141ne" name="L486"> 486
141ne" name="L48"sref">var-    dev_dbg(info->device, blankaming = %dxclock: %ldskHz\n"141ne" n>         */
141ne" name="L49i"> 468        ia>(info-statg var-FBINFO_STATE_RUNNINGfb.c#L433"+codeFBINFO_STATE_RUNNINGref"a||          return 1;
142se" name="L501"> 468        rurr  <_ming var-blank_ming maxclock) {
142ne" name="L501"> 501<"sref">var-    dev_dbg(info->device, ,  0xclock: %ld"           return 1;
142ne" name="L412"> 412142ne" name="L384"> 474        }
142ne" name="L494"> 494
142ne" name="L40/"> 487                 */
142ne" name="L448"> 468        rurr  <_ming var-FB_BLANK_NORMAL142ne" name="L488888468        rurr  <_ming var-FB_BLANK_UNBLANK         */
142ne" name="L498"> 498<0"> 487                 */
142ne" name="L499"> 499< sref">cinfo143se" name="L50else          return 1;
143ne" name="L501"> 501<""> 487                 */
143ne" name="L412"> 412dev_dbg1433e" name="L489"> 489
143ne" name="L400"> 490    va+code=bits_per_pva+ claa|=8468        vga_rseq dev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"CL0xdf           return 1;
143ne" name="L40468        vga_wseq dev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"143ne" name="L486"> 486
143ne" name="L48switch  468        blank_ming maxclock) {
143ne" name="L49casa "sref">var-FB_BLANK_UNBLANKmaxclock) {
143ne" name="L49casa "sref">var-FB_BLANK_NORMALmaxclock) {
144se" name="L501"> 501< sref">dev_dbg144ne" name="L501"> 50114une" name="L41casa "sref">var-FB_BLANK_VSYNC_SUSPENDfb.c#L464ode=deFB_BLANK_VSYNC_SUSPENDref":ef">maxclock) {
144ne" name="L383"> 383< sref">dev_dbg144ne" name="L404"> 40414une" name="L40casa "sref">var-FB_BLANK_HSYNC_SUSPENDfb.c#L464ode=deFB_BLANK_HSYNC_SUSPENDref":ef">maxclock) {
144ne" name="L446"> 446< sref">cinfo14une" name="L4888888888break           return 1;
144ne" name="L49casa "sref">var-FB_BLANK_POWERDOWNfb.c#L464ode=deFB_BLANK_POWERDOWNref":ef">maxclock) {
144ne" name="L499"> 499< sref">cinfo145se" name="L501"> 501145ne" name="L50default:ef">maxclock) {
145ne" name="L412"> 412dev_dbg<    dev_dbg(info->device, ,  1xclock: %ld"           return 1;
145ne" name="L383"> 383145ne" name="L404"> 474        }
14une" n"> 474        }
145ne" name="L44468        vga_wgfx(        a> *var-argbasa href="+code=deargbasar" c kHz\n"1457e" name="L494"> 494
145ne" name="L490"> 490    a> *var-blank_ming var-blank_ming 145ne" name="L49 sref">cinfodev_dbg(info->device, ,  0xclock: %ld"           return 1;
1460e" name="L489"> 489
1461e" name="L38""> 487        blankafor us ncomment">         */
146ne" name="L41return  468        blank_ming var-FB_BLANK_NORMAL1463e" n4"> 474        }
146ne" name="L494"> 494
146ne" n "> 487                 */
1466e" n "> 487                 */
146ne" n "> 487                 */
146ne" n>         */
146ne" nstatic voi  "sref">dev_dbg(e" na*"sref">dev_dbg(         */
14use" nref">maxclock) {
1471e" name="L38        inf="dri_> *(e" na*"sref">dev_dbg *var-/a>(info-p = 147ne" name="L41con        inf="dri_board_> *<_reca href="+code=cinf="dri_board_> *<_rece" na*"sref">dev_dbg1473e" name="L489"> 489
147ne" name="L400"> 490    #L4ert(        a> *var-NULLa href="+code=cNULLrela"           return 1;
147ne" n"> 474        }
147ne" name="L44468        bi C468        inf="dri_board_> * *dev_dbg *var-btypa href="+code=debtypar" c]           return 1;
1477e" name="L494"> 494
147ne" name="L49/"> 487                 */
147ne" name="L49switch  468        a> *var-btypa href="+code=debtypar" c"sref">maxclock) {
148se" name="L44casa "sref">var-BT_PICCOLO href="+code=deBT_PICCOLOref":ef">maxclock) {
148ne" name="L501"> 501<"sref">var-WSFR(        a> *0x01"           return 1;
148ne" name="L412"> 412dev_dbg148ne" name="L383"> 383<"sref">var-WSFR(        a> *0x51"           return 1;
148ne" name="L404"> 404dev_dbg148ne" name="L40ame="L42break           return 1;
148ne" name="L44casa "sref">var-BT_PICASSO href="+code=deBT_PICASSOref":ef">maxclock) {
148ne" name="L4888888888/sref">cinfo        a> *0xff"           return 1;
148ne" name="L498"> 498<0"> 490    udelaya href="+code=cudelaye" n 500"           return 1;
148ne" name="L499"> 499149se" name="L44casa "sref">var-BT_SDusfb.c#L464ode=deBT_SDusref":ef">maxclock) {
1491e" name="L44casa "sref">var-BT_SPECTRUMfb.c#L464ode=deBT_SPECTRUMref":ef">maxclock) {
149ne" name="L412"> 412dev_dbg        a> *0x1f"           return 1;
149ne" name="L383"> 383<"sref">var-udelaya href="+code=cudelaye" n 500"           return 1;
149ne" name="L404"> 404dev_dbg        a> *0x4f"           return 1;
149ne" name="L40ame="L42 sref">cinfo149ne" name="L446"> 446149ne" name="L48casa "sref">var-BT_PICASSOsfb.c#L464ode=deBT_PICASSOsref":ef">maxclock) {
149ne" name="L498"> 498<0"> 487                 */
149ne" name="L499"> 499< sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x00"           return 1;
150se" name="L501"> 501< sref">dev_dbg150ne" name="L501"> 501<""> 487                 */
150ne" name="L412"> 412dev_dbg        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x00"           return 1;
1503e" name="L48casa "sref">var-BT_GD54usfb.c#L480ode=deBT_GD54usref":1<""> 487                 */
150ne" name="L404"> 404<5"> 487                 */
150ne" name="L40ame="L42 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x00"           return 1;
150ne" name="L44casa "sref">var-BT_ALPINE  487                 */
150ne" name="L4888888888/"> 487        blitter into 542x    pat ncomment">         */
150ne" name="L498"> 498<0"> 490    vga_wgfx(        a> *var-argbasa href="+code=deargbasar" c kHz\n"150ne" name="L499"> 4991510e" name="L489"> 489
1511e" name="L44casa "sref">var-BT_LAGUNA maxclock) {
151ne" name="L41casa "sref">var-BT_LAGUNABfb.c#L464ode=deBT_LAGUNABref":ef">maxclock) {
151ne" name="L383"> 383<""> 487        ,  to do to reset thg board. ncomment">         */
151ne" name="L404"> 404151ne" n"> 474        }
151ne" name="L44default:ef">maxclock) {
151ne" name="L4888888888/sref">cinfodev_dbg(info->device, , : Unknown board typaxclock: %ld"           return 1;
151ne" name="L498"> 498151ne" name="L494"> 474        }
1520e" name="L489"> 489
1521e" name="L38""> 487                 */
152ne" name="L410"> 490    #L4ert(        ia>(info-screen_size1523e" name="L489"> 489
152ne" name="L40/"> 487        ,  been ncomment">         */
152ne" name="L40/"> 487                 */
152ne" name="L44/"> 487         498<<<<<<<<<<         */
1527e" name="L494"> 494
152ne" name="L498"> Hz\n"var-btypa href="+code=debtypar" ca!=8"sref">var-BT_PICASSOsfb.c#L464ode=deBT_PICASSOsref""sref">maxclock) {
152ne" name="L499"> 499< sref">cinfo        a> *Hz\n"0x10" ="L44/"> 487        0x16         */
153se" name="L501"> 501< sref">dev_dbg        a> *Hz\n"0x01"           return 1;
153ne" name="L501"> 501<"sref">cinfo        a> *Hz\n"0x08" ="L44/"> 487        0x0g ncomment">         */
1532e" name="L494"> 494
153ne" name="L383"> 383<8"> 468        in *var-btypa href="+code=debtypar" ca!=8"sref">var-BT_SDusfb.c#L464ode=deBT_SDusref"">         */
153ne" name="L404"> 404<8"> 420< sref">dev_dbg        a> *Hz\n"0x01"           return 1;
153ne" n"> 474        }
153ne" name="L446"> 446< "> 487                 */
153ne" name="L4888888888/sref">cinfodev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"153ne" n>         */
153ne" name="L499"> 499< "> 487        
         */
154se" name="L501"> 501< sref">dev_dbgdev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"154ne" n          return 1;
154ne" name="L412"> 412 487                 */
154ne" n "> 487         412         */
154ne" name="L404"> 404< "> 487        un         */
154ne" name="L40ame="L42 sref">cinfodev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"0x12"           return 1;
154ne" name="L486"> 486
15une" name="L4888888888switch  468        a> *var-btypa href="+code=debtypar" c"sref">maxclock) {
154ne" name="L498"> 498var-BT_GD54usfb.c#L480ode=deBT_GD54usref":ef">maxclock) {
154ne" name="L499"> 499cinfodev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"0x98"           return 1;
155se" name="L501"> 501<<<<<<<<155ne" name="L501"> 501var-BT_ALPINE 155ne" name="L412"> 412var-BT_LAGUNA maxclock) {
155ne" name="L383"> 383var-BT_LAGUNABfb.c#L464ode=deBT_LAGUNABref":ef">maxclock) {
155ne" name="L404"> 404<8"> 420155ne" name="L40ame="L42casa "sref">var-BT_SDusfb.c#L464ode=deBT_SDusref":ef">maxclock) {
155ne" n#ifdefkHz\n" 486
155ne" name="L4888888888ame="L42 sref">cinfodev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"0xb8"           return 1;
155ne" n#endif          return 1;
155ne" name="L499"> 499156se" name="L501"> 501maxclock) {
156ne" name="L501"> 501cinfodev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"0x0f"           return 1;
156ne" name="L412"> 412cinfodev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"0xb0"           return 1;
156ne" name="L383"> 383156ne" name="L404"> 404<4"> 474        }
156ne" name="L404"> 474        }
156ne" name="L44/"> 487        ,  ncomment">         */
156ne" name="L48"sref">var-vga_wseq dev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"156ne" name="L49/"> 487                 */
156ne" name="L49 sref">cinfodev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"157se" name="L44/"> 487                 */
1571e" name="L38 sref">cinfodev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"1572e" name="L494"> 494
1573e" name="L49/"> 487        
         */
157ne" name="L408"> 468        bi var-init_sr0sfb.c#L497+code=init_sr0sref"">         */
157ne" name="L40ame="L42 sref">cinfodev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"var-sr0sfb.c#L497+code=sr0sref""           return 1;
157ne" name="L486"> 486
1577e" name="L49/"> 487        0x00"  ncomment">         */
157ne" name="L49/"> 487                 */
157ne" name="L489"> 489
158se" name="L44/"> 487                 */
1581e" name="L38 sref">cinfodev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"0x00"           return 1;
158ne" name="L415"> 487                 */
158ne" name="L38 sref">cinfodev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"0x00"           return 1;
158ne" name="L40/"> 487                 */
158ne" name="L40 sref">cinfodev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"0x00"           return 1;
158ne" name="L44/"> 487                 */
158ne" name="L48"sref">var-vga_wseq dev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"0x00"           return 1;
158ne" n>         */
158ne" name="L49/"> 487        ,  thesa on a P4 might g489 problems..  ncomment">         */
159se" name="L448"> Hz\n"var-btypa href="+code=debtypar" ca!=8"sref">var-BT_PICASSOsfb.c#L464ode=deBT_PICASSOsref""sref">maxclock) {
159ne" name="L501"> 501<""> 487                 */
159ne" name="L412"> 412dev_dbgdev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"0x00"           return 1;
159ne" name="L383"> 383<""> 487                 */
159ne" name="L404"> 404dev_dbgdev_dbg *var-argbasa href="+code=deargbasar" c kHz\n"0x02"           return 1;
159ne" name="L404"> 474        }
159ne" name="L486"> 486
1597e" name="L49/"> 487                 */
159ne" name="L490"> 490    vga_wcrt(        a> *var-argbasa href="+code=deargbasar" c kHz\n"159ne" name="L49/"> 487                 */
160se" name="L500"> 490    vga_wcrt(        a> *var-argbasa href="+code=deargbasar" c kHz\n"1601e" name="L38""> 487                 */
160ne" name="L410"> 490    vga_wcrt(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x00"           return 1;
1603e" name="L49/"> 487                 */
160ne" name="L400"> 490    vga_wcrt(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x00"           return 1;
160ne" name="L40/"> 487                 */
160ne" name="L44468        vga_wcrt(        a> *var-argbasa href="+code=deargbasar" c kHz\n"1607e" name="L494"> 494
160ne" name="L49/"> 487                 */
160ne" name="L49 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"161se" name="L44/"> 487        0x40afor text mings withass=" 30 MHz pix7         */
1611e" name="L38""> 487                 */
161ne" name="L410"> 490    vga_wcrt(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x02"           return 1;
1613e" name="L489"> 489
161ne" name="L40/"> 487                 */
161ne" name="L40 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"161ne" name="L44/"> 487                 */
161ne" name="L48"sref">var-vga_wgfx(        a> *var-argbasa href="+code=deargbasar" c kHz\n"161ne" name="L49/"> 487                 */
161ne" name="L49 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"162se" name="L44/"> 487                 */
1621e" name="L38 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"162ne" name="L415"> 487                 */
162ne" name="L38 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x00"           return 1;
162ne" name="L40/"> 487                 */
162ne" name="L40 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"162ne" name="L44/"> 487                 */
162ne" name="L48"sref">var-vga_wgfx(        a> *var-argbasa href="+code=deargbasar" c kHz\n"162ne" name="L49/"> 487                 */
162ne" name="L49 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"163se" name="L44/"> 487                 */
1631e" name="L38 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"1632e" name="L494"> 494
163ne" name="L388"> Hz\n"var-btypa href="+code=debtypar" ca==8"sref">var-BT_ALPINE         in *var-btypa href="+code=debtypar" ca==8"sref">var-BT_SDusfb.c#L464ode=deBT_SDusref" ||ame="L494"> 494
163ne" name="L404"> "sref">var-is_lagunafb.c#L464ode=deis_lagunae" n 468        a> *         */
163ne" name="L40ame="L42 "> 487                 */
163ne" name="L446"> 446< sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x20"           return 1;
163ne" name="L48else          return 1;
163ne" name="L49/"> 487                 */
163ne" n/"> 487         446<* 8byte data latchesomment">         */
164se" n/"> 487         446<*comment">         */
164ne" name="L501"> 501<"sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x28"           return 1;
1642e" name="L494"> 494
164ne" name="L38 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n" 487                 */
164ne" name="L400"> 490    vga_wgfx(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x00" 9/"> 487                 */
164ne" name="L40 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n" 487                 */
164ne" name="L44/"> 487                 */
1647e" name="L49/"> 487        0x00"  ncomment">         */
164ne" name="L49/"> 487        0x00"  ncomment">         */
164ne" name="L489"> 489
165se" name="L44/"> 487                 */
1651e" name="L38 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x00"           return 1;
165ne" name="L410"> 490    vga_wattr(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x01"           return 1;
165ne" name="L38 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x02"           return 1;
165ne" name="L400"> 490    vga_wattr(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x03"           return 1;
165ne" name="L40 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x04"           return 1;
165ne" name="L44468        vga_wattr(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x05"           return 1;
165ne" name="L48"sref">var-vga_wattr(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x06"           return 1;
165ne" name="L490"> 490    vga_wattr(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x07"           return 1;
165ne" name="L49 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x08"           return 1;
166se" name="L500"> 490    vga_wattr(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x09"           return 1;
1661e" name="L38 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"166ne" name="L410"> 490    vga_wattr(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x0b"           return 1;
166ne" name="L38 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"166ne" name="L400"> 490    vga_wattr(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x0d"           return 1;
166ne" name="L40 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"166ne" name="L44468        vga_wattr(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x0f"           return 1;
1667e" name="L494"> 494
166ne" name="L49/"> 487                 */
166ne" name="L49 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"167se" name="L44/"> 487                 */
1671e" name="L38 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"167ne" name="L415"> 487                 */
167ne" name="L38 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"167ne" name="L40/"> 487                 */
167ne" name="L40 sref">cinfo        a> *var-argbasa href="+code=deargbasar" c kHz\n"167ne" name="L486"> 486
167ne" name="L48"sref">var-WGen(        a> *Hz\n" 487                 */
167ne" n>         */
167ne" name="L49/"> 487                 */
168se" name="L500"> 490    vga_wgfx(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x04"           return 1;
1681e" name="L38""> 487                 */
168ne" name="L410"> 490    vga_wgfx(        a> *var-argbasa href="+code=deargbasar" c kHz\n"0x00"           return 1;
1683e" name="L489"> 489
168ne" name="L40/"> 487                 */
168ne" name="L40 sref">cinfo        a> *0" 9/"> 487        
168ne" name="L44return           return 1;
168ne" n4"> 474        }
168ne" n>         */
168ne" nstatic void0 sref">cinfo        inf="dri_> * *        a> *int0468        on(         */
169se" nref">maxclock) {
169ne" n#ifdefkHz\n" 487                 */
169ne" name="L41static int0468        IsOn( 487                 */
1693e" name="L489"> 489
169ne" name="L408"> 468        in *var-btypa href="+code=debtypar" ca==8"sref">var-BT_PICASSOsfb.c#L464ode=deBT_PICASSOsref""ame="L489"> 489
169ne" name="L40ame="L44return 0ame="L44/"> 487        ,  to8switch ncomment">         */
1696e" name="L408"> 468        in *var-btypa href="+code=debtypar" ca==8"sref">var-BT_ALPINE  489
169ne" name="L4888888888return 0ame="L44/"> 487        ,  to8switch ncomment">         */
169ne" name="L498"> 468        in *var-btypa href="+code=debtypar" ca==8"sref">var-BT_GD548sfb.c#L480ode=deBT_GD548sref""ame="L489"> 489
169ne" name="L499"> 499 487        ,  to8switch ncomment">         */
170se" name="L448"> Hz\n"var-btypa href="+code=debtypar" ca==8"sref">var-BT_PICASSOfb.c#L464ode=deBT_PICASSOref""sref">maxclock) {
170ne" name="L501"> 501<8">  Hz\n"        IsOn(        on(        IsOn( 489
170ne" name="L411111111111111111 sref">cinfo        a> *0xff"           return 1;
170ne" name="L383"> 383170ne" name="L404"> 474        }
170ne" name="L408"> Hz\n"maxclock) {
170ne" name="L446"> 446var-btypa href="+code=debtypar" c"sref">maxclock) {
170ne" name="L4888888888casa "sref">var-BT_SDusfb.c#L464ode=deBT_SDusref":ef">maxclock) {
170ne" name="L491111111111111111 sref">cinfo        a> *Hz\n"var-SFR(0x21"           return 1;
170ne" name="L499"> 499<<<<<<<<171se" name="L4488888888casa "sref">var-BT_PICCOLOfb.c#L464ode=deBT_PICCOLOref":ef">maxclock) {
171ne" name="L501"> 501<11111111 sref">cinfo        a> *Hz\n"var-SFR(0x28"           return 1;
171ne" name="L411111111111111111break           return 1;
171ne" name="L383"> 383var-BT_SPECTRUMfb.c#L464ode=deBT_SPECTRUMref":ef">maxclock) {
171ne" name="L404"> 404<11111111 sref">cinfo        a> *0x6f"           return 1;
171ne" name="L40ame="L4411111111break           return 1;
171ne" name="L446"> 446 487        ,  ncomment"1break           return 1;
171ne" name="L48888888884"> 474        }
171ne" name="L49}8elsesref">maxclock) {
171ne" name="L499"> 499var-btypa href="+code=debtypar" c"sref">maxclock) {
172se" name="L4488888888casa "sref">var-BT_SDusfb.c#L464ode=deBT_SDusref":ef">maxclock) {
172ne" name="L501"> 501<11111111 sref">cinfo        a> *Hz\n"var-SFR(172ne" name="L411111111111111111break           return 1;
172ne" name="L383"> 383var-BT_PICCOLOfb.c#L464ode=deBT_PICCOLOref":ef">maxclock) {
172ne" name="L404"> 404<11111111 sref">cinfo        a> *Hz\n"var-SFR(172ne" name="L40ame="L4411111111break           return 1;
172ne" name="L446"> 446var-BT_SPECTRUMfb.c#L464ode=deBT_SPECTRUMref":ef">maxclock) {
172ne" name="L488888888811111111 sref">cinfo        a> *0x4f"           return 1;
172ne" name="L491111111111111111break           return 1;
172ne" name="L499"> 499 487        ,  ncomment"          return 1;
173se" name="L448888888811111111break           return 1;
173ne" name="L501"> 501<4"> 474        }
173ne" name="L414"> 474        }
173ne" n#endif0/"> 487        173ne" n4"> 474        }
173ne" n"> 474        }
173ne" n/"> 487        173ne" n/"> 487                 */
173ne" n/"> 487        173ne" name="L489"> 489
174se" nstatic int0468        inf="dri_synca href="+code=cinf="dri_synce" n struct0468        ri_> *        > * 489
174ne" nref">maxclock) {
174ne" name="L41struct0468        inf="dri_> * *        a> *var-> *var-par(1743e" name="L489"> 489
174ne" name="L408"> !468        is_lagunafb.c#L464ode=deis_lagunae" n 468        a> *maxclock) {
174ne" name="L40ame="L44while  468        vga_rgfx(        a> *var-argbasa href="+code=deargbasar" c kHz\n" 489
174ne" name="L446"> 446<11111111 sref">cinfo1747e" name="L494"> 474        }
174ne" name="L49return 0           return 1;
174ne" n4"> 474        }
175se" n"> 474        }
1751e" nstatic void0 sref">cinfo        ri_> *        > * 474        }
175ne" name="L411111111111111111111111const1struct0468        ri_fillrect(        rrgion( 489
175ne" nref">maxclock) {
175ne" name="L40struct0468        ri_fillrect(        modded(175ne" name="L40int0468        vxres(175ne" name="L44struct0468        inf="dri_> * *        a> *var-> *var-par(175ne" name="L48int0468        m(var-> *var-var(var-bits_per_pixel href="+code=debits_per_pixel cla           return 1;
175ne" name="L490"> 490    uusfb.c#L432ode=deu3ne" na468        aolora href="+code=ciolor cla =8 468        > *var-fix(var-visual href="+code=devisual cla ==8"sref">var-FB_VISUAL_TRUECOLOR href="+code=deFB_VISUAL_TRUECOLOR cla) ?          return 1;
175ne" name="L499"> 499<468        a> *var-pseudo_palette(var-aolora href="+code=ciolor cla] :<468        rrgion(var-aolora href="+code=ciolor cla           return 1;
176se" n"> 474        }
1761e" name="L388"> Hz\n" *var-state(var-FBINFO_STATE_RUNNING href="+code=deFBINFO_STATE_RUNNING cla)ame="L489"> 489
176ne" name="L4111111111return           return 1;
176ne" name="L388"> Hz\n" *var-flags(var-FBINFO_HWACCEL_DISABLEDfb.c#L464ode=deFBINFO_HWACCEL_DISABLEDr" c"sref">maxclock) {
176ne" name="L404"> 404<"sref">var-ari_fillrect(        > *        rrgion(176ne" name="L40ame="L44return           return 1;
176ne" name="L444"> 474        }
1767e" name="L494"> 494
176ne" name="L490"> 490    vxres(var-> *var-var(var-xres_virtual href="+code=dexres_virtual cla           return 1;
176ne" name="L49 sref">cinfovar-> *var-var(var-yres_virtual href="+code=deyres_virtual cla           return 1;
177se" n"> 474        }
1771e" name="L38 sref">cinfo        modded(        ri_fillrect(1772e" name="L494"> 494
177ne" name="L388"> !468        modded(var-width(        modded(var-height( 494
177ne" name="L404">468        modded(var-dx(var-vxres(        modded(var-dy(var-vyres( 489
177ne" name="L40ame="L44return           return 1;
177ne" name="L486"> 486
177ne" name="L488"> Hz\n"var-dx(        modded(var-width(var-vxres( 489
177ne" name="L4911111111468        modded(var-width(var-vxres(468        modded(var-dx(177ne" name="L498"> Hz\n"var-dy(        modded(var-height(var-vyres( 489
178se" name="L4488888888468        modded(var-height(var-vyres(468        modded(var-dy(1781e" n          return 1;
178ne" name="L410"> 490    inf="dri_RectFilla href="+code=cinf="dri_RectFille" n 468        a> *var-argbasa href="+code=deargbasar" c           return 1;
178ne" name="L383"> 383<4488888888468        > *var-var(var-bits_per_pixel href="+code=debits_per_pixel cla           return 1;
178ne" name="L404"> 404<11111111 > Hz\n"var-dx(        m(var-dy(178ne" name="L40ame="L4411111111 > Hz\n"var-width(        m(var-height(178ne" name="L446"> 446<11111111410"> 490    iolora href="+code=ciolor cla,>Hz\n"178ne" name="L48888888881111111188468        > *var-fix(var-" id_length(0x40"           return 1;
178ne" n4"> 474        }
178ne" name="L489"> 489
179se" nstatic void0 sref">cinfo        ri_> *        > * 474        }
179ne" name="L501"> 501<11111111111111const1struct0468        ri_copyareafb.c#L464ode=deri_copyareae" na*468        areafb.c#L464ode=deareae" n)ame="L489"> 489
179ne" nref">maxclock) {
179ne" name="L38struct0468        ri_copyareafb.c#L464ode=deri_copyareae" na468        modded(179ne" name="L400"> 490    uusfb.c#L432ode=deu3ne" na468        vxres(179ne" name="L40struct0468        inf="dri_> * *        a> *var-> *var-par(1796e" name="L408nt0468        m(var-> *var-var(var-bits_per_pixel href="+code=debits_per_pixel cla           return 1;
1797e" name="L494"> 494
179ne" name="L498"> 468        > *var-state(var-FBINFO_STATE_RUNNING href="+code=deFBINFO_STATE_RUNNING cla)ame="L489"> 489
179ne" name="L499"> 499 489
180se" name="L448"> Hz\n" *var-flags(var-FBINFO_HWACCEL_DISABLEDfb.c#L464ode=deFBINFO_HWACCEL_DISABLEDr" c"sref">maxclock) {
180ne" name="L501"> 501<"sref">var-ari_copyareafb.c#L464ode=deiri_copyareae" n 468        > *        areafb.c#L464ode=deareae" n) ame="L489"> 489
180ne" name="L4111111111return ame="L489"> 489
180ne" name="L384"> 474        }
180ne" n"> 474        }
180ne" name="L40 sref">cinfovar-> *var-var(var-xres_virtual href="+code=dexres_virtual cla           return 1;
180ne" name="L44468        vyres(var-> *var-var(var-yres_virtual href="+code=deyres_virtual cla           return 1;
180ne" name="L48"sref">var-memcpy(        modded(        ri_copyareafb.c#L464ode=deri_copyareae" n)"           return 1;
180ne" n>         */
180ne" name="L498"> !468        modded(var-width(        modded(var-height( 494
181se" name="L44888468        modded(var-sx(var-vxres(        modded(var-sy(var-vyres( 494
181ne" name="L501">Hz\n"var-dx(var-vxres(        modded(var-dy(var-vyres( 489
181ne" name="L4111111111return ame="L489"> 489
1813e" name="L489"> 489
181ne" name="L408"> Hz\n"var-sx(        modded(var-width(var-vxres( 489
181ne" name="L40ame="L44468        modded(var-width(var-vxres(468        modded(var-sx( 489
1816e" name="L408"> 468        modded(var-dx(        modded(var-width(var-vxres( 489
181ne" name="L4888888888468        modded(var-width(var-vxres(468        modded(var-dx(181ne" name="L498"> 468        modded(var-sy(        modded(var-height(var-vyres( 489
181ne" name="L499"> 499<468        modded(var-height(var-vyres(468        modded(var-sy(182se" name="L448"> Hz\n"var-dy(        modded(var-height(var-vyres( 489
182ne" name="L501"> 501<468        modded(var-height(var-vyres(468        modded(var-dy(1822e" name="L494"> 494
182ne" name="L38468        inf="dri_BitBLTa href="+code=cinf="dri_BitBLTe" n 468        a> *var-argbasa href="+code=deargbasar" c kHz\n" *var-var(var-bits_per_pixel href="+code=debits_per_pixel cla,"> 474        }
182ne" name="L404"> 404<11111111 468        areafb.c#L464ode=deareae" nlass="sref">var-sx(        m(var-sy( 474        }
182ne" name="L40ame="L4411111111 468        areafb.c#L464ode=deareae" nlass="sref">var-dx(        m(var-dy(182ne" name="L446"> 446<11111111 468        areafb.c#L464ode=deareae" nlass="sref">var-width(        m(var-height(182ne" name="L488888888811111111 sref">cinfo *var-fix(var-" id_length(182ne" n>         */
182ne" n4"> 474        }
183se" n"> 474        }
1831e" nstatic void0 sref">cinfo        ri_> *        > * 474        }
183ne" name="L4111111111111111111111111const1struct0468        ri_imagea href="+code=cri_>magee" na*468        >magea href="+code=c>magee" n)ame="L489"> 489
183ne" nref">maxclock) {
183ne" name="L40struct0468        inf="dri_> * *        a> *var-> *var-par(183ne" name="L40unsigned char8"sref">var-op(var-var(var-bits_per_pixel href="+code=debits_per_pixel cla ==824) ? 0xc :>0x4           return 1;
183ne" name="L486"> 486
183ne" name="L488"> Hz\n" *var-state(var-FBINFO_STATE_RUNNING href="+code=deFBINFO_STATE_RUNNING cla)ame="L489"> 489
183ne" name="L4911111111return ame="L489"> 489
183ne" name="L49 "> 487                 */
184se" name="L448"> Hz\n" *var-flags(var-FBINFO_HWACCEL_DISABLEDfb.c#L464ode=deFBINFO_HWACCEL_DISABLEDr" c ||0468        >magea href="+code=c>magee" nlass="sref">var-depth( 489
184ne" name="L501"> 501<"sref">var-ari_imageblit(        > *        >magea href="+code=c>magee" n"           return 1;
184ne" name="L41elses8">  Hz\n"var-btypa href="+code=debtypar" ca==8"sref">var-BT_ALPINE         in *var-btypa href="+code=debtypar" ca==8"sref">var-BT_SDusfb.c#L464ode=deBT_SDusref") &&          return 1;
184ne" name="L383"> 383<44"sref">var-op( 489
184ne" name="L404"> 404<"sref">var-ari_imageblit(        > *        >magea href="+code=c>magee" n"           return 1;
184ne" name="L40elsesref">maxclock) {
184ne" name="L446"> 446var-size(magee" nlass="sref">var-width(        >magea href="+code=c>magee" nlass="sref">var-height(184ne" name="L48888888888nt0468        m(var-> *var-var(var-bits_per_pixel href="+code=debits_per_pixel cla           return 1;
184ne" name="L4911111111468        uusfb.c#L432ode=deu3ne" na468        fg(184ne" name="L489"> 489
185se" name="L44888888888"> Hz\n" *var-var(var-bits_per_pixel href="+code=debits_per_pixel cla ==88"sref">maxclock) {
185ne" name="L501"> 501<11111111 sref">cinfovar->magea href="+code=c>magee" nlass="sref">var-fg_iolora href="+code=cfg_iolor cla           return 1;
185ne" name="L411111111111111111468        bg(var->magea href="+code=c>magee" nlass="sref">var-bg_iolora href="+code=cbg_iolor cla           return 1;
185ne" name="L383"> 383<}8elsesref">maxclock) {
185ne" name="L404"> 404<11111111 sref">cinfo *var-pseudo_palette(magee" nlass="sref">var-fg_iolora href="+code=cfg_iolor cla]           return 1;
185ne" name="L40ame="L4411111111468        bg( *var-pseudo_palette(magee" nlass="sref">var-bg_iolora href="+code=cbg_iolor cla]           return 1;
185ne" name="L446"> 446<4"> 474        }
185ne" name="L48888888888"> Hz\n" *var-var(var-bits_per_pixel href="+code=debits_per_pixel cla ==824) ref">maxclock) {
185ne" name="L4911111111111111114"> 487                 */
185ne" name="L499"> 499<11111111468        inf="dri_RectFilla href="+code=cinf="dri_RectFille" n 468        a> *var-argbasa href="+code=deargbasar" c           return 1;
186se" name="L448888888811111111499"> 499<11111111468        > *var-var(var-bits_per_pixel href="+code=debits_per_pixel cla           return 1;
186ne" name="L501"> 501<11111111111111111111111111 468        >magea href="+code=c>magee" nlass="sref">var-dx(        m(magee" nlass="sref">var-dy(186ne" name="L411111111111111111111111111111111111 468        >magea href="+code=c>magee" nlass="sref">var-width(        m(186ne" name="L383"> 383<44888888889"> 499<11111111468        >magea href="+code=c>magee" nlass="sref">var-height(186ne" name="L404"> 404<44888888889"> 499<11111111468        bg(186ne" name="L40ame="L4444888888889"> 499<11111111468        > *var-fix(var-" id_length(0x40"           return 1;
186ne" name="L446"> 446<4"> 474        }
186ne" name="L4888888888468        inf="dri_RectFilla href="+code=cinf="dri_RectFille" n 468        a> *var-argbasa href="+code=deargbasar" c           return 1;
186ne" name="L4911111111111111119<11111111468        > *var-var(var-bits_per_pixel href="+code=debits_per_pixel cla           return 1;
186ne" name="L499"> 499<111111111111111111 468        >magea href="+code=c>magee" nlass="sref">var-dx(        m(magee" nlass="sref">var-dy(187se" name="L448888888811111111499"> 499< 468        >magea href="+code=c>magee" nlass="sref">var-width(        m(magee" nlass="sref">var-height(187ne" name="L501"> 501<111111111111111111468        fg(187ne" name="L4111111111111111111111111111468        > *var-fix(var-" id_length("sref">var-op(187ne" name="L383"> 383<468        memcpy(        > *var-screen_basa href="+code=descreen_basa cla,0468        >magea href="+code=c>magee" nlass="sref">var-datafb.c#L464ode=dedata cla,0468        size(187ne" name="L404"> 474        }
187ne" n4"> 474        }
187ne" name="L486"> 486
187ne" n#ifdef0468        CONFIG_PPC_PREP( 486
187ne" n#def id0468        PREP_VIDEO_BASE 0xC0000000)ame="L489"> 489
187ne" n#def id0468        PREP_IO_BASE 0x80000000)ame="L489"> 489
188se" nstatic void0 sref">cinfo        display( 489
188ne" nref">maxclock) {
188ne" name="L41*468        display(var-PREP_VIDEO_BASE 188ne" name="L38*468        rrgisters(188ne" n4"> 474        }
188ne" n"> 474        }
188ne" n#endif111111111111111111111111114"> 487                 */
1887e" name="L494"> 494
188ne" n#ifdef0468        CONFIG_PCI( 494
188ne" nstatic 8nt0468        releasa_io_ports(189se" n"> 474        }
189ne" n4"> 487                 */
189ne" n4"> 487                 */
189ne" n4"> 487                 */
189ne" n4"> 487                 */
189ne" nstatic unsigned 8nt0468        __devinit(        ri_> *        > * 474        }
189ne" name="L446"> 446<11111111411111111111111111111111111468        u8a href="+code=cu8 cla 468        __iomem(        argbasa href="+code=deargbasar" c"ame="L489"> 489
1897e" nref">maxclock) {
189ne" name="L49unsigned longa468        mem(189ne" name="L49struct0468        inf="dri_> * *        a> *var-> *var-par(190se" n"> 474        }
1901e" name="L388"> Hz\n"s_lagunafb.c#L464ode=de>s_lagunae" n 468        a> *maxclock) {
190ne" name="L4111111111unsigned char8"sref">var-SR1sfb.c#L464ode=deSR1s cla =8"sref">var-vga_rseq(        argbasa href="+code=deargbasar" c kHz\n"1903e" name="L489"> 489
190ne" name="L404"> 404<"sref">var-mem(        SR1sfb.c#L464ode=deSR1s cla & 7) + 1) << 20           return 1;
190ne" name="L40}8elsesref">maxclock) {
190ne" name="L446"> 446var-SRFfb.c#L464ode=deSRF cla =8"sref">var-vga_rseq(        argbasa href="+code=deargbasar" c kHz\n"190ne" name="L4888888888switch8  468        SRFfb.c#L464ode=deSRF cla & 0x18)) ref">maxclock) {
190ne" name="L4911111111casa 0x08:ef">maxclock) {
190ne" name="L499"> 499<11111111468        mem(191se" name="L448888888888888888break           return 1;
191ne" name="L501">11111casa 0x10:ef">maxclock) {
191ne" name="L411111111111111111468        mem(191ne" name="L383"> 383<44888888break           return 1;
191ne" name="L404"> 404<""> 487        ume 2MB.omment">         */
191ne" n4"> 487                 */
1916e" n4"> 487                 */
191ne" name="L4888888888casa 0x18:ef">maxclock) {
191ne" name="L491111111111111111468        mem(191ne" name="L499"> 499<44888888break           return 1;
192se" name="L4488888888default:ef">maxclock) {
192ne" name="L501"> 501<11111111468        dev_warn(        > *var-devica href="+code=dedevicar" c kH"> 487  string">"Unknown memory size!\n"omment""           return 1;
192ne" name="L411111111111111111468        mem(192ne" name="L383"> 383<}          return 1;
192ne" name="L404"> 404<""> 487                 */
192ne" n4"> 487                 */
1926e" n4"> 487                 */
192ne" name="L48888888888"> Hz\n"var-btypa href="+code=debtypar" ca!=8"sref">var-BT_ALPINE  Hz\n" 489
192ne" name="L491111111111111111468        mem(192ne" name="L49}          return 1;
193se" n"> 474        }
193ne" name="L50""> 487                 */
193ne" name="L41returna468        mem(193ne" n}          return 1;
193ne" n"> 474        }
193ne" nstatic void0 sref">cinfo        pci_dev(        pdev( 474        }
193ne" name="L446"> 446<1111111141unsigned longa*468        display( 489
1937e" nref">maxclock) {
193ne" name="L49468        #L4ert(        pdev(var-NULL(193ne" name="L49 68        #L4ert(        display(var-NULL(194se" name="L44 68        #L4ert(        rrgisters(var-NULL(194ne" n          return 1;
194ne" name="L41*468        display(194ne" name="L38*468        rrgisters(194ne" n"> 474        }
194ne" name="L40""> 487                 */
194ne" name="L486"> 486
194ne" name="L488"> Hz\n"        pdev(var-IORESOURCE_IO(maxclock) {
194ne" name="L4911111111*468        display(var-pci_resource_start(        pdev(194ne" name="L499"> 499<*468        rrgisters(var-pci_resource_start(        pdev(195se" name="L44}8elsesref">maxclock) {
195ne" name="L501"> 501<*468        display(var-pci_resource_start(        pdev(195ne" name="L4111111111*468        rrgisters(var-pci_resource_start(        pdev(195ne" name="L38}          return 1;
195ne" n"> 474        }
195ne" name="L40 68        #L4ert(        display(195ne" n}          return 1;
1957e" name="L494"> 494
195ne" nstatic void0 sref">cinfo        ri_> *        > * 489
195ne" nref">maxclock) {
196se" name="L44struct0468        pci_dev(        pdev(var-to_pci_dev(        > *var-devica href="+code=dedevicar" c)           return 1;
196ne" name="L50struct0468        inf="dri_> * *        a> *var-> *var-par(1962e" name="L494"> 494
196ne" name="L388"> Hz\n"var-laguna_mmivar-NULL( 494
196ne" name="L404"> 404<"sref">var->ounmap(        in *var-laguna_mmi196ne" name="L40 68        >ounmap(        > *var-screen_basa href="+code=descreen_basa cla)           return 1;
196ne" n#8">00""> 487        system didn't87         */
196ne" name="L48468        rrleasa_mem_rrgion(196ne" n#endif          return 1;
196ne" name="L498"> Hz\n" 494
197se" name="L4488888888Hz\n"197ne" name="L50"sref">var-pci_releasa_rrgions(        pdev(197ne" n}          return 1;
197ne" n#endif14"> 487                 */
197ne" n"> 474        }
197ne" n#ifdef0468        CONFIG_ZORRO( 474        }
197ne" nstatic void0 sref">cinfo        ri_> *        > * 489
1977e" nref">maxclock) {
197ne" name="L49struct0468        inf="dri_> * *        a> *var-> *var-par(197ne" name="L49struct0468        zorro_dev(        zdev(var-to_zorro_dev(        > *var-devica href="+code=dedevicar" c)           return 1;
198se" n"> 474        }
1981e" name="L388"> Hz\n" *var-fix(var-smem_start(        MB_( 489
198ne" name="L4111111111 68        >ounmap(        > *var-screen_basa href="+code=descreen_basa cla)           return 1;
198ne" name="L388"> Hz\n" *var-fix(var-mmi<_start(        MB_( 489
198ne" name="L404"> 404<"sref">var->ounmap(        in *var-argbasa href="+code=deargbasar" c"           return 1;
198ne" n"> 474        }
198ne" name="L44468        zorro_releasa_devica href="+code=dezorro_releasa_devicae" n 468        zdev(1987e" n}          return 1;
198ne" n#endif14"> 487                 */
198ne" name="L489"> 489
199se" n4"> 487                 */
1991e" nstatic struct0468        ri_ops(        inf="dri_ops(maxclock) {
199ne" name="L41."sref">var-owner(var-THIS_MODULE maxclock) {
1993e" name="L41."sref">var-ri_open(var-inf="dri_open(maxclock) {
1994e" name="L41."sref">var-ri_releasa(var-inf="dri_releasa(maxclock) {
1995e" name="L41."sref">var-ri_setcolarg(var-inf="dri_setcolarg(maxclock) {
199ne" name="L44."sref">var-ri_check_var(var-inf="dri_check_var(maxclock) {
1997e" name="L41."sref">var-ri_set_par(var-inf="dri_set_par(maxclock) {
199ne" name="L49."sref">var-ri_ent_display(var-inf="dri_pnt_display(maxclock) {
199ne" name="L49."sref">var-ri_blank(var-inf="dri_blank(maxclock) {
2000e" name="L49."sref">var-ri_fillarct(var-inf="dri_fillarct(f">maxclock) {
2001e" name="L44."sref">var-ri_copyareafb.c#L464ode=deri_copyareae" name==8"sref">var-inf="dri_copyareafb.c#L464ode=deinf="dri_copyareae" n,ef">maxclock) {
200ne" name="L41."sref">var-ri_sync(var-inf="dri_sync(maxclock) {
2003e" name="L41."sref">var-ri_imageblit(var-inf="dri_imageblit(maxclock) {
200ne" n4           return 1;
200ne" n"> 474        }
200ne" nstatic 8nt0468        __devinit( * *        ri_> *        > * 489
2007e" nref">maxclock) {
200ne" name="L49struct0468        inf="dri_> * *        a> *var-> *var-par(200ne" name="L49struct0468        ri_var_screen> *        var(var-> *var-var(20use" n"> 474        }
20une" name="L50"sref">var-> *var-pseudo_palette(var-in *var-pseudo_palette(20u2e" name="L50"sref">var-> *var-flags(var-FBINFO_DEFAULT( 474        }
20une" name="L383"> 383<4488|8"sref">var-FBINFO_HWACCEL_XPAN( 474        }
20une" name="L404"> 404<4488|8"sref">var-FBINFO_HWACCEL_YPAN( 474        }
20une" name="L40ame="L444488|8"sref">var-FBINFO_HWACCEL_FILLRECT( 474        }
20une" name="L446"> 446<1111|8"sref">var-FBINFO_HWACCEL_IMAGEBLIT( 474        }
20une" name="L48888888881111|8"sref">var-FBINFO_HWACCEL_COPYAREA(20une" name="L498"> Hz\n"var->s_lagunafb.c#L464ode=de>s_lagunae" n 468        a> *maxclock) {
20une" name="L499"> 499<"sref">var-> *var-flags(var-FBINFO_HWACCEL_DISABLED(20use" name="L499"> 499<"sref">var-> *var-fix(var-accel href="+code=deaccele" na=8"sref">var-FB_ACCEL_NONE 20une" name="L50}8else          return 1;
20une" name="L4111111111 68        > *var-fix(var-accel href="+code=deaccele" na=8"sref">var-FB_ACCEL_CIRRUS_ALPINE 20u3e" name="L489"> 489
20une" name="L40 68        > *var-fbops(var-inf="dri_ops(20une" n"> 474        }
20u6e" name="L498"> Hz\n"var-btypa href="+code=debtypar" ca==8"sref">var-BT_GD54usfb.c#L480ode=deBT_GD54us cla) ref">maxclock) {
20une" name="L48888888888"> Hz\n"var-bits_per_pixel href="+code=debits_per_pixel cla ==816"ame="L489"> 489
20une" name="L491111111111111111468        > *var-screen_basa href="+code=descreen_basa cla +=81a*0468        MB_(20une" name="L499"> 499<8"> Hz\n"var-bits_per_pixel href="+code=debits_per_pixel cla ==832"ame="L489"> 489
20use" name="L491111111111111111468        > *var-screen_basa href="+code=descreen_basa cla +=82a*0468        MB_(20une" name="L50}          return 1;
20u2e" name="L494"> 494
20une" name="L384"> 487                 */
20une" name="L40 68        strlcpy(        > *var-fix(var-ida href="+code=cnde" n,8"sref">var-inf="dri_board_> * *var-btypa href="+code=debtypar" c]."sref">var-L434 href="+code=den434e" n,ef">maxclock) {
20une" name="L40ame="L44sizeof 468        > *var-fix(var-ida href="+code=cnde" n)"           return 1;
20une" name="L486"> 486
20u7e" name="L384"> 487                 */
20u8e" name="L384"> 487                 */
20une" name="L49 68        > *var-fix(var-smem_len(var-> *var-screen_size(20use" name="L498"> Hz\n"var-bits_per_pixel href="+code=debits_per_pixel cla ==81"ame="L489"> 489
20une" name="L501"> 501< 68        > *var-fix(var-smem_len(20u2e" name="L50"sref">var-> *var-fix(var-typa_aux(20u3e" name="L50"sref">var-> *var-fix(var-xentstep(20une" name="L40 68        > *var-fix(var-yentstep(20une" name="L40 68        > *var-fix(var-ywrapstep(20une" name="L486"> 486
20u7e" name="L384"> 487        available, fill in here ncomment">         */
20une" name="L49468        > *var-fix(var-mmi<_len(20une" name="L489"> 489
20use" name="L49468        ri_alloc_cmap(var-> *var-cmap(20une" n          return 1;
20une" name="L41returna0           return 1;
20une" n}          return 1;
20une" n"> 474        }
20une" nstatic 8nt0468        __devinit(        ri_> *        > * 489
20une" nref">maxclock) {
20u7e" name="L38struct0468        inf="dri_> * *        a> *var-> *var-par(20une" name="L498nt0468        err(20une" name="L489"> 489
20use" name="L384"> 487                 */
20une" name="L50"sref">var-aL4ert(        in *var-btypa href="+code=debtypar" ca!=8"sref">var-BT_NONE 20u2e" name="L494"> 494
20une" name="L384"> 487                 */
20une" name="L40 68        inf="dri_set_fb> * *        > *20une" n"> 474        }
20une" name="L44468        dev_dbg(        > *var-devica href="+code=dedevicar" c kH"> 487  string">"(RAM0start set to: 0x%p)\n"omment",8"sref">var-> *var-screen_basa href="+code=descreen_basa cla)           return 1;
20u7e" name="L494"> 494
20une" name="L49468        err(var-ri_find_m/a>a href="+code=cri_find_m/a>e" n &"sref">var-> *var-var(var-> *var-m/a>_option(var-NULL(var-NULL(20une" name="L498"> !468        err(maxclock) {
20use" name="L501"> 501< 68        dev_dbg(        > *var-devica href="+code=dedevicar" c kH"> 487  string">"wrongainitial8{
\n"omment""           return 1;
20une" name="L501"> 501< 68        err(20une" name="L4111111111goto< 68        err_dealloc_cmap(20une" name="L38}          return 1;
20une" n"> 474        }
20une" name="L40 68        > *var-var(var-activate(var-FB_ACTIVATE_NOW(20une" name="L486"> 486
20une" name="L48468        err(var-inf="dri_check_var(var-> *var-var(var-> *20une" name="L498"> Hz\n"maxclock) {
20une" name="L499"> 499<""> 487         happen ncomment">         */
20use" name="L501"> 501< 68        dev_dbg(        > *var-devica href="+code=dedevicar" c >         */
20une" name="L501"> 501<111111114"> 487  string">"chokingaon8default var... umm, no1good.\n"omment""           return 1;
20une" name="L4111111111goto< 68        err_dealloc_cmap(20une" name="L38}          return 1;
20une" n"> 474        }
20une" name="L40 68        err(var-rrgister_fr485buffera href="+code=crrgister_fr485buffere" n 468        > *20u6e" name="L498"> Hz\n"maxclock) {
20une" name="L4888888888 68        dev_err(        > *var-devica href="+code=dedevicar" c >         */
20une" name="L4911111111111111114"> 487  string">"could not rrgister fb devica; err =8%d!\n"omment",8"sref">var-err(20une" name="L499"> 499        err_dealloc_cmap(20use" name="L38}          return 1;
20une" n          return 1;
20une" name="L41returna0           return 1;
20u3e" name="L489"> 489
20une" n 68        err_dealloc_cmap( 489
20une" name="L40 68        ri_dealloc_cmap(var-> *var-cmap(20u6e" name="L41returna468        err(20u7e" n}          return 1;
20u8e" name="L489"> 489
20u9e" nstatic void0 sref">cinfo        ri_> *        > * 489
2100e" nref">maxclock) {
210ne" name="L50struct0468        inf="dri_> * *        a> *var-> *var-par(2102e" name="L494"> 494
2103e" name="L50"sref">var-switch_monitor(        in *210ne" name="L40 68        unrrgister_fr485buffera href="+code=cunrrgister_fr485buffere" n 468        > *210ne" name="L40 68        ri_dealloc_cmap(var-> *var-cmap(210ne" name="L44468        dev_dbg(        > *var-devica href="+code=dedevicar" c kH"> 487  string">"Fr485buffer unrrgistered\n"omment""           return 1;
210ne" name="L48468        in *var-unmap(        > *210ne" name="L49468        fr485buffer_releasa(        > *210ne" n}          return 1;
21use" n"> 474        }
21une" n#ifdef0468        CONFIG_PCIa href="+code=cCONFIG_PCIe" n"> 474        }
21u2e" nstatic 8nt0468        __devinit(        pci_dev(        pdev(         */
21une" name="L383"> 383<448888888888888888888888888const4struct0468        pci_devica_ida href="+code=cpci_devica_ide" na*468           489
21une" nref">maxclock) {
21une" name="L40struct0468        inf="dri_> * *        a> *21une" name="L44struct0468        ri_> *        > *21une" name="L48unsigned longa468        board_addra href="+code=cboard_addr cla,8"sref">var-board_size(211ne" name="L498nt0468        re211ne" name="L489"> 489
212se" name="L49468        revar-pci_enable_devica href="+code=depci_enable_devicae" n 468        pdev(2121e" name="L388"> Hz\n"maxclock) {
21une" name="L4111111111 68        printk(        KERN_ERR( 487  string">"cef="dri: Cannot enable PCI devica\n"omment""           return 1;
212ne" name="L383"> 383        err_ou21une" name="L40}          return 1;
21une" n"> 474        }
212ne" name="L44468        > *var-rr485buffer_alloc(        inf="dri_> * *var-pdev(var-dev href="+code=dedeve" n)           return 1;
21une" name="L488"> !468        > *maxclock) {
21une" name="L4911111111 68        printk(        KERN_ERR( 487  string">"cef="dri: could not allocate memory\n"omment""           return 1;
21une" name="L499"> 499<468        re21use" name="L4911111111goto< 68        err_ou21une" name="L50}          return 1;
21u2e" name="L494"> 494
2133e" name="L50"sref">var-a> *var-> *var-par(21une" name="L40 68        in *var-btypa href="+code=debtypar" ca= (enum0468        inf="d_boarda href="+code=cinf="d_board cla" 468          var-deturn_datafb.c#L464ode=dedeturn_data cla           return 1;
213ne" n"> 474        }
213ne" name="L44468        dev_dbg(        > *var-devica href="+code=dedevicar" c "> 474        }
213ne" name="L4888888888 "> 487  string">" Found PCI devica, basa address 0 is 0x%Lx, btypa set to8%d\n"omment","> 474        }
213ne" name="L4911111111(unsigned longalong)"sref">var-pdev(var-resourca href="+code=deresourcae" n[0]."sref">var-start(        in *var-btypa href="+code=debtypar" c"           return 1;
21une" name="L49 68        dev_dbg(        > *var-devica href="+code=dedevicar" c 8 "> 487  string">" basa address 1 is 0x%Lx\n"omment","> 474        }
214se" name="L4911111111(unsigned longalong)"sref">var-pdev(var-resourca href="+code=deresourcae" n[1]."sref">var-start(214ne" n          return 1;
21u2e" name="L508"> Hz\n"sPRePa href="+code=cnsPReP cla" ref">maxclock) {
214ne" name="L383"> 383<"sref">var-pci_write_config_dworda href="+code=cpci_write_config_dworde" n 468        pdev(var-PCI_BASE_ADDRESS_sfb.c#L480ode=dePCI_BASE_ADDRESS_s cla,80x00000000"           return 1;
21une" n#ifdef0468        CONFIG_PPC_PREPa href="+code=cCONFIG_PPC_PREPe" n          return 1;
214ne" name="L40ame="L44468        get_prep_addrs(var-board_addra href="+code=cboard_addr cla,8&"sref">var-> *var-fix(var-mmi<_start(21une" n#endif          return 1;
21u7e" name="L384"> 487        we ioremap the IO rrgisters, but it works w/ou<... ncomment">         */
214ne" name="L4911111111 68        in *var-argbasa href="+code=deargbasar" ca= (char0468        __iomem(        > *var-fix(var-mmi<_start(214ne" name="L49}8else ref">maxclock) {
215se" name="L501"> 501< 68        dev_dbg(        > *var-devica href="+code=dedevicar" c >         */
215ne" name="L501"> 501<111111114"> 487  string">"Attempt to8get PCI nfo" for Cef="d Graphics Card\n"omment""           return 1;
215ne" name="L4111111111 68        get_pci_addrs(        pdev(var-board_addra href="+code=cboard_addr cla,8&"sref">var-> *var-fix(var-mmi<_start(215ne" name="L383"> 383<""> 487                 */
215ne" name="L404"> 404< 68        in *var-argbasa href="+code=deargbasar" ca= "sref">var-NULL(215ne" name="L40ame="L44468        in *var-laguna_mmivar->oremapa href="+code=cnoremape" n 468        > *var-fix(var-mmi<_start(215ne" name="L44}          return 1;
2157e" name="L494"> 494
215ne" name="L49468        dev_dbg(        > *var-devica href="+code=dedevicar" c 14"> 487  string">"Board address: 0x%lx, rrgister address: 0x%lx\n"omment","> 474        }
215ne" name="L499"> 499<468        board_addra href="+code=cboard_addr cla,8"sref">var-> *var-fix(var-mmi<_start(216se" n"> 474        }
21une" name="L50"sref">var-board_size(var-btypa href="+code=debtypar" ca==8"sref">var-BT_GD54usfb.c#L480ode=deBT_GD54us cla) ?"> 474        }
216ne" name="L411111111132a*0468        MB_(        > *var-in *var-argbasa href="+code=deargbasar" c"           return 1;
2163e" name="L489"> 489
21une" name="L40 68        revar-pci_request_rrgions(        pdev( 487  string">"cef="dri"omment""           return 1;
216ne" name="L408"> Hz\n"maxclock) {
216ne" name="L446"> 446<468        dev_err(        > *var-devica href="+code=dedevicar" c 8""> 487  string">"cannot reserve rrgion 0x%lx, abort\n"omment","> 474        }
216ne" name="L48888888881111499<468        board_addra href="+code=cboard_addr cla"           return 1;
216ne" name="L4911111111goto< 68        err_releasa_fbs21une" name="L49}          return 1;
21use" n#8">0<""> 487        the system didn't87we would... ncomment">         */
2171e" name="L388"> !468        request_mem_rrgions 487  string">"cef="dri"omment"") ref">maxclock) {
21une" name="L4111111111468        dev_err(        > *var-devica href="+code=dedevicar" c 8""> 487  string">"cannot reserve rrgion 0x%lx, abort\n"omment","> 474        }
217ne" name="L383"> 383<448888880xA0000L"           return 1;
217ne" name="L404"> 404< 68        re217ne" name="L40ame="L44goto< 68        err_releasa_rrgions(217ne" name="L44}          return 1;
21une" n#endif          return 1;
21une" name="L498"> Hz\n" 487  string">"cef="dri"omment"")          return 1;
21une" name="L499"> 499<"z\n"218se" n"> 474        }
218ne" name="L50"sref">var-> *var-screen_basa href="+code=descreen_basa cla =8"sref">var->oremapa href="+code=cnoremape" n 468        board_addra href="+code=cboard_addr cla,8"sref">var-board_size(2182e" name="L508"> !468        > *var-screen_basa href="+code=descreen_basa cla) ref">maxclock) {
218ne" name="L383"> 383<"sref">var-re218ne" name="L404"> 404        err_releasa_legacy(21une" name="L40}          return 1;
218ne" name="L486"> 486
218ne" name="L48468        > *var-fix(var-smem_start(var-board_addra href="+code=cboard_addr cla           return 1;
218ne" name="L49468        > *var-screen_size(var-board_size(218ne" name="L49 68        in *var-unmap(var-inf="dri_pci_unmap(219se" n"> 474        }
219ne" name="L50"sref">var-dev_n *        > *var-devica href="+code=dedevicar" c >         */
219ne" name="L41111111118""> 487  string">"Cef="d Logic chipset on PCI bus, RAM0(%lu kB) at 0x%lx\n"omment","> 474        }
219ne" name="L383"> 383<4468        > *var-screen_size(var-board_addra href="+code=cboard_addr cla"           return 1;
219ne" name="L40 68        pci_set_drvdatafb.c#L464ode=depci_set_drvdatae" n 468        pdev(        > *219ne" n"> 474        }
219ne" name="L44468        revar-inf="dri_rrgistera href="+code=cinf="dri_rrgistere" n "68        > *219ne" name="L488"> !468        re219ne" name="L4911111111returna0           return 1;
219ne" name="L489"> 489
220se" name="L49468        pci_set_drvdatafb.c#L464ode=depci_set_drvdatae" n 468        pdev(        NULL(220ne" name="L50"sref">var->ounmap(        > *var-screen_basa href="+code=descreen_basa cla)           return 1;
2202e" n 68        err_releasa_legacy( 489
2203e" name="L508"> Hz\n"220ne" name="L404"> 404< 68        releasa_rrgion(220ne" n#8">0          return 1;
220ne" name="L44468        releasa_mem_rrgions220ne" n 68        err_releasa_rrgions( 489
220ne" n#endif          return 1;
220ne" name="L49 68        pci_releasa_rrgions(        pdev(22use" n 68        err_releasa_fbs 489
2211e" name="L388"> Hz\n"var-laguna_mmivar-NULL( 489
221ne" name="L4111111111468        >ounmap(        in *var-laguna_mmi2213e" name="L50"sref">var-fr485buffer_releasa(        > *221ne" n 68        err_ou 489
22une" name="L40returna468        re22une" n}          return 1;
2217e" name="L494"> 494
221ne" nstatic void0 sref">cinfo        pci_dev(        pdev( 489
221ne" nref">maxclock) {
222se" name="L49struct0468        ri_> *        > *var-pci_get_drvdatafb.c#L464ode=depci_get_drvdatae" n 468        pdev(222ne" n          return 1;
22une" name="L41468        inf="dri_cleanup(        > *222ne" n}          return 1;
222ne" n"> 474        }
22une" nstatic struct0468        pci_d     (maxclock) {
222ne" name="L44."sref">var-L426( 487  string">"cef="dri"omment","> 474        }
22une" name="L48."sref">var-id_tablea href="+code=cnd_tablee" name="L4=8"sref">var-inf="dri_pci_tablea href="+code=cinf="dri_pci_tabler" c >         */
22une" name="L49."sref">var-probea href="+code=cprobee" name="L4111=8"sref">var-inf="dri_pci_registera href="+code=cinf="dri_pci_registere" n >         */
22une" name="L49."sref">var-remova href="+code=dearmovae" name="L411=8"sref">var-__devexit_p(        inf="dri_pci_unregistera href="+code=cinf="dri_pci_unregistere" n) >         */
223se" n#8"def0468        CONFIG_PMs 474        }
223ne" n#if>0          return 1;
2232e" name="L49."sref">var-suspenda href="+code=csuspende" name="L49=8"sref">var-inf="dri_pci_suspenda href="+code=cinf="dri_pci_suspende" n >         */
2233e" name="L50."sref">var-resu26(var-inf="dri_pci_resu26(         */
22une" n#endif          return 1;
223ne" n#endif          return 1;
223ne" n}           return 1;
223ne" n#endif<""> 487                 */
2238e" name="L489"> 489
22une" n#8"def0468        CONFIG_ZORROs 489
224se" nstatic 8nt0468        __devinit(        zorro_dev(        z(         */
224ne" name="L501"> 501<11111111111111111111111111111const4struct0468        zorro_devica_ida href="+code=czorro_devica_ide" na*468           489
22u2e" nref">maxclock) {
224ne" name="L38struct0468        ri_> *        > *224ne" name="L408nt0468        error(224ne" name="L40const4struct0468        zorrocla href="+code=czorrocle" na*468        zcla href="+code=czcle" n           return 1;
224ne" name="L44enum0468        inf="d_boarda href="+code=cinf="d_board cla8"sref">var-btypa href="+code=debtypar" c           return 1;
224ne" name="L48unsigned longa468        argbasa href="+code=deargbasar" c,8"68        ramsize(        rambasa href="+code=deaambasar" c           return 1;
224ne" name="L49struct0468        inf="dri_> * *        a> *224ne" name="L489"> 489
225se" name="L49468        > *var-rr485buffer_alloc(        inf="dri_> * *var-z(var-dev href="+code=dedeve" n)           return 1;
2251e" name="L388"> !468        > *maxclock) {
225ne" name="L4111111111 68        printk(        KERN_ERR( 487  string">"cef="dri: could not allocate memory\n"omment""           return 1;
225ne" name="L383"> 383        ENOMEMs225ne" name="L40}          return 1;
225ne" n"> 474        }
225ne" name="L44468        zcla href="+code=czcle" na= (const4struct0468        zorrocla href="+code=czorrocle" na*)"sref">var-  var-deturn_datafb.c#L464ode=dedeturn_data cla           return 1;
225ne" name="L48468        btypa href="+code=debtypar" ca= 468        zcla href="+code=czcle" nlass="sref">var-typa href="+code=detypar" c           return 1;
225ne" name="L49468        argbasa href="+code=deargbasar" ca= "sref">var-zorro_resourca_start(        z(        zcla href="+code=czcle" nlass="sref">var-argoffse225ne" name="L49 68        ramsize(        zcla href="+code=czcle" nlass="sref">var-ramsize(2260e" name="L388"> "sref">var-ramsize(maxclock) {
226ne" name="L501"> 501<"68        rambasa href="+code=deaambasar" ca= "sref">var-zorro_resourca_start(        z(        zcla href="+code=czcle" nlass="sref">var-aamoffse226ne" name="L41111111118"> "sref">var-zorro_resourca_lens        z(        MB_(maxclock) {
226ne" name="L383"> 383<44888888""> 487        o IV ncomment">         */
226ne" name="L404"> 404<1"> 501<"68        rambasa href="+code=deaambasar" ca+= 468        zcla href="+code=czcle" nlass="sref">var-ramoffse226ne" name="L40ame="L40}          return 1;
226ne" name="L44}8else ref">maxclock) {
226ne" name="L4888888888struct0468        zorro_dev(        ramsvar-zorro_find_devica href="+code=dezorro_find_devicae" n 468        zcla href="+code=czcle" nlass="sref">var-ramida href="+code=cramidr" c,8"68        NULL(226ne" name="L49111111118"> !468        rams        zorro_resourca_lens        ramsmaxclock) {
226ne" name="L499"> 499<1"> 501<"68        dev_err(        > *var-devica href="+code=dedevicar" c 8""> 487  string">"No {
227se" name="L501"> 501<1"> 501<"68        error(227ne" name="L501"> 501<11111111goto< 68        err_releasa_fbs22une" name="L4111111111}          return 1;
227ne" name="L383"> 383<"68        rambasa href="+code=deaambasar" ca= "sref">var-zorro_resourca_start(        rams227ne" name="L404"> 404< 68        ramsize(        zorro_resourca_lens        rams227ne" name="L40ame="L448"> "sref">var-zcla href="+code=czcle" nlass="sref">var-ramid2a href="+code=cramidne" na&&          return 1;
227ne" name="L446"> 446<<<<< 468        ramsvar-zorro_find_devica href="+code=dezorro_find_devicae" n 468        zcla href="+code=czcle" nlass="sref">var-ramid2a href="+code=cramidne" n,8"68        NULL(maxclock) {
227ne" name="L48888888881111499<8"> "sref">var-zorro_resourca_start(        ramsvar-rambasa href="+code=deaambasar" ca+< 68        ramsize(maxclock) {
227ne" name="L4911111111ame="L404"> 404< 68        dev_warns        > *var-devica href="+code=dedevicar" c ef">maxclock) {
22une" name="L499"> 499<911111111ame="L404"> 404< "> 487  string">"Skipping non-contiguous RAM0at8%pR\n"omment","> 474        }
228se" name="L501"> 501<1"> 501<<<<<<<<<<<<<<<<<<&"sref">var-ramsvar-resourca href="+code=deresourcae" n"           return 1;
228ne" name="L501"> 501<11111111}8else ref">maxclock) {
228ne" name="L41111111118me="L404"> 404< 68        ramsize(        zorro_resourca_lens        rams228ne" name="L383"> 383<11111111}          return 1;
228ne" name="L404"> 404<}          return 1;
22une" name="L40}          return 1;
228ne" name="L486"> 486
228ne" name="L48468        dev_n *        > *var-devica href="+code=dedevicar" c >         */
228ne" name="L4911111111a "> 487  string">"%s board detected, REG at 0x%lx, %lu MiB RAM0at80x%lx\n"omment","> 474        }
228ne" name="L499"> 499<9468        inf="dri_board_> * *        btypa href="+code=debtypar" c]."sref">var-L426(        rrgbasa href="+code=deargbasar" c,8"68        ramsize(        MB_( 474        }
229se" name="L501"> 501<1"sref">var-rambasa href="+code=deaambasar" c"           return 1;
229ne" n          return 1;
2292e" name="L508"> !468        zorro_request_devica href="+code=dezorro_request_devicae" n 468        z( 487  string">"cef="dri"omment"") ref">maxclock) {
229ne" name="L383"> 383<"68        dev_err(        > *var-devica href="+code=dedevicar" c 8""> 487  string">"Cannot reserve %pR\n"omment",8&"sref">var-z(var-resourca href="+code=deresourcae" n"           return 1;
229ne" name="L404"> 404< 68        error(229ne" name="L40ame="L44goto< 68        err_releasa_fbs229ne" name="L44}          return 1;
2297e" name="L494"> 494
229ne" name="L49468        a> *var-> *var-pa (229ne" name="L49 68        in *var-btypa href="+code=debtypar" ca= 468        btypa href="+code=debtypar" c           return 1;
230se" n"> 474        }
230ne" name="L50"sref">var-> *var-fix(var-mmi<_start(        rrgbasa href="+code=deargbasar" c           return 1;
230ne" name="L41468        in *var-argbasa href="+code=deargbasar" ca= "sref">var-argbasa href="+code=deargbasar" caass= 16a*0468        MB_(var->oremapa href="+code=cnoremape" n 468        rrgbasa href="+code=deargbasar" c,864a*01024"ame="L489"> 489
230ne" name="L383"> 383<1111111111111111111111111111:> Hz\n"        rrgbasa href="+code=deargbasar" c"           return 1;
230ne" name="L408"> !468        in *var-argbasa href="+code=deargbasar" c" ref">maxclock) {
230ne" name="L40ame="L44468        dev_err(        > *var-devica href="+code=dedevicar" c 8""> 487  string">"Cannot map rrgisters\n"omment""           return 1;
230ne" name="L446"> 446<468        error(230ne" name="L4888888888goto< 68        err_releasa_dev(230ne" name="L49}          return 1;
230ne" name="L489"> 489
231se" name="L49468        > *var-fix(var-smem_start(var-rambasa href="+code=deaambasar" c           return 1;
231ne" name="L50"sref">var-> *var-screen_size(var-ramsize(231ne" name="L41468        > *var-screen_basa href="+code=descreen_basa cla =8"sref">var-rambasa href="+code=deaambasar" caass= 16a*0468        MB_(var->oremapa href="+code=cnoremape" n 468        rambasa href="+code=deaambasar" c,8"68        ramsize( 489
231ne" name="L383"> 383<1111111111111111111111111111111:> Hz\n"        rambasa href="+code=deaambasar" c"           return 1;
231ne" name="L408"> !468        > *var-screen_basa href="+code=descreen_basa cla) ref">maxclock) {
231ne" name="L40ame="L44468        dev_err(        > *var-devica href="+code=dedevicar" c 8""> 487  string">"Cannot map {
231ne" name="L446"> 446<468        error(231ne" name="L4888888888goto< 68        err_unmap_reg(231ne" name="L49}          return 1;
231ne" name="L489"> 489
232se" name="L49468        in *var-unmap(var-inf="dri_zorro_unmap(232ne" n          return 1;
23une" name="L41468        dev_n *        > *var-devica href="+code=dedevicar" c >         */
232ne" name="L383"> 383<44"> 487  string">"Cef="d Logic chipset on Zorro bus, RAM0(%lu MiB) at 0x%lx\n"omment","> 474        }
232ne" name="L404"> 404<1"68        ramsize(        MB_(var-rambasa href="+code=deaambasar" c"           return 1;
232ne" n"> 474        }
232ne" name="L44""> 487                 */
232ne" name="L488"> 468        inf="dri_board_> * *        btypa href="+code=debtypar" c]."sref">var-init_sr1fa href="+code=cnfit_sr1fr" c"ame="L489"> 489
232ne" name="L4911111111"sref">var-vga_wseqa href="+code=cvga_wseqe" n 468        in *var-argbasa href="+code=deargbasar" c,1"sref">var-CL_SEQR1F href="+code=deCL_SEQR1Fr" c >         */
232ne" name="L499"> 499<911111111468        inf="dri_board_> * *        btypa href="+code=debtypar" c]."sref">var-sr1fa href="+code=csr1fr" c"           return 1;
233se" n"> 474        }
233ne" name="L50"sref">var-error(        > *2332e" name="L508"> "sref">var-error(maxclock) {
233ne" name="L383"> 383<"68        dev_err(        > *var-devica href="+code=dedevicar" c 8""> 487  string">"Failed to         */
233ne" name="L404"> 404<1"> 501<"68        error(233ne" name="L40ame="L44goto< 68        err_unmap_rams233ne" name="L44}          return 1;
2337e" name="L494"> 494
233ne" name="L49468        zorro_set_drvdatafb.c#L464ode=dezorro_set_drvdatae" n 468        z(        > *233ne" name="L49returna0           return 1;
234se" n"> 474        }
234ne" n 68        err_unmap_rams 489
2342e" name="L508"> "sref">var-rambasa href="+code=deaambasar" caass= 16a*0468        MB_( 489
234ne" name="L383"> 383<"68        >ounmap(        > *var-screen_basa href="+code=descreen_basa cla)           return 1;
234ne" n"> 474        }
234ne" n 68        err_unmap_reg( 489
234ne" name="L448"> Hz\n"        MB_( 489
234ne" name="L4888888888"68        >ounmap(        in *var-argbasa href="+code=deargbasar" c"           return 1;
234ne" n 68        err_releasa_dev( 489
234ne" name="L49 68        zorro_releasa_devica href="+code=dezorro_releasa_devicae" n 468        z(235se" n 68        err_releasa_fbs 489
235ne" name="L50"sref">var-fr485buffer_releasa(        > *235ne" name="L41returna468        error(235ne" n}          return 1;
235ne" n"> 474        }
235ne" nvoid0 sref">cinfo        zorro_dev(        z( 489
235ne" nref">maxclock) {
235ne" name="L48struct0468        ri_> *        > *var-zorro_get_drvdatafb.c#L464ode=dezorro_get_drvdatae" n 468        z(2358e" name="L489"> 489
235ne" name="L49 68        inf="dri_cleanup(        > *236se" name="L49468        zorro_set_drvdatafb.c#L464ode=dezorro_set_drvdatae" n 468        z(        NULL(236ne" n}          return 1;
236ne" n          return 1;
236ne" nstatic struct0468        zorro_deturn(maxclock) {
236ne" name="L40."sref">var-L426( 487  string">"cef="dri"omment","> 474        }
236ne" name="L40."sref">var-id_tablea href="+code=cnd_tablee" name="L4=8"sref">var-inf="dri_zorro_tablea href="+code=cinf="dri_zorro_tabler" c >         */
236ne" name="L44."sref">var-probea href="+code=cprobee" name="L4111=8"sref">var-inf="dri_zorro_registera href="+code=cinf="dri_zorro_registere" n >         */
236ne" name="L48."sref">var-remova href="+code=dearmovae" name="L411=8"sref">var-__devexit_p(        inf="dri_zorro_unregistera href="+code=cinf="dri_zorro_unregistere" n) >         */
236ne" n}           return 1;
236ne" n#endif<""> 487                 */
237se" n"> 474        }
237ne" n#ifndef0468        MODULE( 474        }
23une" nstatic 8nt0468        __init(        options( 489
237ne" nref">maxclock) {
237ne" name="L40chara*468        this_opt(237ne" n"> 474        }
237ne" name="L448"> !468        options(        options( 489
237ne" name="L4888888888returna0           return 1;
2378e" name="L489"> 489
23une" name="L49while ( 468        this_opt(var-strsep(var-options( 487  string">","omment"") !=8"sref">var-NULL(maxclock) {
238se" name="L501"> 501<8"> !*468        this_opt( 489
238ne" name="L501"> 501<11111111continue           return 1;
238ne" n          return 1;
238ne" name="L383"> 383<8"> !468        strcmp(        this_opt( 487  string">"noaccel"omment"")          return 1;
238ne" name="L404"> 404<<<<<<<<<"sref">var-Loaccel(238ne" name="L40ame="L44else 8"> !468        strncmp(        this_opt( 487  string">"m   :"omment",85")          return 1;
238ne" name="L446"> 446<<<<<<<<<"sref">var-m   _option(var-this_opt(238ne" name="L4888888888else          return 1;
238ne" name="L4911111111a<<<<<<<"sref">var-m   _option(var-this_opt(238ne" name="L49}          return 1;
239se" name="L50returna0           return 1;
239ne" n}          return 1;
2392e" n#endif          return 1;
239ne" n          return 1;
239ne" name=""> 487                 */
239ne" n""> 487                 */
239ne" n""> 487                 */
2397e" name="L494"> 494
239ne" n 68        MODULE_AUTHOR( 487  string">"Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.   ass="omment""           return 1;
239ne" n 68        MODULE_DESCRIPTION( 487  string">"Accelerated FBDev return for Cef="d Logic chips"omment""           return 1;
240se" n 68        MODULE_LICENSE( 487  string">"GPL"omment""           return 1;
240ne" n          return 1;
240ne" nstatic 8nt0468        __init(240ne" nref">maxclock) {
240ne" name="L408nt0468        error(240ne" n"> 474        }
240ne" n#ifndef0468        MODULE( 474        }
240ne" name="L48chara*468        option(var-NULL(2408e" name="L489"> 489
240ne" name="L498"> Hz\n" 487  string">"cef="dri"omment",8&"sref">var-option(241se" name="L501"> 501        ENODEVs241ne" name="L50"sref">var-inf="dri_setup(var-option(2412e" n#endif          return 1;
241ne" n          return 1;
241ne" n#ifdef0468        CONFIG_ZORRO(241ne" name="L40468        error(var-inf="dri_zorro_deturn(241ne" n#endif          return 1;
241ne" n#ifdef0468        CONFIG_PCI(241ne" name="L49468        error(var-inf="dri_pci_deturn(2419e" n#endif          return 1;
242se" name="L50returna468        error(242ne" n}          return 1;
242ne" n          return 1;
242ne" nstatic void0 sref">cinfo242ne" nref">maxclock) {
242ne" n#ifdef0468        CONFIG_PCI(242ne" name="L44468        pci_unregister_deturn(var-inf="dri_pci_deturn(242ne" n#endif          return 1;
242ne" n#ifdef0468        CONFIG_ZORRO(242ne" name="L49 68        zorro_unregister_deturn(var-inf="dri_zorro_deturn(243se" n#endif          return 1;
243ne" n}          return 1;
243ne" n          return 1;
243ne" n"sref">var-m  ule_init(        inf="dri_init(243ne" n"> 474        }
243ne" n 68        m  ule_params        m   _option(        charp(243ne" n 68        MODULE_PARM_DESC(        m   _option( 487  string">"Initial {
2437e" n 68        m  ule_params        Loaccel(        bool(243ne" n 68        MODULE_PARM_DESC(        Loaccel( 487  string">"Disable acceleration"omment""           return 1;
243ne" name="L489"> 489
244se" n#ifdef0468        MODULE( 474        }
244ne" n 68        m  ule_exit(        inf="dri_exit(2442e" n#endif          return 1;
244ne" n          return 1;
244ne" n""> 487                 */
244ne" n""> 487                 */
244ne" n""> 487                 */
244ne" n""> 487                 */
244ne" n "> 487                 */
244ne" n""> 487                 */
245se" n"> 474        }
245ne" n""> 487                 */
245ne" nstatic void0 sref">cinfo        inf="dri_in* *        in *         */
245ne" name="L383"> 383<118nt0468        rrgnums         */
245ne" nref">maxclock) {
245ne" name="L40unsigned long 468        rrgofs(245ne" name="L486"> 486
245ne" name="L488"> 468        in *var-btypa href="+code=debtypar" ca== 468        BT_PICASSO(maxclock) {
245ne" name="L4911111111""> 487        o II specific hack<*comment">         */
245ne" n""> 487         383<118"> rrgnuma== VGA_PEL_IRa|| rrgnuma== VGA_PEL_Da||omment">         */
246se" n""> 487                 */
246ne" name="L501"> 501<8"> Hz\n"        rrgnums         */
246ne" name="L41111111118me="L40468        rrgofs(246ne" name="L38}          return 1;
246ne" n"> 474        }
246ne" name="L40468        vga_w(        in *var-argbasa href="+code=deargbasar" c,1"sref">var-rrgofs(        val(246ne" n}          return 1;
2467e" name="L494"> 494
246ne" n "> 487                 */
246ne" nstatic unsigned chara468        RGen(        inf="dri_in* *        in *        rrgnums         */
247se" nref">maxclock) {
247ne" name="L50unsigned long 468        rrgofs(247ne" n          return 1;
247ne" name="L388"> 468        in *var-btypa href="+code=debtypar" ca== 468        BT_PICASSO(maxclock) {
247ne" name="L404"> 404<""> 487        o II specific hack<*comment">         */
247ne" n""> 487         383<118"> rrgnuma== VGA_PEL_IRa|| rrgnuma== VGA_PEL_Da||omment">         */
247ne" n""> 487                 */
247ne" name="L48888888888"> Hz\n"        rrgnums         */
247ne" name="L4911111111a<<<<<<<"sref">var-rrgofs(247ne" name="L49}          return 1;
248se" n"> 474        }
248ne" name="L50returna468        vga_n(        in *var-argbasa href="+code=deargbasar" c,1"sref">var-rrgofs(248ne" n}          return 1;
248ne" n          return 1;
248ne" n""> 487                 */
248ne" nstatic void0 sref">cinfo        inf="dri_in* *        in *         */
248ne" nref">maxclock) {
248ne" name="L48468        #L4ert(        in *var-NULL(2488e" name="L489"> 489
248ne" name="L498"> Hz\n"        in *var-argbasa href="+code=deargbasar" c,1"sref">var-CL_CRTusfb.c#L414"+codeCL_CRTuse" n"8&80x80"8ref">maxclock) {
249se" name="L501"> 501<""> 487        we're just in "write value" m   , write back         */
249ne" name="L501"> 501<""> 487                 */
249ne" name="L4111111111468        vga_w(        in *var-argbasa href="+code=deargbasar" c,1"sref">var-VGA_ATT_IWs249ne" name="L383"> 383<111111468        vga_n(        in *var-argbasa href="+code=deargbasar" c,1"sref">var-VGA_ATT_Rs249ne" name="L40}          return 1;
249ne" name="L404"> 487                 */
249ne" n""> 487         vga_w(info"lass=argbasa, VGA_ATT_IW,80x20); ncomment">         */
249ne" name="L48468        vga_w(        in *var-argbasa href="+code=deargbasar" c,1"sref">var-VGA_ATT_IWs2498e" name="L489"> 489
2499e" name="L404"> 487                 */
250se" name="L49468        vga_w(        in *var-argbasa href="+code=deargbasar" c,1"sref">var-VGA_ATT_IWs250ne" n}          return 1;
250ne" n          return 1;
250ne" n""> 487