linux/drivers/ssb/driver_chipcommon.c
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> /spaon> /formn> a > href="../linux+v3.7.2/drivers/ssb/driver_chipcommon.c"> > img src="../.static/gfx/right.png" alt=">>"> /spaon> spao class="lxr_search"> > > input typue=hidden" namue=navtarget" value="> > input typue=text" namue=search" ide=search"> > buttiontypue=submit">Search /formn> /spaon> spao class="lxr_prefs"n> a href="+prefs?return=drivers/ssb/driver_chipcommon.c" > onclick="return ajax_prefs();"> > Prefs> /a> /spaon> > /divn> > form acptio="ajax+*" method="post" onsubmit="return false;"> input typue=hidden" namue=ajax_lookup" ide=ajax_lookup" value="> > /formn> > div class="headingbottim"> > > div ide=search_results" class="search_results"> n> > /divn> div ide=content">> div ide=file_contents"n
   1 /a> spao class="comment">/* /spaon>   2 /a> spao class="comment"> * Sonics SilicionBackplane /spaon>   3 /a> spao class="comment"> * Broadcom ChipCommon core driver /spaon>   4 /a> spao class="comment"> * /spaon>   5 /a> spao class="comment"> * Copyright 2005, Broadcom Corporaptio /spaon>   6 /a> spao class="comment"> * Copyright 2006, 2007, Michael Buesch <m@bues.ch> /spaon>   7 /a> spao class="comment"> * /spaon>   8 /a> spao class="comment"> * Licensed under the GNU/GPL. See COPYING for details. /spaon>   9 /a> spao class="comment"> */ /spaon>  9  11 /a>#include <linux/ssb/ssb.h /a>>>  12 /a>#include <linux/ssb/ssb_regs.h /a>>>  13 /a>#include <linux/export.h /a>>>  14 /a>#include <linux/pci.h /a>>>  15/oan>  16 /a>#include "ssb_private.h /a>">  17/oan>  18/oan>  19 /a> spao class="comment">/* Clock sources */ /spaon>  2ssb_clksrc/oan {>  21 /a>         spao class="comment">/* PCI clock */ /spaon>  22 /a>         a href="+code=SSB_CHIPCO_CLKSRC_PCI" class="sref">SSB_CHIPCO_CLKSRC_PCI /a>,>  23 /a>         spao class="comment">/* Crystal slow clock oscillator */ /spaon>  24 /a>         a href="+code=SSB_CHIPCO_CLKSRC_XTALOS" class="sref">SSB_CHIPCO_CLKSRC_XTALOS /a>,>  25 /a>         spao class="comment">/* Low power oscillator */ /spaon>  26 /a>         a href="+code=SSB_CHIPCO_CLKSRC_LOPWROS" class="sref">SSB_CHIPCO_CLKSRC_LOPWROS /a>,>  27/oan};>  28/oan>  29/oan>  3inline /a>  a href="+code=u32" class="sref">u32 /a>  a href="+code=chipco_write32_masked" class="sref">chipco_write32_masked /a>(struct  a href="+code=ssb_chipcommon" class="sref">ssb_chipcommon /a> * a href="+code=cc" class="sref">cc/oan,  a href="+code=u16" class="sref">u16 /a>  a href="+code=offset" class="sref">offset /a>,>  31 /a>                                         a href="+code=u32" class="sref">u32 /a>  a href="+code=mask" class="sref">mask/oan,  a href="+code=u32" class="sref">u32 /a>  a href="+code= valu" class="sref"> valu /a>)>  32 /a>{>  33 /a>         a href="+code= valu" class="sref"> valu /a> &=  a href="+code=mask" class="sref">mask/oan;>  34 /a>         a href="+code= valu" class="sref"> valu /a> |=  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=offset" class="sref">offset /a>) & ~ a href="+code=mask" class="sref">mask/oan;>  35 /a>         a href="+code=chipco_write32" class="sref">chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=offset" class="sref">offset /a>,  a href="+code= valu" class="sref"> valu /a>);>  36/oan>  37 /a>        return  a href="+code= valu" class="sref"> valu /a>;>  38/oan}>  39/oan>  4ssb_chipco_set_clockmode /a>(struct  a href="+code=ssb_chipcommon" class="sref">ssb_chipcommon /a> * a href="+code=cc" class="sref">cc/oan,>  41 /a>                              enum  a href="+code=ssb_clkmode" class="sref">ssb_clkmode /a>  a href="+code=mode" class="sref">mode /a>)>  42 /a>{>  43 /a>        struct  a href="+code=ssb_device" class="sref">ssb_device /a> * a href="+code=ccdev" class="sref">ccdev /a> =  a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>;>  44 /a>        struct  a href="+code=ssb_bus" class="sref">ssb_bus /a> * a href="+code=bus" class="sref">bus /a>;>  45 /a>         a href="+code=u32" class="sref">u32 /a>  a href="+code=tmp" class="sref">tmp /a>;>  46/oan>  47 /a>        if (! a href="+code=ccdev" class="sref">ccdev /a>)>  48 /a>                return;>  49 /a>         a href="+code=bus" class="sref">bus /a> =  a href="+code=ccdev" class="sref">ccdev /a>-> a href="+code=bus" class="sref">bus /a>;>  5  51 /a>         spao class="comment">/* We support SLOW only on 6..9 */ /spaon>  52 /a>        if ( a href="+code=ccdev" class="sref">ccdev /a>-> a href="+code=id" class="sref">id /a>. a href="+code=revision" class="sref">revision /a> >= 10 &&  a href="+code=mode" class="sref">mode /a> ==  a href="+code=SSB_CLKMODE_SLOW" class="sref">SSB_CLKMODE_SLOW /a>)>  53 /a>                 a href="+code=mode" class="sref">mode /a> =  a href="+code=SSB_CLKMODE_DYNAMIC" class="sref">SSB_CLKMODE_DYNAMIC /a>;>  54/oan>  55 /a>        if ( a href="+code=cc" class="sref">cc/oan-> a href="+code=capabilities" class="sref">capabilities /a> &  a href="+code=SSB_CHIPCO_CAP_PMU" class="sref">SSB_CHIPCO_CAP_PMU /a>)>  56 /a>                return;  spao class="comment">/* PMU controls clockmode, separated funcptio needed */ /spaon>  57 /a>         a href="+code=SSB_WARN_ON" class="sref">SSB_WARN_ON /a>( a href="+code=ccdev" class="sref">ccdev /a>-> a href="+code=id" class="sref">id /a>. a href="+code=revision" class="sref">revision /a> >= 20);>  58/oan>  59 /a>         spao class="comment">/* chipcommon cores prior to rev6 don't support dynamic clock control */ /spaon>  60 /a>        if ( a href="+code=ccdev" class="sref">ccdev /a>-> a href="+code=id" class="sref">id /a>. a href="+code=revision" class="sref">revision /a> < 6)>  61 /a>                return;>  62/oan>  63 /a>         spao class="comment">/* ChipCommon cores rev10+ need testing */ /spaon>  64 /a>        if ( a href="+code=ccdev" class="sref">ccdev /a>-> a href="+code=id" class="sref">id /a>. a href="+code=revision" class="sref">revision /a> >= 10)>  65 /a>                return;>  66/oan>  67 /a>        if (!( a href="+code=cc" class="sref">cc/oan-> a href="+code=capabilities" class="sref">capabilities /a> &  a href="+code=SSB_CHIPCO_CAP_PCTL" class="sref">SSB_CHIPCO_CAP_PCTL /a>))>  68 /a>                return;>  69/oan>  70 /a>        switch ( a href="+code=mode" class="sref">mode /a>) {>  71 /a>        case  a href="+code=SSB_CLKMODE_SLOW" class="sref">SSB_CLKMODE_SLOW /a>:  spao class="comment">/* For revs 6..9 only */ /spaon>  72 /a>                 a href="+code=tmp" class="sref">tmp /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SLOWCLKCTL" class="sref">SSB_CHIPCO_SLOWCLKCTL /a>);>  73 /a>                 a href="+code=tmp" class="sref">tmp /a> |=  a href="+code=SSB_CHIPCO_SLOWCLKCTL_FSLOW" class="sref">SSB_CHIPCO_SLOWCLKCTL_FSLOW /a>;>  74 /a>                 a href="+code=chipco_write32" class="sref">chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SLOWCLKCTL" class="sref">SSB_CHIPCO_SLOWCLKCTL /a>,  a href="+code=tmp" class="sref">tmp /a>);>  75 /a>                break;>  76 /a>        case  a href="+code=SSB_CLKMODE_FAST" class="sref">SSB_CLKMODE_FAST /a>:>  77 /a>                if ( a href="+code=ccdev" class="sref">ccdev /a>-> a href="+code=id" class="sref">id /a>. a href="+code=revision" class="sref">revision /a> < 10) {>  78 /a>                         a href="+code=ssb_pci_xtal" class="sref">ssb_pci_xtal /a>( a href="+code=bus" class="sref">bus /a>,  a href="+code=SSB_GPIO_XTAL" class="sref">SSB_GPIO_XTAL /a>, 1);  spao class="comment">/* Force crystal on */ /spaon>  79 /a>                         a href="+code=tmp" class="sref">tmp /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SLOWCLKCTL" class="sref">SSB_CHIPCO_SLOWCLKCTL /a>);>  80 /a>                         a href="+code=tmp" class="sref">tmp /a> &= ~ a href="+code=SSB_CHIPCO_SLOWCLKCTL_FSLOW" class="sref">SSB_CHIPCO_SLOWCLKCTL_FSLOW /a>;>  81 /a>                         a href="+code=tmp" class="sref">tmp /a> |=  a href="+code=SSB_CHIPCO_SLOWCLKCTL_IPLL" class="sref">SSB_CHIPCO_SLOWCLKCTL_IPLL /a>;>  82 /a>                         a href="+code=chipco_write32" class="sref">chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SLOWCLKCTL" class="sref">SSB_CHIPCO_SLOWCLKCTL /a>,  a href="+code=tmp" class="sref">tmp /a>);>  83 /a>                } else {>  84 /a>                         a href="+code=chipco_write32" class="sref">chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SYSCLKCTL" class="sref">SSB_CHIPCO_SYSCLKCTL/oan,>  85 /a>                                ( a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SYSCLKCTL" class="sref">SSB_CHIPCO_SYSCLKCTL/oan) |>  86 /a>                                  a href="+code=SSB_CHIPCO_SYSCLKCTL_FORCEHT" class="sref">SSB_CHIPCO_SYSCLKCTL_FORCEHT /a>));>  87 /a>                         spao class="comment">/* udelay(150); TODO: not available in early init */ /spaon>  88 /a>                }>  89 /a>                break;>  90 /a>        case  a href="+code=SSB_CLKMODE_DYNAMIC" class="sref">SSB_CLKMODE_DYNAMIC /a>:>  91 /a>                if ( a href="+code=ccdev" class="sref">ccdev /a>-> a href="+code=id" class="sref">id /a>. a href="+code=revision" class="sref">revision /a> < 10) {>  92 /a>                         a href="+code=tmp" class="sref">tmp /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SLOWCLKCTL" class="sref">SSB_CHIPCO_SLOWCLKCTL /a>);>  93 /a>                         a href="+code=tmp" class="sref">tmp /a> &= ~ a href="+code=SSB_CHIPCO_SLOWCLKCTL_FSLOW" class="sref">SSB_CHIPCO_SLOWCLKCTL_FSLOW /a>;>  94 /a>                         a href="+code=tmp" class="sref">tmp /a> &= ~ a href="+code=SSB_CHIPCO_SLOWCLKCTL_IPLL" class="sref">SSB_CHIPCO_SLOWCLKCTL_IPLL /a>;>  95 /a>                         a href="+code=tmp" class="sref">tmp /a> &= ~ a href="+code=SSB_CHIPCO_SLOWCLKCTL_ENXTAL" class="sref">SSB_CHIPCO_SLOWCLKCTL_ENXTAL /a>;>  96 /a>                        if (( a href="+code=tmp" class="sref">tmp /a> &  a href="+code=SSB_CHIPCO_SLOWCLKCTL_SRC" class="sref">SSB_CHIPCO_SLOWCLKCTL_SRC/oan) !=>  97 /a>                             a href="+code=SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL" class="sref">SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL /a>)>  98 /a>                                 a href="+code=tmp" class="sref">tmp /a> |=  a href="+code=SSB_CHIPCO_SLOWCLKCTL_ENXTAL" class="sref">SSB_CHIPCO_SLOWCLKCTL_ENXTAL /a>;>  99 /a>                         a href="+code=chipco_write32" class="sref">chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SLOWCLKCTL" class="sref">SSB_CHIPCO_SLOWCLKCTL /a>,  a href="+code=tmp" class="sref">tmp /a>);> 100/oan> 101 /a>                         spao class="comment">/* For dynamic control, we have to release our xtal_pu /spaon> 102 /a> spao class="comment">                         * "force on" */ /spaon> 103 /a>                        if ( a href="+code=tmp" class="sref">tmp /a> &  a href="+code=SSB_CHIPCO_SLOWCLKCTL_ENXTAL" class="sref">SSB_CHIPCO_SLOWCLKCTL_ENXTAL /a>)> 104 /a>                                 a href="+code=ssb_pci_xtal" class="sref">ssb_pci_xtal /a>( a href="+code=bus" class="sref">bus /a>,  a href="+code=SSB_GPIO_XTAL" class="sref">SSB_GPIO_XTAL /a>, 0);> 105 /a>                } else {> 106 /a>                         a href="+code=chipco_write32" class="sref">chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SYSCLKCTL" class="sref">SSB_CHIPCO_SYSCLKCTL/oan,> 107 /a>                                ( a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SYSCLKCTL" class="sref">SSB_CHIPCO_SYSCLKCTL/oan) &> 108 /a>                                 ~ a href="+code=SSB_CHIPCO_SYSCLKCTL_FORCEHT" class="sref">SSB_CHIPCO_SYSCLKCTL_FORCEHT /a>));> 109 /a>                }> 110 /a>                break;> 111 /a>        default:> 112 /a>                 a href="+code=SSB_WARN_ON" class="sref">SSB_WARN_ON /a>(1);> 113 /a>        }> 114 /a>}> 115/oan> 116 /a> spao class="comment">/* Get the Slow Clock Source */ /spaon> 117/oanstatic enum  a href="+code=ssb_clksrc" class="sref">ssb_clksrc/oan  a href="+code=chipco_pctl_get_slowclksrc" class="sref">chipco_pctl_get_slowclksrc /a>(struct  a href="+code=ssb_chipcommon" class="sref">ssb_chipcommon /a> * a href="+code=cc" class="sref">cc/oan)> 118/oan{> 119 /a>        struct  a href="+code=ssb_bus" class="sref">ssb_bus /a> * a href="+code=bus" class="sref">bus /a> =  a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>-> a href="+code=bus" class="sref">bus /a>;> 120 /a>         a href="+code=u32" class="sref">u32 /a>  a href="+code=uninitialized_var" class="sref">uninitialized_var /a>( a href="+code=tmp" class="sref">tmp /a>);> 121 /a>> 122 /a>        if ( a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>-> a href="+code=id" class="sref">id /a>. a href="+code=revision" class="sref">revision /a> < 6) {> 123 /a>                if ( a href="+code=bus" class="sref">bus /a>-> a href="+code=bustypu" class="sref">bustypu /a> ==  a href="+code=SSB_BUSTYPE_SSB" class="sref">SSB_BUSTYPE_SSB /a> ||> 124 /a>                     a href="+code=bus" class="sref">bus /a>-> a href="+code=bustypu" class="sref">bustypu /a> ==  a href="+code=SSB_BUSTYPE_PCMCIA" class="sref">SSB_BUSTYPE_PCMCIA/oan)> 125 /a>                        return  a href="+code=SSB_CHIPCO_CLKSRC_XTALOS" class="sref">SSB_CHIPCO_CLKSRC_XTALOS /a>;> 126 /a>                if ( a href="+code=bus" class="sref">bus /a>-> a href="+code=bustypu" class="sref">bustypu /a> ==  a href="+code=SSB_BUSTYPE_PCI" class="sref">SSB_BUSTYPE_PCI/oan) {> 127 /a>                         a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword /a>( a href="+code=bus" class="sref">bus /a>-> a href="+code=host_pci" class="sref">host_pci /a>,  a href="+code=SSB_GPIO_OUT" class="sref">SSB_GPIO_OUT /a>, & a href="+code=tmp" class="sref">tmp /a>);> 128 /a>                        if ( a href="+code=tmp" class="sref">tmp /a> & 0x10)> 129 /a>                                return  a href="+code=SSB_CHIPCO_CLKSRC_PCI" class="sref">SSB_CHIPCO_CLKSRC_PCI /a>;> 130 /a>                        return  a href="+code=SSB_CHIPCO_CLKSRC_XTALOS" class="sref">SSB_CHIPCO_CLKSRC_XTALOS /a>;> 131 /a>                }> 132 /a>        }> 133 /a>        if ( a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>-> a href="+code=id" class="sref">id /a>. a href="+code=revision" class="sref">revision /a> < 10) {> 134 /a>                 a href="+code=tmp" class="sref">tmp /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SLOWCLKCTL" class="sref">SSB_CHIPCO_SLOWCLKCTL /a>);> 135 /a>                 a href="+code=tmp" class="sref">tmp /a> &= 0x7;> 136 /a>                if ( a href="+code=tmp" class="sref">tmp /a> == 0)> 137 /a>                        return  a href="+code=SSB_CHIPCO_CLKSRC_LOPWROS" class="sref">SSB_CHIPCO_CLKSRC_LOPWROS /a>;> 138 /a>                if ( a href="+code=tmp" class="sref">tmp /a> == 1)> 139 /a>                        return  a href="+code=SSB_CHIPCO_CLKSRC_XTALOS" class="sref">SSB_CHIPCO_CLKSRC_XTALOS /a>;> 140 /a>                if ( a href="+code=tmp" class="sref">tmp /a> == 2)> 141 /a>                        return  a href="+code=SSB_CHIPCO_CLKSRC_PCI" class="sref">SSB_CHIPCO_CLKSRC_PCI /a>;> 142 /a>        }> 143 /a>> 144 /a>        return  a href="+code=SSB_CHIPCO_CLKSRC_XTALOS" class="sref">SSB_CHIPCO_CLKSRC_XTALOS /a>;> 145 /a>}> 146/oan> 147 /a> spao class="comment">/* Get maximum or minimum (depending on get_max flag) slowclock frequency. */ /spaon> 148 /a>static int  a href="+code=chipco_pctl_clockfreqlimit" class="sref">chipco_pctl_clockfreqlimit /a>(struct  a href="+code=ssb_chipcommon" class="sref">ssb_chipcommon /a> * a href="+code=cc" class="sref">cc/oan, int  a href="+code=get_max" class="sref">get_max/oan)> 149 /a>{> 150 /a>        int  a href="+code=uninitialized_var" class="sref">uninitialized_var /a>( a href="+code=limit" class="sref">limit /a>);> 151 /a>        enum  a href="+code=ssb_clksrc" class="sref">ssb_clksrc/oan  a href="+code=clocksrc" class="sref">clocksrc /a>;> 152 /a>        int  a href="+code=divisor" class="sref">divisor /a> = 1;> 153 /a>         a href="+code=u32" class="sref">u32 /a>  a href="+code=tmp" class="sref">tmp /a>;> 154/oan> 155 /a>         a href="+code=clocksrc" class="sref">clocksrc /a> =  a href="+code=chipco_pctl_get_slowclksrc" class="sref">chipco_pctl_get_slowclksrc /a>( a href="+code=cc" class="sref">cc/oan);> 156 /a>        if ( a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>-> a href="+code=id" class="sref">id /a>. a href="+code=revision" class="sref">revision /a> < 6) {> 157 /a>                switch ( a href="+code=clocksrc" class="sref">clocksrc /a>) {> 158 /a>                case  a href="+code=SSB_CHIPCO_CLKSRC_PCI" class="sref">SSB_CHIPCO_CLKSRC_PCI /a>:> 159 /a>                         a href="+code=divisor" class="sref">divisor /a> = 64;> 160 /a>                        break;> 161 /a>                case  a href="+code=SSB_CHIPCO_CLKSRC_XTALOS" class="sref">SSB_CHIPCO_CLKSRC_XTALOS /a>:> 162 /a>                         a href="+code=divisor" class="sref">divisor /a> = 32;> 163 /a>                        break;> 164 /a>                default:> 165 /a>                         a href="+code=SSB_WARN_ON" class="sref">SSB_WARN_ON /a>(1);> 166 /a>                }> 167 /a>        } else if ( a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>-> a href="+code=id" class="sref">id /a>. a href="+code=revision" class="sref">revision /a> < 10) {> 168 /a>                switch ( a href="+code=clocksrc" class="sref">clocksrc /a>) {> 169 /a>                case  a href="+code=SSB_CHIPCO_CLKSRC_LOPWROS" class="sref">SSB_CHIPCO_CLKSRC_LOPWROS /a>:> 170 /a>                        break;> 171 /a>                case  a href="+code=SSB_CHIPCO_CLKSRC_XTALOS" class="sref">SSB_CHIPCO_CLKSRC_XTALOS /a>:> 172 /a>                case  a href="+code=SSB_CHIPCO_CLKSRC_PCI" class="sref">SSB_CHIPCO_CLKSRC_PCI /a>:> 173 /a>                         a href="+code=tmp" class="sref">tmp /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SLOWCLKCTL" class="sref">SSB_CHIPCO_SLOWCLKCTL /a>);> 174 /a>                         a href="+code=divisor" class="sref">divisor /a> = ( a href="+code=tmp" class="sref">tmp /a> >> 16) + 1;> 175 /a>                         a href="+code=divisor" class="sref">divisor /a> *= 4;> 176 /a>                        break;> 177 /a>                }> 178 /a>        } else {> 179 /a>                 a href="+code=tmp" class="sref">tmp /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SYSCLKCTL" class="sref">SSB_CHIPCO_SYSCLKCTL/oan);> 180 /a>                 a href="+code=divisor" class="sref">divisor /a> = ( a href="+code=tmp" class="sref">tmp /a> >> 16) + 1;> 181 /a>                 a href="+code=divisor" class="sref">divisor /a> *= 4;> 182 /a>        }> 183 /a>> 184 /a>        switch ( a href="+code=clocksrc" class="sref">clocksrc /a>) {> 185 /a>        case  a href="+code=SSB_CHIPCO_CLKSRC_LOPWROS" class="sref">SSB_CHIPCO_CLKSRC_LOPWROS /a>:> 186 /a>                if ( a href="+code=get_max" class="sref">get_max/oan)> 187 /a>                         a href="+code=limit" class="sref">limit /a> = 43000;> 188 /a>                else> 189 /a>                         a href="+code=limit" class="sref">limit /a> = 25000;> 190 /a>                break;> 191 /a>        case  a href="+code=SSB_CHIPCO_CLKSRC_XTALOS" class="sref">SSB_CHIPCO_CLKSRC_XTALOS /a>:> 192 /a>                if ( a href="+code=get_max" class="sref">get_max/oan)> 193 /a>                         a href="+code=limit" class="sref">limit /a> = 20200000;> 194 /a>                else> 195 /a>                         a href="+code=limit" class="sref">limit /a> = 19800000;> 196 /a>                break;> 197 /a>        case  a href="+code=SSB_CHIPCO_CLKSRC_PCI" class="sref">SSB_CHIPCO_CLKSRC_PCI /a>:> 198 /a>                if ( a href="+code=get_max" class="sref">get_max/oan)> 199 /a>                         a href="+code=limit" class="sref">limit /a> = 34000000;> 200 /a>                else> 201 /a>                         a href="+code=limit" class="sref">limit /a> = 25000000;> 202 /a>                break;> 203 /a>        }> 204 /a>         a href="+code=limit" class="sref">limit /a> /=  a href="+code=divisor" class="sref">divisor /a>;> 205/oan> 206 /a>        return  a href="+code=limit" class="sref">limit /a>;> 207 /a>}> 208/oan> 209 /a>static void  a href="+code=chipco_powercontrol_init" class="sref">chipco_powercontrol_init /a>(struct  a href="+code=ssb_chipcommon" class="sref">ssb_chipcommon /a> * a href="+code=cc" class="sref">cc/oan)> 210 /a>{> 211 /a>        struct  a href="+code=ssb_bus" class="sref">ssb_bus /a> * a href="+code=bus" class="sref">bus /a> =  a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>-> a href="+code=bus" class="sref">bus /a>;> 212/oan> 213 /a>        if ( a href="+code=bus" class="sref">bus /a>-> a href="+code=chip_id" class="sref">chip_id /a> == 0x4321) {> 214 /a>                if ( a href="+code=bus" class="sref">bus /a>-> a href="+code=chip_rev" class="sref">chip_rev /a> == 0)> 215 /a>                         a href="+code=chipco_write32" class="sref">chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_CHIPCTL" class="sref">SSB_CHIPCO_CHIPCTL/oan, 0x3A4);> 216 /a>                else if ( a href="+code=bus" class="sref">bus /a>-> a href="+code=chip_rev" class="sref">chip_rev /a> == 1)> 217 /a>                         a href="+code=chipco_write32" class="sref">chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_CHIPCTL" class="sref">SSB_CHIPCO_CHIPCTL/oan, 0xA4);> 218 /a>        }> 219/oan> 220 /a>        if (!( a href="+code=cc" class="sref">cc/oan-> a href="+code=capabilities" class="sref">capabilities /a> &  a href="+code=SSB_CHIPCO_CAP_PCTL" class="sref">SSB_CHIPCO_CAP_PCTL /a>))> 221 /a>                return;> 222/oan> 223 /a>        if ( a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>-> a href="+code=id" class="sref">id /a>. a href="+code=revision" class="sref">revision /a> >= 10) {> 224 /a>                 spao class="comment">/* Set Idle Power clock rate to 1Mhz */ /spaon> 225 /a>                 a href="+code=chipco_write32" class="sref">chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SYSCLKCTL" class="sref">SSB_CHIPCO_SYSCLKCTL/oan,> 226 /a>                               ( a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SYSCLKCTL" class="sref">SSB_CHIPCO_SYSCLKCTL/oan) &> 227 /a>                                0x0000FFFF) | 0x00040000);> 228 /a>        } else {> 229 /a>                int  a href="+code=maxfreq" class="sref">maxfreq /a>;> 230/oan> 231 /a>                 a href="+code=maxfreq" class="sref">maxfreq /a> =  a href="+code=chipco_pctl_clockfreqlimit" class="sref">chipco_pctl_clockfreqlimit /a>( a href="+code=cc" class="sref">cc/oan, 1);> 232 /a>                 a href="+code=chipco_write32" class="sref">chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_PLLONDELAY" class="sref">SSB_CHIPCO_PLLONDELAY/oan,> 233 /a>                               ( a href="+code=maxfreq" class="sref">maxfreq /a> * 150 + 999999) / 1000000);> 234 /a>                 a href="+code=chipco_write32" class="sref">chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_FREFSELDELAY" class="sref">SSB_CHIPCO_FREFSELDELAY/oan,> 235 /a>                               ( a href="+code=maxfreq" class="sref">maxfreq /a> * 15 + 999999) / 1000000);> 236 /a>        }> 237 /a>}> 238/oan> 239 /a> spao class="comment">/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */ /spaon> 240 /a>static  a href="+code=u16" class="sref">u16 /a>  a href="+code=pmu_fast_powerup_delay" class="sref">pmu_fast_powerup_delay /a>(struct  a href="+code=ssb_chipcommon" class="sref">ssb_chipcommon /a> * a href="+code=cc" class="sref">cc/oan)> 241 /a>{> 242 /a>        struct  a href="+code=ssb_bus" class="sref">ssb_bus /a> * a href="+code=bus" class="sref">bus /a> =  a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>-> a href="+code=bus" class="sref">bus /a>;> 243 /a>> 244 /a>        switch ( a href="+code=bus" class="sref">bus /a>-> a href="+code=chip_id" class="sref">chip_id /a>) {> 245 /a>        case 0x4312:> 246 /a>        case 0x4322:> 247 /a>        case 0x4328:> 248 /a>                return 7000;> 249 /a>        case 0x4325:> 250 /a>                 spao class="comment">/* TODO: */ /spaon> 251 /a>        default:> 252 /a>                return 15000;> 253 /a>        }> 254 /a>}> 255/oan> 256 /a> spao class="comment">/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */ /spaon> 257/oanstatic void  a href="+code=calc_fast_powerup_delay" class="sref">calc_fast_powerup_delay /a>(struct  a href="+code=ssb_chipcommon" class="sref">ssb_chipcommon /a> * a href="+code=cc" class="sref">cc/oan)> 258/oan{> 259 /a>        struct  a href="+code=ssb_bus" class="sref">ssb_bus /a> * a href="+code=bus" class="sref">bus /a> =  a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>-> a href="+code=bus" class="sref">bus /a>;> 260 /a>        int  a href="+code=minfreq" class="sref">minfreq /a>;> 261 /a>        unsigned int  a href="+code=tmp" class="sref">tmp /a>;> 262 /a>         a href="+code=u32" class="sref">u32 /a>  a href="+code=pll_on_delay" class="sref">pll_on_delay /a>;> 263 /a>> 264 /a>        if ( a href="+code=bus" class="sref">bus /a>-> a href="+code=bustypu" class="sref">bustypu /a> !=  a href="+code=SSB_BUSTYPE_PCI" class="sref">SSB_BUSTYPE_PCI/oan)> 265 /a>                return;> 266/oan> 267 /a>        if ( a href="+code=cc" class="sref">cc/oan-> a href="+code=capabilities" class="sref">capabilities /a> &  a href="+code=SSB_CHIPCO_CAP_PMU" class="sref">SSB_CHIPCO_CAP_PMU /a>) {> 268 /a>                 a href="+code=cc" class="sref">cc/oan-> a href="+code=fast_pwrup_delay" class="sref">fast_pwrup_delay /a> =  a href="+code=pmu_fast_powerup_delay" class="sref">pmu_fast_powerup_delay /a>( a href="+code=cc" class="sref">cc/oan);> 269 /a>                return;> 270 /a>        }> 271 /a>> 272 /a>        if (!( a href="+code=cc" class="sref">cc/oan-> a href="+code=capabilities" class="sref">capabilities /a> &  a href="+code=SSB_CHIPCO_CAP_PCTL" class="sref">SSB_CHIPCO_CAP_PCTL /a>))> 273 /a>                return;> 274/oan> 275 /a>         a href="+code=minfreq" class="sref">minfreq /a> =  a href="+code=chipco_pctl_clockfreqlimit" class="sref">chipco_pctl_clockfreqlimit /a>( a href="+code=cc" class="sref">cc/oan, 0);> 276 /a>         a href="+code=pll_on_delay" class="sref">pll_on_delay /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_PLLONDELAY" class="sref">SSB_CHIPCO_PLLONDELAY/oan);> 277 /a>         a href="+code=tmp" class="sref">tmp /a> = ((( a href="+code=pll_on_delay" class="sref">pll_on_delay /a> + 2) * 1000000) + ( a href="+code=minfreq" class="sref">minfreq /a> - 1)) /  a href="+code=minfreq" class="sref">minfreq /a>;> 278 /a>         a href="+code=SSB_WARN_ON" class="sref">SSB_WARN_ON /a>( a href="+code=tmp" class="sref">tmp /a> & ~0xFFFF);> 279/oan> 280 /a>         a href="+code=cc" class="sref">cc/oan-> a href="+code=fast_pwrup_delay" class="sref">fast_pwrup_delay /a> =  a href="+code=tmp" class="sref">tmp /a>;> 281 /a>}> 282/oan> 283 /a>void  a href="+code=ssb_chipcommon_init" class="sref">ssb_chipcommon_init /a>(struct  a href="+code=ssb_chipcommon" class="sref">ssb_chipcommon /a> * a href="+code=cc" class="sref">cc/oan)> 284 /a>{> 285 /a>        if (! a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>)> 286 /a>                return;  spao class="comment">/* We don't have a ChipCommon */ /spaon> 287 /a>        if ( a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>-> a href="+code=id" class="sref">id /a>. a href="+code=revision" class="sref">revision /a> >= 11)> 288 /a>                 a href="+code=cc" class="sref">cc/oan-> a href="+code=status" class="sref">status /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_CHIPSTAT" class="sref">SSB_CHIPCO_CHIPSTAT/oan);> 289 /a>         a href="+code=ssb_dprintk" class="sref">ssb_dprintk /a>( a href="+code=KERN_INFO" class="sref">KERN_INFO /a>  a href="+code=PFX" class="sref">PFX /a>  spao class="string">"chipcommon status is 0x%x\n" /spaon,  a href="+code=cc" class="sref">cc/oan-> a href="+code=status" class="sref">status /a>);> 290/oan> 291 /a>        if ( a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>-> a href="+code=id" class="sref">id /a>. a href="+code=revision" class="sref">revision /a> >= 20) {> 292 /a>                 a href="+code=chipco_write32" class="sref">chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_GPIOPULLUP" class="sref">SSB_CHIPCO_GPIOPULLUP/oan, 0);> 293 /a>                 a href="+code=chipco_write32" class="sref">chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_GPIOPULLDOWN" class="sref">SSB_CHIPCO_GPIOPULLDOWN/oan, 0);> 294 /a>        }> 295/oan> 296 /a>         a href="+code=ssb_pmu_init" class="sref">ssb_pmu_init /a>( a href="+code=cc" class="sref">cc/oan);> 297 /a>         a href="+code=chipco_powercontrol_init" class="sref">chipco_powercontrol_init /a>( a href="+code=cc" class="sref">cc/oan);> 298 /a>         a href="+code=ssb_chipco_set_clockmode" class="sref">ssb_chipco_set_clockmode /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CLKMODE_FAST" class="sref">SSB_CLKMODE_FAST/oan);> 299 /a>         a href="+code=calc_fast_powerup_delay" class="sref">calc_fast_powerup_delay /a>( a href="+code=cc" class="sref">cc/oan);> 300 /a>}> 301 /a>> 302 /a>void  a href="+code=ssb_chipco_suspend" class="sref">ssb_chipco_suspend /a>(struct  a href="+code=ssb_chipcommon" class="sref">ssb_chipcommon /a> * a href="+code=cc" class="sref">cc/oan)> 303 /a>{> 304 /a>        if (! a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>)> 305 /a>                return;> 306 /a>         a href="+code=ssb_chipco_set_clockmode" class="sref">ssb_chipco_set_clockmode /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CLKMODE_SLOW" class="sref">SSB_CLKMODE_SLOW/oan);> 307 /a>}> 308/oan> 309 /a>void  a href="+code=ssb_chipco_resume" class="sref">ssb_chipco_resume /a>(struct  a href="+code=ssb_chipcommon" class="sref">ssb_chipcommon /a> * a href="+code=cc" class="sref">cc/oan)> 310 /a>{> 311 /a>        if (! a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>)> 312 /a>                return;> 313 /a>         a href="+code=chipco_powercontrol_init" class="sref">chipco_powercontrol_init /a>( a href="+code=cc" class="sref">cc/oan);> 314 /a>         a href="+code=ssb_chipco_set_clockmode" class="sref">ssb_chipco_set_clockmode /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CLKMODE_FAST" class="sref">SSB_CLKMODE_FAST/oan);> 315 /a>}> 316/oan> 317 /a> spao class="comment">/* Get the processor clock */ /spaon> 318 /a>void  a href="+code=ssb_chipco_get_clockcpu" class="sref">ssb_chipco_get_clockcpu /a>(struct  a href="+code=ssb_chipcommon" class="sref">ssb_chipcommon /a> * a href="+code=cc" class="sref">cc/oan,> 319 /a>                              a href="+code=u32" class="sref">u32 /a> * a href="+code=plltypu" class="sref">plltypu/oan,  a href="+code=u32" class="sref">u32 /a> * a href="+code=n" class="sref">n/oan,  a href="+code=u32" class="sref">u32 /a> * a href="+code=m" class="sref">m /a>)> 320 /a>{> 321 /a>        * a href="+code=n" class="sref">n/oan =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_CLOCK_N" class="sref">SSB_CHIPCO_CLOCK_N/oan);> 322 /a>        * a href="+code=plltypu" class="sref">plltypu/oan = ( a href="+code=cc" class="sref">cc/oan-> a href="+code=capabilities" class="sref">capabilities /a> &  a href="+code=SSB_CHIPCO_CAP_PLLT" class="sref">SSB_CHIPCO_CAP_PLLT/oan);> 323 /a>        switch (* a href="+code=plltypu" class="sref">plltypu/oan) {> 324 /a>        case  a href="+code=SSB_PLLTYPE_2" class="sref">SSB_PLLTYPE_2 /a>:> 325 /a>        case  a href="+code=SSB_PLLTYPE_4" class="sref">SSB_PLLTYPE_4 /a>:> 326 /a>        case  a href="+code=SSB_PLLTYPE_6" class="sref">SSB_PLLTYPE_6 /a>:> 327 /a>        case  a href="+code=SSB_PLLTYPE_7" class="sref">SSB_PLLTYPE_7 /a>:> 328 /a>                * a href="+code=m" class="sref">m /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_CLOCK_MIPS" class="sref">SSB_CHIPCO_CLOCK_MIPS/oan);> 329 /a>                break;> 330 /a>        case  a href="+code=SSB_PLLTYPE_3" class="sref">SSB_PLLTYPE_3 /a>:> 331 /a>                 spao class="comment">/* 5350 uses m2 to control mips */ /spaon> 332 /a>                * a href="+code=m" class="sref">m /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_CLOCK_M2" class="sref">SSB_CHIPCO_CLOCK_M2/oan);> 333 /a>                break;> 334 /a>        default:> 335 /a>                * a href="+code=m" class="sref">m /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_CLOCK_SB" class="sref">SSB_CHIPCO_CLOCK_SB/oan);> 336 /a>                break;> 337 /a>        }> 338/oan}> 339/oan> 340 /a> spao class="comment">/* Get the bus clock */ /spaon> 341 /a>void  a href="+code=ssb_chipco_get_clockcontrol" class="sref">ssb_chipco_get_clockcontrol /a>(struct  a href="+code=ssb_chipcommon" class="sref">ssb_chipcommon /a> * a href="+code=cc" class="sref">cc/oan,> 342 /a>                                  a href="+code=u32" class="sref">u32 /a> * a href="+code=plltypu" class="sref">plltypu/oan,  a href="+code=u32" class="sref">u32 /a> * a href="+code=n" class="sref">n/oan,  a href="+code=u32" class="sref">u32 /a> * a href="+code=m" class="sref">m /a>)> 343 /a>{> 344 /a>        * a href="+code=n" class="sref">n/oan =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_CLOCK_N" class="sref">SSB_CHIPCO_CLOCK_N/oan);> 345 /a>        * a href="+code=plltypu" class="sref">plltypu/oan = ( a href="+code=cc" class="sref">cc/oan-> a href="+code=capabilities" class="sref">capabilities /a> &  a href="+code=SSB_CHIPCO_CAP_PLLT" class="sref">SSB_CHIPCO_CAP_PLLT/oan);> 346 /a>        switch (* a href="+code=plltypu" class="sref">plltypu/oan) {> 347 /a>        case  a href="+code=SSB_PLLTYPE_6" class="sref">SSB_PLLTYPE_6 /a>:  spao class="comment">/* 100/200 or 120/240 only */ /spaon> 348 /a>                * a href="+code=m" class="sref">m /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_CLOCK_MIPS" class="sref">SSB_CHIPCO_CLOCK_MIPS/oan);> 349 /a>                break;> 350 /a>        case  a href="+code=SSB_PLLTYPE_3" class="sref">SSB_PLLTYPE_3 /a>:  spao class="comment">/* 25Mhz, 2 dividers */ /spaon> 351 /a>                if ( a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>-> a href="+code=bus" class="sref">bus /a>-> a href="+code=chip_id" class="sref">chip_id /a> != 0x5365) {> 352 /a>                        * a href="+code=m" class="sref">m /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_CLOCK_M2" class="sref">SSB_CHIPCO_CLOCK_M2/oan);> 353 /a>                        break;> 354 /a>                }> 355 /a>                 spao class="comment">/* Fallthough */ /spaon> 356 /a>        default:> 357 /a>                * a href="+code=m" class="sref">m /a> =  a href="+code=chipco_read32" class="sref">chipco_read32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_CLOCK_SB" class="sref">SSB_CHIPCO_CLOCK_SB/oan);> 358 /a>        }> 359 /a>}> 360/oan> 361 /a>void  a href="+code=ssb_chipco_timing_init" class="sref">ssb_chipco_timing_init /a>(struct  a href="+code=ssb_chipcommon" class="sref">ssb_chipcommon /a> * a href="+code=cc" class="sref">cc/oan,> 362 /a>                            unsigned long  a href="+code=ns" class="sref">ns /a>)> 363 /a>{> 364 /a>        struct  a href="+code=ssb_device" class="sref">ssb_device /a> * a href="+code=dev" class="sref">dev /a> =  a href="+code=cc" class="sref">cc/oan-> a href="+code=dev" class="sref">dev /a>;> 3ef">u32 /a>  astruct  a href="+code=ssb_bus" class="sref">ssb_bus /a> * a href="+code=bus" class="sref">bus /a> =  a href="+code= spao class="comment">/* 25Mhz, 2 dividers */ /spaon> 351 /a>                if ( a href="+code=3/ssb/driv3r_chipcommon.c#L267" ide3L267"36f">ssb_chipco_set_clockmode ef">pll_on_delay /a>;> 281 /a>}>cc/oan-3gt; a3href=""line" namue=L281"> 281 /a>}>cc/3an-&g3; a href="+codsb/driver_chipcommon.c#L3set register f.c#external IOn.c#L332" idLED.56" class="line" namue=L356"> 356 /a>        default:>eturn;>calc_fast_powerup_delay /a>" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_GPIOPULLDOWN" class="sref">SSB_CHIPCO_GPIOPULLDOWN/oan, 0);> 232 /a>                3="drivers3ssb/driver_chipcommon.c#3271" 37"+code=fast_pwrup_delay" clas="sref">pll_on_delay /a> + wrup_delay" claDIV_ROUND_/ssb/driver_chipcDIV_ROUND_/sCHIPC10O_GPIOPULLDOWN/oac#L363" ide=L363" class= <<spao class="comment">ROG_WCNT_3_SHIFriver_chipcommon.c#L>ROG_WCNT_3_SHIFrlass=f="drivers/ssb/driver_chipcommon.c#L3Waitcount-3  clan351" class="line" namue=L351"> 351 /a>                i/ssb/driv3r_chipcommon.c#L272" ide3L272"371+code=fast_pwrup_delay" clas="sref">pll_on_delay /a> |+ wrup_delay" claDIV_ROUND_/ssb/driver_chipcDIV_ROUND_/sCHIPC40O_GPIOPULLDOWN/oac#L363" ide=L363" class= <<spao class="comment">ROG_WCNT_1_SHIFriver_chipcommon.c#L>ROG_WCNT_1_SHIFrlass=f="sb/driver_chipcommon.c#L3Waitcount-1  c4an351" class="line" namue=L351"> 351 /a>                i/         e=cc" class="sref">cc/oa3->3a href="+code=wrup_delay" clas="sref">pll_on_delay /a> |+ wrup_delay" claDIV_ROUND_/ssb/driver_chipcDIV_ROUND_/sCHIPC240O_GPIOPULLDOWN/oac#L363" ide=L363" class==f="drivers/sssssssssssssssssb/driver_chipcommon.c#L3Waitcount-0L2024an351" class="line" namue=L351"> 351 /a>                i//ssb/drivhref="drivers/ssb/driver3chipc3mmon.c#L274" iowerup_delay /a>" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_GPIOPULLDOWN" class="sref">SSB_CHIPCO_GPIOPULLDOWN/oan, 0);>pll_on_delay /a>==f="drivsb/driver_chipcommon.c#L30x01020a0c f.c#ahipc=L22de=L341" class="line" namue=L341"> 341 /a>void  a href="+co/ssb/driv3r_chipcommon.c#L275" ide3L275"3class="line" namue=L275"> 275 /a>         a href=3+code=min3req" class="sref">minfre3 /a> 3  a href="+codeaon>ssb f.c##L34f hr356" class="line" namue=L356"> 356 /a>        default:>+code=pll3on_delay" class="sref">p3l_on_3elay /a> =  a href="+code=chis="sref">pll_on_delay /a> + wrup_delay" claDIV_ROUND_/ssb/driver_chipcDIV_ROUND_/sCHIPC10O_GPIOPULLDOWN/oac#L363" ide=L363" class= <<spao class="comment"FLASH_WCNT_3_SHIFriver_chipcommon.c#LFLASH_WCNT_3_SHIFrlass=f="sb/driver_chipcommon.c#L3Waitcount-3  clanS56" class="line" namue=L356"> 356 /a>        default:>+f="+code3 class="sref">tmp /a> = 3(( a 3ref="+code=pll_on_delay" class="sref">pll_on_delay /a> |+ wrup_delay" claDIV_ROUND_/ssb/driver_chipcDIV_ROUND_/sCHIPC10O_GPIOPULLDOWN/oac#L363" ide=L363" class= <<spao class="comment"FLASH_WCNT_1_SHIFriver_chipcommon.c#LFLASH_WCNT_1_SHIFrlass=f=sb/driver_chipcommon.c#L3Waitcount-1  clanS56" class="line" namue=L356"> 356 /a>        default:>+"drivers/WARN_ON" class="sref">SS3_WARN3ON /a>( a href="+code=tmp" cls="sref">pll_on_delay /a> |+ wrup_delay" claDIV_ROUND_/ssb/driver_chipcDIV_ROUND_/sCHIPC120O_GPIOPULLDOWN/oac#L363" ide=L363" class==f="drivers/sssssssssssssssssb/driver_chipcommon.c#L3Waitcount-0L20120nS56" class="line" namue=L356"> 356 /a>        default:>+turn;>calc_fast_pv" cp_id" class="sref">chip_id /a>) {> 356 /a>        default:>+code=cc"3class="sref">cc/oan->3a hre38 href="drivers/ssp_id" class="sre /a>. a href="+code=revision" class="sref">revision /a> >= 20) {> 273 /a>                3s/ssb/dri3er_chipcommon.c#L282" id3=L28238q /a> =  a href="+code=chipco_pctl_c>" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_GPIOPULLDOWN" class="sref">SSB_CHIPCO_GPIOPULLDOWN/oan, 0);>pll_on_delay /a>=="line" namue=L273"> 273 /a>                3s         r_chipcommon.c#L283" ide3L283"38 href="+code=capap_id" class="sref">chip_id /a>) {> 356 /a>        default:>+/ssb/drivpcommon_init" class="sre3">ssb38chipcommon.c#L354p_id" class="sre /a>. a href="+code=revision" class="sref">revision /a> >= 20) {> 356 /a>        default:>+ssb/driv3er_chipcommon.c#L285" id3=L28538L355" ide=L355" cap_id" class="sref">chip_id /a>) {>chip_id /a>) {> 273 /a>                3scode=min3=cc" class="sref">cc/oan3> 38>chipco_write32 /a>( a href="+code=cc" class="sref">cc/oan,  a href="+code=SSB_CHIPCO_SYSCLKCTL" class="sref">SSB_CHIPCO_SYSCLKCTL/oan,>pll_on_delay /a>=="line" namue=L273"> 273 /a>                3scode=pll3ao class="comment">/* We3don&lass="line" namue=L317"> 317 /a> spao class="commef="+code3cc" class="sref">cc/oan-3gt; a3href="+code=dev" class="sref">devf">chip_id /a>) {> 364 /a>        struct  aa href="+3304" ide=="driver04aoaa href="+3304" ide=="driver04aoaa h" class="sref">4devf">chip_id /a>) {>calc_fast_pv" cp_id" class="sref">chip_id /aERN_INFO 3a>  a href="+code=PFX" c3ass="38LTYPE_3" class="sref"_ROUND_/sCHIPC10O_GPIOPULLDOWN/oac#L363" ide=L363" class= <<spao class="comment"FLASH_WCNT_3_SHIFriver_chipcommon.c#LFLASH_WCNT_3_SHIFrlass=f="sb/driver_chipcommon.c#L3on.c#L3Waitcount-3  clan351" class="line" namue=L351"> 351 /a>          i/ssb/driv3r_chipcommon.c#L272" ide3L272"371+code=fast_pwrup_delay" clas="sref">pll_on_de href="+c3de=cc" class="sref">cc/o3n->39        default:>        default:>+"drivers/WARN_ON" class="2b/dride3L272"371+code=fast_pwrup_delay" clas="sref">pll_on_de ref">cc/oid" class="sref">id /a>.3a hre39IOPULLDOWN" class="sref">SSB_CHIPCO_10O_GPIOPULLDOWN/oac#L363" ide=L363" class= <<spao class="comment"FLASH_WCNT_1_SHIFriver_chipcommon.c#L>ROG_WCNT_1_SHIFrlass=f="sb/driver_chipcommon.c#L3Waitcount-1  c4an351" class="line" namue=L351"> 351 /a>      default:>+"drivers/WARN_ON" class="sref">ide3L272"371+code=fast_pwrup_delay" clas="sref">pll_on_de ) {>SSB_CHIPCO_GP120O_GPIOPULLDOWN/oac#L363" ide=L363" class==f="drivers/sssssssssssssssssb/driver_chipcommon.c#L3Waitcount-0L20120nS56" class="line" namue=L356"> 356 /a>  default:>+turn;>pll_on_de +code=revan,  a href="+code=SSB_C3IPCO_3PIOPULLDOWN" class="sref">SSB_CHIPCO_GPIOPULLDOWN/oan, 0);> 294 /a>  elay /a>==f="drivsb/driver_chipcommon.c#L30x01020a0c f.c#ahipc=L22de=L341" class="line" namue=L341"/a>void  a href="+co/ssb/driv3r_chipcommon.c#L275" ide3L275"3class="line" namue=L275"> 275 /a>         a hreref="driv3rs/ssb/driver_chipcommon3c#L293" ide=L296" class="line" namue=L296"> 296 /a>         a hr3f="+code=3sb_pmu_init" class="sref3>ssb_397" class="line" namue=L317"> 317 /a> spao class="c);>devf">chip_id /a>=cc" clas3="sref">cc/oan);>void  a href="+code=ssb_chipon_dvf"> watchdog resn_delaeriverfire in cc" clickscc" c backplane cyclee3L272"371+code=fast_pwrup_delay" clas="sref">pll_on_de chip_id /="sref">cc/oan,  a href=3+code39mmon /a> * a href="+code=cc" class="watchdog_elaerver_> 362 /a>                            unsigned long  a href="+code=ns" " namue=L281"> 281 /a>}> 364 /a>        strucc" class=3sref">cc/oan);>4devf4vers/ssb/4river_chipcommon.c#L302"4ide=L40iver_chipcDIV_  a href="+code=ssb_chipinstant NMI3L272"371+code=fast_pwrup_delay" clas="sref">pll_on_d4+code=ssb4chipco_suspend" class="s4ef">s40river_chipcDIV_ROUND_/sCHIPCGPIOPULLDOWN/oan, 0);> 294 /a>  WATCHDO  3="drivers3ssb/driver_chiWATCHDO 0c f.c#ahipc=L22de=L34icks class="line" naicks4" class="line" namue=L317"> 317 /a> spao class="4pcommon" 4lass="sref">ssb_chipcomm4n /a>4* a hrass="line" namue=L317"> 317 /a> spao class="4 a href="4code=cc" class="sref">cc4oan-&40; a href="+code=bustypu" class="sref">bustypu /a4="drivers4ssb/driver_chipcommon.c#4305" 4de=L30/a> * a href="+code=cc" class="irq_mas;chipcommon status iclass="irq_mas;on.c#L362" ide=L362" class="line" namue=L362"> 362 /a>                            unsigned long  a href="+code=ns" " namue=L281"> 281 /a>}> 281 /a>}>;> 364 /a>        stru4> 306 /a>4        a href="+code=ss4_chip4o_set_04" ide=="driver04aoaa h" class="sref">4devf4v6306 /a>4 "drivers/ssb/driver_chi4+code4SSB_CLKMODE_SLOW" class="sref="drivers/ssb/_mas;eef="+3304" ide=="driivers/ssb/_mas;eedriver_chipcommon.c#L294" ide=L294" class="line" namue=L294"> 294 /a>  IRQMASK 3="drivers3ssb/driver_chiIRQMASKss="line" namue=L294"mas;chipcommon statmas;on.c " namue=L281"> 2valuev /a>;> 317 /a> spao class="4p7306 /a>4 "sref">cc/oan);> 309 /a>void  a href=4+code=ssb4chipco_resume" class="sr4f">ss4_chipco_resume /a>(struct  a href="+code=ssb_chip4ommon" cl4ss="sref">ssb_chipcommon4/a> *4a href namue=L281"> 281 /a>}> 362 /a>                            unsigned long  a href="+code=ns" " namue=L281"> 281 /a>}> 364 /a>        stru4 a href="4code=cc" class="sref">cc4oan-&4t; a href="+code=dev" class="sref">dev /a>)> 358 /a>        }> 346 /a>  mas;chipcommon statmas;on.cass="line" namue=L317"> 317 /a> spao class="4> 313 /a>4        a href="+code=ch4pco_p41 a hrass="line" namue=L317"> 317 /a> spao class="4=cc" clas4="sref">cc/oan);>bustypu /a4=cc" clas4="sref">cc/oan,  a href=4+code4SSB_CL namue=L281"> 281 /a>}> 362 /a>            "gpi="iLon.c#L362" ide=L362" class="line" namue=L362"> 362 /a>                            unsigned long  a href="+code=ns" " namue=L281"> 281 /a>}> 364 /a>        stru4  306 /a>4river_chipcommon.c#L317"4ide=L41_set_04" ide=="driver04aoaa h" class="sref">4devf4omment">/4 Get the processor clock4*/ /s416=L312" class="srefSB_CHIPCO_CLOCK_SB/oan);> 358 /a>        }> 346 /a>  mas;chipcommon statmas;on.cass="line" namue=L317"> 317 /a> spao class="4>7306 /a>4 class="line" namue=L3184> 318419" class="line" namue=L309"> 309 /a>void  a href=4de=ssb_ch4pcommon" class="sref">ss4_chip41chipco_resume /a>(struct  a href="+code=ssb_chip4f">plltyp4/oan,  a href="+code=u324 clas41 href namue=L281"> 281 /a>}> 362 /a>                            unsigned long  a href="+code=ns" " namue=L281"> 281 /a>}> 281 /a>}>;> 364 /a>        stru4ref="+cod4=n" class="sref">n/oan =4 a hr4f="+code=chipco_read32" class="sref">chipco_read324/a>( a hr4f="+code=cc" class="sref4>cc/o42e=L312" class="srefSB_CHIPCO_CLOCK_SB/oan)rs/ssb/_mas;eef="+3304" ide=="driivers/ssb/_mas;eedriver_chipcommon.c#L294" ide=L294" class="line" namue=L294"> 294 /a>  ipcoOUde=ssb_dprintk" class="srefipcoOUdss="line" namue=L294"mas;chipcommon statmas;on.c " namue=L281"> 2valuev /a>;> 317 /a> spao class="42 313 /a>42       a href="+code=ch42co_p42 a hrass="line" namue=L317"> 317 /a> spao class="4on.c#L3244 ide=L324" class="line" 4amue=42; a href="+code=bustypu" class="sref">bustypu /a4ipcommon.4#L325" ide=L325" class="4ine" 42SB_CL namue=L281"> 281 /a>}> 362 /a>            "gpi="ou_eLon.c#L362" ide=L362" class="line" namue=L362"> 362 /a>                            unsigned long  a href="+code=ns" " namue=L281"> 281 /a>}> 281 /a>}>;> 364 /a>        stru4r 306 /a>4#L326" ide=L326" class="4ine" 42_set_04" ide=="driver04aoaa h" class="sref">4devf4ipcommon.4#L327" ide=L327" class="4ine" 426=L312" class="srefSB_CHIPCO_CLOCK_SB/oan)rs/ssb/_mas;eef="+3304" ide=="driivers/ssb/_mas;eedriver_chipcommon.c#L294" ide=L294" class="line" namue=L294"> 294 /a>  ipcoOUdEhref="drivers/ssb/driver_chipcoOUdEhss="line" namue=L294"mas;chipcommon statmas;on.c " namue=L281"> 2valuev /a>;> 317 /a> spao class="427306 /a>4#L328" ide=L328" class="4ine" 429" class="line" namue=L309"> 309 /a>void  a href=4_read32 /4>( a href="+code=cc" cla4s="sr42chipco_resume /a>(struct  a href="+code=ssb_chip4 330 /a> 4      case  a href="+cod4=SSB_42 href namue=L281"> 281 /a>}>cc/oan,>ccon.c#L362" ide=L362" class="line" namue=L362"> 362 /a>                            unsigned long  a href="+code=ns" " namue=L281"> 281 /a>}> 281 /a>}>;> 364 /a>        stru4ipcommon.4#L331" ide=L331" class="4ine" 43="+code=chipco_read32" class="sref">chipco_read324er_chipco4mon.c#L332" ide=L332" cl4ss="l43e=L312" class="srefSB_CHIPCO_CLOCK_SB/oan)rs/ssb/_mas;eef="+3304" ide=="driivers/ssb/_mas;eedriver_chipcommon.c#L294" ide=L294" class="line" namue=L294"> 294 /a>  ipcoCTLref="drivers/ssb/driver_chipcoCTLss="line" namue=L294"mas;chipcommon statmas;on.c " namue=L281"> 2valuev /a>;> 317 /a> spao class="4_read32 /4>( a href="+code=cc" cla4s="sr43 a hrass="line" namue=L317"> 317 /a> spao class="4 334 /a> 4      default:> 2EXPORT_SYMBOLref="drivers/ssEXPORT_SYMBOLdriver_chipcommon.c#us iclass="gpi="ref">cc/oan,>ccon.class="line" namue=L317"> 317 /a> spao class="4_pcommon.4        * a href="+code=4" cla43 3  a href="+codeaon>4_read32 /4>( a href="+code=cc" cla4s="sr4f">cc/ namue=L281"> 281 /a>}> 362 /a>                            unsigned long  a href="+code=ns" " namue=L281"> 281 /a>}> 281 /a>}>;> 364 /a>        stru4ipcommon.4      }>chipco_read324e7306 /a>4ers/ssb/driver_chipcommo4.c#L349" ide=L339" c="srefSB_CHIPCO_CLOCK_SB/oan)rs/ssb/_mas;eef="+3304" ide=="driivers/ssb/_mas;eedriver_chipcommon.c#L294" ide=L294" class="line" namue=L294"> 294 /a>  ipcoIRQref="drivers/ssb/driver_chipcoIRQss="line" namue=L294"mas;chipcommon statmas;on.c " namue=L281"> 2valuev /a>;> 317 /a> spao class="4_read32 /4river_chipcommon.c#L340"4ide=L440" class="line" namue=L340"> 340 /a> spao class="4omment">/4 Get the bus clock */ /s4aon><4 href="drivers/ssb/driver_chipcommon.c#L341" ide=4341" clas4="line" namue=L341"> 3414/a>vo4d  a hrnamue=L281"> 281 /a>}> us iclass="gpi="polas/seon.c#L362" ide=L362" class="line" namue=L362"> 362 /a>                            unsigned long  a href="+code=ns" " namue=L281"> 281 /a>}> 281 /a>}>;> 364 /a>        stru4ref="+cod4=ssb_chipcommon" class="4ref">4sb_chide=chipco_read32" class="sref">chipco_read324"sref">pl4typu/oan,  a href="+code4u32" 4lass="sref">u3="srefSB_CHIPCO_CLOCK_SB/oan)rs/ssb/_mas;eef="+3304" ide=="driivers/ssb/_mas;eedriver_chipcommon.c#L294" ide=L294" class="line" namue=L294"> 294 /a>  ipcoPOLref="drivers/ss> 294 /a>  ipcoPOLss="line" namue=L294"mas;chipcommon statmas;on.c " namue=L281"> 2valuev /a>;> 317 /a> spao class="4ref="+cod4=n" class="sref">n/oan =4 a hr4f="+coass="line" namue=L340"> 340 /a> spao class="4/a>( a hr4f="+code=cc" class="sref4>cc/o44 3  a href="+codeaon>4a href="+4ode=capabilities" class=4sref"4capabi#ifdef" namue=L281"> 2CONFIG_> 29SERIALref="drivers/ssCONFIG_> 29SERIAL3  a href="+codeaon>4apcommon.4 ide=L347" class="line" 4amue=4347"> iLt="+code3cc" clasus iclass="serias="line" namue=L314">us iclass="serias="linon.c#L362" ide=L362" class="line" namue=L362"> 362 /a>                            unsigned long  a href="+code=ns"  href="+codeaon>4a7306 /a>4240 only */ /spaon>cc/oan,  a href="+ccccccccccccL362" ide=L362" class="linserias=porne" namue=L314">us iserias=porn            unsigned porncommon.c#L291" ipornc4" class="line" namue=L364"> 364 /a>        stru4rread32 /4>( a href="+code=cc" cla4s="sr4f">cc/de=chipco_read32" class="sref">chipco_read324"mment">/4      case  a href="+cod4=SSB_4LLTYPE_3" clasiders */ /spaon> 351 /a>         f">chip_id /a> != 0x5365) {> 35ass="line" namue=L317"> 317 /a> spao class="4, 2 divid4rs */ /spaon> 30ass="line" namue=L317"> 317 /a> spao class="4,ef="+cod4="+code=bus" class="sref4>bus 45river_chipcDIV_ROUND_/sCHIPC81 /a>}>SSass="line" namue=L317"> 317 /a> spao class="4,sref">pl4ead32 /a>( a href="+code4cc" c4ass="sref">cc/f="driveriLt="+code3cc" clasirqPLLTYPE_6" clasirq">SSass="line" namue=L317"> 317 /a> spao class="4,ef="+cod454 /a>                }>4a hre4="drivers/ssb/V_ROUND_/sCHIPC81 /a>}> 2dissb/driver_chipcoi_bus /a> * a href="+code=bus" class="sref">bus /a4/a>      4          spao class="co4ment"4/* Fallthough V_ROUND_/sCHIPC81 /a>}> 2LOCK_N" class="sref">/a> * a href="+code=bus" class="sref">bus /a4/ href="+456" class="line" namue=L456"> 456 /a>        f="driveriLt="+code3cc" clasccmin3=cc" class="srecrlass="line" namue=L365"> 3ef">u32 /a>  astruct  a href="+code=ssb_bus" class="sref">ssb_bus " ide=L2lt;s9ss||"line" namue=L356"> 356 /a>        default:>+ssb/driv3er_chipcommon.c#L285" i/a> * a href="+code=bus" class="sref">bus /a4/pcommon.4        * a href="+code=4" cla45a3href="+code=dev" class="sref">devf">chip_id /a4_read32 /4>( a href="+code=cc" cla4s="sr45river_chipcDIV_ROUND_/sCHIPC="+code=SSB_CHIPCO_CAP_PLLT" class="sref">SSB_CHIPCO_CAP_PLLT/oan);> 346 /a>        switch (* a href="+code=plltypu" class="sref">plltypu/oan) {>SSline" namue=L365">chip>m /_irqPLLTYPE_6" claschip>m /_irqdriver_chipcommon.c#L294" ide=L294" class=" return;>/4river_chipcommon.c#L361"4ide=L45href="drivers/ssb/driver_chipcommon.c#L341" ide=4+code=ssb4chipco_timing_init" clas4="sre46b/driver_chipi245" claclass" c50="+code=SSB_CHIPCO_CAP_PLLT" class=ine" namue=L365">"> 351 /a>  1ref="+code=plltypu"51 /a>  1commo304" ide=="driver04aoaa h" class="sref">4devf4=ssb_chip4ommon" class="sref">ssb_4hipco46e" namue=L332"> 332 /a>                * a hre51  " ide3L275"3class="line" namue=L275"> 275 /a>         a hr4iver_chip4ommon.c#L363" ide=L363" 4lass=4line" namue=L363"> 363"+code3cc" clasbaud_bas_PLLTYPE_6" clasbaud_bas_on.cline" namue=L365">chipcalciver_c_rat_PLLTYPE_6" claschipcalciver_c_rat_driver_chipcommon.c#/a> * a href="+code=m" class="srefss="line" namue=L275"> 275 /a>         a hr4ief="+cod4"+code=ssb_device" class4"sref46"drivers/ssb/driver_chipcommoooooooooooooooooooooooooB_CHIPCO_CLOCK_SB/oan) 345 /a>        * a href="+code=plltypu" class="sref">plltypu/oan = fss="line" namue=L275"> 275 /a>         a hr4ia>      4a href="+code=cc" class=4sref"46on.c#L245" ide=L2er_chipcommoooooooooooooooooooooooooB_CHIPCO_CLOCK_SB/oan) 345 /a>        * a href="+co     break;>46SCLKCTL" class="sref">SSB_CHIPCO_SYSdissb/driver_chipcoi_bus 280"u/oan) {>4devf4=read32 /4rs/ode=cc" class="sref">4c/3an46">cc/oan,  a href="+cchip_id" class="sref"min3=cc" class="srecrlass="li/drio304" ide=="driver04aoaa h" class="sref">4devf4=read32 /4xternal IOn.c#L332" idLE4.56" 46r_chipco3ip_id /a>) {s="sref">>                * a hreBCM5354code=mconstant 25MH75" ide3L275"3class="line" namue=L275"> 275 /a>         a hr4/oan,  a 4ref="+code=SSB_CHIPCO_GP4OPULL46LTYPE_3" class="sref"s="sref">SSB_CHIPCO_SYSbaud_bas_PLLTYPE_6" clasbaud_bas_on.clin25000000u/oan) {>SSB_CHIPCO_SYSdissb/driver_chipcoi_bus 28048u/oan) {> 332 /s="sref">>                * a hreSclockcoossbride bit so we doncc" clss="sre it L275"3class="line" namue=L275"> 275 /a>         a hr4lay /a> |4 wrup_delay" claDIV_ROUN4_/ssb47ine" namue=L363"> 363s="sref">SSB_CHIPCO_SYS"driivers/ssb/f="+3304" ide=="driivers/ssb/mmon.c#L345" ide=L345" class="line" namue=L345"> 345 /a>        * a hrefORECTLref="drivers/ssb/driver_chfORECTL"srefss="line" namue=L275"> 275 /a>         a hr4/oan,  a 4ref="+code=SSB_CHIPCO_GP4OPULL47"drivers/ssb/driver_chipcommooooooooooooooooB_CHIPCO_CLOCK_SB/oan) 345 /a>        * a hrefORECTLref="drivers/ssb/driver_chfORECTL"srelass="line" namue=L364"> 364 /a>        stru4f=3+code=4in3req" class="sref">min4re3 /47on.c#L245" ide=L2er_chipcommoooooooooooooooo|45"> 345 /a>        * a hrefORECTL_UARTCLK0ref="drivers/ssb/driver_chfORECTL_UARTCLK0commou/oan) {>4devf4lay /a> +4wrup_delay" claDIV_ROUND4/ssb/47ver_chipcommon.c#L338ooooooooB 275 /a>         a hr4lay /a> |4 wrup_delay" claDIV_ROUN4_/ssb47">cc/oan,  a href="+ccccccccc>SSB_CHIPCO_SYSbaud_bas_PLLTYPE_6" clasbaud_bas_on.clin20000000u/oan) {>) {s="sref"chip_id" class="sref">chip_id /a> != 0x5365) {> 346 /a>        switch (* MUref="+code=plltypu" class="srefMUcommo304" ide=="driver04aoaa h" class="sref">4devf4>) {> 275 /a>         a hr4"+code=re4ision" class="sref">revi4ion /4> >= 20) {>pll_on_d4sref">cc/4an,  a href="+code=SSB_C4IPCO_4PIOPULLDOWN" class="srrrrrrrrrass="line" namue=L340"> 340 /a> spao class="4>) {> 363s="sref">SSB_CHIPCO_SYSdissb/driver_chipcoi_bus 280"u/oan) {>revi4ion /4> >= 20) {>) {s="sref"chip_id" class="sref"min3=cc" class="srecrlass="lretu8021o304" ide=="driver04aoaa h" class="sref">4devf4a>) {>calc_fast_powerup_delay /a>" class="sref">c4sref">cc/4an,  a href="+code=SSB_C4IPCO_4YSCLKCTL" class="sref"63"> 363s="sref">SSB_CHIPCO_SYS"driivers/ssb/f="+3304" ide=="driivers/ssb/mmon.c#L345" ide=L345" class="line" namue=L345"> 345 /a>        * a hrefORECTLref="drivers/ssb/driver_chfORECTL"srefss="line" namue=L275"> 275 /a>         a hr4ommef="+c4de3cc" class="sref">cc/o4n-3gt48ver_chipcommon.c#L338oooooooo="sref"63"> 363s="sref">SSB_CHIPCO_SYS"driive 345 /a>        * a hrefORECTLref="drivers/ssb/driver_chfORECTL"srelass="line" namue=L364"> 364 /a>        stru4) {>cc/oan,  a href="+ccccccccccccccccccccccccccccccccamue=L~5"> 345 /a>        * a hrefORECTL_UARTCLKEhref="drivers/ssb/driver_chfORECTL_UARTCLKEhcommou/oan) {>) {{{{{{{{{ass="line" namue=L340"> 340 /a> spao class="4>) {>  a href="+code=PFX" c4ass="48LTYPE_3" class="sref"s="sref">>                * a hreSclockcoossbride bit so we doncc" clss="sre it L275"3class="line" namue=L275"> 275 /a>         a hr4 href="+c4de=cc" class="sref">cc/o4n->49        default:>SSB_CHIPCO_SYS"driivers/ssb/f="+3304" ide=="driivers/ssb/mmon.c#L345" ide=L345" class="line" namue=L345"> 345 /a>        * a hrefORECTLref="drivers/ssb/driver_chfORECTL"srefss="line" namue=L275"> 275 /a>         a hr4 ref">cc/4id" class="sref">id /a>.4a hre49IOPULLDOWN" class="sr  default:>SSB_CHIPCO_SYS"driive 345 /a>        * a hrefORECTLref="drivers/ssb/driver_chfORECTL"srelass="line" namue=L364"> 364 /a>        stru4 ) {> 345 /a>        * a hrefORECTL_UARTCLK0ref="drivers/ssb/driver_chfORECTL_UARTCLK0commou/oan) {>4devf4ref="driv4rs/ssb/driver_chipcommon4c#L2949on.c#L245" ide=L2ref"s="sref"ooooooooBcalc_fast_powerup_delay /a>" class="sref">c4f="+code=4sb_pmu_init" class="sref4>ssb_49SCLKCTL" class="sref"63"> 363s="sref">SSB_CHIPCO_SYS"driivers/ssb/f="+3304" ide=="driivers/ssb/mmon.c#L345" ide=L345" class="line" namue=L345"> 345 /a>        * a hrefORECTLref="drivers/ssb/driver_chfORECTL"srefss="line" namue=L275"> 275 /a>         a hr4);> 363s="sref">SSB_CHIPCO_SYS"driive 345 /a>        * a hrefORECTLref="drivers/ssb/driver_chfORECTL"srelass="line" namue=L364"> 364 /a>        a hr4) {>cc/oan);>cc/oan,  a href="+cccccccccccccccccccccccccccccccc|45"> 345 /a>        * a hrefORECTL_UARTCLKEhref="drivers/ssb/driver_chfORECTL_UARTCLKEhcommou/oan) {>cc/oan,  a href=4+code49r_chipco3ip_id /a>) {{{{{{{{{ass="line" namue=L340"> 340 /a> spao class="4c" class=4sref">cc/oan);>4devf5vers/ssb/5river_chipcommon.c#L302"5ide=L50        default:> 275 /a>         a hr5+code=ssb5chipco_suspend" class="s5ef">s50e" namue=L332"> 332 /s="sref">+code3cc" clasbaud_bas_PLLTYPE_6" clasbaud_bas_on.cline" namue=L365">chipc idespeeef="+3304" ide==chipc idespeeemmon.c#L345" ide=L34ss="line" namue=L352"> 35ou/oan) {>ssb_chipcomm5n /a>50ine" namue=L363"> 363s="sref">SSB_CHIPCO_SYSdissb/driver_chipcoi_bus 280>SSB_CHIPCO_SYS"driive 345 /a>        * a hrefLKDIV   break;> 364 /a>        a hr5 a href="5code=cc" class="sref">cc5oan-&50"drivers/ssb/driver_chipcommoooooooamue=L346"> 346 /a>        switchsKDIV_UART   break;> * a href="+code=bus" class="sref">bus /a5="drivers5ssb/driver_chipcommon.c#5305" 50on.c#L245" ide=L2ref"} else304" ide=="driver04aoaa h" class="sref">4devf5> 306 /a>5        a href="+code=ss5_chip50SCLKCTL" class="sref"63"> 363B 275 /a>         a hr5+6306 /a>5 "drivers/ssb/driver_chi5+code50ver_chipcommon.c#L338ooooooooB+code3cc" clasbaud_bas_PLLTYPE_6" clasbaud_bas_on.clin88000000u/oan) {>cc/oan);>cc/oan,  a href="+ccccccccc>SSB_CHIPCO_SYSdissb/driver_chipcoi_bus 28048u/oan) {>ss50r_chipco3ip_id /a>) {ass="line" namue=L340"> 340 /a> spao class="5ommon" cl5ss="sref">ssb_chipcommon5/a> *50href="drivers/ssb/driver_chipcommon.c#L341" ide=5 a href="5code=cc" class="sref">cc5oan-&51        default:> 275 /a>         a hr5="drivers5ssb/driver_chipcommon.c#5312" 51e" namue=L332"> 332 /=L245" claclass" claf"min3=cc" class="srecrlass="lretu href="+cod_chss="line" namue=L275"> 275 /a>         a hr5=common" 5        a href="+code=ch5pco_p51ine" namue=L363"> 363s="s!5" claclass" clafdriive 345 /a>        * a hrefORECTLref="drivers/ssb/driver_chfORECTL"sreloamue=L346"> 346 /a>        switchORECTL_UARTCLK0ref="drivers/ssb/driver_chfORECTL_UARTCLK0commoo304" ide=="driver04aoaa h" class="sref">4devf5=cc" clas5="sref">cc/oan);>chip_id /a> != 0x5365) {> 346 /a>        switch (*UARTCLKref="+code=plltypu" class="sreUARTCLK"srelo==4" ide=="driver04aoaa h" class="sref">4devf5="drivers5="sref">cc/oan,  a href=5+code51on.c#L245" ide=L2ref"s="sref"oooo346"> 346 /a>        switch (*UARTCLK_If="drivsb/driver_chipcommon.h (*UARTCLK_If=commo304" ide=="driver04aoaa h" class="sref">4devf5  306 /a>5river_chipcommon.c#L317"5ide=L51SCLKCTL" class="sref"63"> 363s="sref"> 275 /a>         a hr5omment">/5 Get the processor clock5*/ /s51ver_chipcommon.c#L338oooooooo="sref"6B+code3cc" clasbaud_bas_PLLTYPE_6" clasbaud_bas_on.cl/80>SSB_CHIPCO_SYSdissb/driver_chipcoi_bus /a> * a href="+code=bus" class="sref">bus /a5>7306 /a>5 class="line" namue=L3185> 31851">cc/oan,  a href="+ccccccccc} else304" ide=="driver04aoaa h" class="sref">4devf5de=ssb_ch5pcommon" class="sref">ss5_chip51r_chipco3ip_id /a>) {{{{{{{{{s="sref"> 275 /a>         a hr5ommon" cl5/oan,  a href="+code=u325 clas51LTYPE_3" class="sref"s="sref"ooooooooB+code3cc" clasbaud_bas_PLLTYPE_6" clasbaud_bas_on.clin1843200u/oan) {>n/oan =5 a hr52        default:> 340 /a> spao class="5/a>( a hr5f="+code=cc" class="sref5>cc/o52e" namue=L332"> 332 /ass="line" namue=L340"> 340 /a> spao class="5/common" 52       a href="+code=ch52co_p52ine" namue=L3ass="line" namue=L340"> 340 /a> spao class="5/cc" clas5 ide=L324" class="line" 5amue=52; a href="+code=bustypu" class="sref">bustypu /a5ipcommon.5#L325" ide=L325" class="5ine" 52* Fallthough Vpll_on_d5r 306 /a>5#L326" ide=L326" class="5ine" 52SCLKCTL" clasB+code3cc" clasLOCK_N" class="sref">s="sref">SSB_CHIPCO_CAP_PLLT/oan);> 346 /a>        switch (*NRUART   break;>SSB_CHIPCOiPLLTYPE_6" clasion.c> 30a="+code3cc" clasiPLLTYPE_6" clasion.c driver_chipcommon.c#LOCK_N" class="sref">/="+code3cc" clasiPLLTYPE_6" clasion.c++o304" ide=="driver04aoaa h" class="sref">4devf527306 /a>5#L328" ide=L328" class="5ine" 52">cc/oan,  a href="+c/a> * a href="+code=__iomemPLLTYPE_6" clas__iomem>cc/o       unsigned lo_mmioAP_PLLT/oan);> * a href="+code=bus" class="sref">bus /a5_read32 /5>( a href="+code=cc" cla5s="sr52r_chipco3ip_id /a>) {/a> * a href="+code=__iomemPLLTYPE_6" clas__iomem>cc/o       unsigned uart_chg.c#L346" ide=L34uart_chg.bus /a> * a href="+code=bus" class="sref">bus /a5_mmon" cl5      case  a href="+cod5=SSB_52href="drivers/ssb/driver_chipcommon.c#L341" ide=5ipcommon.5#L331" ide=L331" class="5ine" 53        default:> 351 /a>         f">chip_id /a> != 0x5365) {> 35#L352" ide=L352" clammioAP_PLLT/oan);>+"sref">SSB_CHIPCO_CAP_PLLT/oan);>cc/o L346"> 346 /a>       ORE_SIZE   break;>SSB_CHIPCO_uart_chg.c#L346" ide=L34uart_chg.bus > 351 /a>         f"_mmioAP_PLLT/oan);>+L346"> 346 /a>        switcUART0_DATA   break;>bus /a5_read32 /5>( a href="+code=cc" cla5s="sr53ine" namue=L363"> 363"pll_on_d5 334 /a> 5      default:> 364 /a>        a hr5_pcommon.5        * a href="+code=5" cla53on.c#L245" ide=L2ref"s="sref"ef">SSB_CHIPCO_uart_chg.c#L346" ide=L34uart_chg.bus >+="sref">SSB_CHIPCOiPLLTYPE_6" clasion.c * 8ou/oan) {>+="sref">SSB_CHIPCOiPLLTYPE_6" clasion.c * 256ou/oan) {>) {>_chipcommon.c#Lr_porncommon.c#L291" inr_pornc351"++u/oan) {><53LTYPE_3" class="sref"_ROUND_/sCHIPC1porncommon.c#L291" ipornc4" c[ref">SSB_CHIPCOiPLLTYPE_6" clasion.c]>        default:>g.c#L346" ide=L34chg.bus > 351 /a>         uart_chg.c#L346" ide=L34uart_chg.bus /a> * a href="+code=bus" class="sref">bus /a5341" clas5="line" namue=L341"> 3415/a>vo54        default:>SSB_CHIPCOiPLLTYPE_6" clasion.c]>        defaultirqPLLTYPE_6" clasirq">SSline" namue=L365">irqPLLTYPE_6" clasirq">SSass="line" namue=L317"> 317 /a> spao class="5ref="+cod5=ssb_chipcommon" class="5ref">54IOPULLDOWN" class="sref">SSB_CHIPCO_porncommon.c#L291" ipornc4" c[ref">SSB_CHIPCOiPLLTYPE_6" clasion.c]>        defaultbaud_bas_PLLTYPE_6" clasbaud_bas_on.cline" namue=L365">baud_bas_PLLTYPE_6" clasbaud_bas_on.cass="line" namue=L317"> 317 /a> spao class="5rread32 /5typu/oan,  a href="+code5u32" 54ine" namue=L363"> 363"+code3cc" clasporncommon.c#L291" ipornc4" c[ref">SSB_CHIPCOiPLLTYPE_6" clasion.c]>        default:>g_shifne" namue=L314">:>g_shifnon.c> 30ass="line" namue=L317"> 317 /a> spao class="5r334 /a> 5=n" class="sref">n/oan =5 a hr54IOPULLDOWN" cass="line" namue=L340"> 340 /a> spao class="5/a>( a hr5f="+code=cc" class="sref5>cc/o54 3  a href="+codeaon>5a href="+5ode=capabilities" class=5sref"54SCLKCTL" clas="srefSB_CHIPCO_CLOCK_Lr_porncommon.c#L291" inr_pornc351"ass="line" namue=L317"> 317 /a> spao class="5rpcommon.5 ide=L347" class="line" 5amue=5347"> ass="line" namue=L340"> 340 /a> spao class="5/7306 /a>5240 only */ /spaon>cc/#endchirpll_on_d5rread32 /5>( a href="+code=cc" cla5s="sr5f">cc/
Tkcoorigief="LXR software by ckcoode=fast_http://sourceforge.net/projects/lxr">LXR ">plun/seon.c, ckis experis/ssf="up_dion by ode=fast_mailto:lxr@+coux.no">lxr@+coux.noon.c.
lxr.+coux.no kindly hosted"byoode=fast_http://www.redpill-+copro.no">Redpill Lcopro ASon.c, pro"srer3of Lcouxmconsulty" cand operations serrs/ss since 1995.