linux/drivers/mfd/ezx-pcap.c
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 L1">. .14/a>4spa> class="comment">/*4/spa>
 
 L2">. .24/a>4spa> class="comment"> * Driver for Motorola PCAP2 as present in EZX phones4/spa>
 
 L3">. .34/a>4spa> class="comment"> *4/spa>
 
 L4">. .44/a>4spa> class="comment"> * Copyright (C) 2006 Harald Welte <laforge@openezx.org>4/spa>
 
 L5">. .54/a>4spa> class="comment"> * Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>4/spa>
 
 L6">. .64/a>4spa> class="comment"> *4/spa>
 
 L7">. .74/a>4spa> class="comment"> * This program is free software; you ca> redistribute it and/or modify4/spa>
 
 L8">. .84/a>4spa> class="comment"> * it under the terms of the GNU General Public License vers
 
 L9">. .94/a>4spa> class="comment"> * published by the Free Software Founda	2 >.4/spa>
 
 L10">. .9.5a>4spa> class="comment"> *4/spa>
 
 L11">. 114/a>4spa> class="comment"> */4/spa>
 
 L12">. 124/a> 
 L13">. 134/a>#include <linux/module.h4/a>> 
 L14">. 144/a>#include <linux/kernel.h4/a>> 
 L15">. 154/a>#include <linux/platform_device.h4/a>> 
 L16">. 164/a>#include <linux/interrupt.h4/a>> 
 L17">. 174/a>#include <linux/irq.h4/a>> 
 L18">. 184/a>#include <linux/mfd/ezx-pcap.h4/a>> 
 L19">. 194/a>#include <linux/spi/spi.h4/a>> 
 L20">. 204/a>#include <linux/gpio.h4/a>> 
 L21">. 214/a>#include <linux/slab.h4/a>> 
 L22">. 224/a> 
 L23">. 234/a>#define.4a href="+code=PCAP_ADC_MAXQ" class="sref">PCAP_ADC_MAXQ4/a>           8 
 L24">. 244/a>struct.4a href="+code=pcap_adc_request" class="sref">pcap_adc_request4/a> { 
 L25">. 254/a>        4a href="+code=u8" class="sref">u84/a> 4a href="+code=bank" class="sref">bank4/a>; 
 L26">. 264/a>        4a href="+code=u8" class="sref">u84/a> 4a href="+code=ch" class="sref">ch4/a>[2]; 
 L27">. 274/a>        4a href="+code=u32" class="sref">u324/a> 4a href="+code=flags" class="sref">flags4/a>; 
 L28">. 284/a>        void (*4a href="+code=callback" class="sref">callback4/a>)(void *, 4a href="+code=u16" class="sref">u164/a>[]); 
 L29">. 294/a>        void *4a href="+code=da	a" class="sref">da	a4/a>; 
 L30">. 304/a>}; 
 L31">. 314/a> 
 L32">. 324/a>struct.4a href="+code=pcap_adc_sync_request" class="sref">pcap_adc_sync_request4/a> { 
 L33">. 334/a>        4a href="+code=u16" class="sref">u164/a> 4a href="+code=res" class="sref">res4/a>[2]; 
 L34">. 344/a>        struct.4a href="+code=comple	2 >" class="sref">comple	2 >4/a> 4a href="+code=comple	2 >" class="sref">comple	2 >4/a>; 
 L35">. 354/a>}; 
 L36">. 364/a> 
 L37">. 374/a>struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> { 
 L38">. 384/a>        struct.4a href="+code=spi_device" class="sref">spi_device4/a> *4a href="+code=spi" class="sref">spi4/a>; 
 L39">. 394/a> 
 L40">. 404/a>        4spa> class="comment">/* IO */4/spa>
 
 L41">. 414/a>        4a href="+code=u32" class="sref">u324/a> 4a href="+code=buf" class="sref">buf4/a>; 
 L42">. 424/a>        struct.4a href="+code=mutex" class="sref">mutex4/a> 4a href="+code=io_mutex" class="sref">io_mutex4/a>; 
 L43">. 434/a> 
 L44">. 444/a>        4spa> class="comment">/* IRQ */4/spa>
 
 L45">. 454/a>        unsigned int.4a href="+code=irq_base" class="sref">irq_base4/a>; 
 L46">. 464/a>        4a href="+code=u32" class="sref">u324/a> 4a href="+code=msr" class="sref">msr4/a>; 
 L47">. 474/a>        struct.4a href="+code=work_struct" class="sref">work_struct4/a> 4a href="+code=isr_work" class="sref">isr_work4/a>; 
 L48">. 484/a>        struct.4a href="+code=work_struct" class="sref">work_struct4/a> 4a href="+code=msr_work" class="sref">msr_work4/a>; 
 L49">. 494/a>        struct.4a href="+code=workqueue_struct" class="sref">workqueue_struct4/a> *4a href="+code=workqueue" class="sref">workqueue4/a>; 
 L50">. 504/a> 
 L51">. 514/a>        4spa> class="comment">/* ADC */4/spa>
 
 L52">. 524/a>        struct.4a href="+code=pcap_adc_request" class="sref">pcap_adc_request4/a> *4a href="+code=adc_queue" class="sref">adc_queue4/a>[4a href="+code=PCAP_ADC_MAXQ" class="sref">PCAP_ADC_MAXQ4/a>]; 
 L53">. 534/a>        4a href="+code=u8" class="sref">u84/a> 4a href="+code=adc_head" class="sref">adc_head4/a>; 
 L54">. 544/a>        4a href="+code=u8" class="sref">u84/a> 4a href="+code=adc_tail" class="sref">adc_tail4/a>; 
 L55">. 554/a>        struct.4a href="+code=mutex" class="sref">mutex4/a> 4a href="+code=adc_mutex" class="sref">adc_mutex4/a>; 
 L56">. 564/a>}; 
 L57">. 574/a> 
 L58">. 584/a>4spa> class="comment">/* IO */4/spa>
 
 L59">. 594/a>static int.4a href="+code=ezx_pcap_putget" class="sref">ezx_pcap_putget4/a>(struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=u32" class="sref">u324/a> *4a href="+code=da	a" class="sref">da	a4/a>) 
 L60">. 604/a>{ 
 L61">. 614/a>        struct.4a href="+code=spi_transfer" class="sref">spi_transfer4/a> 4a href="+code=t" class="sref">t4/a>; 
 L62">. 624/a>        struct.4a href="+code=spi_message" class="sref">spi_message4/a> 4a href="+code=m" class="sref">m4/a>; 
 L63">. 634/a>        int.4a href="+code=status" class="sref">status4/a>; 
 L64">. 644/a> 
 L65">. 654/a>        4a href="+code=memset" class="sref">memset4/a>(&4a href="+code=t" class="sref">t4/a>, 0, sizeof 4a href="+code=t" class="sref">t4/a>); 
 L66">. 664/a>        4a href="+code=spi_message_init" class="sref">spi_message_init4/a>(&4a href="+code=m" class="sref">m4/a>); 
 L67">. 674/a>        4a href="+code=t" class="sref">t4/a>.4a href="+code=le>" class="sref">le>4/a> = sizeof(4a href="+code=u32" class="sref">u324/a>); 
 L68">. 684/a>        4a href="+code=spi_message_add_tail" class="sref">spi_message_add_tail4/a>(&4a href="+code=t" class="sref">t4/a>, &4a href="+code=m" class="sref">m4/a>); 
 L69">. 694/a> 
 L70">. 704/a>        4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=buf" class="sref">buf4/a> = *4a href="+code=da	a" class="sref">da	a4/a>; 
 L71">. 714/a>        4a href="+code=t" class="sref">t4/a>.4a href="+code=tx_buf" class="sref">tx_buf4/a> = (4a href="+code=u8" class="sref">u84/a> *) &4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=buf" class="sref">buf4/a>; 
 L72">. 724/a>        4a href="+code=t" class="sref">t4/a>.4a href="+code=rx_buf" class="sref">rx_buf4/a> = (4a href="+code=u8" class="sref">u84/a> *) &4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=buf" class="sref">buf4/a>; 
 L73">. 734/a>        4a href="+code=status" class="sref">status4/a> = 4a href="+code=spi_sync" class="sref">spi_sync4/a>(4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=spi" class="sref">spi4/a>, &4a href="+code=m" class="sref">m4/a>); 
 L74">. 744/a> 
 L75">. 754/a>        if (4a href="+code=status" class="sref">status4/a> == 0) 
 L76">. 764/a>                *4a href="+code=da	a" class="sref">da	a4/a> = 4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=buf" class="sref">buf4/a>; 
 L77">. 774/a> 
 L78">. 784/a>        return 4a href="+code=status" class="sref">status4/a>; 
 L79">. 794/a>} 
 L80">. 804/a> 
 L81">. 814/a>int.4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>(struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=u8" class="sref">u84/a> 4a href="+code=reg_num" class="sref">reg_num4/a>, 4a href="+code=u32" class="sref">u324/a> 4a href="+code=tion>" class="sref">tion>4/a>) 
 L82">. 824/a>{ 
 L83">. 834/a>        int.4a href="+code=ret" class="sref">ret4/a>; 
 L84">. 844/a> 
 L85">. 854/a>        4a href="+code=mutex_lock" class="sref">mutex_lock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=io_mutex" class="sref">io_mutex4/a>); 
 L86">. 864/a>        4a href="+code=tion>" class="sref">tion>4/a> &= 4a href="+code=PCAP_REGISTER_VALUE_MASK" class="sref">PCAP_REGISTER_VALUE_MASK4/a>; 
 L87">. 874/a>        4a href="+code=tion>" class="sref">tion>4/a> |= 4a href="+code=PCAP_REGISTER_WRITE_OP_BIT" class="sref">PCAP_REGISTER_WRITE_OP_BIT4/a> 
 L88">. 884/a>                | (4a href="+code=reg_num" class="sref">reg_num4/a> << 4a href="+code=PCAP_REGISTER_ADDRESS_SHIFT" class="sref">PCAP_REGISTER_ADDRESS_SHIFT4/a>); 
 L89">. 894/a>        4a href="+code=ret" class="sref">ret4/a> = 4a href="+code=ezx_pcap_putget" class="sref">ezx_pcap_putget4/a>(4a href="+code=pcap" class="sref">pcap4/a>, &4a href="+code=tion>" class="sref">tion>4/a>); 
 L90">. 904/a>        4a href="+code=mutex_unlock" class="sref">mutex_unlock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=io_mutex" class="sref">io_mutex4/a>); 
 L91">. 914/a> 
 L92">. 924/a>        return 4a href="+code=ret" class="sref">ret4/a>; 
 L93">. 934/a>} 
 L94">. 944/a>4a href="+code=EXPORT_SYMBOL_GPL" class="sref">EXPORT_SYMBOL_GPL4/a>(4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>); 
 L95">. 954/a> 
 L96">. 964/a>int.4a href="+code=ezx_pcap_read" class="sref">ezx_pcap_read4/a>(struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=u8" class="sref">u84/a> 4a href="+code=reg_num" class="sref">reg_num4/a>, 4a href="+code=u32" class="sref">u324/a> *4a href="+code=tion>" class="sref">tion>4/a>) 
 L97">. 974/a>{ 
 L98">. 984/a>        int.4a href="+code=ret" class="sref">ret4/a>; 
 L99">. 994/a> 
 L100">.1004/a>        4a href="+code=mutex_lock" class="sref">mutex_lock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=io_mutex" class="sref">io_mutex4/a>); 
 L101">.1014/a>        *4a href="+code=tion>" class="sref">tion>4/a> = 4a href="+code=PCAP_REGISTER_READ_OP_BIT" class="sref">PCAP_REGISTER_READ_OP_BIT4/a> 
 L102">.1024/a>                | (4a href="+code=reg_num" class="sref">reg_num4/a> << 4a href="+code=PCAP_REGISTER_ADDRESS_SHIFT" class="sref">PCAP_REGISTER_ADDRESS_SHIFT4/a>); 
 L103">.1034/a> 
 L104">.1044/a>        4a href="+code=ret" class="sref">ret4/a> = 4a href="+code=ezx_pcap_putget" class="sref">ezx_pcap_putget4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=tion>" class="sref">tion>4/a>); 
 L105">.1054/a>        4a href="+code=mutex_unlock" class="sref">mutex_unlock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=io_mutex" class="sref">io_mutex4/a>); 
 L106">.1064/a> 
 L107">.1074/a>        return 4a href="+code=ret" class="sref">ret4/a>; 
 L108">.1084/a>} 
 L109">.1094/a>4a href="+code=EXPORT_SYMBOL_GPL" class="sref">EXPORT_SYMBOL_GPL4/a>(4a href="+code=ezx_pcap_read" class="sref">ezx_pcap_read4/a>); 
 L110">.1104/a> 
 L111">.1114/a>int.4a href="+code=ezx_pcap_set_bits" class="sref">ezx_pcap_set_bits4/a>(struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=u8" class="sref">u84/a> 4a href="+code=reg_num" class="sref">reg_num4/a>, 4a href="+code=u32" class="sref">u324/a> 4a href="+code=mask" class="sref">mask4/a>, 4a href="+code=u32" class="sref">u324/a> 4a href="+code=tio" class="sref">tio4/a>) 
 L112">.1124/a>{ 
 L113">.1134/a>        int.4a href="+code=ret" class="sref">ret4/a>; 
 L114">.1144/a>        4a href="+code=u32" class="sref">u324/a> 4a href="+code=tmp" class="sref">tmp4/a> = 4a href="+code=PCAP_REGISTER_READ_OP_BIT" class="sref">PCAP_REGISTER_READ_OP_BIT4/a> | 
 L115">.1154/a>                (4a href="+code=reg_num" class="sref">reg_num4/a> << 4a href="+code=PCAP_REGISTER_ADDRESS_SHIFT" class="sref">PCAP_REGISTER_ADDRESS_SHIFT4/a>); 
 L116">.1164/a> 
 L117">.1174/a>        4a href="+code=mutex_lock" class="sref">mutex_lock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=io_mutex" class="sref">io_mutex4/a>); 
 L118">.1184/a>        4a href="+code=ret" class="sref">ret4/a> = 4a href="+code=ezx_pcap_putget" class="sref">ezx_pcap_putget4/a>(4a href="+code=pcap" class="sref">pcap4/a>, &4a href="+code=tmp" class="sref">tmp4/a>); 
 L119">.1194/a>        if (4a href="+code=ret" class="sref">ret4/a>) 
 L120">.1204/a>                goto 4a href="+code=out_unlock" class="sref">out_unlock4/a>; 
 L121">.1214/a> 
 L122">.1224/a>        4a href="+code=tmp" class="sref">tmp4/a> &= (4a href="+code=PCAP_REGISTER_VALUE_MASK" class="sref">PCAP_REGISTER_VALUE_MASK4/a> & ~4a href="+code=mask" class="sref">mask4/a>); 
 L123">.1234/a>        4a href="+code=tmp" class="sref">tmp4/a> |= (4a href="+code=tio" class="sref">tio4/a> & 4a href="+code=mask" class="sref">mask4/a>) | 4a href="+code=PCAP_REGISTER_WRITE_OP_BIT" class="sref">PCAP_REGISTER_WRITE_OP_BIT4/a> | 
 L124">.1244/a>                (4a href="+code=reg_num" class="sref">reg_num4/a> << 4a href="+code=PCAP_REGISTER_ADDRESS_SHIFT" class="sref">PCAP_REGISTER_ADDRESS_SHIFT4/a>); 
 L125">.1254/a> 
 L126">.1264/a>        4a href="+code=ret" class="sref">ret4/a> = 4a href="+code=ezx_pcap_putget" class="sref">ezx_pcap_putget4/a>(4a href="+code=pcap" class="sref">pcap4/a>, &4a href="+code=tmp" class="sref">tmp4/a>); 
 L127">.1274/a>4a href="+code=out_unlock" class="sref">out_unlock4/a>: 
 L128">.1284/a>        4a href="+code=mutex_unlock" class="sref">mutex_unlock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=io_mutex" class="sref">io_mutex4/a>); 
 L129">.1294/a> 
 L130">.1304/a>        return 4a href="+code=ret" class="sref">ret4/a>; 
 L131">.1314/a>} 
 L132">.1324/a>4a href="+code=EXPORT_SYMBOL_GPL" class="sref">EXPORT_SYMBOL_GPL4/a>(4a href="+code=ezx_pcap_set_bits" class="sref">ezx_pcap_set_bits4/a>); 
 L133">.1334/a> 
 L134">.1344/a>4spa> class="comment">/* IRQ */4/spa>
 
 L135">.1354/a>int.4a href="+code=irq_to_pcap" class="sref">irq_to_pcap4/a>(struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a>, int.4a href="+code=irq" class="sref">irq4/a>) 
 L136">.1364/a>{ 
 L137">.1374/a>        return 4a href="+code=irq" class="sref">irq4/a> - 4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=irq_base" class="sref">irq_base4/a>; 
 L138">.1384/a>} 
 L139">.1394/a>4a href="+code=EXPORT_SYMBOL_GPL" class="sref">EXPORT_SYMBOL_GPL4/a>(4a href="+code=irq_to_pcap" class="sref">irq_to_pcap4/a>); 
 L140">.1404/a> 
 L141">.1414/a>int.4a href="+code=pcap_to_irq" class="sref">pcap_to_irq4/a>(struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a>, int.4a href="+code=irq" class="sref">irq4/a>) 
 L142">.1424/a>{ 
 L143">.1434/a>        return 4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=irq_base" class="sref">irq_base4/a> +.4a href="+code=irq" class="sref">irq4/a>; 
 L144">.1444/a>} 
 L145">.1454/a>4a href="+code=EXPORT_SYMBOL_GPL" class="sref">EXPORT_SYMBOL_GPL4/a>(4a href="+code=pcap_to_irq" class="sref">pcap_to_irq4/a>); 
 L146">.1464/a> 
 L147">.1474/a>static void 4a href="+code=pcap_mask_irq" class="sref">pcap_mask_irq4/a>(struct.4a href="+code=irq_da	a" class="sref">irq_da	a4/a> *4a href="+code=d" class="sref">d4/a>) 
 L148">.1484/a>{ 
 L149">.1494/a>        struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a> = 4a href="+code=irq_da	a_get_irq_chip_da	a" class="sref">irq_da	a_get_irq_chip_da	a4/a>(4a href="+code=d" class="sref">d4/a>); 
 L150">.1504/a> 
 L151">.1514/a>        4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=msr" class="sref">msr4/a> |= 1 << 4a href="+code=irq_to_pcap" class="sref">irq_to_pcap4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=d" class="sref">d4/a>->4a href="+code=irq" class="sref">irq4/a>); 
 L152">.1524/a>        4a href="+code=queue_work" class="sref">queue_work4/a>(4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=workqueue" class="sref">workqueue4/a>, &4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=msr_work" class="sref">msr_work4/a>); 
 L153">.1534/a>} 
 L154">.1544/a> 
 L155">.1554/a>static void 4a href="+code=pcap_unmask_irq" class="sref">pcap_unmask_irq4/a>(struct.4a href="+code=irq_da	a" class="sref">irq_da	a4/a> *4a href="+code=d" class="sref">d4/a>) 
 L156">.1564/a>{ 
 L157">.1574/a>        struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a> = 4a href="+code=irq_da	a_get_irq_chip_da	a" class="sref">irq_da	a_get_irq_chip_da	a4/a>(4a href="+code=d" class="sref">d4/a>); 
 L158">.1584/a> 
 L159">.1594/a>        4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=msr" class="sref">msr4/a> &= ~(1 << 4a href="+code=irq_to_pcap" class="sref">irq_to_pcap4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=d" class="sref">d4/a>->4a href="+code=irq" class="sref">irq4/a>)); 
 L160">.1604/a>        4a href="+code=queue_work" class="sref">queue_work4/a>(4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=workqueue" class="sref">workqueue4/a>, &4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=msr_work" class="sref">msr_work4/a>); 
 L161">.1614/a>} 
 L162">.1624/a> 
 L163">.1634/a>static struct.4a href="+code=irq_chip" class="sref">irq_chip4/a> 4a href="+code=pcap_irq_chip" class="sref">pcap_irq_chip4/a> = { 
 L164">.1644/a>        .4a href="+code=nam>" class="sref">nam>4/a>           = 4spa> class="string">"pcap"4/spa>
, 
 L165">.1654/a>        .4a href="+code=irq_disable" class="sref">irq_disable4/a>    = 4a href="+code=pcap_mask_irq" class="sref">pcap_mask_irq4/a>, 
 L166">.1664/a>        .4a href="+code=irq_mask" class="sref">irq_mask4/a>       = 4a href="+code=pcap_mask_irq" class="sref">pcap_mask_irq4/a>, 
 L167">.1674/a>        .4a href="+code=irq_unmask" class="sref">irq_unmask4/a>     = 4a href="+code=pcap_unmask_irq" class="sref">pcap_unmask_irq4/a>, 
 L168">.1684/a>}; 
 L169">.1694/a> 
 L170">.1704/a>static void 4a href="+code=pcap_msr_work" class="sref">pcap_msr_work4/a>(struct.4a href="+code=work_struct" class="sref">work_struct4/a> *4a href="+code=work" class="sref">work4/a>) 
 L171">.1714/a>{ 
 L172">.1724/a>        struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a> = 4a href="+code=container_of" class="sref">container_of4/a>(4a href="+code=work" class="sref">work4/a>, struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a>, 4a href="+code=msr_work" class="sref">msr_work4/a>); 
 L173">.1734/a> 
 L174">.1744/a>        4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_MSR" class="sref">PCAP_REG_MSR4/a>, 4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=msr" class="sref">msr4/a>); 
 L175">.1754/a>} 
 L176">.1764/a> 
 L177">.1774/a>static void 4a href="+code=pcap_isr_work" class="sref">pcap_isr_work4/a>(struct.4a href="+code=work_struct" class="sref">work_struct4/a> *4a href="+code=work" class="sref">work4/a>) 
 L178">.1784/a>{ 
 L179">.1794/a>        struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a> = 4a href="+code=container_of" class="sref">container_of4/a>(4a href="+code=work" class="sref">work4/a>, struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a>, 4a href="+code=isr_work" class="sref">isr_work4/a>); 
 L180">.1804/a>        struct.4a href="+code=pcap_platform_da	a" class="sref">pcap_platform_da	a4/a> *4a href="+code=pda	a" class="sref">pda	a4/a> = 4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=spi" class="sref">spi4/a>->4a href="+code=dev" class="sref">dev4/a>.4a href="+code=platform_da	a" class="sref">platform_da	a4/a>; 
 L181">.1814/a>        4a href="+code=u32" class="sref">u324/a> 4a href="+code=msr" class="sref">msr4/a>, 4a href="+code=isr" class="sref">isr4/a>, 4a href="+code=int_seo" class="sref">int_seo4/a>, 4a href="+code=service" class="sref">service4/a>; 
 L182">.1824/a>        int.4a href="+code=irq" class="sref">irq4/a>; 
 L183">.1834/a> 
 L184">.1844/a>        do { 
 L185">.1854/a>                4a href="+code=ezx_pcap_read" class="sref">ezx_pcap_read4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_MSR" class="sref">PCAP_REG_MSR4/a>, &4a href="+code=msr" class="sref">msr4/a>); 
 L186">.1864/a>                4a href="+code=ezx_pcap_read" class="sref">ezx_pcap_read4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_ISR" class="sref">PCAP_REG_ISR4/a>, &4a href="+code=isr" class="sref">isr4/a>); 
 L187">.1874/a> 
 L188">.1884/a>                4spa> class="comment">/* We can't service/ack irqs that are assigned to port 2 */4/spa>
 
 L189">.1894/a>                if (!(4a href="+code=pda	a" class="sref">pda	a4/a>->4a href="+code=config" class="sref">config4/a> & 4a href="+code=PCAP_SECOND_PORT" class="sref">PCAP_SECOND_PORT4/a>)) { 
 L190">.1904/a>                        4a href="+code=ezx_pcap_read" class="sref">ezx_pcap_read4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_INT_SEL" class="sref">PCAP_REG_INT_SEL4/a>, &4a href="+code=int_seo" class="sref">int_seo4/a>); 
 L191">.1914/a>                        4a href="+code=isr" class="sref">isr4/a> &= ~4a href="+code=int_seo" class="sref">int_seo4/a>; 
 L192">.1924/a>                } 
 L193">.1934/a> 
 L194">.1944/a>                4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_MSR" class="sref">PCAP_REG_MSR4/a>, 4a href="+code=isr" class="sref">isr4/a> | 4a href="+code=msr" class="sref">msr4/a>); 
 L195">.1954/a>                4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_ISR" class="sref">PCAP_REG_ISR4/a>, 4a href="+code=isr" class="sref">isr4/a>); 
 L196">.1964/a> 
 L197">.1974/a>                4a href="+code=local_irq_disable" class="sref">local_irq_disable4/a>(); 
 L198">.1984/a>                4a href="+code=service" class="sref">service4/a> = 4a href="+code=isr" class="sref">isr4/a> & ~4a href="+code=msr" class="sref">msr4/a>; 
 L199">.1994/a>                for (4a href="+code=irq" class="sref">irq4/a> = 4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=irq_base" class="sref">irq_base4/a>; 4a href="+code=service" class="sref">service4/a>; 4a href="+code=service" class="sref">service4/a> >>= 1, 4a href="+code=irq" class="sref">irq4/a>++) { 
 L200">.2004/a>                        if (4a href="+code=service" class="sref">service4/a> & 1) 
 L201">.2014/a>                                4a href="+code=generic_handle_irq" class="sref">generic_handle_irq4/a>(4a href="+code=irq" class="sref">irq4/a>); 
 L202">.2024/a>                } 
 L203">.2034/a>                4a href="+code=local_irq_enable" class="sref">local_irq_enable4/a>(); 
 L204">.2044/a>                4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_MSR" class="sref">PCAP_REG_MSR4/a>, 4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=msr" class="sref">msr4/a>); 
 L205">.2054/a>        } while (4a href="+code=gpio_get_tion>" class="sref">gpio_get_tion>4/a>(4a href="+code=pda	a" class="sref">pda	a4/a>->4a href="+code=gpio" class="sref">gpio4/a>)); 
 L206">.2064/a>} 
 L207">.2074/a> 
 L208">.2084/a>static void 4a href="+code=pcap_irq_handler" class="sref">pcap_irq_handler4/a>(unsigned int.4a href="+code=irq" class="sref">irq4/a>, struct.4a href="+code=irq_desc" class="sref">irq_desc4/a> *4a href="+code=desc" class="sref">desc4/a>) 
 L209">.2094/a>{ 
 L210">.2104/a>        struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a> = 4a href="+code=irq_get_handler_da	a" class="sref">irq_get_handler_da	a4/a>(4a href="+code=irq" class="sref">irq4/a>); 
 L211">.2114/a> 
 L212">.2124/a>        4a href="+code=desc" class="sref">desc4/a>->4a href="+code=irq_da	a" class="sref">irq_da	a4/a>.4a href="+code=chip" class="sref">chip4/a>->4a href="+code=irq_ack" class="sref">irq_ack4/a>(&4a href="+code=desc" class="sref">desc4/a>->4a href="+code=irq_da	a" class="sref">irq_da	a4/a>); 
 L213">.2134/a>        4a href="+code=queue_work" class="sref">queue_work4/a>(4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=workqueue" class="sref">workqueue4/a>, &4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=isr_work" class="sref">isr_work4/a>); 
 L214">.2144/a>        return; 
 L215">.2154/a>} 
 L216">.2164/a> 
 L217">.2174/a>4spa> class="comment">/* ADC */4/spa>
 
 L218">.2184/a>void 4a href="+code=pcap_set_ts_bits" class="sref">pcap_set_ts_bits4/a>(struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=u32" class="sref">u324/a> 4a href="+code=bits" class="sref">bits4/a>) 
 L219">.2194/a>{ 
 L220">.2204/a>        4a href="+code=u32" class="sref">u324/a> 4a href="+code=tmp" class="sref">tmp4/a>; 
 L221">.2214/a> 
 L222">.2224/a>        4a href="+code=mutex_lock" class="sref">mutex_lock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L223">.2234/a>        4a href="+code=ezx_pcap_read" class="sref">ezx_pcap_read4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_ADC" class="sref">PCAP_REG_ADC4/a>, &4a href="+code=tmp" class="sref">tmp4/a>); 
 L224">.2244/a>        4a href="+code=tmp" class="sref">tmp4/a> &= ~(4a href="+code=PCAP_ADC_TS_M_MASK" class="sref">PCAP_ADC_TS_M_MASK4/a> | 4a href="+code=PCAP_ADC_TS_REF_LOWPWR" class="sref">PCAP_ADC_TS_REF_LOWPWR4/a>); 
 L225">.2254/a>        4a href="+code=tmp" class="sref">tmp4/a> |= 4a href="+code=bits" class="sref">bits4/a> & (4a href="+code=PCAP_ADC_TS_M_MASK" class="sref">PCAP_ADC_TS_M_MASK4/a> | 4a href="+code=PCAP_ADC_TS_REF_LOWPWR" class="sref">PCAP_ADC_TS_REF_LOWPWR4/a>); 
 L226">.2264/a>        4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_ADC" class="sref">PCAP_REG_ADC4/a>, 4a href="+code=tmp" class="sref">tmp4/a>); 
 L227">.2274/a>        4a href="+code=mutex_unlock" class="sref">mutex_unlock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L228">.2284/a>} 
 L229">.2294/a>4a href="+code=EXPORT_SYMBOL_GPL" class="sref">EXPORT_SYMBOL_GPL4/a>(4a href="+code=pcap_set_ts_bits" class="sref">pcap_set_ts_bits4/a>); 
 L230">.2304/a> 
 L231">.2314/a>static void 4a href="+code=pcap_disable_adc" class="sref">pcap_disable_adc4/a>(struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a>) 
 L232">.2324/a>{ 
 L233">.2334/a>        4a href="+code=u32" class="sref">u324/a> 4a href="+code=tmp" class="sref">tmp4/a>; 
 L234">.2344/a> 
 L235">.2354/a>        4a href="+code=ezx_pcap_read" class="sref">ezx_pcap_read4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_ADC" class="sref">PCAP_REG_ADC4/a>, &4a href="+code=tmp" class="sref">tmp4/a>); 
 L236">.2364/a>        4a href="+code=tmp" class="sref">tmp4/a> &= ~(4a href="+code=PCAP_ADC_ADEN" class="sref">PCAP_ADC_ADEN4/a>|4a href="+code=PCAP_ADC_BATT_I_ADC" class="sref">PCAP_ADC_BATT_I_ADC4/a>|4a href="+code=PCAP_ADC_BATT_I_POLARITY" class="sref">PCAP_ADC_BATT_I_POLARITY4/a>); 
 L237">.2374/a>        4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_ADC" class="sref">PCAP_REG_ADC4/a>, 4a href="+code=tmp" class="sref">tmp4/a>); 
 L238">.2384/a>} 
 L239">.2394/a> 
 L240">.2404/a>static void 4a href="+code=pcap_adc_trigger" class="sref">pcap_adc_trigger4/a>(struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a>) 
 L241">.2414/a>{ 
 L242">.2424/a>        4a href="+code=u32" class="sref">u324/a> 4a href="+code=tmp" class="sref">tmp4/a>; 
 L243">.2434/a>        4a href="+code=u8" class="sref">u84/a> 4a href="+code=head" class="sref">head4/a>; 
 L244">.2444/a> 
 L245">.2454/a>        4a href="+code=mutex_lock" class="sref">mutex_lock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L246">.2464/a>        4a href="+code=head" class="sref">head4/a> = 4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_head" class="sref">adc_head4/a>; 
 L247">.2474/a>        if (!4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_queue" class="sref">adc_queue4/a>[4a href="+code=head" class="sref">head4/a>]) { 
 L248">.2484/a>                4spa> class="comment">/* queue is empty, save power */4/spa>
 
 L249">.2494/a>                4a href="+code=pcap_disable_adc" class="sref">pcap_disable_adc4/a>(4a href="+code=pcap" class="sref">pcap4/a>); 
 L250">.2504/a>                4a href="+code=mutex_unlock" class="sref">mutex_unlock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L251">.2514/a>                return; 
 L252">.2524/a>        } 
 L253">.2534/a>        4spa> class="comment">/* start conversion on requested bank, save TS_M bits */4/spa>
 
 L254">.2544/a>        4a href="+code=ezx_pcap_read" class="sref">ezx_pcap_read4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_ADC" class="sref">PCAP_REG_ADC4/a>, &4a href="+code=tmp" class="sref">tmp4/a>); 
 L255">.2554/a>        4a href="+code=tmp" class="sref">tmp4/a> &= (4a href="+code=PCAP_ADC_TS_M_MASK" class="sref">PCAP_ADC_TS_M_MASK4/a> | 4a href="+code=PCAP_ADC_TS_REF_LOWPWR" class="sref">PCAP_ADC_TS_REF_LOWPWR4/a>); 
 L256">.2564/a>        4a href="+code=tmp" class="sref">tmp4/a> |= 4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_queue" class="sref">adc_queue4/a>[4a href="+code=head" class="sref">head4/a>]->4a href="+code=flags" class="sref">flags4/a> | 4a href="+code=PCAP_ADC_ADEN" class="sref">PCAP_ADC_ADEN4/a>; 
 L257">.2574/a> 
 L258">.2584/a>        if (4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_queue" class="sref">adc_queue4/a>[4a href="+code=head" class="sref">head4/a>]->4a href="+code=bank" class="sref">bank4/a> == 4a href="+code=PCAP_ADC_BANK_1" class="sref">PCAP_ADC_BANK_14/a>) 
 L259">.2594/a>                4a href="+code=tmp" class="sref">tmp4/a> |= 4a href="+code=PCAP_ADC_AD_SEL1" class="sref">PCAP_ADC_AD_SEL14/a>; 
 L260">.2604/a> 
 L261">.2614/a>        4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_ADC" class="sref">PCAP_REG_ADC4/a>, 4a href="+code=tmp" class="sref">tmp4/a>); 
 L262">.2624/a>        4a href="+code=mutex_unlock" class="sref">mutex_unlock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L263">.2634/a>        4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_ADR" class="sref">PCAP_REG_ADR4/a>, 4a href="+code=PCAP_ADR_ASC" class="sref">PCAP_ADR_ASC4/a>); 
 L264">.2644/a>} 
 L265">.2654/a> 
 L266">.2664/a>static 4a href="+code=irqreturn_t" class="sref">irqreturn_t4/a> 4a href="+code=pcap_adc_irq" class="sref">pcap_adc_irq4/a>(int.4a href="+code=irq" class="sref">irq4/a>, void *4a href="+code=_pcap" class="sref">_pcap4/a>) 
 L267">.2674/a>{ 
 L268">.2684/a>        struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a> = 4a href="+code=_pcap" class="sref">_pcap4/a>; 
 L269">.2694/a>        struct.4a href="+code=pcap_adc_request" class="sref">pcap_adc_request4/a> *4a href="+code=req" class="sref">req4/a>; 
 L270">.2704/a>        4a href="+code=u16" class="sref">u164/a> 4a href="+code=res" class="sref">res4/a>[2]; 
 L271">.2714/a>        4a href="+code=u32" class="sref">u324/a> 4a href="+code=tmp" class="sref">tmp4/a>; 
 L272">.2724/a> 
 L273">.2734/a>        4a href="+code=mutex_lock" class="sref">mutex_lock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L274">.2744/a>        4a href="+code=req" class="sref">req4/a> = 4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_queue" class="sref">adc_queue4/a>[4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_head" class="sref">adc_head4/a>]; 
 L275">.2754/a> 
 L276">.2764/a>        if (4a href="+code=WARN" class="sref">WARN4/a>(!4a href="+code=req" class="sref">req4/a>, 4spa> class="string">"adc irq without pending request\n"4/spa>
)) { 
 L277">.2774/a>                4a href="+code=mutex_unlock" class="sref">mutex_unlock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L278">.2784/a>                return 4a href="+code=IRQ_HANDLED" class="sref">IRQ_HANDLED4/a>; 
 L279">.2794/a>        } 
 L280">.2804/a> 
 L281">.2814/a>        4spa> class="comment">/* read requested channels results */4/spa>
 
 L282">.2824/a>        4a href="+code=ezx_pcap_read" class="sref">ezx_pcap_read4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_ADC" class="sref">PCAP_REG_ADC4/a>, &4a href="+code=tmp" class="sref">tmp4/a>); 
 L283">.2834/a>        4a href="+code=tmp" class="sref">tmp4/a> &= ~(4a href="+code=PCAP_ADC_ADA1_MASK" class="sref">PCAP_ADC_ADA1_MASK4/a> | 4a href="+code=PCAP_ADC_ADA2_MASK" class="sref">PCAP_ADC_ADA2_MASK4/a>); 
 L284">.2844/a>        4a href="+code=tmp" class="sref">tmp4/a> |= (4a href="+code=req" class="sref">req4/a>->4a href="+code=ch" class="sref">ch4/a>[0] << 4a href="+code=PCAP_ADC_ADA1_SHIFT" class="sref">PCAP_ADC_ADA1_SHIFT4/a>); 
 L285">.2854/a>        4a href="+code=tmp" class="sref">tmp4/a> |= (4a href="+code=req" class="sref">req4/a>->4a href="+code=ch" class="sref">ch4/a>[1] << 4a href="+code=PCAP_ADC_ADA2_SHIFT" class="sref">PCAP_ADC_ADA2_SHIFT4/a>); 
 L286">.2864/a>        4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_ADC" class="sref">PCAP_REG_ADC4/a>, 4a href="+code=tmp" class="sref">tmp4/a>); 
 L287">.2874/a>        4a href="+code=ezx_pcap_read" class="sref">ezx_pcap_read4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_ADR" class="sref">PCAP_REG_ADR4/a>, &4a href="+code=tmp" class="sref">tmp4/a>); 
 L288">.2884/a>        4a href="+code=res" class="sref">res4/a>[0] = (4a href="+code=tmp" class="sref">tmp4/a> & 4a href="+code=PCAP_ADR_ADD1_MASK" class="sref">PCAP_ADR_ADD1_MASK4/a>) >> 4a href="+code=PCAP_ADR_ADD1_SHIFT" class="sref">PCAP_ADR_ADD1_SHIFT4/a>; 
 L289">.2894/a>        4a href="+code=res" class="sref">res4/a>[1] = (4a href="+code=tmp" class="sref">tmp4/a> & 4a href="+code=PCAP_ADR_ADD2_MASK" class="sref">PCAP_ADR_ADD2_MASK4/a>) >> 4a href="+code=PCAP_ADR_ADD2_SHIFT" class="sref">PCAP_ADR_ADD2_SHIFT4/a>; 
 L290">.2904/a> 
 L291">.2914/a>        4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_queue" class="sref">adc_queue4/a>[4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_head" class="sref">adc_head4/a>] = 4a href="+code=NULL" class="sref">NULL4/a>; 
 L292">.2924/a>        4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_head" class="sref">adc_head4/a> = (4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_head" class="sref">adc_head4/a> + 1) & (4a href="+code=PCAP_ADC_MAXQ" class="sref">PCAP_ADC_MAXQ4/a> - 1); 
 L293">.2934/a>        4a href="+code=mutex_unlock" class="sref">mutex_unlock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L294">.2944/a> 
 L295">.2954/a>        4spa> class="comment">/* pass the results and release memory */4/spa>
 
 L296">.2964/a>        4a href="+code=req" class="sref">req4/a>->4a href="+code=callback" class="sref">callback4/a>(4a href="+code=req" class="sref">req4/a>->4a href="+code=da	a" class="sref">da	a4/a>, 4a href="+code=res" class="sref">res4/a>); 
 L297">.2974/a>        4a href="+code=kfree" class="sref">kfree4/a>(4a href="+code=req" class="sref">req4/a>); 
 L298">.2984/a> 
 L299">.2994/a>        4spa> class="comment">/* trigger next conversion (if any) on queue */4/spa>
 
 L300">.3004/a>        4a href="+code=pcap_adc_trigger" class="sref">pcap_adc_trigger4/a>(4a href="+code=pcap" class="sref">pcap4/a>); 
 L301">.3014/a> 
 L302">.3024/a>        return 4a href="+code=IRQ_HANDLED" class="sref">IRQ_HANDLED4/a>; 
 L303">.3034/a>} 
 L304">.3044/a> 
 L305">.3054/a>int.4a href="+code=pcap_adc_async" class="sref">pcap_adc_async4/a>(struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=u8" class="sref">u84/a> 4a href="+code=bank" class="sref">bank4/a>, 4a href="+code=u32" class="sref">u324/a> 4a href="+code=flags" class="sref">flags4/a>, 4a href="+code=u8" class="sref">u84/a> 4a href="+code=ch" class="sref">ch4/a>[], 
 L306">.3064/a>                                                void *4a href="+code=callback" class="sref">callback4/a>, void *4a href="+code=da	a" class="sref">da	a4/a>) 
 L307">.3074/a>{ 
 L308">.3084/a>        struct.4a href="+code=pcap_adc_request" class="sref">pcap_adc_request4/a> *4a href="+code=req" class="sref">req4/a>; 
 L309">.3094/a> 
 L310">.3104/a>        4spa> class="comment">/* This will be freed after we have a result */4/spa>
 
 L311">.3114/a>        4a href="+code=req" class="sref">req4/a> = 4a href="+code=kmalloc" class="sref">kmalloc4/a>(sizeof(struct.4a href="+code=pcap_adc_request" class="sref">pcap_adc_request4/a>), 4a href="+code=GFP_KERNEL" class="sref">GFP_KERNEL4/a>); 
 L312">.3124/a>        if (!4a href="+code=req" class="sref">req4/a>) 
 L313">.3134/a>                return -4a href="+code=ENOMEM" class="sref">ENOMEM4/a>; 
 L314">.3144/a> 
 L315">.3154/a>        4a href="+code=req" class="sref">req4/a>->4a href="+code=bank" class="sref">bank4/a> = 4a href="+code=bank" class="sref">bank4/a>; 
 L316">.3164/a>        4a href="+code=req" class="sref">req4/a>->4a href="+code=flags" class="sref">flags4/a> = 4a href="+code=flags" class="sref">flags4/a>; 
 L317">.3174/a>        4a href="+code=req" class="sref">req4/a>->4a href="+code=ch" class="sref">ch4/a>[0] = 4a href="+code=ch" class="sref">ch4/a>[0]; 
 L318">.3184/a>        4a href="+code=req" class="sref">req4/a>->4a href="+code=ch" class="sref">ch4/a>[1] = 4a href="+code=ch" class="sref">ch4/a>[1]; 
 L319">.3194/a>        4a href="+code=req" class="sref">req4/a>->4a href="+code=callback" class="sref">callback4/a> = 4a href="+code=callback" class="sref">callback4/a>; 
 L320">.3204/a>        4a href="+code=req" class="sref">req4/a>->4a href="+code=da	a" class="sref">da	a4/a> = 4a href="+code=da	a" class="sref">da	a4/a>; 
 L321">.3214/a> 
 L322">.3224/a>        4a href="+code=mutex_lock" class="sref">mutex_lock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L323">.3234/a>        if (4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_queue" class="sref">adc_queue4/a>[4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_taio" class="sref">adc_taio4/a>]) { 
 L324">.3244/a>                4a href="+code=mutex_unlock" class="sref">mutex_unlock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L325">.3254/a>                4a href="+code=kfree" class="sref">kfree4/a>(4a href="+code=req" class="sref">req4/a>); 
 L326">.3264/a>                return -4a href="+code=EBUSY" class="sref">EBUSY4/a>; 
 L327">.3274/a>        } 
 L328">.3284/a>        4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_queue" class="sref">adc_queue4/a>[4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_taio" class="sref">adc_taio4/a>] = 4a href="+code=req" class="sref">req4/a>; 
 L329">.3294/a>        4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_taio" class="sref">adc_taio4/a> = (4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_taio" class="sref">adc_taio4/a> + 1) & (4a href="+code=PCAP_ADC_MAXQ" class="sref">PCAP_ADC_MAXQ4/a> - 1); 
 L330">.3304/a>        4a href="+code=mutex_unlock" class="sref">mutex_unlock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L331">.3314/a> 
 L332">.3324/a>        4spa> class="comment">/* start conversion */4/spa>
 
 L333">.3334/a>        4a href="+code=pcap_adc_trigger" class="sref">pcap_adc_trigger4/a>(4a href="+code=pcap" class="sref">pcap4/a>); 
 L334">.3344/a> 
 L335">.3354/a>        return 0; 
 L336">.3364/a>} 
 L337">.3374/a>4a href="+code=EXPORT_SYMBOL_GPL" class="sref">EXPORT_SYMBOL_GPL4/a>(4a href="+code=pcap_adc_async" class="sref">pcap_adc_async4/a>); 
 L338">.3384/a> 
 L339">.3394/a>static void 4a href="+code=pcap_adc_sync_cb" class="sref">pcap_adc_sync_cb4/a>(void *4a href="+code=param" class="sref">param4/a>, 4a href="+code=u16" class="sref">u164/a> 4a href="+code=res" class="sref">res4/a>[]) 
 L340">.3404/a>{ 
 L341">.3414/a>        struct.4a href="+code=pcap_adc_sync_request" class="sref">pcap_adc_sync_request4/a> *4a href="+code=req" class="sref">req4/a> = 4a href="+code=param" class="sref">param4/a>; 
 L342">.3424/a> 
 L343">.3434/a>        4a href="+code=req" class="sref">req4/a>->4a href="+code=res" class="sref">res4/a>[0] = 4a href="+code=res" class="sref">res4/a>[0]; 
 L344">.3444/a>        4a href="+code=req" class="sref">req4/a>->4a href="+code=res" class="sref">res4/a>[1] = 4a href="+code=res" class="sref">res4/a>[1]; 
 L345">.3454/a>        4a href="+code=complete" class="sref">complete4/a>(&4a href="+code=req" class="sref">req4/a>->4a href="+code=completion" class="sref">completion4/a>); 
 L346">.3464/a>} 
 L347">.3474/a> 
 L348">.3484/a>int.4a href="+code=pcap_adc_sync" class="sref">pcap_adc_sync4/a>(struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=u8" class="sref">u84/a> 4a href="+code=bank" class="sref">bank4/a>, 4a href="+code=u32" class="sref">u324/a> 4a href="+code=flags" class="sref">flags4/a>, 4a href="+code=u8" class="sref">u84/a> 4a href="+code=ch" class="sref">ch4/a>[], 
 L349">.3494/a>                                                                4a href="+code=u16" class="sref">u164/a> 4a href="+code=res" class="sref">res4/a>[]) 
 L350">.3504/a>{ 
 L351">.3514/a>        struct.4a href="+code=pcap_adc_sync_request" class="sref">pcap_adc_sync_request4/a> 4a href="+code=sync_da	a" class="sref">sync_da	a4/a>; 
 L352">.3524/a>        int.4a href="+code=ret" class="sref">ret4/a>; 
 L353">.3534/a> 
 L354">.3544/a>        4a href="+code=init_completion" class="sref">init_completion4/a>(&4a href="+code=sync_da	a" class="sref">sync_da	a4/a>.4a href="+code=completion" class="sref">completion4/a>); 
 L355">.3554/a>        4a href="+code=ret" class="sref">ret4/a> = 4a href="+code=pcap_adc_async" class="sref">pcap_adc_async4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=bank" class="sref">bank4/a>, 4a href="+code=flags" class="sref">flags4/a>, 4a href="+code=ch" class="sref">ch4/a>, 4a href="+code=pcap_adc_sync_cb" class="sref">pcap_adc_sync_cb4/a>, 
 L356">.3564/a>                                                                &4a href="+code=sync_da	a" class="sref">sync_da	a4/a>); 
 L357">.3574/a>        if (4a href="+code=ret" class="sref">ret4/a>) 
 L358">.3584/a>                return 4a href="+code=ret" class="sref">ret4/a>; 
 L359">.3594/a>        4a href="+code=wait_for_completion" class="sref">wait_for_completion4/a>(&4a href="+code=sync_da	a" class="sref">sync_da	a4/a>.4a href="+code=completion" class="sref">completion4/a>); 
 L360">.3604/a>        4a href="+code=res" class="sref">res4/a>[0] = 4a href="+code=sync_da	a" class="sref">sync_da	a4/a>.4a href="+code=res" class="sref">res4/a>[0]; 
 L361">.3614/a>        4a href="+code=res" class="sref">res4/a>[1] = 4a href="+code=sync_da	a" class="sref">sync_da	a4/a>.4a href="+code=res" class="sref">res4/a>[1]; 
 L362">.3624/a> 
 L363">.3634/a>        return 0; 
 L364">.3644/a>} 
 L365">.3654/a>4a href="+code=EXPORT_SYMBOL_GPL" class="sref">EXPORT_SYMBOL_GPL4/a>(4a href="+code=pcap_adc_sync" class="sref">pcap_adc_sync4/a>); 
 L366">.3664/a> 
 L367">.3674/a>4spa> class="comment">/* subdevs */4/spa>
 
 L368">.3684/a>static int.4a href="+code=pcap_remove_subdev" class="sref">pcap_remove_subdev4/a>(struct.4a href="+code=device" class="sref">device4/a> *4a href="+code=dev" class="sref">dev4/a>, void *4a href="+code=unused" class="sref">unused4/a>) 
 L369">.3694/a>{ 
 L370">.3704/a>        4a href="+code=platform_device_unregister" class="sref">platform_device_unregister4/a>(4a href="+code=to_platform_device" class="sref">to_platform_device4/a>(4a href="+code=dev" class="sref">dev4/a>)); 
 L371">.3714/a>        return 0; 
 L372">.3724/a>} 
 L373">.3734/a> 
 L374">.3744/a>static int.4a href="+code=__devinit" class="sref">__devinit4/a> 4a href="+code=pcap_add_subdev" class="sref">pcap_add_subdev4/a>(struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a>, 
 L375">.3754/a>                                                struct.4a href="+code=pcap_subdev" class="sref">pcap_subdev4/a> *4a href="+code=subdev" class="sref">subdev4/a>) 
 L376">.3764/a>{ 
 L377">.3774/a>        struct.4a href="+code=platform_device" class="sref">platform_device4/a> *4a href="+code=pdev" class="sref">pdev4/a>; 
 L378">.3784/a>        int.4a href="+code=ret" class="sref">ret4/a>; 
 L379">.3794/a> 
 L380">.3804/a>        4a href="+code=pdev" class="sref">pdev4/a> = 4a href="+code=platform_device_alloc" class="sref">platform_device_alloc4/a>(4a href="+code=subdev" class="sref">subdev4/a>->4a href="+code=nam>" class="sref">nam>4/a>, 4a href="+code=subdev" class="sref">subdev4/a>->4a href="+code=id" class="sref">id4/a>); 
 L381">.3814/a>        if (!4a href="+code=pdev" class="sref">pdev4/a>) 
 L382">.3824/a>                return -4a href="+code=ENOMEM" class="sref">ENOMEM4/a>; 
 L383">.3834/a> 
 L384">.3844/a>        4a href="+code=pdev" class="sref">pdev4/a>->4a href="+code=dev" class="sref">dev4/a>.4a href="+code=parent" class="sref">parent4/a> = &4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=spi" class="sref">spi4/a>->4a href="+code=dev" class="sref">dev4/a>; 
 L385">.3854/a>        4a href="+code=pdev" class="sref">pdev4/a>->4a href="+code=dev" class="sref">dev4/a>.4a href="+code=platform_da	a" class="sref">platform_da	a4/a> = 4a href="+code=subdev" class="sref">subdev4/a>->4a href="+code=platform_da	a" class="sref">platform_da	a4/a>; 
 L386">.3864/a> 
 L387">.3874/a>        4a href="+code=ret" class="sref">ret4/a> = 4a href="+code=platform_device_add" class="sref">platform_device_add4/a>(4a href="+code=pdev" class="sref">pdev4/a>); 
 L388">.3884/a>        if (4a href="+code=ret" class="sref">ret4/a>) 
 L389">.3894/a>                4a href="+code=platform_device_put" class="sref">platform_device_put4/a>(4a href="+code=pdev" class="sref">pdev4/a>); 
 L390">.3904/a> 
 L391">.3914/a>        return 4a href="+code=ret" class="sref">ret4/a>; 
 L392">.3924/a>} 
 L393">.3934/a> 
 L394">.3944/a>static int.4a href="+code=__devexit" class="sref">__devexit4/a> 4a href="+code=ezx_pcap_remove" class="sref">ezx_pcap_remove4/a>(struct.4a href="+code=spi_device" class="sref">spi_device4/a> *4a href="+code=spi" class="sref">spi4/a>) 
 L395">.3954/a>{ 
 L396">.3964/a>        struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a> = 4a href="+code=dev_get_drvda	a" class="sref">dev_get_drvda	a4/a>(&4a href="+code=spi" class="sref">spi4/a>->4a href="+code=dev" class="sref">dev4/a>); 
 L397">.3974/a>        struct.4a href="+code=pcap_platform_da	a" class="sref">pcap_platform_da	a4/a> *4a href="+code=pda	a" class="sref">pda	a4/a> = 4a href="+code=spi" class="sref">spi4/a>->4a href="+code=dev" class="sref">dev4/a>.4a href="+code=platform_da	a" class="sref">platform_da	a4/a>; 
 L398">.3984/a>        int.4a href="+code=i" class="sref">i4/a>, 4a href="+code=adc_irq" class="sref">adc_irq4/a>; 
 L399">.3994/a> 
 L400">.4004/a>        4spa> class="comment">/* remove all registered subdevs */4/spa>
 
 L401">.4014/a>        4a href="+code=device_for_each_child" class="sref">device_for_each_child4/a>(&4a href="+code=spi" class="sref">spi4/a>->4a href="+code=dev" class="sref">dev4/a>, 4a href="+code=NULL" class="sref">NULL4/a>, 4a href="+code=pcap_remove_subdev" class="sref">pcap_remove_subdev4/a>); 
 L402">.4024/a> 
 L403">.4034/a>        4spa> class="comment">/* cleanup ADC */4/spa>
 
 L404">.4044/a>        4a href="+code=adc_irq" class="sref">adc_irq4/a> = 4a href="+code=pcap_to_irq" class="sref">pcap_to_irq4/a>(4a href="+code=pcap" class="sref">pcap4/a>, (4a href="+code=pda	a" class="sref">pda	a4/a>->4a href="+code=config" class="sref">config4/a> & 4a href="+code=PCAP_SECOND_PORT" class="sref">PCAP_SECOND_PORT4/a>) ? 
 L405">.4054/a>                                4a href="+code=PCAP_IRQ_ADCDONE2" class="sref">PCAP_IRQ_ADCDONE24/a> : 4a href="+code=PCAP_IRQ_ADCDONE" class="sref">PCAP_IRQ_ADCDONE4/a>); 
 L406">.4064/a>        4a href="+code=free_irq" class="sref">free_irq4/a>(4a href="+code=adc_irq" class="sref">adc_irq4/a>, 4a href="+code=pcap" class="sref">pcap4/a>); 
 L407">.4074/a>        4a href="+code=mutex_lock" class="sref">mutex_lock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L408">.4084/a>        for (4a href="+code=i" class="sref">i4/a> = 0; 4a href="+code=i" class="sref">i4/a> < 4a href="+code=PCAP_ADC_MAXQ" class="sref">PCAP_ADC_MAXQ4/a>; 4a href="+code=i" class="sref">i4/a>++) 
 L409">.4094/a>                4a href="+code=kfree" class="sref">kfree4/a>(4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_queue" class="sref">adc_queue4/a>[4a href="+code=i" class="sref">i4/a>]); 
 L410">.4104/a>        4a href="+code=mutex_unlock" class="sref">mutex_unlock4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L411">.4114/a> 
 L412">.4124/a>        4spa> class="comment">/* cleanup irqchip */4/spa>
 
 L413">.4134/a>        for (4a href="+code=i" class="sref">i4/a> = 4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=irq_base" class="sref">irq_base4/a>; 4a href="+code=i" class="sref">i4/a> < (4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=irq_base" class="sref">irq_base4/a> + 4a href="+code=PCAP_NIRQS" class="sref">PCAP_NIRQS4/a>); 4a href="+code=i" class="sref">i4/a>++) 
 L414">.4144/a>                4a href="+code=irq_set_chip_and_handler" class="sref">irq_set_chip_and_handler4/a>(4a href="+code=i" class="sref">i4/a>, 4a href="+code=NULL" class="sref">NULL4/a>, 4a href="+code=NULL" class="sref">NULL4/a>); 
 L415">.4154/a> 
 L416">.4164/a>        4a href="+code=destroy_workqueue" class="sref">destroy_workqueue4/a>(4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=workqueue" class="sref">workqueue4/a>); 
 L417">.4174/a> 
 L418">.4184/a>        4a href="+code=kfree" class="sref">kfree4/a>(4a href="+code=pcap" class="sref">pcap4/a>); 
 L419">.4194/a> 
 L420">.4204/a>        return 0; 
 L421">.4214/a>} 
 L422">.4224/a> 
 L423">.4234/a>static int.4a href="+code=__devinit" class="sref">__devinit4/a> 4a href="+code=ezx_pcap_probe" class="sref">ezx_pcap_probe4/a>(struct.4a href="+code=spi_device" class="sref">spi_device4/a> *4a href="+code=spi" class="sref">spi4/a>) 
 L424">.4244/a>{ 
 L425">.4254/a>        struct.4a href="+code=pcap_platform_da	a" class="sref">pcap_platform_da	a4/a> *4a href="+code=pda	a" class="sref">pda	a4/a> = 4a href="+code=spi" class="sref">spi4/a>->4a href="+code=dev" class="sref">dev4/a>.4a href="+code=platform_da	a" class="sref">platform_da	a4/a>; 
 L426">.4264/a>        struct.4a href="+code=pcap_chip" class="sref">pcap_chip4/a> *4a href="+code=pcap" class="sref">pcap4/a>; 
 L427">.4274/a>        int.4a href="+code=i" class="sref">i4/a>, 4a href="+code=adc_irq" class="sref">adc_irq4/a>; 
 L428">.4284/a>        int.4a href="+code=ret" class="sref">ret4/a> = -4a href="+code=ENODEV" class="sref">ENODEV4/a>; 
 L429">.4294/a> 
 L430">.4304/a>        4spa> class="comment">/* platform da	a is required */4/spa>
 
 L431">.4314/a>        if (!4a href="+code=pda	a" class="sref">pda	a4/a>) 
 L432">.4324/a>                goto 4a href="+code=ret" class="sref">ret4/a>; 
 L433">.4334/a> 
 L434">.4344/a>        4a href="+code=pcap" class="sref">pcap4/a> = 4a href="+code=kzalloc" class="sref">kzalloc4/a>(sizeof(*4a href="+code=pcap" class="sref">pcap4/a>), 4a href="+code=GFP_KERNEL" class="sref">GFP_KERNEL4/a>); 
 L435">.4354/a>        if (!4a href="+code=pcap" class="sref">pcap4/a>) { 
 L436">.4364/a>                4a href="+code=ret" class="sref">ret4/a> = -4a href="+code=ENOMEM" class="sref">ENOMEM4/a>; 
 L437">.4374/a>                goto 4a href="+code=ret" class="sref">ret4/a>; 
 L438">.4384/a>        } 
 L439">.4394/a> 
 L440">.4404/a>        4a href="+code=mutex_init" class="sref">mutex_init4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=io_mutex" class="sref">io_mutex4/a>); 
 L441">.4414/a>        4a href="+code=mutex_init" class="sref">mutex_init4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=adc_mutex" class="sref">adc_mutex4/a>); 
 L442">.4424/a>        4a href="+code=INIT_WORK" class="sref">INIT_WORK4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=isr_work" class="sref">isr_work4/a>, 4a href="+code=pcap_isr_work" class="sref">pcap_isr_work4/a>); 
 L443">.4434/a>        4a href="+code=INIT_WORK" class="sref">INIT_WORK4/a>(&4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=msr_work" class="sref">msr_work4/a>, 4a href="+code=pcap_msr_work" class="sref">pcap_msr_work4/a>); 
 L444">.4444/a>        4a href="+code=dev_set_drvda	a" class="sref">dev_set_drvda	a4/a>(&4a href="+code=spi" class="sref">spi4/a>->4a href="+code=dev" class="sref">dev4/a>, 4a href="+code=pcap" class="sref">pcap4/a>); 
 L445">.4454/a> 
 L446">.4464/a>        4spa> class="comment">/* setup spi */4/spa>
 
 L447">.4474/a>        4a href="+code=spi" class="sref">spi4/a>->4a href="+code=bits_per_word" class="sref">bits_per_word4/a> = 32; 
 L448">.4484/a>        4a href="+code=spi" class="sref">spi4/a>->4a href="+code=mode" class="sref">mode4/a> = 4a href="+code=SPI_MODE_0" class="sref">SPI_MODE_04/a> | (4a href="+code=pda	a" class="sref">pda	a4/a>->4a href="+code=config" class="sref">config4/a> & 4a href="+code=PCAP_CS_AH" class="sref">PCAP_CS_AH4/a> ? 4a href="+code=SPI_CS_HIGH" class="sref">SPI_CS_HIGH4/a> : 0); 
 L449">.4494/a>        4a href="+code=ret" class="sref">ret4/a> = 4a href="+code=spi_setup" class="sref">spi_setup4/a>(4a href="+code=spi" class="sref">spi4/a>); 
 L450">.4504/a>        if (4a href="+code=ret" class="sref">ret4/a>) 
 L451">.4514/a>                goto 4a href="+code=free_pcap" class="sref">free_pcap4/a>; 
 L452">.4524/a> 
 L453">.4534/a>        4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=spi" class="sref">spi4/a> = 4a href="+code=spi" class="sref">spi4/a>; 
 L454">.4544/a> 
 L455">.4554/a>        4spa> class="comment">/* setup irq */4/spa>
 
 L456">.4564/a>        4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=irq_base" class="sref">irq_base4/a> = 4a href="+code=pda	a" class="sref">pda	a4/a>->4a href="+code=irq_base" class="sref">irq_base4/a>; 
 L457">.4574/a>        4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=workqueue" class="sref">workqueue4/a> = 4a href="+code=create_singlethread_workqueue" class="sref">create_singlethread_workqueue4/a>(4spa> class="string">"pcapd"4/spa>
); 
 L458">.4584/a>        if (!4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=workqueue" class="sref">workqueue4/a>) { 
 L459">.4594/a>                4a href="+code=ret" class="sref">ret4/a> = -4a href="+code=ENOMEM" class="sref">ENOMEM4/a>; 
 L460">.4604/a>                4a href="+code=dev_err" class="sref">dev_err4/a>(&4a href="+code=spi" class="sref">spi4/a>->4a href="+code=dev" class="sref">dev4/a>, 4spa> class="string">"can't create pcap thread\n"4/spa>
); 
 L461">.4614/a>                goto 4a href="+code=free_pcap" class="sref">free_pcap4/a>; 
 L462">.4624/a>        } 
 L463">.4634/a> 
 L464">.4644/a>        4spa> class="comment">/* redirect interrupts to AP, except adcdone2 */4/spa>
 
 L465">.4654/a>        if (!(4a href="+code=pda	a" class="sref">pda	a4/a>->4a href="+code=config" class="sref">config4/a> & 4a href="+code=PCAP_SECOND_PORT" class="sref">PCAP_SECOND_PORT4/a>)) 
 L466">.4664/a>                4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_INT_SEL" class="sref">PCAP_REG_INT_SEL4/a>, 
 L467">.4674/a>                                        (1 << 4a href="+code=PCAP_IRQ_ADCDONE2" class="sref">PCAP_IRQ_ADCDONE24/a>)); 
 L468">.4684/a> 
 L469">.4694/a>        4spa> class="comment">/* setup irq chip */4/spa>
 
 L470">.4704/a>        for (4a href="+code=i" class="sref">i4/a> = 4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=irq_base" class="sref">irq_base4/a>; 4a href="+code=i" class="sref">i4/a> < (4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=irq_base" class="sref">irq_base4/a> + 4a href="+code=PCAP_NIRQS" class="sref">PCAP_NIRQS4/a>); 4a href="+code=i" class="sref">i4/a>++) { 
 L471">.4714/a>                4a href="+code=irq_set_chip_and_handler" class="sref">irq_set_chip_and_handler4/a>(4a href="+code=i" class="sref">i4/a>, &4a href="+code=pcap_irq_chip" class="sref">pcap_irq_chip4/a>, 4a href="+code=handle_simple_irq" class="sref">handle_simple_irq4/a>); 
 L472">.4724/a>                4a href="+code=irq_set_chip_da	a" class="sref">irq_set_chip_da	a4/a>(4a href="+code=i" class="sref">i4/a>, 4a href="+code=pcap" class="sref">pcap4/a>); 
 L473">.4734/a>#ifdef 4a href="+code=CONFIG_ARM" class="sref">CONFIG_ARM4/a> 
 L474">.4744/a>                4a href="+code=set_irq_flags" class="sref">set_irq_flags4/a>(4a href="+code=i" class="sref">i4/a>, 4a href="+code=IRQF_VALID" class="sref">IRQF_VALID4/a>); 
 L475">.4754/a>#else 
 L476">.4764/a>                4a href="+code=irq_set_noprobe" class="sref">irq_set_noprobe4/a>(4a href="+code=i" class="sref">i4/a>); 
 L477">.4774/a>#endif 
 L478">.4784/a>        } 
 L479">.4794/a> 
 L480">.4804/a>        4spa> class="comment">/* mask/ack all PCAP interrupts */4/spa>
 
 L481">.4814/a>        4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_MSR" class="sref">PCAP_REG_MSR4/a>, 4a href="+code=PCAP_MASK_ALL_INTERRUPT" class="sref">PCAP_MASK_ALL_INTERRUPT4/a>); 
 L482">.4824/a>        4a href="+code=ezx_pcap_write" class="sref">ezx_pcap_write4/a>(4a href="+code=pcap" class="sref">pcap4/a>, 4a href="+code=PCAP_REG_ISR" class="sref">PCAP_REG_ISR4/a>, 4a href="+code=PCAP_CLEAR_INTERRUPT_REGISTER" class="sref">PCAP_CLEAR_INTERRUPT_REGISTER4/a>); 
 L483">.4834/a>        4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=msr" class="sref">msr4/a> = 4a href="+code=PCAP_MASK_ALL_INTERRUPT" class="sref">PCAP_MASK_ALL_INTERRUPT4/a>; 
 L484">.4844/a> 
 L485">.4854/a>        4a href="+code=irq_set_irq_type" class="sref">irq_set_irq_type4/a>(4a href="+code=spi" class="sref">spi4/a>->4a href="+code=irq" class="sref">irq4/a>, 4a href="+code=IRQ_TYPE_EDGE_RISING" class="sref">IRQ_TYPE_EDGE_RISING4/a>); 
 L486">.4864/a>        4a href="+code=irq_set_handler_da	a" class="sref">irq_set_handler_da	a4/a>(4a href="+code=spi" class="sref">spi4/a>->4a href="+code=irq" class="sref">irq4/a>, 4a href="+code=pcap" class="sref">pcap4/a>); 
 L487">.4874/a>        4a href="+code=irq_set_chained_handler" class="sref">irq_set_chained_handler4/a>(4a href="+code=spi" class="sref">spi4/a>->4a href="+code=irq" class="sref">irq4/a>, 4a href="+code=pcap_irq_handler" class="sref">pcap_irq_handler4/a>); 
 L488">.4884/a>        4a href="+code=irq_set_irq_wake" class="sref">irq_set_irq_wake4/a>(4a href="+code=spi" class="sref">spi4/a>->4a href="+code=irq" class="sref">irq4/a>, 1); 
 L489">.4894/a> 
 L490">.4904/a>        4spa> class="comment">/* ADC */4/spa>
 
 L491">.4914/a>        4a href="+code=adc_irq" class="sref">adc_irq4/a> = 4a href="+code=pcap_to_irq" class="sref">pcap_to_irq4/a>(4a href="+code=pcap" class="sref">pcap4/a>, (4a href="+code=pda	a" class="sref">pda	a4/a>->4a href="+code=config" class="sref">config4/a> & 4a href="+code=PCAP_SECOND_PORT" class="sref">PCAP_SECOND_PORT4/a>) ? 
 L492">.4924/a>                                        4a href="+code=PCAP_IRQ_ADCDONE2" class="sref">PCAP_IRQ_ADCDONE24/a> : 4a href="+code=PCAP_IRQ_ADCDONE" class="sref">PCAP_IRQ_ADCDONE4/a>); 
 L493">.4934/a> 
 L494">.4944/a>        4a href="+code=ret" class="sref">ret4/a> = 4a href="+code=request_irq" class="sref">request_irq4/a>(4a href="+code=adc_irq" class="sref">adc_irq4/a>, 4a href="+code=pcap_adc_irq" class="sref">pcap_adc_irq4/a>, 0, 4spa> class="string">"ADC"4/spa>
, 4a href="+code=pcap" class="sref">pcap4/a>); 
 L495">.4954/a>        if (4a href="+code=ret" class="sref">ret4/a>) 
 L496">.4964/a>                goto 4a href="+code=free_irqchip" class="sref">free_irqchip4/a>; 
 L497">.4974/a> 
 L498">.4984/a>        4spa> class="comment">/* setup subdevs */4/spa>
 
 L499">.4994/a>        for (4a href="+code=i" class="sref">i4/a> = 0; 4a href="+code=i" class="sref">i4/a> < 4a href="+code=pda	a" class="sref">pda	a4/a>->4a href="+code=num_subdevs" class="sref">num_subdevs4/a>; 4a href="+code=i" class="sref">i4/a>++) { 
 L500">.5004/a>                4a href="+code=ret" class="sref">ret4/a> = 4a href="+code=pcap_add_subdev" class="sref">pcap_add_subdev4/a>(4a href="+code=pcap" class="sref">pcap4/a>, &4a href="+code=pda	a" class="sref">pda	a4/a>->4a href="+code=subdevs" class="sref">subdevs4/a>[4a href="+code=i" class="sref">i4/a>]); 
 L501">.5014/a>                if (4a href="+code=ret" class="sref">ret4/a>) 
 L502">.5024/a>                        goto 4a href="+code=remove_subdevs" class="sref">remove_subdevs4/a>; 
 L503">.5034/a>        } 
 L504">.5044/a> 
 L505">.5054/a>        4spa> class="comment">/* board specific quirks */4/spa>
 
 L506">.5064/a>        if (4a href="+code=pda	a" class="sref">pda	a4/a>->4a href="+code=init" class="sref">init4/a>) 
 L507">.5074/a>                4a href="+code=pda	a" class="sref">pda	a4/a>->4a href="+code=init" class="sref">init4/a>(4a href="+code=pcap" class="sref">pcap4/a>); 
 L508">.5084/a> 
 L509">.5094/a>        return 0; 
 L510">.5104/a> 
 L511">.5114/a>4a href="+code=remove_subdevs" class="sref">remove_subdevs4/a>: 
 L512">.5124/a>        4a href="+code=device_for_each_child" class="sref">device_for_each_child4/a>(&4a href="+code=spi" class="sref">spi4/a>->4a href="+code=dev" class="sref">dev4/a>, 4a href="+code=NULL" class="sref">NULL4/a>, 4a href="+code=pcap_remove_subdev" class="sref">pcap_remove_subdev4/a>); 
 L513">.5134/a>4spa> class="comment">/* free_adc: */4/spa>
 
 L514">.5144/a>        4a href="+code=free_irq" class="sref">free_irq4/a>(4a href="+code=adc_irq" class="sref">adc_irq4/a>, 4a href="+code=pcap" class="sref">pcap4/a>); 
 L515">.5154/a>4a href="+code=free_irqchip" class="sref">free_irqchip4/a>: 
 L516">.5164/a>        for (4a href="+code=i" class="sref">i4/a> = 4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=irq_base" class="sref">irq_base4/a>; 4a href="+code=i" class="sref">i4/a> < (4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=irq_base" class="sref">irq_base4/a> + 4a href="+code=PCAP_NIRQS" class="sref">PCAP_NIRQS4/a>); 4a href="+code=i" class="sref">i4/a>++) 
 L517">.5174/a>                4a href="+code=irq_set_chip_and_handler" class="sref">irq_set_chip_and_handler4/a>(4a href="+code=i" class="sref">i4/a>, 4a href="+code=NULL" class="sref">NULL4/a>, 4a href="+code=NULL" class="sref">NULL4/a>); 
 L518">.5184/a>4spa> class="comment">/* destroy_workqueue: */4/spa>
 
 L519">.5194/a>        4a href="+code=destroy_workqueue" class="sref">destroy_workqueue4/a>(4a href="+code=pcap" class="sref">pcap4/a>->4a href="+code=workqueue" class="sref">workqueue4/a>); 
 L520">.5204/a>4a href="+code=free_pcap" class="sref">free_pcap4/a>: 
 L521">.5214/a>        4a href="+code=kfree" class="sref">kfree4/a>(4a href="+code=pcap" class="sref">pcap4/a>); 
 L522">.5224/a>4a href="+code=ret" class="sref">ret4/a>: 
 L523">.5234/a>        return 4a href="+code=ret" class="sref">ret4/a>; 
 L524">.5244/a>} 
 L525">.5254/a> 
 L526">.5264/a>static struct.4a href="+code=spi_driver" class="sref">spi_driver4/a> 4a href="+code=ezxpcap_driver" class="sref">ezxpcap_driver4/a> = { 
 L527">.5274/a>        .4a href="+code=probe" class="sref">probe4/a>  = 4a href="+code=ezx_pcap_probe" class="sref">ezx_pcap_probe4/a>, 
 L528">.5284/a>        .4a href="+code=remove" class="sref">remove4/a> = 4a href="+code=__devexit_p" class="sref">__devexit_p4/a>(4a href="+code=ezx_pcap_remove" class="sref">ezx_pcap_remove4/a>), 
 L529">.5294/a>        .4a href="+code=driver" class="sref">driver4/a> = { 
 L530">.5304/a>                .4a href="+code=nam>" class="sref">name4/a>   = 4spa> class="string">"ezx-pcap"4/spa>
, 
 L531">.5314/a>                .4a href="+code=owner" class="sref">owner4/a>  = 4a href="+code=THIS_MODULE" class="sref">THIS_MODULE4/a>, 
 L532">.5324/a>        }, 
 L533">.5334/a>}; 
 L534">.5344/a> 
 L535">.5354/a>static int.4a href="+code=__init" class="sref">__init4/a> 4a href="+code=ezx_pcap_init" class="sref">ezx_pcap_init4/a>(void) 
 L536">.5364/a>{ 
 L537">.5374/a>        return 4a href="+code=spi_register_driver" class="sref">spi_register_driver4/a>(&4a href="+code=ezxpcap_driver" class="sref">ezxpcap_driver4/a>); 
 L538">.5384/a>} 
 L539">.5394/a> 
 L540">.5404/a>static void.4a href="+code=__exit" class="sref">__exit4/a> 4a href="+code=ezx_pcap_exit" class="sref">ezx_pcap_exit4/a>(void) 
 L541">.5414/a>{ 
 L542">.5424/a>        4a href="+code=spi_unregister_driver" class="sref">spi_unregister_driver4/a>(&4a href="+code=ezxpcap_driver" class="sref">ezxpcap_driver4/a>); 
 L543">.5434/a>} 
 L544">.5444/a> 
 L545">.5454/a>4a href="+code=subsys_initcall" class="sref">subsys_initcall4/a>(4a href="+code=ezx_pcap_init" class="sref">ezx_pcap_init4/a>); 
 L546">.5464/a>4a href="+code=module_exit" class="sref">module_exit4/a>(4a href="+code=ezx_pcap_exit" class="sref">ezx_pcap_exit4/a>); 
 L547">.5474/a> 
 L548">.5484/a>4a href="+code=MODULE_LICENSE" class="sref">MODULE_LICENSE4/a>(4spa> class="string">"GPL"4/spa>
); 
 L549">.5494/a>4a href="+code=MODULE_AUTHOR" class="sref">MODULE_AUTHOR4/a>(4spa> class="string">"Daniel Ribeiro / Harald Welte"4/spa>
); 
 L550">.5504/a>4a href="+code=MODULE_DESCRIPTION" class="sref">MODULE_DESCRIPTION4/a>(4spa> class="string">"Motorola PCAP2 ASIC Driver"4/spa>
); 
 L551">.5514/a>4a href="+code=MODULE_ALIAS" class="sref">MODULE_ALIAS4/a>(4spa> class="string">"spi:ezx-pcap"4/spa>
); 
 L552">.5524/a>
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