linux/drivers/ide/slc90e66.c
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   1/*
   2 *  Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
   3 *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
   4 *
   5 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
   6 * but this keeps the ISA-Bridge and slots alive.
   7 *
   8 */
   9
  10#include <linux/types.h>
  11#include <linux/module.h>
  12#include <linux/kernel.h>
  13#include <linux/pci.h>
  14#include <linux/ide.h>
  15#include <linux/init.h>
  16
  17#define DRV_NAME "slc90e66"
  18
  19static DEFINE_SPINLOCK(slc90e66_lock);
  20
  21static void slc90e66_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  22{
  23        struct pci_dev *dev     = to_pci_dev(hwif->dev);
  24        int is_slave            = drive->dn & 1;
  25        int master_port         = hwif->channel ? 0x42 : 0x40;
  26        int slave_port          = 0x44;
  27        unsigned long flags;
  28        u16 master_data;
  29        u8 slave_data;
  30        int control = 0;
  31        const u8 pio = drive->pio_mode - XFER_PIO_0;
  32
  33                                     /* ISP  RTC */
  34        static const u8 timings[][2] = {
  35                                        { 0, 0 },
  36                                        { 0, 0 },
  37                                        { 1, 0 },
  38                                        { 2, 1 },
  39                                        { 2, 3 }, };
  40
  41        spin_lock_irqsave(&slc90e66_lock, flags);
  42        pci_read_config_word(dev, master_port, &master_data);
  43
  44        if (pio > 1)
  45                control |= 1;   /* Programmable timing on */
  46        if (drive->media == ide_disk)
  47                control |= 4;   /* Prefetch, post write */
  48        if (ide_pio_need_iordy(drive, pio))
  49                control |= 2;   /* IORDY */
  50        if (is_slave) {
  51                master_data |=  0x4000;
  52                master_data &= ~0x0070;
  53                if (pio > 1) {
  54                        /* Set PPE, IE and TIME */
  55                        master_data |= control << 4;
  56                }
  57                pci_read_config_byte(dev, slave_port, &slave_data);
  58                slave_data &= hwif->channel ? 0x0f : 0xf0;
  59                slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
  60                               (hwif->channel ? 4 : 0);
  61        } else {
  62                master_data &= ~0x3307;
  63                if (pio > 1) {
  64                        /* enable PPE, IE and TIME */
  65                        master_data |= control;
  66                }
  67                master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
  68        }
  69        pci_write_config_word(dev, master_port, master_data);
  70        if (is_slave)
  71                pci_write_config_byte(dev, slave_port, slave_data);
  72        spin_unlock_irqrestore(&slc90e66_lock, flags);
  73}
  74
  75static void slc90e66_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  76{
  77        struct pci_dev *dev     = to_pci_dev(hwif->dev);
  78        u8 maslave              = hwif->channel ? 0x42 : 0x40;
  79        int sitre = 0, a_speed  = 7 << (drive->dn * 4);
  80        int u_speed = 0, u_flag = 1 << drive->dn;
  81        u16                     reg4042, reg44, reg48, reg4a;
  82        const u8 speed          = drive->dma_mode;
  83
  84        pci_read_config_word(dev, maslave, &reg4042);
  85        sitre = (reg4042 & 0x4000) ? 1 : 0;
  86        pci_read_config_word(dev, 0x44, &reg44);
  87        pci_read_config_word(dev, 0x48, &reg48);
  88        pci_read_config_word(dev, 0x4a, &reg4a);
  89
  90        if (speed >= XFER_UDMA_0) {
  91                u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4);
  92
  93                if (!(reg48 & u_flag))
  94                        pci_write_config_word(dev, 0x48, reg48|u_flag);
  95                if ((reg4a & a_speed) != u_speed) {
  96                        pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
  97                        pci_read_config_word(dev, 0x4a, &reg4a);
  98                        pci_write_config_word(dev, 0x4a, reg4a|u_speed);
  99                }
 100        } else {
 101                const u8 mwdma_to_pio[] = { 0, 3, 4 };
 102
 103                if (reg48 & u_flag)
 104                        pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
 105                if (reg4a & a_speed)
 106                        pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 107
 108                if (speed >= XFER_MW_DMA_0)
 109                        drive->pio_mode =
 110                                mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
 111                else
 112                        drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
 113
 114                slc90e66_set_pio_mode(hwif, drive);
 115        }
 116}
 117
 118static u8 slc90e66_cable_detect(ide_hwif_t *hwif)
 119{
 120        struct pci_dev *dev = to_pci_dev(hwif->dev);
 121        u8 reg47 = 0, mask = hwif->channel ? 0x01 : 0x02;
 122
 123        pci_read_config_byte(dev, 0x47, &reg47);
 124
 125        /* bit[0(1)]: 0:80, 1:40 */
 126        return (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 127}
 128
 129static const struct ide_port_ops slc90e66_port_ops = {
 130        .set_pio_mode           = slc90e66_set_pio_mode,
 131        .set_dma_mode           = slc90e66_set_dma_mode,
 132        .cable_detect           = slc90e66_cable_detect,
 133};
 134
 135static const struct ide_port_info slc90e66_chipset __devinitconst = {
 136        .name           = DRV_NAME,
 137        .enablebits     = { {0x41, 0x80, 0x80}, {0x43, 0x80, 0x80} },
 138        .port_ops       = &slc90e66_port_ops,
 139        .pio_mask       = ATA_PIO4,
 140        .swdma_mask     = ATA_SWDMA2_ONLY,
 141        .mwdma_mask     = ATA_MWDMA12_ONLY,
 142        .udma_mask      = ATA_UDMA4,
 143};
 144
 145static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 146{
 147        return ide_pci_init_one(dev, &slc90e66_chipset, NULL);
 148}
 149
 150static const struct pci_device_id slc90e66_pci_tbl[] = {
 151        { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 },
 152        { 0, },
 153};
 154MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
 155
 156static struct pci_driver slc90e66_pci_driver = {
 157        .name           = "SLC90e66_IDE",
 158        .id_table       = slc90e66_pci_tbl,
 159        .probe          = slc90e66_init_one,
 160        .remove         = ide_pci_remove,
 161        .suspend        = ide_pci_suspend,
 162        .resume         = ide_pci_resume,
 163};
 164
 165static int __init slc90e66_ide_init(void)
 166{
 167        return ide_pci_register_driver(&slc90e66_pci_driver);
 168}
 169
 170static void __exit slc90e66_ide_exit(void)
 171{
 172        pci_unregister_driver(&slc90e66_pci_driver);
 173}
 174
 175module_init(slc90e66_ide_init);
 176module_exit(slc90e66_ide_exit);
 177
 178MODULE_AUTHOR("Andre Hedrick");
 179MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
 180MODULE_LICENSE("GPL");
 181
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