linux/drivers/atm/horizon.c
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   1/*
   2  Madge Horizon ATM Adapter driver.
   3  Copyright (C) 1995-1999  Madge Networks Ltd.
   4  
   5  This program is free software; you can redistribute it and/or modify
   6  it under the terms of the GNU General Public License as published by
   7  the Free Software Foundation; either version 2 of the License, or
   8  (at your option) any later version.
   9  
  10  This program is distributed in the hope that it will be useful,
  11  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  GNU General Public License for more details.
  14  
  15  You should have received a copy of the GNU General Public License
  16  along with this program; if not, write to the Free Software
  17  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  
  19  The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
  20  system and in the file COPYING in the Linux kernel source.
  21*/
  22
  23/*
  24  IMPORTANT NOTE: Madge Networks no longer makes the adapters
  25  supported by this driver and makes no commitment to maintain it.
  26*/
  27
  28#include <linux/module.h>
  29#include <linux/kernel.h>
  30#include <linux/mm.h>
  31#include <linux/pci.h>
  32#include <linux/errno.h>
  33#include <linux/atm.h>
  34#include <linux/atmdev.h>
  35#include <linux/sonet.h>
  36#include <linux/skbuff.h>
  37#include <linux/time.h>
  38#include <linux/delay.h>
  39#include <linux/uio.h>
  40#include <linux/init.h>
  41#include <linux/interrupt.h>
  42#include <linux/ioport.h>
  43#include <linux/wait.h>
  44#include <linux/slab.h>
  45
  46#include <asm/io.h>
  47#include <linux/atomic.h>
  48#include <asm/uaccess.h>
  49#include <asm/string.h>
  50#include <asm/byteorder.h>
  51
  52#include "horizon.h"
  53
  54#define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>"
  55#define description_string "Madge ATM Horizon [Ultra] driver"
  56#define version_string "1.2.1"
  57
  58static inline void __init show_version (void) {
  59  printk ("%s version %s\n", description_string, version_string);
  60}
  61
  62/*
  63  
  64  CREDITS
  65  
  66  Driver and documentation by:
  67  
  68  Chris Aston        Madge Networks
  69  Giuliano Procida   Madge Networks
  70  Simon Benham       Madge Networks
  71  Simon Johnson      Madge Networks
  72  Various Others     Madge Networks
  73  
  74  Some inspiration taken from other drivers by:
  75  
  76  Alexandru Cucos    UTBv
  77  Kari Mettinen      University of Helsinki
  78  Werner Almesberger EPFL LRC
  79  
  80  Theory of Operation
  81  
  82  I Hardware, detection, initialisation and shutdown.
  83  
  84  1. Supported Hardware
  85  
  86  This driver should handle all variants of the PCI Madge ATM adapters
  87  with the Horizon chipset. These are all PCI cards supporting PIO, BM
  88  DMA and a form of MMIO (registers only, not internal RAM).
  89  
  90  The driver is only known to work with SONET and UTP Horizon Ultra
  91  cards at 155Mb/s. However, code is in place to deal with both the
  92  original Horizon and 25Mb/s operation.
  93  
  94  There are two revisions of the Horizon ASIC: the original and the
  95  Ultra. Details of hardware bugs are in section III.
  96  
  97  The ASIC version can be distinguished by chip markings but is NOT
  98  indicated by the PCI revision (all adapters seem to have PCI rev 1).
  99  
 100  I believe that:
 101  
 102  Horizon       => Collage  25 PCI Adapter (UTP and STP)
 103  Horizon Ultra => Collage 155 PCI Client (UTP or SONET)
 104  Ambassador x  => Collage 155 PCI Server (completely different)
 105  
 106  Horizon (25Mb/s) is fitted with UTP and STP connectors. It seems to
 107  have a Madge B154 plus glue logic serializer. I have also found a
 108  really ancient version of this with slightly different glue. It
 109  comes with the revision 0 (140-025-01) ASIC.
 110  
 111  Horizon Ultra (155Mb/s) is fitted with either a Pulse Medialink
 112  output (UTP) or an HP HFBR 5205 output (SONET). It has either
 113  Madge's SAMBA framer or a SUNI-lite device (early versions). It
 114  comes with the revision 1 (140-027-01) ASIC.
 115  
 116  2. Detection
 117  
 118  All Horizon-based cards present with the same PCI Vendor and Device
 119  IDs. The standard Linux 2.2 PCI API is used to locate any cards and
 120  to enable bus-mastering (with appropriate latency).
 121  
 122  ATM_LAYER_STATUS in the control register distinguishes between the
 123  two possible physical layers (25 and 155). It is not clear whether
 124  the 155 cards can also operate at 25Mbps. We rely on the fact that a
 125  card operates at 155 if and only if it has the newer Horizon Ultra
 126  ASIC.
 127  
 128  For 155 cards the two possible framers are probed for and then set
 129  up for loop-timing.
 130  
 131  3. Initialisation
 132  
 133  The card is reset and then put into a known state. The physical
 134  layer is configured for normal operation at the appropriate speed;
 135  in the case of the 155 cards, the framer is initialised with
 136  line-based timing; the internal RAM is zeroed and the allocation of
 137  buffers for RX and TX is made; the Burnt In Address is read and
 138  copied to the ATM ESI; various policy settings for RX (VPI bits,
 139  unknown VCs, oam cells) are made. Ideally all policy items should be
 140  configurable at module load (if not actually on-demand), however,
 141  only the vpi vs vci bit allocation can be specified at insmod.
 142  
 143  4. Shutdown
 144  
 145  This is in response to module_cleaup. No VCs are in use and the card
 146  should be idle; it is reset.
 147  
 148  II Driver software (as it should be)
 149  
 150  0. Traffic Parameters
 151  
 152  The traffic classes (not an enumeration) are currently: ATM_NONE (no
 153  traffic), ATM_UBR, ATM_CBR, ATM_VBR and ATM_ABR, ATM_ANYCLASS
 154  (compatible with everything). Together with (perhaps only some of)
 155  the following items they make up the traffic specification.
 156  
 157  struct atm_trafprm {
 158    unsigned char traffic_class; traffic class (ATM_UBR, ...)
 159    int           max_pcr;       maximum PCR in cells per second
 160    int           pcr;           desired PCR in cells per second
 161    int           min_pcr;       minimum PCR in cells per second
 162    int           max_cdv;       maximum CDV in microseconds
 163    int           max_sdu;       maximum SDU in bytes
 164  };
 165  
 166  Note that these denote bandwidth available not bandwidth used; the
 167  possibilities according to ATMF are:
 168  
 169  Real Time (cdv and max CDT given)
 170  
 171  CBR(pcr)             pcr bandwidth always available
 172  rtVBR(pcr,scr,mbs)   scr bandwidth always available, up to pcr at mbs too
 173  
 174  Non Real Time
 175  
 176  nrtVBR(pcr,scr,mbs)  scr bandwidth always available, up to pcr at mbs too
 177  UBR()
 178  ABR(mcr,pcr)         mcr bandwidth always available, up to pcr (depending) too
 179  
 180  mbs is max burst size (bucket)
 181  pcr and scr have associated cdvt values
 182  mcr is like scr but has no cdtv
 183  cdtv may differ at each hop
 184  
 185  Some of the above items are qos items (as opposed to traffic
 186  parameters). We have nothing to do with qos. All except ABR can have
 187  their traffic parameters converted to GCRA parameters. The GCRA may
 188  be implemented as a (real-number) leaky bucket. The GCRA can be used
 189  in complicated ways by switches and in simpler ways by end-stations.
 190  It can be used both to filter incoming cells and shape out-going
 191  cells.
 192  
 193  ATM Linux actually supports:
 194  
 195  ATM_NONE() (no traffic in this direction)
 196  ATM_UBR(max_frame_size)
 197  ATM_CBR(max/min_pcr, max_cdv, max_frame_size)
 198  
 199  0 or ATM_MAX_PCR are used to indicate maximum available PCR
 200  
 201  A traffic specification consists of the AAL type and separate
 202  traffic specifications for either direction. In ATM Linux it is:
 203  
 204  struct atm_qos {
 205  struct atm_trafprm txtp;
 206  struct atm_trafprm rxtp;
 207  unsigned char aal;
 208  };
 209  
 210  AAL types are:
 211  
 212  ATM_NO_AAL    AAL not specified
 213  ATM_AAL0      "raw" ATM cells
 214  ATM_AAL1      AAL1 (CBR)
 215  ATM_AAL2      AAL2 (VBR)
 216  ATM_AAL34     AAL3/4 (data)
 217  ATM_AAL5      AAL5 (data)
 218  ATM_SAAL      signaling AAL
 219  
 220  The Horizon has support for AAL frame types: 0, 3/4 and 5. However,
 221  it does not implement AAL 3/4 SAR and it has a different notion of
 222  "raw cell" to ATM Linux's (48 bytes vs. 52 bytes) so neither are
 223  supported by this driver.
 224  
 225  The Horizon has limited support for ABR (including UBR), VBR and
 226  CBR. Each TX channel has a bucket (containing up to 31 cell units)
 227  and two timers (PCR and SCR) associated with it that can be used to
 228  govern cell emissions and host notification (in the case of ABR this
 229  is presumably so that RM cells may be emitted at appropriate times).
 230  The timers may either be disabled or may be set to any of 240 values
 231  (determined by the clock crystal, a fixed (?) per-device divider, a
 232  configurable divider and a configurable timer preload value).
 233  
 234  At the moment only UBR and CBR are supported by the driver. VBR will
 235  be supported as soon as ATM for Linux supports it. ABR support is
 236  very unlikely as RM cell handling is completely up to the driver.
 237  
 238  1. TX (TX channel setup and TX transfer)
 239  
 240  The TX half of the driver owns the TX Horizon registers. The TX
 241  component in the IRQ handler is the BM completion handler. This can
 242  only be entered when tx_busy is true (enforced by hardware). The
 243  other TX component can only be entered when tx_busy is false
 244  (enforced by driver). So TX is single-threaded.
 245  
 246  Apart from a minor optimisation to not re-select the last channel,
 247  the TX send component works as follows:
 248  
 249  Atomic test and set tx_busy until we succeed; we should implement
 250  some sort of timeout so that tx_busy will never be stuck at true.
 251  
 252  If no TX channel is set up for this VC we wait for an idle one (if
 253  necessary) and set it up.
 254  
 255  At this point we have a TX channel ready for use. We wait for enough
 256  buffers to become available then start a TX transmit (set the TX
 257  descriptor, schedule transfer, exit).
 258  
 259  The IRQ component handles TX completion (stats, free buffer, tx_busy
 260  unset, exit). We also re-schedule further transfers for the same
 261  frame if needed.
 262  
 263  TX setup in more detail:
 264  
 265  TX open is a nop, the relevant information is held in the hrz_vcc
 266  (vcc->dev_data) structure and is "cached" on the card.
 267  
 268  TX close gets the TX lock and clears the channel from the "cache".
 269  
 270  2. RX (Data Available and RX transfer)
 271  
 272  The RX half of the driver owns the RX registers. There are two RX
 273  components in the IRQ handler: the data available handler deals with
 274  fresh data that has arrived on the card, the BM completion handler
 275  is very similar to the TX completion handler. The data available
 276  handler grabs the rx_lock and it is only released once the data has
 277  been discarded or completely transferred to the host. The BM
 278  completion handler only runs when the lock is held; the data
 279  available handler is locked out over the same period.
 280  
 281  Data available on the card triggers an interrupt. If the data is not
 282  suitable for our existing RX channels or we cannot allocate a buffer
 283  it is flushed. Otherwise an RX receive is scheduled. Multiple RX
 284  transfers may be scheduled for the same frame.
 285  
 286  RX setup in more detail:
 287  
 288  RX open...
 289  RX close...
 290  
 291  III Hardware Bugs
 292  
 293  0. Byte vs Word addressing of adapter RAM.
 294  
 295  A design feature; see the .h file (especially the memory map).
 296  
 297  1. Bus Master Data Transfers (original Horizon only, fixed in Ultra)
 298  
 299  The host must not start a transmit direction transfer at a
 300  non-four-byte boundary in host memory. Instead the host should
 301  perform a byte, or a two byte, or one byte followed by two byte
 302  transfer in order to start the rest of the transfer on a four byte
 303  boundary. RX is OK.
 304  
 305  Simultaneous transmit and receive direction bus master transfers are
 306  not allowed.
 307  
 308  The simplest solution to these two is to always do PIO (never DMA)
 309  in the TX direction on the original Horizon. More complicated
 310  solutions are likely to hurt my brain.
 311  
 312  2. Loss of buffer on close VC
 313  
 314  When a VC is being closed, the buffer associated with it is not
 315  returned to the pool. The host must store the reference to this
 316  buffer and when opening a new VC then give it to that new VC.
 317  
 318  The host intervention currently consists of stacking such a buffer
 319  pointer at VC close and checking the stack at VC open.
 320  
 321  3. Failure to close a VC
 322  
 323  If a VC is currently receiving a frame then closing the VC may fail
 324  and the frame continues to be received.
 325  
 326  The solution is to make sure any received frames are flushed when
 327  ready. This is currently done just before the solution to 2.
 328  
 329  4. PCI bus (original Horizon only, fixed in Ultra)
 330  
 331  Reading from the data port prior to initialisation will hang the PCI
 332  bus. Just don't do that then! We don't.
 333  
 334  IV To Do List
 335  
 336  . Timer code may be broken.
 337  
 338  . Allow users to specify buffer allocation split for TX and RX.
 339  
 340  . Deal once and for all with buggy VC close.
 341  
 342  . Handle interrupted and/or non-blocking operations.
 343  
 344  . Change some macros to functions and move from .h to .c.
 345  
 346  . Try to limit the number of TX frames each VC may have queued, in
 347    order to reduce the chances of TX buffer exhaustion.
 348  
 349  . Implement VBR (bucket and timers not understood) and ABR (need to
 350    do RM cells manually); also no Linux support for either.
 351  
 352  . Implement QoS changes on open VCs (involves extracting parts of VC open
 353    and close into separate functions and using them to make changes).
 354  
 355*/
 356
 357/********** globals **********/
 358
 359static void do_housekeeping (unsigned long arg);
 360
 361static unsigned short debug = 0;
 362static unsigned short vpi_bits = 0;
 363static int max_tx_size = 9000;
 364static int max_rx_size = 9000;
 365static unsigned char pci_lat = 0;
 366
 367/********** access functions **********/
 368
 369/* Read / Write Horizon registers */
 370static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) {
 371  outl (cpu_to_le32 (data), dev->iobase + reg);
 372}
 373
 374static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) {
 375  return le32_to_cpu (inl (dev->iobase + reg));
 376}
 377
 378static inline void wr_regw (const hrz_dev * dev, unsigned char reg, u16 data) {
 379  outw (cpu_to_le16 (data), dev->iobase + reg);
 380}
 381
 382static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) {
 383  return le16_to_cpu (inw (dev->iobase + reg));
 384}
 385
 386static inline void wrs_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
 387  outsb (dev->iobase + reg, addr, len);
 388}
 389
 390static inline void rds_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
 391  insb (dev->iobase + reg, addr, len);
 392}
 393
 394/* Read / Write to a given address in Horizon buffer memory.
 395   Interrupts must be disabled between the address register and data
 396   port accesses as these must form an atomic operation. */
 397static inline void wr_mem (const hrz_dev * dev, HDW * addr, u32 data) {
 398  // wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr);
 399  wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
 400  wr_regl (dev, MEMORY_PORT_OFF, data);
 401}
 402
 403static inline u32 rd_mem (const hrz_dev * dev, HDW * addr) {
 404  // wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr);
 405  wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
 406  return rd_regl (dev, MEMORY_PORT_OFF);
 407}
 408
 409static inline void wr_framer (const hrz_dev * dev, u32 addr, u32 data) {
 410  wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000);
 411  wr_regl (dev, MEMORY_PORT_OFF, data);
 412}
 413
 414static inline u32 rd_framer (const hrz_dev * dev, u32 addr) {
 415  wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000);
 416  return rd_regl (dev, MEMORY_PORT_OFF);
 417}
 418
 419/********** specialised access functions **********/
 420
 421/* RX */
 422
 423static inline void FLUSH_RX_CHANNEL (hrz_dev * dev, u16 channel) {
 424  wr_regw (dev, RX_CHANNEL_PORT_OFF, FLUSH_CHANNEL | channel);
 425  return;
 426}
 427
 428static void WAIT_FLUSH_RX_COMPLETE (hrz_dev * dev) {
 429  while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & FLUSH_CHANNEL)
 430    ;
 431  return;
 432}
 433
 434static inline void SELECT_RX_CHANNEL (hrz_dev * dev, u16 channel) {
 435  wr_regw (dev, RX_CHANNEL_PORT_OFF, channel);
 436  return;
 437}
 438
 439static void WAIT_UPDATE_COMPLETE (hrz_dev * dev) {
 440  while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & RX_CHANNEL_UPDATE_IN_PROGRESS)
 441    ;
 442  return;
 443}
 444
 445/* TX */
 446
 447static inline void SELECT_TX_CHANNEL (hrz_dev * dev, u16 tx_channel) {
 448  wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel);
 449  return;
 450}
 451
 452/* Update or query one configuration parameter of a particular channel. */
 453
 454static inline void update_tx_channel_config (hrz_dev * dev, short chan, u8 mode, u16 value) {
 455  wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
 456           chan * TX_CHANNEL_CONFIG_MULT | mode);
 457    wr_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF, value);
 458    return;
 459}
 460
 461static inline u16 query_tx_channel_config (hrz_dev * dev, short chan, u8 mode) {
 462  wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
 463           chan * TX_CHANNEL_CONFIG_MULT | mode);
 464    return rd_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF);
 465}
 466
 467/********** dump functions **********/
 468
 469static inline void dump_skb (char * prefix, unsigned int vc, struct sk_buff * skb) {
 470#ifdef DEBUG_HORIZON
 471  unsigned int i;
 472  unsigned char * data = skb->data;
 473  PRINTDB (DBG_DATA, "%s(%u) ", prefix, vc);
 474  for (i=0; i<skb->len && i < 256;i++)
 475    PRINTDM (DBG_DATA, "%02x ", data[i]);
 476  PRINTDE (DBG_DATA,"");
 477#else
 478  (void) prefix;
 479  (void) vc;
 480  (void) skb;
 481#endif
 482  return;
 483}
 484
 485static inline void dump_regs (hrz_dev * dev) {
 486#ifdef DEBUG_HORIZON
 487  PRINTD (DBG_REGS, "CONTROL 0: %#x", rd_regl (dev, CONTROL_0_REG));
 488  PRINTD (DBG_REGS, "RX CONFIG: %#x", rd_regw (dev, RX_CONFIG_OFF));
 489  PRINTD (DBG_REGS, "TX CONFIG: %#x", rd_regw (dev, TX_CONFIG_OFF));
 490  PRINTD (DBG_REGS, "TX STATUS: %#x", rd_regw (dev, TX_STATUS_OFF));
 491  PRINTD (DBG_REGS, "IRQ ENBLE: %#x", rd_regl (dev, INT_ENABLE_REG_OFF));
 492  PRINTD (DBG_REGS, "IRQ SORCE: %#x", rd_regl (dev, INT_SOURCE_REG_OFF));
 493#else
 494  (void) dev;
 495#endif
 496  return;
 497}
 498
 499static inline void dump_framer (hrz_dev * dev) {
 500#ifdef DEBUG_HORIZON
 501  unsigned int i;
 502  PRINTDB (DBG_REGS, "framer registers:");
 503  for (i = 0; i < 0x10; ++i)
 504    PRINTDM (DBG_REGS, " %02x", rd_framer (dev, i));
 505  PRINTDE (DBG_REGS,"");
 506#else
 507  (void) dev;
 508#endif
 509  return;
 510}
 511
 512/********** VPI/VCI <-> (RX) channel conversions **********/
 513
 514/* RX channels are 10 bit integers, these fns are quite paranoid */
 515
 516static inline int channel_to_vpivci (const u16 channel, short * vpi, int * vci) {
 517  unsigned short vci_bits = 10 - vpi_bits;
 518  if ((channel & RX_CHANNEL_MASK) == channel) {
 519    *vci = channel & ((~0)<<vci_bits);
 520    *vpi = channel >> vci_bits;
 521    return channel ? 0 : -EINVAL;
 522  }
 523  return -EINVAL;
 524}
 525
 526static inline int vpivci_to_channel (u16 * channel, const short vpi, const int vci) {
 527  unsigned short vci_bits = 10 - vpi_bits;
 528  if (0 <= vpi && vpi < 1<<vpi_bits && 0 <= vci && vci < 1<<vci_bits) {
 529    *channel = vpi<<vci_bits | vci;
 530    return *channel ? 0 : -EINVAL;
 531  }
 532  return -EINVAL;
 533}
 534
 535/********** decode RX queue entries **********/
 536
 537static inline u16 rx_q_entry_to_length (u32 x) {
 538  return x & RX_Q_ENTRY_LENGTH_MASK;
 539}
 540
 541static inline u16 rx_q_entry_to_rx_channel (u32 x) {
 542  return (x>>RX_Q_ENTRY_CHANNEL_SHIFT) & RX_CHANNEL_MASK;
 543}
 544
 545/* Cell Transmit Rate Values
 546 *
 547 * the cell transmit rate (cells per sec) can be set to a variety of
 548 * different values by specifying two parameters: a timer preload from
 549 * 1 to 16 (stored as 0 to 15) and a clock divider (2 to the power of
 550 * an exponent from 0 to 14; the special value 15 disables the timer).
 551 *
 552 * cellrate = baserate / (preload * 2^divider)
 553 *
 554 * The maximum cell rate that can be specified is therefore just the
 555 * base rate. Halving the preload is equivalent to adding 1 to the
 556 * divider and so values 1 to 8 of the preload are redundant except
 557 * in the case of a maximal divider (14).
 558 *
 559 * Given a desired cell rate, an algorithm to determine the preload
 560 * and divider is:
 561 * 
 562 * a) x = baserate / cellrate, want p * 2^d = x (as far as possible)
 563 * b) if x > 16 * 2^14 then set p = 16, d = 14 (min rate), done
 564 *    if x <= 16 then set p = x, d = 0 (high rates), done
 565 * c) now have 16 < x <= 2^18, or 1 < x/16 <= 2^14 and we want to
 566 *    know n such that 2^(n-1) < x/16 <= 2^n, so slide a bit until
 567 *    we find the range (n will be between 1 and 14), set d = n
 568 * d) Also have 8 < x/2^n <= 16, so set p nearest x/2^n
 569 *
 570 * The algorithm used below is a minor variant of the above.
 571 *
 572 * The base rate is derived from the oscillator frequency (Hz) using a
 573 * fixed divider:
 574 *
 575 * baserate = freq / 32 in the case of some Unknown Card
 576 * baserate = freq / 8  in the case of the Horizon        25
 577 * baserate = freq / 8  in the case of the Horizon Ultra 155
 578 *
 579 * The Horizon cards have oscillators and base rates as follows:
 580 *
 581 * Card               Oscillator  Base Rate
 582 * Unknown Card       33 MHz      1.03125 MHz (33 MHz = PCI freq)
 583 * Horizon        25  32 MHz      4       MHz
 584 * Horizon Ultra 155  40 MHz      5       MHz
 585 *
 586 * The following defines give the base rates in Hz. These were
 587 * previously a factor of 100 larger, no doubt someone was using
 588 * cps*100.
 589 */
 590
 591#define BR_UKN 1031250l
 592#define BR_HRZ 4000000l
 593#define BR_ULT 5000000l
 594
 595// d is an exponent
 596#define CR_MIND 0
 597#define CR_MAXD 14
 598
 599// p ranges from 1 to a power of 2
 600#define CR_MAXPEXP 4
 601 
 602static int make_rate (const hrz_dev * dev, u32 c, rounding r,
 603                      u16 * bits, unsigned int * actual)
 604{
 605        // note: rounding the rate down means rounding 'p' up
 606        const unsigned long br = test_bit(ultra, &dev->flags) ? BR_ULT : BR_HRZ;
 607  
 608        u32 div = CR_MIND;
 609        u32 pre;
 610  
 611        // br_exp and br_man are used to avoid overflowing (c*maxp*2^d) in
 612        // the tests below. We could think harder about exact possibilities
 613        // of failure...
 614  
 615        unsigned long br_man = br;
 616        unsigned int br_exp = 0;
 617  
 618        PRINTD (DBG_QOS|DBG_FLOW, "make_rate b=%lu, c=%u, %s", br, c,
 619                r == round_up ? "up" : r == round_down ? "down" : "nearest");
 620  
 621        // avoid div by zero
 622        if (!c) {
 623                PRINTD (DBG_QOS|DBG_ERR, "zero rate is not allowed!");
 624                return -EINVAL;
 625        }
 626  
 627        while (br_exp < CR_MAXPEXP + CR_MIND && (br_man % 2 == 0)) {
 628                br_man = br_man >> 1;
 629                ++br_exp;
 630        }
 631        // (br >>br_exp) <<br_exp == br and
 632        // br_exp <= CR_MAXPEXP+CR_MIND
 633  
 634        if (br_man <= (c << (CR_MAXPEXP+CR_MIND-br_exp))) {
 635                // Equivalent to: B <= (c << (MAXPEXP+MIND))
 636                // take care of rounding
 637                switch (r) {
 638                        case round_down:
 639                                pre = DIV_ROUND_UP(br, c<<div);
 640                                // but p must be non-zero
 641                                if (!pre)
 642                                        pre = 1;
 643                                break;
 644                        case round_nearest:
 645                                pre = DIV_ROUND_CLOSEST(br, c<<div);
 646                                // but p must be non-zero
 647                                if (!pre)
 648                                        pre = 1;
 649                                break;
 650                        default:        /* round_up */
 651                                pre = br/(c<<div);
 652                                // but p must be non-zero
 653                                if (!pre)
 654                                        return -EINVAL;
 655                }
 656                PRINTD (DBG_QOS, "A: p=%u, d=%u", pre, div);
 657                goto got_it;
 658        }
 659  
 660        // at this point we have
 661        // d == MIND and (c << (MAXPEXP+MIND)) < B
 662        while (div < CR_MAXD) {
 663                div++;
 664                if (br_man <= (c << (CR_MAXPEXP+div-br_exp))) {
 665                        // Equivalent to: B <= (c << (MAXPEXP+d))
 666                        // c << (MAXPEXP+d-1) < B <= c << (MAXPEXP+d)
 667                        // 1 << (MAXPEXP-1) < B/2^d/c <= 1 << MAXPEXP
 668                        // MAXP/2 < B/c2^d <= MAXP
 669                        // take care of rounding
 670                        switch (r) {
 671                                case round_down:
 672                                        pre = DIV_ROUND_UP(br, c<<div);
 673                                        break;
 674                                case round_nearest:
 675                                        pre = DIV_ROUND_CLOSEST(br, c<<div);
 676                                        break;
 677                                default: /* round_up */
 678                                        pre = br/(c<<div);
 679                        }
 680                        PRINTD (DBG_QOS, "B: p=%u, d=%u", pre, div);
 681                        goto got_it;
 682                }
 683        }
 684        // at this point we have
 685        // d == MAXD and (c << (MAXPEXP+MAXD)) < B
 686        // but we cannot go any higher
 687        // take care of rounding
 688        if (r == round_down)
 689                return -EINVAL;
 690        pre = 1 << CR_MAXPEXP;
 691        PRINTD (DBG_QOS, "C: p=%u, d=%u", pre, div);
 692got_it:
 693        // paranoia
 694        if (div > CR_MAXD || (!pre) || pre > 1<<CR_MAXPEXP) {
 695                PRINTD (DBG_QOS, "set_cr internal failure: d=%u p=%u",
 696                        div, pre);
 697                return -EINVAL;
 698        } else {
 699                if (bits)
 700                        *bits = (div<<CLOCK_SELECT_SHIFT) | (pre-1);
 701                if (actual) {
 702                        *actual = DIV_ROUND_UP(br, pre<<div);
 703                        PRINTD (DBG_QOS, "actual rate: %u", *actual);
 704                }
 705                return 0;
 706        }
 707}
 708
 709static int make_rate_with_tolerance (const hrz_dev * dev, u32 c, rounding r, unsigned int tol,
 710                                     u16 * bit_pattern, unsigned int * actual) {
 711  unsigned int my_actual;
 712  
 713  PRINTD (DBG_QOS|DBG_FLOW, "make_rate_with_tolerance c=%u, %s, tol=%u",
 714          c, (r == round_up) ? "up" : (r == round_down) ? "down" : "nearest", tol);
 715  
 716  if (!actual)
 717    // actual rate is not returned
 718    actual = &my_actual;
 719  
 720  if (make_rate (dev, c, round_nearest, bit_pattern, actual))
 721    // should never happen as round_nearest always succeeds
 722    return -1;
 723  
 724  if (c - tol <= *actual && *actual <= c + tol)
 725    // within tolerance
 726    return 0;
 727  else
 728    // intolerant, try rounding instead
 729    return make_rate (dev, c, r, bit_pattern, actual);
 730}
 731
 732/********** Listen on a VC **********/
 733
 734static int hrz_open_rx (hrz_dev * dev, u16 channel) {
 735  // is there any guarantee that we don't get two simulataneous
 736  // identical calls of this function from different processes? yes
 737  // rate_lock
 738  unsigned long flags;
 739  u32 channel_type; // u16?
 740  
 741  u16 buf_ptr = RX_CHANNEL_IDLE;
 742  
 743  rx_ch_desc * rx_desc = &memmap->rx_descs[channel];
 744  
 745  PRINTD (DBG_FLOW, "hrz_open_rx %x", channel);
 746  
 747  spin_lock_irqsave (&dev->mem_lock, flags);
 748  channel_type = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
 749  spin_unlock_irqrestore (&dev->mem_lock, flags);
 750  
 751  // very serious error, should never occur
 752  if (channel_type != RX_CHANNEL_DISABLED) {
 753    PRINTD (DBG_ERR|DBG_VCC, "RX channel for VC already open");
 754    return -EBUSY; // clean up?
 755  }
 756  
 757  // Give back spare buffer
 758  if (dev->noof_spare_buffers) {
 759    buf_ptr = dev->spare_buffers[--dev->noof_spare_buffers];
 760    PRINTD (DBG_VCC, "using a spare buffer: %u", buf_ptr);
 761    // should never occur
 762    if (buf_ptr == RX_CHANNEL_DISABLED || buf_ptr == RX_CHANNEL_IDLE) {
 763      // but easy to recover from
 764      PRINTD (DBG_ERR|DBG_VCC, "bad spare buffer pointer, using IDLE");
 765      buf_ptr = RX_CHANNEL_IDLE;
 766    }
 767  } else {
 768    PRINTD (DBG_VCC, "using IDLE buffer pointer");
 769  }
 770  
 771  // Channel is currently disabled so change its status to idle
 772  
 773  // do we really need to save the flags again?
 774  spin_lock_irqsave (&dev->mem_lock, flags);
 775  
 776  wr_mem (dev, &rx_desc->wr_buf_type,
 777          buf_ptr | CHANNEL_TYPE_AAL5 | FIRST_CELL_OF_AAL5_FRAME);
 778  if (buf_ptr != RX_CHANNEL_IDLE)
 779    wr_mem (dev, &rx_desc->rd_buf_type, buf_ptr);
 780  
 781  spin_unlock_irqrestore (&dev->mem_lock, flags);
 782  
 783  // rxer->rate = make_rate (qos->peak_cells);
 784  
 785  PRINTD (DBG_FLOW, "hrz_open_rx ok");
 786  
 787  return 0;
 788}
 789
 790#if 0
 791/********** change vc rate for a given vc **********/
 792
 793static void hrz_change_vc_qos (ATM_RXER * rxer, MAAL_QOS * qos) {
 794  rxer->rate = make_rate (qos->peak_cells);
 795}
 796#endif
 797
 798/********** free an skb (as per ATM device driver documentation) **********/
 799
 800static void hrz_kfree_skb (struct sk_buff * skb) {
 801  if (ATM_SKB(skb)->vcc->pop) {
 802    ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
 803  } else {
 804    dev_kfree_skb_any (skb);
 805  }
 806}
 807
 808/********** cancel listen on a VC **********/
 809
 810static void hrz_close_rx (hrz_dev * dev, u16 vc) {
 811  unsigned long flags;
 812  
 813  u32 value;
 814  
 815  u32 r1, r2;
 816  
 817  rx_ch_desc * rx_desc = &memmap->rx_descs[vc];
 818  
 819  int was_idle = 0;
 820  
 821  spin_lock_irqsave (&dev->mem_lock, flags);
 822  value = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
 823  spin_unlock_irqrestore (&dev->mem_lock, flags);
 824  
 825  if (value == RX_CHANNEL_DISABLED) {
 826    // I suppose this could happen once we deal with _NONE traffic properly
 827    PRINTD (DBG_VCC, "closing VC: RX channel %u already disabled", vc);
 828    return;
 829  }
 830  if (value == RX_CHANNEL_IDLE)
 831    was_idle = 1;
 832  
 833  spin_lock_irqsave (&dev->mem_lock, flags);
 834  
 835  for (;;) {
 836    wr_mem (dev, &rx_desc->wr_buf_type, RX_CHANNEL_DISABLED);
 837    
 838    if ((rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK) == RX_CHANNEL_DISABLED)
 839      break;
 840    
 841    was_idle = 0;
 842  }
 843  
 844  if (was_idle) {
 845    spin_unlock_irqrestore (&dev->mem_lock, flags);
 846    return;
 847  }
 848  
 849  WAIT_FLUSH_RX_COMPLETE(dev);
 850  
 851  // XXX Is this all really necessary? We can rely on the rx_data_av
 852  // handler to discard frames that remain queued for delivery. If the
 853  // worry is that immediately reopening the channel (perhaps by a
 854  // different process) may cause some data to be mis-delivered then
 855  // there may still be a simpler solution (such as busy-waiting on
 856  // rx_busy once the channel is disabled or before a new one is
 857  // opened - does this leave any holes?). Arguably setting up and
 858  // tearing down the TX and RX halves of each virtual circuit could
 859  // most safely be done within ?x_busy protected regions.
 860  
 861  // OK, current changes are that Simon's marker is disabled and we DO
 862  // look for NULL rxer elsewhere. The code here seems flush frames
 863  // and then remember the last dead cell belonging to the channel
 864  // just disabled - the cell gets relinked at the next vc_open.
 865  // However, when all VCs are closed or only a few opened there are a
 866  // handful of buffers that are unusable.
 867  
 868  // Does anyone feel like documenting spare_buffers properly?
 869  // Does anyone feel like fixing this in a nicer way?
 870  
 871  // Flush any data which is left in the channel
 872  for (;;) {
 873    // Change the rx channel port to something different to the RX
 874    // channel we are trying to close to force Horizon to flush the rx
 875    // channel read and write pointers.
 876    
 877    u16 other = vc^(RX_CHANS/2);
 878    
 879    SELECT_RX_CHANNEL (dev, other);
 880    WAIT_UPDATE_COMPLETE (dev);
 881    
 882    r1 = rd_mem (dev, &rx_desc->rd_buf_type);
 883    
 884    // Select this RX channel. Flush doesn't seem to work unless we
 885    // select an RX channel before hand
 886    
 887    SELECT_RX_CHANNEL (dev, vc);
 888    WAIT_UPDATE_COMPLETE (dev);
 889    
 890    // Attempt to flush a frame on this RX channel
 891    
 892    FLUSH_RX_CHANNEL (dev, vc);
 893    WAIT_FLUSH_RX_COMPLETE (dev);
 894    
 895    // Force Horizon to flush rx channel read and write pointers as before
 896    
 897    SELECT_RX_CHANNEL (dev, other);
 898    WAIT_UPDATE_COMPLETE (dev);
 899    
 900    r2 = rd_mem (dev, &rx_desc->rd_buf_type);
 901    
 902    PRINTD (DBG_VCC|DBG_RX, "r1 = %u, r2 = %u", r1, r2);
 903    
 904    if (r1 == r2) {
 905      dev->spare_buffers[dev->noof_spare_buffers++] = (u16)r1;
 906      break;
 907    }
 908  }
 909  
 910#if 0
 911  {
 912    rx_q_entry * wr_ptr = &memmap->rx_q_entries[rd_regw (dev, RX_QUEUE_WR_PTR_OFF)];
 913    rx_q_entry * rd_ptr = dev->rx_q_entry;
 914    
 915    PRINTD (DBG_VCC|DBG_RX, "rd_ptr = %u, wr_ptr = %u", rd_ptr, wr_ptr);
 916    
 917    while (rd_ptr != wr_ptr) {
 918      u32 x = rd_mem (dev, (HDW *) rd_ptr);
 919      
 920      if (vc == rx_q_entry_to_rx_channel (x)) {
 921        x |= SIMONS_DODGEY_MARKER;
 922        
 923        PRINTD (DBG_RX|DBG_VCC|DBG_WARN, "marking a frame as dodgey");
 924        
 925        wr_mem (dev, (HDW *) rd_ptr, x);
 926      }
 927      
 928      if (rd_ptr == dev->rx_q_wrap)
 929        rd_ptr = dev->rx_q_reset;
 930      else
 931        rd_ptr++;
 932    }
 933  }
 934#endif
 935  
 936  spin_unlock_irqrestore (&dev->mem_lock, flags);
 937  
 938  return;
 939}
 940
 941/********** schedule RX transfers **********/
 942
 943// Note on tail recursion: a GCC developer said that it is not likely
 944// to be fixed soon, so do not define TAILRECUSRIONWORKS unless you
 945// are sure it does as you may otherwise overflow the kernel stack.
 946
 947// giving this fn a return value would help GCC, allegedly
 948
 949static void rx_schedule (hrz_dev * dev, int irq) {
 950  unsigned int rx_bytes;
 951  
 952  int pio_instead = 0;
 953#ifndef TAILRECURSIONWORKS
 954  pio_instead = 1;
 955  while (pio_instead) {
 956#endif
 957    // bytes waiting for RX transfer
 958    rx_bytes = dev->rx_bytes;
 959    
 960#if 0
 961    spin_count = 0;
 962    while (rd_regl (dev, MASTER_RX_COUNT_REG_OFF)) {
 963      PRINTD (DBG_RX|DBG_WARN, "RX error: other PCI Bus Master RX still in progress!");
 964      if (++spin_count > 10) {
 965        PRINTD (DBG_RX|DBG_ERR, "spun out waiting PCI Bus Master RX completion");
 966        wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
 967        clear_bit (rx_busy, &dev->flags);
 968        hrz_kfree_skb (dev->rx_skb);
 969        return;
 970      }
 971    }
 972#endif
 973    
 974    // this code follows the TX code but (at the moment) there is only
 975    // one region - the skb itself. I don't know if this will change,
 976    // but it doesn't hurt to have the code here, disabled.
 977    
 978    if (rx_bytes) {
 979      // start next transfer within same region
 980      if (rx_bytes <= MAX_PIO_COUNT) {
 981        PRINTD (DBG_RX|DBG_BUS, "(pio)");
 982        pio_instead = 1;
 983      }
 984      if (rx_bytes <= MAX_TRANSFER_COUNT) {
 985        PRINTD (DBG_RX|DBG_BUS, "(simple or last multi)");
 986        dev->rx_bytes = 0;
 987      } else {
 988        PRINTD (DBG_RX|DBG_BUS, "(continuing multi)");
 989        dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
 990        rx_bytes = MAX_TRANSFER_COUNT;
 991      }
 992    } else {
 993      // rx_bytes == 0 -- we're between regions
 994      // regions remaining to transfer
 995#if 0
 996      unsigned int rx_regions = dev->rx_regions;
 997#else
 998      unsigned int rx_regions = 0;
 999#endif
1000      
1001      if (rx_regions) {
1002#if 0
1003        // start a new region
1004        dev->rx_addr = dev->rx_iovec->iov_base;
1005        rx_bytes = dev->rx_iovec->iov_len;
1006        ++dev->rx_iovec;
1007        dev->rx_regions = rx_regions - 1;
1008        
1009        if (rx_bytes <= MAX_PIO_COUNT) {
1010          PRINTD (DBG_RX|DBG_BUS, "(pio)");
1011          pio_instead = 1;
1012        }
1013        if (rx_bytes <= MAX_TRANSFER_COUNT) {
1014          PRINTD (DBG_RX|DBG_BUS, "(full region)");
1015          dev->rx_bytes = 0;
1016        } else {
1017          PRINTD (DBG_RX|DBG_BUS, "(start multi region)");
1018          dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
1019          rx_bytes = MAX_TRANSFER_COUNT;
1020        }
1021#endif
1022      } else {
1023        // rx_regions == 0
1024        // that's all folks - end of frame
1025        struct sk_buff * skb = dev->rx_skb;
1026        // dev->rx_iovec = 0;
1027        
1028        FLUSH_RX_CHANNEL (dev, dev->rx_channel);
1029        
1030        dump_skb ("<<<", dev->rx_channel, skb);
1031        
1032        PRINTD (DBG_RX|DBG_SKB, "push %p %u", skb->data, skb->len);
1033        
1034        {
1035          struct atm_vcc * vcc = ATM_SKB(skb)->vcc;
1036          // VC layer stats
1037          atomic_inc(&vcc->stats->rx);
1038          __net_timestamp(skb);
1039          // end of our responsibility
1040          vcc->push (vcc, skb);
1041        }
1042      }
1043    }
1044    
1045    // note: writing RX_COUNT clears any interrupt condition
1046    if (rx_bytes) {
1047      if (pio_instead) {
1048        if (irq)
1049          wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1050        rds_regb (dev, DATA_PORT_OFF, dev->rx_addr, rx_bytes);
1051      } else {
1052        wr_regl (dev, MASTER_RX_ADDR_REG_OFF, virt_to_bus (dev->rx_addr));
1053        wr_regl (dev, MASTER_RX_COUNT_REG_OFF, rx_bytes);
1054      }
1055      dev->rx_addr += rx_bytes;
1056    } else {
1057      if (irq)
1058        wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1059      // allow another RX thread to start
1060      YELLOW_LED_ON(dev);
1061      clear_bit (rx_busy, &dev->flags);
1062      PRINTD (DBG_RX, "cleared rx_busy for dev %p", dev);
1063    }
1064    
1065#ifdef TAILRECURSIONWORKS
1066    // and we all bless optimised tail calls
1067    if (pio_instead)
1068      return rx_schedule (dev, 0);
1069    return;
1070#else
1071    // grrrrrrr!
1072    irq = 0;
1073  }
1074  return;
1075#endif
1076}
1077
1078/********** handle RX bus master complete events **********/
1079
1080static void rx_bus_master_complete_handler (hrz_dev * dev) {
1081  if (test_bit (rx_busy, &dev->flags)) {
1082    rx_schedule (dev, 1);
1083  } else {
1084    PRINTD (DBG_RX|DBG_ERR, "unexpected RX bus master completion");
1085    // clear interrupt condition on adapter
1086    wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1087  }
1088  return;
1089}
1090
1091/********** (queue to) become the next TX thread **********/
1092
1093static int tx_hold (hrz_dev * dev) {
1094  PRINTD (DBG_TX, "sleeping at tx lock %p %lu", dev, dev->flags);
1095  wait_event_interruptible(dev->tx_queue, (!test_and_set_bit(tx_busy, &dev->flags)));
1096  PRINTD (DBG_TX, "woken at tx lock %p %lu", dev, dev->flags);
1097  if (signal_pending (current))
1098    return -1;
1099  PRINTD (DBG_TX, "set tx_busy for dev %p", dev);
1100  return 0;
1101}
1102
1103/********** allow another TX thread to start **********/
1104
1105static inline void tx_release (hrz_dev * dev) {
1106  clear_bit (tx_busy, &dev->flags);
1107  PRINTD (DBG_TX, "cleared tx_busy for dev %p", dev);
1108  wake_up_interruptible (&dev->tx_queue);
1109}
1110
1111/********** schedule TX transfers **********/
1112
1113static void tx_schedule (hrz_dev * const dev, int irq) {
1114  unsigned int tx_bytes;
1115  
1116  int append_desc = 0;
1117  
1118  int pio_instead = 0;
1119#ifndef TAILRECURSIONWORKS
1120  pio_instead = 1;
1121  while (pio_instead) {
1122#endif
1123    // bytes in current region waiting for TX transfer
1124    tx_bytes = dev->tx_bytes;
1125    
1126#if 0
1127    spin_count = 0;
1128    while (rd_regl (dev, MASTER_TX_COUNT_REG_OFF)) {
1129      PRINTD (DBG_TX|DBG_WARN, "TX error: other PCI Bus Master TX still in progress!");
1130      if (++spin_count > 10) {
1131        PRINTD (DBG_TX|DBG_ERR, "spun out waiting PCI Bus Master TX completion");
1132        wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1133        tx_release (dev);
1134        hrz_kfree_skb (dev->tx_skb);
1135        return;
1136      }
1137    }
1138#endif
1139    
1140    if (tx_bytes) {
1141      // start next transfer within same region
1142      if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1143        PRINTD (DBG_TX|DBG_BUS, "(pio)");
1144        pio_instead = 1;
1145      }
1146      if (tx_bytes <= MAX_TRANSFER_COUNT) {
1147        PRINTD (DBG_TX|DBG_BUS, "(simple or last multi)");
1148        if (!dev->tx_iovec) {
1149          // end of last region
1150          append_desc = 1;
1151        }
1152        dev->tx_bytes = 0;
1153      } else {
1154        PRINTD (DBG_TX|DBG_BUS, "(continuing multi)");
1155        dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1156        tx_bytes = MAX_TRANSFER_COUNT;
1157      }
1158    } else {
1159      // tx_bytes == 0 -- we're between regions
1160      // regions remaining to transfer
1161      unsigned int tx_regions = dev->tx_regions;
1162      
1163      if (tx_regions) {
1164        // start a new region
1165        dev->tx_addr = dev->tx_iovec->iov_base;
1166        tx_bytes = dev->tx_iovec->iov_len;
1167        ++dev->tx_iovec;
1168        dev->tx_regions = tx_regions - 1;
1169        
1170        if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1171          PRINTD (DBG_TX|DBG_BUS, "(pio)");
1172          pio_instead = 1;
1173        }
1174        if (tx_bytes <= MAX_TRANSFER_COUNT) {
1175          PRINTD (DBG_TX|DBG_BUS, "(full region)");
1176          dev->tx_bytes = 0;
1177        } else {
1178          PRINTD (DBG_TX|DBG_BUS, "(start multi region)");
1179          dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1180          tx_bytes = MAX_TRANSFER_COUNT;
1181        }
1182      } else {
1183        // tx_regions == 0
1184        // that's all folks - end of frame
1185        struct sk_buff * skb = dev->tx_skb;
1186        dev->tx_iovec = NULL;
1187        
1188        // VC layer stats
1189        atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
1190        
1191        // free the skb
1192        hrz_kfree_skb (skb);
1193      }
1194    }
1195    
1196    // note: writing TX_COUNT clears any interrupt condition
1197    if (tx_bytes) {
1198      if (pio_instead) {
1199        if (irq)
1200          wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1201        wrs_regb (dev, DATA_PORT_OFF, dev->tx_addr, tx_bytes);
1202        if (append_desc)
1203          wr_regl (dev, TX_DESCRIPTOR_PORT_OFF, cpu_to_be32 (dev->tx_skb->len));
1204      } else {
1205        wr_regl (dev, MASTER_TX_ADDR_REG_OFF, virt_to_bus (dev->tx_addr));
1206        if (append_desc)
1207          wr_regl (dev, TX_DESCRIPTOR_REG_OFF, cpu_to_be32 (dev->tx_skb->len));
1208        wr_regl (dev, MASTER_TX_COUNT_REG_OFF,
1209                 append_desc
1210                 ? tx_bytes | MASTER_TX_AUTO_APPEND_DESC
1211                 : tx_bytes);
1212      }
1213      dev->tx_addr += tx_bytes;
1214    } else {
1215      if (irq)
1216        wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1217      YELLOW_LED_ON(dev);
1218      tx_release (dev);
1219    }
1220    
1221#ifdef TAILRECURSIONWORKS
1222    // and we all bless optimised tail calls
1223    if (pio_instead)
1224      return tx_schedule (dev, 0);
1225    return;
1226#else
1227    // grrrrrrr!
1228    irq = 0;
1229  }
1230  return;
1231#endif
1232}
1233
1234/********** handle TX bus master complete events **********/
1235
1236static void tx_bus_master_complete_handler (hrz_dev * dev) {
1237  if (test_bit (tx_busy, &dev->flags)) {
1238    tx_schedule (dev, 1);
1239  } else {
1240    PRINTD (DBG_TX|DBG_ERR, "unexpected TX bus master completion");
1241    // clear interrupt condition on adapter
1242    wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1243  }
1244  return;
1245}
1246
1247/********** move RX Q pointer to next item in circular buffer **********/
1248
1249// called only from IRQ sub-handler
1250static u32 rx_queue_entry_next (hrz_dev * dev) {
1251  u32 rx_queue_entry;
1252  spin_lock (&dev->mem_lock);
1253  rx_queue_entry = rd_mem (dev, &dev->rx_q_entry->entry);
1254  if (dev->rx_q_entry == dev->rx_q_wrap)
1255    dev->rx_q_entry = dev->rx_q_reset;
1256  else
1257    dev->rx_q_entry++;
1258  wr_regw (dev, RX_QUEUE_RD_PTR_OFF, dev->rx_q_entry - dev->rx_q_reset);
1259  spin_unlock (&dev->mem_lock);
1260  return rx_queue_entry;
1261}
1262
1263/********** handle RX disabled by device **********/
1264
1265static inline void rx_disabled_handler (hrz_dev * dev) {
1266  wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
1267  // count me please
1268  PRINTK (KERN_WARNING, "RX was disabled!");
1269}
1270
1271/********** handle RX data received by device **********/
1272
1273// called from IRQ handler
1274static void rx_data_av_handler (hrz_dev * dev) {
1275  u32 rx_queue_entry;
1276  u32 rx_queue_entry_flags;
1277  u16 rx_len;
1278  u16 rx_channel;
1279  
1280  PRINTD (DBG_FLOW, "hrz_data_av_handler");
1281  
1282  // try to grab rx lock (not possible during RX bus mastering)
1283  if (test_and_set_bit (rx_busy, &dev->flags)) {
1284    PRINTD (DBG_RX, "locked out of rx lock");
1285    return;
1286  }
1287  PRINTD (DBG_RX, "set rx_busy for dev %p", dev);
1288  // lock is cleared if we fail now, o/w after bus master completion
1289  
1290  YELLOW_LED_OFF(dev);
1291  
1292  rx_queue_entry = rx_queue_entry_next (dev);
1293  
1294  rx_len = rx_q_entry_to_length (rx_queue_entry);
1295  rx_channel = rx_q_entry_to_rx_channel (rx_queue_entry);
1296  
1297  WAIT_FLUSH_RX_COMPLETE (dev);
1298  
1299  SELECT_RX_CHANNEL (dev, rx_channel);
1300  
1301  PRINTD (DBG_RX, "rx_queue_entry is: %#x", rx_queue_entry);
1302  rx_queue_entry_flags = rx_queue_entry & (RX_CRC_32_OK|RX_COMPLETE_FRAME|SIMONS_DODGEY_MARKER);
1303  
1304  if (!rx_len) {
1305    // (at least) bus-mastering breaks if we try to handle a
1306    // zero-length frame, besides AAL5 does not support them
1307    PRINTK (KERN_ERR, "zero-length frame!");
1308    rx_queue_entry_flags &= ~RX_COMPLETE_FRAME;
1309  }
1310  
1311  if (rx_queue_entry_flags & SIMONS_DODGEY_MARKER) {
1312    PRINTD (DBG_RX|DBG_ERR, "Simon's marker detected!");
1313  }
1314  if (rx_queue_entry_flags == (RX_CRC_32_OK | RX_COMPLETE_FRAME)) {
1315    struct atm_vcc * atm_vcc;
1316    
1317    PRINTD (DBG_RX, "got a frame on rx_channel %x len %u", rx_channel, rx_len);
1318    
1319    atm_vcc = dev->rxer[rx_channel];
1320    // if no vcc is assigned to this channel, we should drop the frame
1321    // (is this what SIMONS etc. was trying to achieve?)
1322    
1323    if (atm_vcc) {
1324      
1325      if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
1326        
1327        if (rx_len <= atm_vcc->qos.rxtp.max_sdu) {
1328            
1329          struct sk_buff * skb = atm_alloc_charge (atm_vcc, rx_len, GFP_ATOMIC);
1330          if (skb) {
1331            // remember this so we can push it later
1332            dev->rx_skb = skb;
1333            // remember this so we can flush it later
1334            dev->rx_channel = rx_channel;
1335            
1336            // prepare socket buffer
1337            skb_put (skb, rx_len);
1338            ATM_SKB(skb)->vcc = atm_vcc;
1339            
1340            // simple transfer
1341            // dev->rx_regions = 0;
1342            // dev->rx_iovec = 0;
1343            dev->rx_bytes = rx_len;
1344            dev->rx_addr = skb->data;
1345            PRINTD (DBG_RX, "RX start simple transfer (addr %p, len %d)",
1346                    skb->data, rx_len);
1347            
1348            // do the business
1349            rx_schedule (dev, 0);
1350            return;
1351            
1352          } else {
1353            PRINTD (DBG_SKB|DBG_WARN, "failed to get skb");
1354          }
1355          
1356        } else {
1357          PRINTK (KERN_INFO, "frame received on TX-only VC %x", rx_channel);
1358          // do we count this?
1359        }
1360        
1361      } else {
1362        PRINTK (KERN_WARNING, "dropped over-size frame");
1363        // do we count this?
1364      }
1365      
1366    } else {
1367      PRINTD (DBG_WARN|DBG_VCC|DBG_RX, "no VCC for this frame (VC closed)");
1368      // do we count this?
1369    }
1370    
1371  } else {
1372    // Wait update complete ? SPONG
1373  }
1374  
1375  // RX was aborted
1376  YELLOW_LED_ON(dev);
1377  
1378  FLUSH_RX_CHANNEL (dev,rx_channel);
1379  clear_bit (rx_busy, &dev->flags);
1380  
1381  return;
1382}
1383
1384/********** interrupt handler **********/
1385
1386static irqreturn_t interrupt_handler(int irq, void *dev_id)
1387{
1388  hrz_dev *dev = dev_id;
1389  u32 int_source;
1390  unsigned int irq_ok;
1391  
1392  PRINTD (DBG_FLOW, "interrupt_handler: %p", dev_id);
1393  
1394  // definitely for us
1395  irq_ok = 0;
1396  while ((int_source = rd_regl (dev, INT_SOURCE_REG_OFF)
1397          & INTERESTING_INTERRUPTS)) {
1398    // In the interests of fairness, the handlers below are
1399    // called in sequence and without immediate return to the head of
1400    // the while loop. This is only of issue for slow hosts (or when
1401    // debugging messages are on). Really slow hosts may find a fast
1402    // sender keeps them permanently in the IRQ handler. :(
1403    
1404    // (only an issue for slow hosts) RX completion goes before
1405    // rx_data_av as the former implies rx_busy and so the latter
1406    // would just abort. If it reschedules another transfer
1407    // (continuing the same frame) then it will not clear rx_busy.
1408    
1409    // (only an issue for slow hosts) TX completion goes before RX
1410    // data available as it is a much shorter routine - there is the
1411    // chance that any further transfers it schedules will be complete
1412    // by the time of the return to the head of the while loop
1413    
1414    if (int_source & RX_BUS_MASTER_COMPLETE) {
1415      ++irq_ok;
1416      PRINTD (DBG_IRQ|DBG_BUS|DBG_RX, "rx_bus_master_complete asserted");
1417      rx_bus_master_complete_handler (dev);
1418    }
1419    if (int_source & TX_BUS_MASTER_COMPLETE) {
1420      ++irq_ok;
1421      PRINTD (DBG_IRQ|DBG_BUS|DBG_TX, "tx_bus_master_complete asserted");
1422      tx_bus_master_complete_handler (dev);
1423    }
1424    if (int_source & RX_DATA_AV) {
1425      ++irq_ok;
1426      PRINTD (DBG_IRQ|DBG_RX, "rx_data_av asserted");
1427      rx_data_av_handler (dev);
1428    }
1429  }
1430  if (irq_ok) {
1431    PRINTD (DBG_IRQ, "work done: %u", irq_ok);
1432  } else {
1433    PRINTD (DBG_IRQ|DBG_WARN, "spurious interrupt source: %#x", int_source);
1434  }
1435  
1436  PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler done: %p", dev_id);
1437  if (irq_ok)
1438        return IRQ_HANDLED;
1439  return IRQ_NONE;
1440}
1441
1442/********** housekeeping **********/
1443
1444static void do_housekeeping (unsigned long arg) {
1445  // just stats at the moment
1446  hrz_dev * dev = (hrz_dev *) arg;
1447
1448  // collect device-specific (not driver/atm-linux) stats here
1449  dev->tx_cell_count += rd_regw (dev, TX_CELL_COUNT_OFF);
1450  dev->rx_cell_count += rd_regw (dev, RX_CELL_COUNT_OFF);
1451  dev->hec_error_count += rd_regw (dev, HEC_ERROR_COUNT_OFF);
1452  dev->unassigned_cell_count += rd_regw (dev, UNASSIGNED_CELL_COUNT_OFF);
1453
1454  mod_timer (&dev->housekeeping, jiffies + HZ/10);
1455
1456  return;
1457}
1458
1459/********** find an idle channel for TX and set it up **********/
1460
1461// called with tx_busy set
1462static short setup_idle_tx_channel (hrz_dev * dev, hrz_vcc * vcc) {
1463  unsigned short idle_channels;
1464  short tx_channel = -1;
1465  unsigned int spin_count;
1466  PRINTD (DBG_FLOW|DBG_TX, "setup_idle_tx_channel %p", dev);
1467  
1468  // better would be to fail immediately, the caller can then decide whether
1469  // to wait or drop (depending on whether this is UBR etc.)
1470  spin_count = 0;
1471  while (!(idle_channels = rd_regw (dev, TX_STATUS_OFF) & IDLE_CHANNELS_MASK)) {
1472    PRINTD (DBG_TX|DBG_WARN, "waiting for idle TX channel");
1473    // delay a bit here
1474    if (++spin_count > 100) {
1475      PRINTD (DBG_TX|DBG_ERR, "spun out waiting for idle TX channel");
1476      return -EBUSY;
1477    }
1478  }
1479  
1480  // got an idle channel
1481  {
1482    // tx_idle ensures we look for idle channels in RR order
1483    int chan = dev->tx_idle;
1484    
1485    int keep_going = 1;
1486    while (keep_going) {
1487      if (idle_channels & (1<<chan)) {
1488        tx_channel = chan;
1489        keep_going = 0;
1490      }
1491      ++chan;
1492      if (chan == TX_CHANS)
1493        chan = 0;
1494    }
1495    
1496    dev->tx_idle = chan;
1497  }
1498  
1499  // set up the channel we found
1500  {
1501    // Initialise the cell header in the transmit channel descriptor
1502    // a.k.a. prepare the channel and remember that we have done so.
1503    
1504    tx_ch_desc * tx_desc = &memmap->tx_descs[tx_channel];
1505    u32 rd_ptr;
1506    u32 wr_ptr;
1507    u16 channel = vcc->channel;
1508    
1509    unsigned long flags;
1510    spin_lock_irqsave (&dev->mem_lock, flags);
1511    
1512    // Update the transmit channel record.
1513    dev->tx_channel_record[tx_channel] = channel;
1514    
1515    // xBR channel
1516    update_tx_channel_config (dev, tx_channel, RATE_TYPE_ACCESS,
1517                              vcc->tx_xbr_bits);
1518    
1519    // Update the PCR counter preload value etc.
1520    update_tx_channel_config (dev, tx_channel, PCR_TIMER_ACCESS,
1521                              vcc->tx_pcr_bits);
1522
1523#if 0
1524    if (vcc->tx_xbr_bits == VBR_RATE_TYPE) {
1525      // SCR timer
1526      update_tx_channel_config (dev, tx_channel, SCR_TIMER_ACCESS,
1527                                vcc->tx_scr_bits);
1528      
1529      // Bucket size...
1530      update_tx_channel_config (dev, tx_channel, BUCKET_CAPACITY_ACCESS,
1531                                vcc->tx_bucket_bits);
1532      
1533      // ... and fullness
1534      update_tx_channel_config (dev, tx_channel, BUCKET_FULLNESS_ACCESS,
1535                                vcc->tx_bucket_bits);
1536    }
1537#endif
1538
1539    // Initialise the read and write buffer pointers
1540    rd_ptr = rd_mem (dev, &tx_desc->rd_buf_type) & BUFFER_PTR_MASK;
1541    wr_ptr = rd_mem (dev, &tx_desc->wr_buf_type) & BUFFER_PTR_MASK;
1542    
1543    // idle TX channels should have identical pointers
1544    if (rd_ptr != wr_ptr) {
1545      PRINTD (DBG_TX|DBG_ERR, "TX buffer pointers are broken!");
1546      // spin_unlock... return -E...
1547      // I wonder if gcc would get rid of one of the pointer aliases
1548    }
1549    PRINTD (DBG_TX, "TX buffer pointers are: rd %x, wr %x.",
1550            rd_ptr, wr_ptr);
1551    
1552    switch (vcc->aal) {
1553      case aal0:
1554        PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal0");
1555        rd_ptr |= CHANNEL_TYPE_RAW_CELLS;
1556        wr_ptr |= CHANNEL_TYPE_RAW_CELLS;
1557        break;
1558      case aal34:
1559        PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal34");
1560        rd_ptr |= CHANNEL_TYPE_AAL3_4;
1561        wr_ptr |= CHANNEL_TYPE_AAL3_4;
1562        break;
1563      case aal5:
1564        rd_ptr |= CHANNEL_TYPE_AAL5;
1565        wr_ptr |= CHANNEL_TYPE_AAL5;
1566        // Initialise the CRC
1567        wr_mem (dev, &tx_desc->partial_crc, INITIAL_CRC);
1568        break;
1569    }
1570    
1571    wr_mem (dev, &tx_desc->rd_buf_type, rd_ptr);
1572    wr_mem (dev, &tx_desc->wr_buf_type, wr_ptr);
1573    
1574    // Write the Cell Header
1575    // Payload Type, CLP and GFC would go here if non-zero
1576    wr_mem (dev, &tx_desc->cell_header, channel);
1577    
1578    spin_unlock_irqrestore (&dev->mem_lock, flags);
1579  }
1580  
1581  return tx_channel;
1582}
1583
1584/********** send a frame **********/
1585
1586static int hrz_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) {
1587  unsigned int spin_count;
1588  int free_buffers;
1589  hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
1590  hrz_vcc * vcc = HRZ_VCC(atm_vcc);
1591  u16 channel = vcc->channel;
1592  
1593  u32 buffers_required;
1594  
1595  /* signed for error return */
1596  short tx_channel;
1597  
1598  PRINTD (DBG_FLOW|DBG_TX, "hrz_send vc %x data %p len %u",
1599          channel, skb->data, skb->len);
1600  
1601  dump_skb (">>>", channel, skb);
1602  
1603  if (atm_vcc->qos.txtp.traffic_class == ATM_NONE) {
1604    PRINTK (KERN_ERR, "attempt to send on RX-only VC %x", channel);
1605    hrz_kfree_skb (skb);
1606    return -EIO;
1607  }
1608  
1609  // don't understand this
1610  ATM_SKB(skb)->vcc = atm_vcc;
1611  
1612  if (skb->len > atm_vcc->qos.txtp.max_sdu) {
1613    PRINTK (KERN_ERR, "sk_buff length greater than agreed max_sdu, dropping...");
1614    hrz_kfree_skb (skb);
1615    return -EIO;
1616  }
1617  
1618  if (!channel) {
1619    PRINTD (DBG_ERR|DBG_TX, "attempt to transmit on zero (rx_)channel");
1620    hrz_kfree_skb (skb);
1621    return -EIO;
1622  }
1623  
1624#if 0
1625  {
1626    // where would be a better place for this? housekeeping?
1627    u16 status;
1628    pci_read_config_word (dev->pci_dev, PCI_STATUS, &status);
1629    if (status & PCI_STATUS_REC_MASTER_ABORT) {
1630      PRINTD (DBG_BUS|DBG_ERR, "Clearing PCI Master Abort (and cleaning up)");
1631      status &= ~PCI_STATUS_REC_MASTER_ABORT;
1632      pci_write_config_word (dev->pci_dev, PCI_STATUS, status);
1633      if (test_bit (tx_busy, &dev->flags)) {
1634        hrz_kfree_skb (dev->tx_skb);
1635        tx_release (dev);
1636      }
1637    }
1638  }
1639#endif
1640  
1641#ifdef DEBUG_HORIZON
1642  /* wey-hey! */
1643  if (channel == 1023) {
1644    unsigned int i;
1645    unsigned short d = 0;
1646    char * s = skb->data;
1647    if (*s++ == 'D') {
1648        for (i = 0; i < 4; ++i)
1649                d = (d << 4) | hex_to_bin(*s++);
1650      PRINTK (KERN_INFO, "debug bitmap is now %hx", debug = d);
1651    }
1652  }
1653#endif
1654  
1655  // wait until TX is free and grab lock
1656  if (tx_hold (dev)) {
1657    hrz_kfree_skb (skb);
1658    return -ERESTARTSYS;
1659  }
1660 
1661  // Wait for enough space to be available in transmit buffer memory.
1662  
1663  // should be number of cells needed + 2 (according to hardware docs)
1664  // = ((framelen+8)+47) / 48 + 2
1665  // = (framelen+7) / 48 + 3, hmm... faster to put addition inside XXX
1666  buffers_required = (skb->len+(ATM_AAL5_TRAILER-1)) / ATM_CELL_PAYLOAD + 3;
1667  
1668  // replace with timer and sleep, add dev->tx_buffers_queue (max 1 entry)
1669  spin_count = 0;
1670  while ((free_buffers = rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF)) < buffers_required) {
1671    PRINTD (DBG_TX, "waiting for free TX buffers, got %d of %d",
1672            free_buffers, buffers_required);
1673    // what is the appropriate delay? implement a timeout? (depending on line speed?)
1674    // mdelay (1);
1675    // what happens if we kill (current_pid, SIGKILL) ?
1676    schedule();
1677    if (++spin_count > 1000) {
1678      PRINTD (DBG_TX|DBG_ERR, "spun out waiting for tx buffers, got %d of %d",
1679              free_buffers, buffers_required);
1680      tx_release (dev);
1681      hrz_kfree_skb (skb);
1682      return -ERESTARTSYS;
1683    }
1684  }
1685  
1686  // Select a channel to transmit the frame on.
1687  if (channel == dev->last_vc) {
1688    PRINTD (DBG_TX, "last vc hack: hit");
1689    tx_channel = dev->tx_last;
1690  } else {
1691    PRINTD (DBG_TX, "last vc hack: miss");
1692    // Are we currently transmitting this VC on one of the channels?
1693    for (tx_channel = 0; tx_channel < TX_CHANS; ++tx_channel)
1694      if (dev->tx_channel_record[tx_channel] == channel) {
1695        PRINTD (DBG_TX, "vc already on channel: hit");
1696        break;
1697      }
1698    if (tx_channel == TX_CHANS) { 
1699      PRINTD (DBG_TX, "vc already on channel: miss");
1700      // Find and set up an idle channel.
1701      tx_channel = setup_idle_tx_channel (dev, vcc);
1702      if (tx_channel < 0) {
1703        PRINTD (DBG_TX|DBG_ERR, "failed to get channel");
1704        tx_release (dev);
1705        return tx_channel;
1706      }
1707    }
1708    
1709    PRINTD (DBG_TX, "got channel");
1710    SELECT_TX_CHANNEL(dev, tx_channel);
1711    
1712    dev->last_vc = channel;
1713    dev->tx_last = tx_channel;
1714  }
1715  
1716  PRINTD (DBG_TX, "using channel %u", tx_channel);
1717  
1718  YELLOW_LED_OFF(dev);
1719  
1720  // TX start transfer
1721  
1722  {
1723    unsigned int tx_len = skb->len;
1724    unsigned int tx_iovcnt = skb_shinfo(skb)->nr_frags;
1725    // remember this so we can free it later
1726    dev->tx_skb = skb;
1727    
1728    if (tx_iovcnt) {
1729      // scatter gather transfer
1730      dev->tx_regions = tx_iovcnt;
1731      dev->tx_iovec = NULL;             /* @@@ needs rewritten */
1732      dev->tx_bytes = 0;
1733      PRINTD (DBG_TX|DBG_BUS, "TX start scatter-gather transfer (iovec %p, len %d)",
1734              skb->data, tx_len);
1735      tx_release (dev);
1736      hrz_kfree_skb (skb);
1737      return -EIO;
1738    } else {
1739      // simple transfer
1740      dev->tx_regions = 0;
1741      dev->tx_iovec = NULL;
1742      dev->tx_bytes = tx_len;
1743      dev->tx_addr = skb->data;
1744      PRINTD (DBG_TX|DBG_BUS, "TX start simple transfer (addr %p, len %d)",
1745              skb->data, tx_len);
1746    }
1747    
1748    // and do the business
1749    tx_schedule (dev, 0);
1750    
1751  }
1752  
1753  return 0;
1754}
1755
1756/********** reset a card **********/
1757
1758static void hrz_reset (const hrz_dev * dev) {
1759  u32 control_0_reg = rd_regl (dev, CONTROL_0_REG);
1760  
1761  // why not set RESET_HORIZON to one and wait for the card to
1762  // reassert that bit as zero? Like so:
1763  control_0_reg = control_0_reg & RESET_HORIZON;
1764  wr_regl (dev, CONTROL_0_REG, control_0_reg);
1765  while (control_0_reg & RESET_HORIZON)
1766    control_0_reg = rd_regl (dev, CONTROL_0_REG);
1767  
1768  // old reset code retained:
1769  wr_regl (dev, CONTROL_0_REG, control_0_reg |
1770           RESET_ATM | RESET_RX | RESET_TX | RESET_HOST);
1771  // just guessing here
1772  udelay (1000);
1773  
1774  wr_regl (dev, CONTROL_0_REG, control_0_reg);
1775}
1776
1777/********** read the burnt in address **********/
1778
1779static void WRITE_IT_WAIT (const hrz_dev *dev, u32 ctrl)
1780{
1781        wr_regl (dev, CONTROL_0_REG, ctrl);
1782        udelay (5);
1783}
1784  
1785static void CLOCK_IT (const hrz_dev *dev, u32 ctrl)
1786{
1787        // DI must be valid around rising SK edge
1788        WRITE_IT_WAIT(dev, ctrl & ~SEEPROM_SK);
1789        WRITE_IT_WAIT(dev, ctrl | SEEPROM_SK);
1790}
1791
1792static u16 __devinit read_bia (const hrz_dev * dev, u16 addr)
1793{
1794  u32 ctrl = rd_regl (dev, CONTROL_0_REG);
1795  
1796  const unsigned int addr_bits = 6;
1797  const unsigned int data_bits = 16;
1798  
1799  unsigned int i;
1800  
1801  u16 res;
1802  
1803  ctrl &= ~(SEEPROM_CS | SEEPROM_SK | SEEPROM_DI);
1804  WRITE_IT_WAIT(dev, ctrl);
1805  
1806  // wake Serial EEPROM and send 110 (READ) command
1807  ctrl |=  (SEEPROM_CS | SEEPROM_DI);
1808  CLOCK_IT(dev, ctrl);
1809  
1810  ctrl |= SEEPROM_DI;
1811  CLOCK_IT(dev, ctrl);
1812  
1813  ctrl &= ~SEEPROM_DI;
1814  CLOCK_IT(dev, ctrl);
1815  
1816  for (i=0; i<addr_bits; i++) {
1817    if (addr & (1 << (addr_bits-1)))
1818      ctrl |= SEEPROM_DI;
1819    else
1820      ctrl &= ~SEEPROM_DI;
1821    
1822    CLOCK_IT(dev, ctrl);
1823    
1824    addr = addr << 1;
1825  }
1826  
1827  // we could check that we have DO = 0 here
1828  ctrl &= ~SEEPROM_DI;
1829  
1830  res = 0;
1831  for (i=0;i<data_bits;i++) {
1832    res = res >> 1;
1833    
1834    CLOCK_IT(dev, ctrl);
1835    
1836    if (rd_regl (dev, CONTROL_0_REG) & SEEPROM_DO)
1837      res |= (1 << (data_bits-1));
1838  }
1839  
1840  ctrl &= ~(SEEPROM_SK | SEEPROM_CS);
1841  WRITE_IT_WAIT(dev, ctrl);
1842  
1843  return res;
1844}
1845
1846/********** initialise a card **********/
1847
1848static int __devinit hrz_init (hrz_dev * dev) {
1849  int onefivefive;
1850  
1851  u16 chan;
1852  
1853  int buff_count;
1854  
1855  HDW * mem;
1856  
1857  cell_buf * tx_desc;
1858  cell_buf * rx_desc;
1859  
1860  u32 ctrl;
1861  
1862  ctrl = rd_regl (dev, CONTROL_0_REG);
1863  PRINTD (DBG_INFO, "ctrl0reg is %#x", ctrl);
1864  onefivefive = ctrl & ATM_LAYER_STATUS;
1865  
1866  if (onefivefive)
1867    printk (DEV_LABEL ": Horizon Ultra (at 155.52 MBps)");
1868  else
1869    printk (DEV_LABEL ": Horizon (at 25 MBps)");
1870  
1871  printk (":");
1872  // Reset the card to get everything in a known state
1873  
1874  printk (" reset");
1875  hrz_reset (dev);
1876  
1877  // Clear all the buffer memory
1878  
1879  printk (" clearing memory");
1880  
1881  for (mem = (HDW *) memmap; mem < (HDW *) (memmap + 1); ++mem)
1882    wr_mem (dev, mem, 0);
1883  
1884  printk (" tx channels");
1885  
1886  // All transmit eight channels are set up as AAL5 ABR channels with
1887  // a 16us cell spacing. Why?
1888  
1889  // Channel 0 gets the free buffer at 100h, channel 1 gets the free
1890  // buffer at 110h etc.
1891  
1892  for (chan = 0; chan < TX_CHANS; ++chan) {
1893    tx_ch_desc * tx_desc = &memmap->tx_descs[chan];
1894    cell_buf * buf = &memmap->inittxbufs[chan];
1895    
1896    // initialise the read and write buffer pointers
1897    wr_mem (dev, &tx_desc->rd_buf_type, BUF_PTR(buf));
1898    wr_mem (dev, &tx_desc->wr_buf_type, BUF_PTR(buf));
1899    
1900    // set the status of the initial buffers to empty
1901    wr_mem (dev, &buf->next, BUFF_STATUS_EMPTY);
1902  }
1903  
1904  // Use space bufn3 at the moment for tx buffers
1905  
1906  printk (" tx buffers");
1907  
1908  tx_desc = memmap->bufn3;
1909  
1910  wr_mem (dev, &memmap->txfreebufstart.next, BUF_PTR(tx_desc) | BUFF_STATUS_EMPTY);
1911  
1912  for (buff_count = 0; buff_count < BUFN3_SIZE-1; buff_count++) {
1913    wr_mem (dev, &tx_desc->next, BUF_PTR(tx_desc+1) | BUFF_STATUS_EMPTY);
1914    tx_desc++;
1915  }
1916  
1917  wr_mem (dev, &tx_desc->next, BUF_PTR(&memmap->txfreebufend) | BUFF_STATUS_EMPTY);
1918  
1919  // Initialise the transmit free buffer count
1920  wr_regw (dev, TX_FREE_BUFFER_COUNT_OFF, BUFN3_SIZE);
1921  
1922  printk (" rx channels");
1923  
1924  // Initialise all of the receive channels to be AAL5 disabled with
1925  // an interrupt threshold of 0
1926  
1927  for (chan = 0; chan < RX_CHANS; ++chan) {
1928    rx_ch_desc * rx_desc = &memmap->rx_descs[chan];
1929    
1930    wr_mem (dev, &rx_desc->wr_buf_type, CHANNEL_TYPE_AAL5 | RX_CHANNEL_DISABLED);
1931  }
1932  
1933  printk (" rx buffers");
1934  
1935  // Use space bufn4 at the moment for rx buffers
1936  
1937  rx_desc = memmap->bufn4;
1938  
1939  wr_mem (dev, &memmap->rxfreebufstart.next, BUF_PTR(rx_desc) | BUFF_STATUS_EMPTY);
1940  
1941  for (buff_count = 0; buff_count < BUFN4_SIZE-1; buff_count++) {
1942    wr_mem (dev, &rx_desc->next, BUF_PTR(rx_desc+1) | BUFF_STATUS_EMPTY);
1943    
1944    rx_desc++;
1945  }
1946  
1947  wr_mem (dev, &rx_desc->next, BUF_PTR(&memmap->rxfreebufend) | BUFF_STATUS_EMPTY);
1948  
1949  // Initialise the receive free buffer count
1950  wr_regw (dev, RX_FREE_BUFFER_COUNT_OFF, BUFN4_SIZE);
1951  
1952  // Initialize Horizons registers
1953  
1954  // TX config
1955  wr_regw (dev, TX_CONFIG_OFF,
1956           ABR_ROUND_ROBIN | TX_NORMAL_OPERATION | DRVR_DRVRBAR_ENABLE);
1957  
1958  // RX config. Use 10-x VC bits, x VP bits, non user cells in channel 0.
1959  wr_regw (dev, RX_CONFIG_OFF,
1960           DISCARD_UNUSED_VPI_VCI_BITS_SET | NON_USER_CELLS_IN_ONE_CHANNEL | vpi_bits);
1961  
1962  // RX line config
1963  wr_regw (dev, RX_LINE_CONFIG_OFF,
1964           LOCK_DETECT_ENABLE | FREQUENCY_DETECT_ENABLE | GXTALOUT_SELECT_DIV4);
1965  
1966  // Set the max AAL5 cell count to be just enough to contain the
1967  // largest AAL5 frame that the user wants to receive
1968  wr_regw (dev, MAX_AAL5_CELL_COUNT_OFF,
1969           DIV_ROUND_UP(max_rx_size + ATM_AAL5_TRAILER, ATM_CELL_PAYLOAD));
1970  
1971  // Enable receive
1972  wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
1973  
1974  printk (" control");
1975  
1976  // Drive the OE of the LEDs then turn the green LED on
1977  ctrl |= GREEN_LED_OE | YELLOW_LED_OE | GREEN_LED | YELLOW_LED;
1978  wr_regl (dev, CONTROL_0_REG, ctrl);
1979  
1980  // Test for a 155-capable card
1981  
1982  if (onefivefive) {
1983    // Select 155 mode... make this a choice (or: how do we detect
1984    // external line speed and switch?)
1985    ctrl |= ATM_LAYER_SELECT;
1986    wr_regl (dev, CONTROL_0_REG, ctrl);
1987    
1988    // test SUNI-lite vs SAMBA
1989    
1990    // Register 0x00 in the SUNI will have some of bits 3-7 set, and
1991    // they will always be zero for the SAMBA.  Ha!  Bloody hardware
1992    // engineers.  It'll never work.
1993    
1994    if (rd_framer (dev, 0) & 0x00f0) {
1995      // SUNI
1996      printk (" SUNI");
1997      
1998      // Reset, just in case
1999      wr_framer (dev, 0x00, 0x0080);
2000      wr_framer (dev, 0x00, 0x0000);
2001      
2002      // Configure transmit FIFO
2003      wr_framer (dev, 0x63, rd_framer (dev, 0x63) | 0x0002);
2004      
2005      // Set line timed mode
2006      wr_framer (dev, 0x05, rd_framer (dev, 0x05) | 0x0001);
2007    } else {
2008      // SAMBA
2009      printk (" SAMBA");
2010      
2011      // Reset, just in case
2012      wr_framer (dev, 0, rd_framer (dev, 0) | 0x0001);
2013      wr_framer (dev, 0, rd_framer (dev, 0) &~ 0x0001);
2014      
2015      // Turn off diagnostic loopback and enable line-timed mode
2016      wr_framer (dev, 0, 0x0002);
2017      
2018      // Turn on transmit outputs
2019      wr_framer (dev, 2, 0x0B80);
2020    }
2021  } else {
2022    // Select 25 mode
2023    ctrl &= ~ATM_LAYER_SELECT;
2024    
2025    // Madge B154 setup
2026    // none required?
2027  }
2028  
2029  printk (" LEDs");
2030  
2031  GREEN_LED_ON(dev);
2032  YELLOW_LED_ON(dev);
2033  
2034  printk (" ESI=");
2035  
2036  {
2037    u16 b = 0;
2038    int i;
2039    u8 * esi = dev->atm_dev->esi;
2040    
2041    // in the card I have, EEPROM
2042    // addresses 0, 1, 2 contain 0
2043    // addresess 5, 6 etc. contain ffff
2044    // NB: Madge prefix is 00 00 f6 (which is 00 00 6f in Ethernet bit order)
2045    // the read_bia routine gets the BIA in Ethernet bit order
2046    
2047    for (i=0; i < ESI_LEN; ++i) {
2048      if (i % 2 == 0)
2049        b = read_bia (dev, i/2 + 2);
2050      else
2051        b = b >> 8;
2052      esi[i] = b & 0xFF;
2053      printk ("%02x", esi[i]);
2054    }
2055  }
2056  
2057  // Enable RX_Q and ?X_COMPLETE interrupts only
2058  wr_regl (dev, INT_ENABLE_REG_OFF, INTERESTING_INTERRUPTS);
2059  printk (" IRQ on");
2060  
2061  printk (".\n");
2062  
2063  return onefivefive;
2064}
2065
2066/********** check max_sdu **********/
2067
2068static int check_max_sdu (hrz_aal aal, struct atm_trafprm * tp, unsigned int max_frame_size) {
2069  PRINTD (DBG_FLOW|DBG_QOS, "check_max_sdu");
2070  
2071  switch (aal) {
2072    case aal0:
2073      if (!(tp->max_sdu)) {
2074        PRINTD (DBG_QOS, "defaulting max_sdu");
2075        tp->max_sdu = ATM_AAL0_SDU;
2076      } else if (tp->max_sdu != ATM_AAL0_SDU) {
2077        PRINTD (DBG_QOS|DBG_ERR, "rejecting max_sdu");
2078        return -EINVAL;
2079      }
2080      break;
2081    case aal34:
2082      if (tp->max_sdu == 0 || tp->max_sdu > ATM_MAX_AAL34_PDU) {
2083        PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2084        tp->max_sdu = ATM_MAX_AAL34_PDU;
2085      }
2086      break;
2087    case aal5:
2088      if (tp->max_sdu == 0 || tp->max_sdu > max_frame_size) {
2089        PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2090        tp->max_sdu = max_frame_size;
2091      }
2092      break;
2093  }
2094  return 0;
2095}
2096
2097/********** check pcr **********/
2098
2099// something like this should be part of ATM Linux
2100static int atm_pcr_check (struct atm_trafprm * tp, unsigned int pcr) {
2101  // we are assuming non-UBR, and non-special values of pcr
2102  if (tp->min_pcr == ATM_MAX_PCR)
2103    PRINTD (DBG_QOS, "luser gave min_pcr = ATM_MAX_PCR");
2104  else if (tp->min_pcr < 0)
2105    PRINTD (DBG_QOS, "luser gave negative min_pcr");
2106  else if (tp->min_pcr && tp->min_pcr > pcr)
2107    PRINTD (DBG_QOS, "pcr less than min_pcr");
2108  else
2109    // !! max_pcr = UNSPEC (0) is equivalent to max_pcr = MAX (-1)
2110    // easier to #define ATM_MAX_PCR 0 and have all rates unsigned?
2111    // [this would get rid of next two conditionals]
2112    if ((0) && tp->max_pcr == ATM_MAX_PCR)
2113      PRINTD (DBG_QOS, "luser gave max_pcr = ATM_MAX_PCR");
2114    else if ((tp->max_pcr != ATM_MAX_PCR) && tp->max_pcr < 0)
2115      PRINTD (DBG_QOS, "luser gave negative max_pcr");
2116    else if (tp->max_pcr && tp->max_pcr != ATM_MAX_PCR && tp->max_pcr < pcr)
2117      PRINTD (DBG_QOS, "pcr greater than max_pcr");
2118    else {
2119      // each limit unspecified or not violated
2120      PRINTD (DBG_QOS, "xBR(pcr) OK");
2121      return 0;
2122    }
2123  PRINTD (DBG_QOS, "pcr=%u, tp: min_pcr=%d, pcr=%d, max_pcr=%d",
2124          pcr, tp->min_pcr, tp->pcr, tp->max_pcr);
2125  return -EINVAL;
2126}
2127
2128/********** open VC **********/
2129
2130static int hrz_open (struct atm_vcc *atm_vcc)
2131{
2132  int error;
2133  u16 channel;
2134  
2135  struct atm_qos * qos;
2136  struct atm_trafprm * txtp;
2137  struct atm_trafprm * rxtp;
2138  
2139  hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2140  hrz_vcc vcc;
2141  hrz_vcc * vccp; // allocated late
2142  short vpi = atm_vcc->vpi;
2143  int vci = atm_vcc->vci;
2144  PRINTD (DBG_FLOW|DBG_VCC, "hrz_open %x %x", vpi, vci);
2145  
2146#ifdef ATM_VPI_UNSPEC
2147  // UNSPEC is deprecated, remove this code eventually
2148  if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) {
2149    PRINTK (KERN_WARNING, "rejecting open with unspecified VPI/VCI (deprecated)");
2150    return -EINVAL;
2151  }
2152#endif
2153  
2154  error = vpivci_to_channel (&channel, vpi, vci);
2155  if (error) {
2156    PRINTD (DBG_WARN|DBG_VCC, "VPI/VCI out of range: %hd/%d", vpi, vci);
2157    return error;
2158  }
2159  
2160  vcc.channel = channel;
2161  // max speed for the moment
2162  vcc.tx_rate = 0x0;
2163  
2164  qos = &atm_vcc->qos;
2165  
2166  // check AAL and remember it
2167  switch (qos->aal) {
2168    case ATM_AAL0:
2169      // we would if it were 48 bytes and not 52!
2170      PRINTD (DBG_QOS|DBG_VCC, "AAL0");
2171      vcc.aal = aal0;
2172      break;
2173    case ATM_AAL34:
2174      // we would if I knew how do the SAR!
2175      PRINTD (DBG_QOS|DBG_VCC, "AAL3/4");
2176      vcc.aal = aal34;
2177      break;
2178    case ATM_AAL5:
2179      PRINTD (DBG_QOS|DBG_VCC, "AAL5");
2180      vcc.aal = aal5;
2181      break;
2182    default:
2183      PRINTD (DBG_QOS|DBG_VCC, "Bad AAL!");
2184      return -EINVAL;
2185  }
2186  
2187  // TX traffic parameters
2188  
2189  // there are two, interrelated problems here: 1. the reservation of
2190  // PCR is not a binary choice, we are given bounds and/or a
2191  // desirable value; 2. the device is only capable of certain values,
2192  // most of which are not integers. It is almost certainly acceptable
2193  // to be off by a maximum of 1 to 10 cps.
2194  
2195  // Pragmatic choice: always store an integral PCR as that which has
2196  // been allocated, even if we allocate a little (or a lot) less,
2197  // after rounding. The actual allocation depends on what we can
2198  // manage with our rate selection algorithm. The rate selection
2199  // algorithm is given an integral PCR and a tolerance and told
2200  // whether it should round the value up or down if the tolerance is
2201  // exceeded; it returns: a) the actual rate selected (rounded up to
2202  // the nearest integer), b) a bit pattern to feed to the timer
2203  // register, and c) a failure value if no applicable rate exists.
2204  
2205  // Part of the job is done by atm_pcr_goal which gives us a PCR
2206  // specification which says: EITHER grab the maximum available PCR
2207  // (and perhaps a lower bound which we musn't pass), OR grab this
2208  // amount, rounding down if you have to (and perhaps a lower bound
2209  // which we musn't pass) OR grab this amount, rounding up if you
2210  // have to (and perhaps an upper bound which we musn't pass). If any
2211  // bounds ARE passed we fail. Note that rounding is only rounding to
2212  // match device limitations, we do not round down to satisfy
2213  // bandwidth availability even if this would not violate any given
2214  // lower bound.
2215  
2216  // Note: telephony = 64kb/s = 48 byte cell payload @ 500/3 cells/s
2217  // (say) so this is not even a binary fixpoint cell rate (but this
2218  // device can do it). To avoid this sort of hassle we use a
2219  // tolerance parameter (currently fixed at 10 cps).
2220  
2221  PRINTD (DBG_QOS, "TX:");
2222  
2223  txtp = &qos->txtp;
2224  
2225  // set up defaults for no traffic
2226  vcc.tx_rate = 0;
2227  // who knows what would actually happen if you try and send on this?
2228  vcc.tx_xbr_bits = IDLE_RATE_TYPE;
2229  vcc.tx_pcr_bits = CLOCK_DISABLE;
2230#if 0
2231  vcc.tx_scr_bits = CLOCK_DISABLE;
2232  vcc.tx_bucket_bits = 0;
2233#endif
2234  
2235  if (txtp->traffic_class != ATM_NONE) {
2236    error = check_max_sdu (vcc.aal, txtp, max_tx_size);
2237    if (error) {
2238      PRINTD (DBG_QOS, "TX max_sdu check failed");
2239      return error;
2240    }
2241    
2242    switch (txtp->traffic_class) {
2243      case ATM_UBR: {
2244        // we take "the PCR" as a rate-cap
2245        // not reserved
2246        vcc.tx_rate = 0;
2247        make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, NULL);
2248        vcc.tx_xbr_bits = ABR_RATE_TYPE;
2249        break;
2250      }
2251#if 0
2252      case ATM_ABR: {
2253        // reserve min, allow up to max
2254        vcc.tx_rate = 0; // ?
2255        make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0);
2256        vcc.tx_xbr_bits = ABR_RATE_TYPE;
2257        break;
2258      }
2259#endif
2260      case ATM_CBR: {
2261        int pcr = atm_pcr_goal (txtp);
2262        rounding r;
2263        if (!pcr) {
2264          // down vs. up, remaining bandwidth vs. unlimited bandwidth!!
2265          // should really have: once someone gets unlimited bandwidth
2266          // that no more non-UBR channels can be opened until the
2267          // unlimited one closes?? For the moment, round_down means
2268          // greedy people actually get something and not nothing
2269          r = round_down;
2270          // slight race (no locking) here so we may get -EAGAIN
2271          // later; the greedy bastards would deserve it :)
2272          PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2273          pcr = dev->tx_avail;
2274        } else if (pcr < 0) {
2275          r = round_down;
2276          pcr = -pcr;
2277        } else {
2278          r = round_up;
2279        }
2280        error = make_rate_with_tolerance (dev, pcr, r, 10,
2281                                          &vcc.tx_pcr_bits, &vcc.tx_rate);
2282        if (error) {
2283          PRINTD (DBG_QOS, "could not make rate from TX PCR");
2284          return error;
2285        }
2286        // not really clear what further checking is needed
2287        error = atm_pcr_check (txtp, vcc.tx_rate);
2288        if (error) {
2289          PRINTD (DBG_QOS, "TX PCR failed consistency check");
2290          return error;
2291        }
2292        vcc.tx_xbr_bits = CBR_RATE_TYPE;
2293        break;
2294      }
2295#if 0
2296      case ATM_VBR: {
2297        int pcr = atm_pcr_goal (txtp);
2298        // int scr = atm_scr_goal (txtp);
2299        int scr = pcr/2; // just for fun
2300        unsigned int mbs = 60; // just for fun
2301        rounding pr;
2302        rounding sr;
2303        unsigned int bucket;
2304        if (!pcr) {
2305          pr = round_nearest;
2306          pcr = 1<<30;
2307        } else if (pcr < 0) {
2308          pr = round_down;
2309          pcr = -pcr;
2310        } else {
2311          pr = round_up;
2312        }
2313        error = make_rate_with_tolerance (dev, pcr, pr, 10,
2314                                          &vcc.tx_pcr_bits, 0);
2315        if (!scr) {
2316          // see comments for PCR with CBR above
2317          sr = round_down;
2318          // slight race (no locking) here so we may get -EAGAIN
2319          // later; the greedy bastards would deserve it :)
2320          PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2321          scr = dev->tx_avail;
2322        } else if (scr < 0) {
2323          sr = round_down;
2324          scr = -scr;
2325        } else {
2326          sr = round_up;
2327        }
2328        error = make_rate_with_tolerance (dev, scr, sr, 10,
2329                                          &vcc.tx_scr_bits, &vcc.tx_rate);
2330        if (error) {
2331          PRINTD (DBG_QOS, "could not make rate from TX SCR");
2332          return error;
2333        }
2334        // not really clear what further checking is needed
2335        // error = atm_scr_check (txtp, vcc.tx_rate);
2336        if (error) {
2337          PRINTD (DBG_QOS, "TX SCR failed consistency check");
2338          return error;
2339        }
2340        // bucket calculations (from a piece of paper...) cell bucket
2341        // capacity must be largest integer smaller than m(p-s)/p + 1
2342        // where m = max burst size, p = pcr, s = scr
2343        bucket = mbs*(pcr-scr)/pcr;
2344        if (bucket*pcr != mbs*(pcr-scr))
2345          bucket += 1;
2346        if (bucket > BUCKET_MAX_SIZE) {
2347          PRINTD (DBG_QOS, "shrinking bucket from %u to %u",
2348                  bucket, BUCKET_MAX_SIZE);
2349          bucket = BUCKET_MAX_SIZE;
2350        }
2351        vcc.tx_xbr_bits = VBR_RATE_TYPE;
2352        vcc.tx_bucket_bits = bucket;
2353        break;
2354      }
2355#endif
2356      default: {
2357        PRINTD (DBG_QOS, "unsupported TX traffic class");
2358        return -EINVAL;
2359      }
2360    }
2361  }
2362  
2363  // RX traffic parameters
2364  
2365  PRINTD (DBG_QOS, "RX:");
2366  
2367  rxtp = &qos->rxtp;
2368  
2369  // set up defaults for no traffic
2370  vcc.rx_rate = 0;
2371  
2372  if (rxtp->traffic_class != ATM_NONE) {
2373    error = check_max_sdu (vcc.aal, rxtp, max_rx_size);
2374    if (error) {
2375      PRINTD (DBG_QOS, "RX max_sdu check failed");
2376      return error;
2377    }
2378    switch (rxtp->traffic_class) {
2379      case ATM_UBR: {
2380        // not reserved
2381        break;
2382      }
2383#if 0
2384      case ATM_ABR: {
2385        // reserve min
2386        vcc.rx_rate = 0; // ?
2387        break;
2388      }
2389#endif
2390      case ATM_CBR: {
2391        int pcr = atm_pcr_goal (rxtp);
2392        if (!pcr) {
2393          // slight race (no locking) here so we may get -EAGAIN
2394          // later; the greedy bastards would deserve it :)
2395          PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2396          pcr = dev->rx_avail;
2397        } else if (pcr < 0) {
2398          pcr = -pcr;
2399        }
2400        vcc.rx_rate = pcr;
2401        // not really clear what further checking is needed
2402        error = atm_pcr_check (rxtp, vcc.rx_rate);
2403        if (error) {
2404          PRINTD (DBG_QOS, "RX PCR failed consistency check");
2405          return error;
2406        }
2407        break;
2408      }
2409#if 0
2410      case ATM_VBR: {
2411        // int scr = atm_scr_goal (rxtp);
2412        int scr = 1<<16; // just for fun
2413        if (!scr) {
2414          // slight race (no locking) here so we may get -EAGAIN
2415          // later; the greedy bastards would deserve it :)
2416          PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2417          scr = dev->rx_avail;
2418        } else if (scr < 0) {
2419          scr = -scr;
2420        }
2421        vcc.rx_rate = scr;
2422        // not really clear what further checking is needed
2423        // error = atm_scr_check (rxtp, vcc.rx_rate);
2424        if (error) {
2425          PRINTD (DBG_QOS, "RX SCR failed consistency check");
2426          return error;
2427        }
2428        break;
2429      }
2430#endif
2431      default: {
2432        PRINTD (DBG_QOS, "unsupported RX traffic class");
2433        return -EINVAL;
2434      }
2435    }
2436  }
2437  
2438  
2439  // late abort useful for diagnostics
2440  if (vcc.aal != aal5) {
2441    PRINTD (DBG_QOS, "AAL not supported");
2442    return -EINVAL;
2443  }
2444  
2445  // get space for our vcc stuff and copy parameters into it
2446  vccp = kmalloc (sizeof(hrz_vcc), GFP_KERNEL);
2447  if (!vccp) {
2448    PRINTK (KERN_ERR, "out of memory!");
2449    return -ENOMEM;
2450  }
2451  *vccp = vcc;
2452  
2453  // clear error and grab cell rate resource lock
2454  error = 0;
2455  spin_lock (&dev->rate_lock);
2456  
2457  if (vcc.tx_rate > dev->tx_avail) {
2458    PRINTD (DBG_QOS, "not enough TX PCR left");
2459    error = -EAGAIN;
2460  }
2461  
2462  if (vcc.rx_rate > dev->rx_avail) {
2463    PRINTD (DBG_QOS, "not enough RX PCR left");
2464    error = -EAGAIN;
2465  }
2466  
2467  if (!error) {
2468    // really consume cell rates
2469    dev->tx_avail -= vcc.tx_rate;
2470    dev->rx_avail -= vcc.rx_rate;
2471    PRINTD (DBG_QOS|DBG_VCC, "reserving %u TX PCR and %u RX PCR",
2472            vcc.tx_rate, vcc.rx_rate);
2473  }
2474  
2475  // release lock and exit on error
2476  spin_unlock (&dev->rate_lock);
2477  if (error) {
2478    PRINTD (DBG_QOS|DBG_VCC, "insufficient cell rate resources");
2479    kfree (vccp);
2480    return error;
2481  }
2482  
2483  // this is "immediately before allocating the connection identifier
2484  // in hardware" - so long as the next call does not fail :)
2485  set_bit(ATM_VF_ADDR,&atm_vcc->flags);
2486  
2487  // any errors here are very serious and should never occur
2488  
2489  if (rxtp->traffic_class != ATM_NONE) {
2490    if (dev->rxer[channel]) {
2491      PRINTD (DBG_ERR|DBG_VCC, "VC already open for RX");
2492      error = -EBUSY;
2493    }
2494    if (!error)
2495      error = hrz_open_rx (dev, channel);
2496    if (error) {
2497      kfree (vccp);
2498      return error;
2499    }
2500    // this link allows RX frames through
2501    dev->rxer[channel] = atm_vcc;
2502  }
2503  
2504  // success, set elements of atm_vcc
2505  atm_vcc->dev_data = (void *) vccp;
2506  
2507  // indicate readiness
2508  set_bit(ATM_VF_READY,&atm_vcc->flags);
2509  
2510  return 0;
2511}
2512
2513/********** close VC **********/
2514
2515static void hrz_close (struct atm_vcc * atm_vcc) {
2516  hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2517  hrz_vcc * vcc = HRZ_VCC(atm_vcc);
2518  u16 channel = vcc->channel;
2519  PRINTD (DBG_VCC|DBG_FLOW, "hrz_close");
2520  
2521  // indicate unreadiness
2522  clear_bit(ATM_VF_READY,&atm_vcc->flags);
2523
2524  if (atm_vcc->qos.txtp.traffic_class != ATM_NONE) {
2525    unsigned int i;
2526    
2527    // let any TX on this channel that has started complete
2528    // no restart, just keep trying
2529    while (tx_hold (dev))
2530      ;
2531    // remove record of any tx_channel having been setup for this channel
2532    for (i = 0; i < TX_CHANS; ++i)
2533      if (dev->tx_channel_record[i] == channel) {
2534        dev->tx_channel_record[i] = -1;
2535        break;
2536      }
2537    if (dev->last_vc == channel)
2538      dev->tx_last = -1;
2539    tx_release (dev);
2540  }
2541
2542  if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
2543    // disable RXing - it tries quite hard
2544    hrz_close_rx (dev, channel);
2545    // forget the vcc - no more skbs will be pushed
2546    if (atm_vcc != dev->rxer[channel])
2547      PRINTK (KERN_ERR, "%s atm_vcc=%p rxer[channel]=%p",
2548              "arghhh! we're going to die!",
2549              atm_vcc, dev->rxer[channel]);
2550    dev->rxer[channel] = NULL;
2551  }
2552  
2553  // atomically release our rate reservation
2554  spin_lock (&dev->rate_lock);
2555  PRINTD (DBG_QOS|DBG_VCC, "releasing %u TX PCR and %u RX PCR",
2556          vcc->tx_rate, vcc->rx_rate);
2557  dev->tx_avail += vcc->tx_rate;
2558  dev->rx_avail += vcc->rx_rate;
2559  spin_unlock (&dev->rate_lock);
2560  
2561  // free our structure
2562  kfree (vcc);
2563  // say the VPI/VCI is free again
2564  clear_bit(ATM_VF_ADDR,&atm_vcc->flags);
2565}
2566
2567#if 0
2568static int hrz_getsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2569                           void *optval, int optlen) {
2570  hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2571  PRINTD (DBG_FLOW|DBG_VCC, "hrz_getsockopt");
2572  switch (level) {
2573    case SOL_SOCKET:
2574      switch (optname) {
2575//      case SO_BCTXOPT:
2576//        break;
2577//      case SO_BCRXOPT:
2578//        break;
2579        default:
2580          return -ENOPROTOOPT;
2581      };
2582      break;
2583  }
2584  return -EINVAL;
2585}
2586
2587static int hrz_setsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2588                           void *optval, unsigned int optlen) {
2589  hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2590  PRINTD (DBG_FLOW|DBG_VCC, "hrz_setsockopt");
2591  switch (level) {
2592    case SOL_SOCKET:
2593      switch (optname) {
2594//      case SO_BCTXOPT:
2595//        break;
2596//      case SO_BCRXOPT:
2597//        break;
2598        default:
2599          return -ENOPROTOOPT;
2600      };
2601      break;
2602  }
2603  return -EINVAL;
2604}
2605#endif
2606
2607#if 0
2608static int hrz_ioctl (struct atm_dev * atm_dev, unsigned int cmd, void *arg) {
2609  hrz_dev * dev = HRZ_DEV(atm_dev);
2610  PRINTD (DBG_FLOW, "hrz_ioctl");
2611  return -1;
2612}
2613
2614unsigned char hrz_phy_get (struct atm_dev * atm_dev, unsigned long addr) {
2615  hrz_dev * dev = HRZ_DEV(atm_dev);
2616  PRINTD (DBG_FLOW, "hrz_phy_get");
2617  return 0;
2618}
2619
2620static void hrz_phy_put (struct atm_dev * atm_dev, unsigned char value,
2621                         unsigned long addr) {
2622  hrz_dev * dev = HRZ_DEV(atm_dev);
2623  PRINTD (DBG_FLOW, "hrz_phy_put");
2624}
2625
2626static int hrz_change_qos (struct atm_vcc * atm_vcc, struct atm_qos *qos, int flgs) {
2627  hrz_dev * dev = HRZ_DEV(vcc->dev);
2628  PRINTD (DBG_FLOW, "hrz_change_qos");
2629  return -1;
2630}
2631#endif
2632
2633/********** proc file contents **********/
2634
2635static int hrz_proc_read (struct atm_dev * atm_dev, loff_t * pos, char * page) {
2636  hrz_dev * dev = HRZ_DEV(atm_dev);
2637  int left = *pos;
2638  PRINTD (DBG_FLOW, "hrz_proc_read");
2639  
2640  /* more diagnostics here? */
2641  
2642#if 0
2643  if (!left--) {
2644    unsigned int count = sprintf (page, "vbr buckets:");
2645    unsigned int i;
2646    for (i = 0; i < TX_CHANS; ++i)
2647      count += sprintf (page, " %u/%u",
2648                        query_tx_channel_config (dev, i, BUCKET_FULLNESS_ACCESS),
2649                        query_tx_channel_config (dev, i, BUCKET_CAPACITY_ACCESS));
2650    count += sprintf (page+count, ".\n");
2651    return count;
2652  }
2653#endif
2654  
2655  if (!left--)
2656    return sprintf (page,
2657                    "cells: TX %lu, RX %lu, HEC errors %lu, unassigned %lu.\n",
2658                    dev->tx_cell_count, dev->rx_cell_count,
2659                    dev->hec_error_count, dev->unassigned_cell_count);
2660  
2661  if (!left--)
2662    return sprintf (page,
2663                    "free cell buffers: TX %hu, RX %hu+%hu.\n",
2664                    rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF),
2665                    rd_regw (dev, RX_FREE_BUFFER_COUNT_OFF),
2666                    dev->noof_spare_buffers);
2667  
2668  if (!left--)
2669    return sprintf (page,
2670                    "cps remaining: TX %u, RX %u\n",
2671                    dev->tx_avail, dev->rx_avail);
2672  
2673  return 0;
2674}
2675
2676static const struct atmdev_ops hrz_ops = {
2677  .open = hrz_open,
2678  .close        = hrz_close,
2679  .send = hrz_send,
2680  .proc_read    = hrz_proc_read,
2681  .owner        = THIS_MODULE,
2682};
2683
2684static int __devinit hrz_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_ent)
2685{
2686        hrz_dev * dev;
2687        int err = 0;
2688
2689        // adapter slot free, read resources from PCI configuration space
2690        u32 iobase = pci_resource_start (pci_dev, 0);
2691        u32 * membase = bus_to_virt (pci_resource_start (pci_dev, 1));
2692        unsigned int irq;
2693        unsigned char lat;
2694
2695        PRINTD (DBG_FLOW, "hrz_probe");
2696
2697        if (pci_enable_device(pci_dev))
2698                return -EINVAL;
2699
2700        /* XXX DEV_LABEL is a guess */
2701        if (!request_region(iobase, HRZ_IO_EXTENT, DEV_LABEL)) {
2702                err = -EINVAL;
2703                goto out_disable;
2704        }
2705
2706        dev = kzalloc(sizeof(hrz_dev), GFP_KERNEL);
2707        if (!dev) {
2708                // perhaps we should be nice: deregister all adapters and abort?
2709                PRINTD(DBG_ERR, "out of memory");
2710                err = -ENOMEM;
2711                goto out_release;
2712        }
2713
2714        pci_set_drvdata(pci_dev, dev);
2715
2716        // grab IRQ and install handler - move this someplace more sensible
2717        irq = pci_dev->irq;
2718        if (request_irq(irq,
2719                        interrupt_handler,
2720                        IRQF_SHARED, /* irqflags guess */
2721                        DEV_LABEL, /* name guess */
2722                        dev)) {
2723                PRINTD(DBG_WARN, "request IRQ failed!");
2724                err = -EINVAL;
2725                goto out_free;
2726        }
2727
2728        PRINTD(DBG_INFO, "found Madge ATM adapter (hrz) at: IO %x, IRQ %u, MEM %p",
2729               iobase, irq, membase);
2730
2731        dev->atm_dev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &hrz_ops, -1,
2732                                        NULL);
2733        if (!(dev->atm_dev)) {
2734                PRINTD(DBG_ERR, "failed to register Madge ATM adapter");
2735                err = -EINVAL;
2736                goto out_free_irq;
2737        }
2738
2739        PRINTD(DBG_INFO, "registered Madge ATM adapter (no. %d) (%p) at %p",
2740               dev->atm_dev->number, dev, dev->atm_dev);
2741        dev->atm_dev->dev_data = (void *) dev;
2742        dev->pci_dev = pci_dev; 
2743
2744        // enable bus master accesses
2745        pci_set_master(pci_dev);
2746
2747        // frobnicate latency (upwards, usually)
2748        pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &lat);
2749        if (pci_lat) {
2750                PRINTD(DBG_INFO, "%s PCI latency timer from %hu to %hu",
2751                       "changing", lat, pci_lat);
2752                pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, pci_lat);
2753        } else if (lat < MIN_PCI_LATENCY) {
2754                PRINTK(KERN_INFO, "%s PCI latency timer from %hu to %hu",
2755                       "increasing", lat, MIN_PCI_LATENCY);
2756                pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, MIN_PCI_LATENCY);
2757        }
2758
2759        dev->iobase = iobase;
2760        dev->irq = irq; 
2761        dev->membase = membase; 
2762
2763        dev->rx_q_entry = dev->rx_q_reset = &memmap->rx_q_entries[0];
2764        dev->rx_q_wrap  = &memmap->rx_q_entries[RX_CHANS-1];
2765
2766        // these next three are performance hacks
2767        dev->last_vc = -1;
2768        dev->tx_last = -1;
2769        dev->tx_idle = 0;
2770
2771        dev->tx_regions = 0;
2772        dev->tx_bytes = 0;
2773        dev->tx_skb = NULL;
2774        dev->tx_iovec = NULL;
2775
2776        dev->tx_cell_count = 0;
2777        dev->rx_cell_count = 0;
2778        dev->hec_error_count = 0;
2779        dev->unassigned_cell_count = 0;
2780
2781        dev->noof_spare_buffers = 0;
2782
2783        {
2784                unsigned int i;
2785                for (i = 0; i < TX_CHANS; ++i)
2786                        dev->tx_channel_record[i] = -1;
2787        }
2788
2789        dev->flags = 0;
2790
2791        // Allocate cell rates and remember ASIC version
2792        // Fibre: ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53
2793        // Copper: (WRONG) we want 6 into the above, close to 25Mb/s
2794        // Copper: (plagarise!) 25600000/8/270*260/53 - n/53
2795
2796        if (hrz_init(dev)) {
2797                // to be really pedantic, this should be ATM_OC3c_PCR
2798                dev->tx_avail = ATM_OC3_PCR;
2799                dev->rx_avail = ATM_OC3_PCR;
2800                set_bit(ultra, &dev->flags); // NOT "|= ultra" !
2801        } else {
2802                dev->tx_avail = ((25600000/8)*26)/(27*53);
2803                dev->rx_avail = ((25600000/8)*26)/(27*53);
2804                PRINTD(DBG_WARN, "Buggy ASIC: no TX bus-mastering.");
2805        }
2806
2807        // rate changes spinlock
2808        spin_lock_init(&dev->rate_lock);
2809
2810        // on-board memory access spinlock; we want atomic reads and
2811        // writes to adapter memory (handles IRQ and SMP)
2812        spin_lock_init(&dev->mem_lock);
2813
2814        init_waitqueue_head(&dev->tx_queue);
2815
2816        // vpi in 0..4, vci in 6..10
2817        dev->atm_dev->ci_range.vpi_bits = vpi_bits;
2818        dev->atm_dev->ci_range.vci_bits = 10-vpi_bits;
2819
2820        init_timer(&dev->housekeeping);
2821        dev->housekeeping.function = do_housekeeping;
2822        dev->housekeeping.data = (unsigned long) dev;
2823        mod_timer(&dev->housekeeping, jiffies);
2824
2825out:
2826        return err;
2827
2828out_free_irq:
2829        free_irq(dev->irq, dev);
2830out_free:
2831        kfree(dev);
2832out_release:
2833        release_region(iobase, HRZ_IO_EXTENT);
2834out_disable:
2835        pci_disable_device(pci_dev);
2836        goto out;
2837}
2838
2839static void __devexit hrz_remove_one(struct pci_dev *pci_dev)
2840{
2841        hrz_dev *dev;
2842
2843        dev = pci_get_drvdata(pci_dev);
2844
2845        PRINTD(DBG_INFO, "closing %p (atm_dev = %p)", dev, dev->atm_dev);
2846        del_timer_sync(&dev->housekeeping);
2847        hrz_reset(dev);
2848        atm_dev_deregister(dev->atm_dev);
2849        free_irq(dev->irq, dev);
2850        release_region(dev->iobase, HRZ_IO_EXTENT);
2851        kfree(dev);
2852
2853        pci_disable_device(pci_dev);
2854}
2855
2856static void __init hrz_check_args (void) {
2857#ifdef DEBUG_HORIZON
2858  PRINTK (KERN_NOTICE, "debug bitmap is %hx", debug &= DBG_MASK);
2859#else
2860  if (debug)
2861    PRINTK (KERN_NOTICE, "no debug support in this image");
2862#endif
2863  
2864  if (vpi_bits > HRZ_MAX_VPI)
2865    PRINTK (KERN_ERR, "vpi_bits has been limited to %hu",
2866            vpi_bits = HRZ_MAX_VPI);
2867  
2868  if (max_tx_size < 0 || max_tx_size > TX_AAL5_LIMIT)
2869    PRINTK (KERN_NOTICE, "max_tx_size has been limited to %hu",
2870            max_tx_size = TX_AAL5_LIMIT);
2871  
2872  if (max_rx_size < 0 || max_rx_size > RX_AAL5_LIMIT)
2873    PRINTK (KERN_NOTICE, "max_rx_size has been limited to %hu",
2874            max_rx_size = RX_AAL5_LIMIT);
2875  
2876  return;
2877}
2878
2879MODULE_AUTHOR(maintainer_string);
2880MODULE_DESCRIPTION(description_string);
2881MODULE_LICENSE("GPL");
2882module_param(debug, ushort, 0644);
2883module_param(vpi_bits, ushort, 0);
2884module_param(max_tx_size, int, 0);
2885module_param(max_rx_size, int, 0);
2886module_param(pci_lat, byte, 0);
2887MODULE_PARM_DESC(debug, "debug bitmap, see .h file");
2888MODULE_PARM_DESC(vpi_bits, "number of bits (0..4) to allocate to VPIs");
2889MODULE_PARM_DESC(max_tx_size, "maximum size of TX AAL5 frames");
2890MODULE_PARM_DESC(max_rx_size, "maximum size of RX AAL5 frames");
2891MODULE_PARM_DESC(pci_lat, "PCI latency in bus cycles");
2892
2893static struct pci_device_id hrz_pci_tbl[] = {
2894        { PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_HORIZON, PCI_ANY_ID, PCI_ANY_ID,
2895          0, 0, 0 },
2896        { 0, }
2897};
2898
2899MODULE_DEVICE_TABLE(pci, hrz_pci_tbl);
2900
2901static struct pci_driver hrz_driver = {
2902        .name =         "horizon",
2903        .probe =        hrz_probe,
2904        .remove =       __devexit_p(hrz_remove_one),
2905        .id_table =     hrz_pci_tbl,
2906};
2907
2908/********** module entry **********/
2909
2910static int __init hrz_module_init (void) {
2911  // sanity check - cast is needed since printk does not support %Zu
2912  if (sizeof(struct MEMMAP) != 128*1024/4) {
2913    PRINTK (KERN_ERR, "Fix struct MEMMAP (is %lu fakewords).",
2914            (unsigned long) sizeof(struct MEMMAP));
2915    return -ENOMEM;
2916  }
2917  
2918  show_version();
2919  
2920  // check arguments
2921  hrz_check_args();
2922  
2923  // get the juice
2924  return pci_register_driver(&hrz_driver);
2925}
2926
2927/********** module exit **********/
2928
2929static void __exit hrz_module_exit (void) {
2930  PRINTD (DBG_FLOW, "cleanup_module");
2931
2932  pci_unregister_driver(&hrz_driver);
2933}
2934
2935module_init(hrz_module_init);
2936module_exit(hrz_module_exit);
2937
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