linux/Documentation/frv/kernel-ABI.txt
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tion v3/spa v3/form v3a tion v href="../linux+v3.7.2/Documenta1" /frv/kernel-ABI.txt">tion v3img src="../.sta1"c/gfx/right.png" alt=">>">ti3/spa ti3spa class="lxr_search">tiontion v3input typionhidden" namionnavtarget" /option">tion v3input typiontext" namionsearch" idonsearch">tion v3butt11Searchtion v3img src="../.sta1"c/gfx/right.pn"fvrtion val>.sta1"c/gfx/right.l>.div/right.l>tion v3input ta1"+*idden" namionnavtarget" /option">falseght.p namionsearch" idonsearch">ta1"clookup/spa ta1"clookup/s11.umentasight.l>divABI.txt"headingbo?remethodiv/righthodiv/right ht.l>divApa ti3sp_results"ABI.txt" ti3sp_results" va/right.l>.div/r >divApa cont 2="/r >divApa file_cont 2=ncl 2=v32v34ov onclick=LABI.tx#L1/spa L1/sBI.txt"tine/sarch">L1/>t.l1>.st ================================= 2=v32v34ov onclick=LABI.tx#L2/spa L2/sBI.txt"tine/sarch">L2/>t.l2>.st INTERNAL KERNEL LAB FOR FR-V ARCH 2=v32v34ov onclick=LABI.tx#L3/spa L3/sBI.txt"tine/sarch">L3/>t.l3>.st ================================= 2=v32v34ov onclick=LABI.tx#L4/spa L4/sBI.txt"tine/sarch">L4/>t.l4>.sta 2=v32v34ov onclick=LABI.tx#L5/spa L5/sBI.txt"tine/sarch">L5/>t.l5>.stThe int rnal FRV nclick LAB is not quite the srch as the user/gfce LAB. Aa 2=v32v34ov onclick=LABI.tx#L6/spa L6/sBI.txt"tine/sarch">L6/>t.l6>.stnumber of the regist rs are used ume special purioned, and the LAB is nota 2=v32v34ov onclick=LABI.tx#L7/spa L7/sBI.txt"tine/sarch">L7/>t.l7>.stconsist nt between modules vs core, and MMU vs no-MMU.a 2=v32v34ov onclick=LABI.tx#L8/spa L8/sBI.txt"tine/sarch">L8/>t.l8>.sta 2=v32v34ov onclick=LABI.tx#L9/spa L9/sBI.txt"tine/sarch">L9/>t.l9>.stThis partly st ms from the fv3i that FRV CPUs>ti not havh a separatea 2=v32v34ov onclick=LABI.tx#L10/spa L10/sBI.txt"tine/sarch">L10/>t. v3.a>supervisme stack point r, and monn of them>ti not havh any scratcha 2=v32v34ov onclick=LABI.tx#L11/spa L11/sBI.txt"tine/sarch">L11/>t.11>.stregist rs, thus requiring at leann one general purione regist r to bea 2=v32v34ov onclick=LABI.tx#L12/spa L12/sBI.txt"tine/sarch">L12/>t.12>.stclobbered in such an ev 2=. Also, wiut n the nclick core, it is ionsible toa 2=v32v34ov onclick=LABI.tx#L13/spa L13/sBI.txt"tine/sarch">L13/>t.13>.stsimply jump me call dirntaly between fun3inpus using a relv32vh offset.a 2=v32v34ov onclick=LABI.tx#L14/spa L14/sBI.txt"tine/sarch">L14/>t.14>.stThis cannot be 11 ended to modules ume the displfce 2= is likely to be tooa 2=v32v34ov onclick=LABI.tx#L15/spa L15/sBI.txt"tine/sarch">L15/>t.15>.stfar. Thus in modules the address of a fun3inpu to call must be calculv3eda 2=v32v34ov onclick=LABI.tx#L16/spa L16/sBI.txt"tine/sarch">L16/>t.16>.stin a regist r and then used, requiring two 11 ra instru3inpus.a 2=v32v34ov onclick=LABI.tx#L17/spa L17/sBI.txt"tine/sarch">L17/>t.17>.sta 2=v32v34ov onclick=LABI.tx#L18/spa L18/sBI.txt"tine/sarch">L18/>t.18>.stThis don> 2= has the following se3inpus:a 2=v32v34ov onclick=LABI.tx#L19/spa L19/sBI.txt"tine/sarch">L19/>t.19>.sta 2=v32v34ov onclick=LABI.tx#L20/spa L20/sBI.txt"tine/sarch">L20/>t.2v3.a> (*) Syst m call regist r LABa 2=v32v34ov onclick=LABI.tx#L21/spa L21/sBI.txt"tine/sarch">L21/>t.213.a> (*) CPU operv32ng modesa 2=v32v34ov onclick=LABI.tx#L22/spa L22/sBI.txt"tine/sarch">L22/>t.223.a> (*) Int rnal nclick=mode regist r LABa 2=v32v34ov onclick=LABI.tx#L23/spa L23/sBI.txt"tine/sarch">L23/>t.233.a> (*) Int rnal debug=mode regist r LABa 2=v32v34ov onclick=LABI.tx#L24/spa L24/sBI.txt"tine/sarch">L24/>t.243.a> (*) Virtual int rrup= handtinga 2=v32v34ov onclick=LABI.tx#L25/spa L25/sBI.txt"tine/sarch">L25/>t.25>.sta 2=v32v34ov onclick=LABI.tx#L26/spa L26/sBI.txt"tine/sarch">L26/>t.26>.sta 2=v32v34ov onclick=LABI.tx#L27/spa L27/sBI.txt"tine/sarch">L27/>t.27>.st======================== 2=v32v34ov onclick=LABI.tx#L28/spa L28/sBI.txt"tine/sarch">L28/>t.28>.stSYSTEM CALL REGISTER LABa 2=v32v34ov onclick=LABI.tx#L29/spa L29/sBI.txt"tine/sarch">L29/>t.29>.st======================== 2=v32v34ov onclick=LABI.tx#L30/spa L30/sBI.txt"tine/sarch">L30/>t.30>.sta 2=v32v34ov onclick=LABI.tx#L31/spa L31/sBI.txt"tine/sarch">L31/>t.313.a>When a syst m call is made, the following regist rs are effe3inve:a 2=v32v34ov onclick=LABI.tx#L32/spa L32/sBI.txt"tine/sarch">L32/>t.32>.sta 2=v32v34ov onclick=LABI.tx#L33/spa L33/sBI.txt"tine/sarch">L33/>t.33>.st REGISTERS CALL RETURNa 2=v32v34ov onclick=LABI.tx#L34/spa L34/sBI.txt"tine/sarch">L34/>t.34>.st =============== ======================= =======================a 2=v32v34ov onclick=LABI.tx#L35/spa L35/sBI.txt"tine/sarch">L35/>t.35>.st GR7 Syst m call number Preserveda 2=v32v34ov onclick=LABI.tx#L36/spa L36/sBI.txt"tine/sarch">L36/>t.36>.st GR8 Syscall arg #1 Rtion">11 2=v32v34ov onclick=LABI.tx#L37/spa L37/sBI.txt"tine/sarch">L37/>t.37>.st GR9-GR13 Syscall arg #2-6 Preserveda 2=v32v34ov onclick=LABI.tx#L38/spa L38/sBI.txt"tine/sarch">L38/>t.38>.sta 2=v32v34ov onclick=LABI.tx#L39/spa L39/sBI.txt"tine/sarch">L39/>t.39>.sta 2=v32v34ov onclick=LABI.tx#L40/spa L40/sBI.txt"tine/sarch">L40/>t.40>.st===================a 2=v32v34ov onclick=LABI.tx#L41/spa L41/sBI.txt"tine/sarch">L41/>t.413.a>CPU OPERATING MODESa 2=v32v34ov onclick=LABI.tx#L42/spa L42/sBI.txt"tine/sarch">L42/>t.42>.st===================a 2=v32v34ov onclick=LABI.tx#L43/spa L43/sBI.txt"tine/sarch">L43/>t.43>.sta 2=v32v34ov onclick=LABI.tx#L44/spa L44/sBI.txt"tine/sarch">L44/>t.44>.stThe FR-V CPU has three basic operv32ng modes. In meder of increaninga 2=v32v34ov onclick=LABI.tx#L45/spa L45/sBI.txt"tine/sarch">L45/>t.45>.stcapability:a 2=v32v34ov onclick=LABI.tx#L46/spa L46/sBI.txt"tine/sarch">L46/>t.46>.sta 2=v32v34ov onclick=LABI.tx#L47/spa L47/sBI.txt"tine/sarch">L47/>t.47>.st (1) User mode.a 2=v32v34ov onclick=LABI.tx#L48/spa L48/sBI.txt"tine/sarch">L48/>t.48>.sta 2=v32v34ov onclick=LABI.tx#L49/spa L49/sBI.txt"tine/sarch">L49/>t.49>.st Basic user/gfce runn2ng mode.a 2=v32v34ov onclick=LABI.tx#L50/spa L50/sBI.txt"tine/sarch">L50/>t.50>.sta 2=v32v34ov onclick=LABI.tx#L51/spa L51/sBI.txt"tine/sarch">L51/>t.51>.st (2) Kclick mode.a 2=v32v34ov onclick=LABI.tx#L52/spa L52/sBI.txt"tine/sarch">L52/>t.52>.sta 2=v32v34ov onclick=LABI.tx#L53/spa L53/sBI.txt"tine/sarch">L53/>t.53>.st Normal nclick mode. There are many addi32v3ak control regist rsa 2=v32v34ov onclick=LABI.tx#L54/spa L54/sBI.txt"tine/sarch">L54/>t.54>.st available that may be accessed in ut t mode, in addi32v3 to all thea 2=v32v34ov onclick=LABI.tx#L55/spa L55/sBI.txt"tine/sarch">L55/>t.55>.st stuff available to user mode. Th t has two rgetodes:a 2=v32v34ov onclick=LABI.tx#L56/spa L56/sBI.txt"tine/sarch">L56/>t.56>.sta 2=v32v34ov onclick=LABI.tx#L57/spa L57/sBI.txt"tine/sarch">L57/>t.57>.st (a) Excepinpus enabled (PSR.T == 1).a 2=v32v34ov onclick=LABI.tx#L58/spa L58/sBI.txt"tine/sarch">L58/>t.58>.sta 2=v32v34ov onclick=LABI.tx#L59/spa L59/sBI.txt"tine/sarch">L59/>t.59>.st Excepinpus will invoke the appropriate normal nclick modea 2=v32v34ov onclick=LABI.tx#L60/spa L60/sBI.txt"tine/sarch">L60/>t.60>.st handter. On entry to the handter, the PSR.T bit will be cleared.a 2=v32v34ov onclick=LABI.tx#L61/spa L61/sBI.txt"tine/sarch">L61/>t.61>.sta 2=v32v34ov onclick=LABI.tx#L62/spa L62/sBI.txt"tine/sarch">L62/>t.62>.st (b) Excepinpus disabled (PSR.T == 0).a 2=v32v34ov onclick=LABI.tx#L63/spa L63/sBI.txt"tine/sarch">L63/>t.63>.sta 2=v32v34ov onclick=LABI.tx#L64/spa L64/sBI.txt"tine/sarch">L64/>t.64>.st No 11cepinpus or int rrup=s may happen. Any mandatory 11cepinpusa 2=v32v34ov onclick=LABI.tx#L65/spa L65/sBI.txt"tine/sarch">L65/>t.65>.st will cause the CPU to halt unless the CPU t told to jump intoa 2=v32v34ov onclick=LABI.tx#L66/spa L66/sBI.txt"tine/sarch">L66/>t.66>.st debug mode instead.a 2=v32v34ov onclick=LABI.tx#L67/spa L67/sBI.txt"tine/sarch">L67/>t.67>.sta 2=v32v34ov onclick=LABI.tx#L68/spa L68/sBI.txt"tine/sarch">L68/>t.68>.st (3) Debug mode.a 2=v32v34ov onclick=LABI.tx#L69/spa L69/sBI.txt"tine/sarch">L69/>t.69>.sta 2=v32v34ov onclick=LABI.tx#L70/spa L70/sBI.txt"tine/sarch">L70/>t.70>.st No 11cepinpus may happen in ut t mode. Memory prote3inpu anda 2=v32v34ov onclick=LABI.tx#L71/spa L71/sBI.txt"tine/sarch">L71/>t.71>.st manage 2= excepinpus will be flagged ume lv3er considerv32on, buta 2=v32v34ov onclick=LABI.tx#L72/spa L72/sBI.txt"tine/sarch">L72/>t.72>.st the excepinpu handter won't be invoked. Debugging traps such asa 2=v32v34ov onclick=LABI.tx#L73/spa L73/sBI.txt"tine/sarch">L73/>t.73>.st hardware breakpoints and watchpoints will be ignored. Tt t mode ta 2=v32v34ov onclick=LABI.tx#L74/spa L74/sBI.txt"tine/sarch">L74/>t.74>.st ent red only by debugging ev 2=s obtained from the other two modes.a 2=v32v34ov onclick=LABI.tx#L75/spa L75/sBI.txt"tine/sarch">L75/>t.75>.sta 2=v32v34ov onclick=LABI.tx#L76/spa L76/sBI.txt"tine/sarch">L76/>t.76>.st All nclick mode regist rs may be accessed, plus a few 11 ra debugginga 2=v32v34ov onclick=LABI.tx#L77/spa L77/sBI.txt"tine/sarch">L77/>t.77>.st specific regist rs.a 2=v32v34ov onclick=LABI.tx#L78/spa L78/sBI.txt"tine/sarch">L78/>t.78>.sta 2=v32v34ov onclick=LABI.tx#L79/spa L79/sBI.txt"tine/sarch">L79/>t.79>.sta 2=v32v34ov onclick=LABI.tx#L80/spa L80/sBI.txt"tine/sarch">L80/>t.80>.st=================================a 2=v32v34ov onclick=LABI.tx#L81/spa L81/sBI.txt"tine/sarch">L81/>t.81>.stINTERNAL KERNEL-MODE REGISTER LABa 2=v32v34ov onclick=LABI.tx#L82/spa L82/sBI.txt"tine/sarch">L82/>t.82>.st=================================a 2=v32v34ov onclick=LABI.tx#L83/spa L83/sBI.txt"tine/sarch">L83/>t.83>.sta 2=v32v34ov onclick=LABI.tx#L84/spa L84/sBI.txt"tine/sarch">L84/>t.84>.stThere are a number of perman 2= regist r assignm 2=s that are set up bya 2=v32v34ov onclick=LABI.tx#L85/spa L85/sBI.txt"tine/sarch">L85/>t.85>.stentry.S n the excepinpu prologue. Note that there is a complete set ofa 2=v32v34ov onclick=LABI.tx#L86/spa L86/sBI.txt"tine/sarch">L86/>t.86>.stexcepinpu prologues ume each of user-h" mnclick ransiinpu and nclick=h" mnclicka 2=v32v34ov onclick=LABI.tx#L87/spa L87/sBI.txt"tine/sarch">L87/>t.87>.st ransiinpu. There are also user-h" mdebug and nclick=h" mdebug mode ransiinpua 2=v32v34ov onclick=LABI.tx#L88/spa L88/sBI.txt"tine/sarch">L88/>t.88>.stprologues.a 2=v32v34ov onclick=LABI.tx#L89/spa L89/sBI.txt"tine/sarch">L89/>t.89>.sta 2=v32v34ov onclick=LABI.tx#L90/spa L90/sBI.txt"tine/sarch">L90/>t.90>.sta 2=v32v34ov onclick=LABI.tx#L91/spa L91/sBI.txt"tine/sarch">L91/>t.91>.st REGISTER FLAVOUR USEa 2=v32v34ov onclick=LABI.tx#L92/spa L92/sBI.txt"tine/sarch">L92/>t.92>.st =============== ======= ==============================================a 2=v32v34ov onclick=LABI.tx#L93/spa L93/sBI.txt"tine/sarch">L93/>t.93>.st GR1 Supervisme stack point ra 2=v32v34ov onclick=LABI.tx#L94/spa L94/sBI.txt"tine/sarch">L94/>t.94>.st GR15 Curr 2= thread info point ra 2=v32v34ov onclick=LABI.tx#L95/spa L95/sBI.txt"tine/sarch">L95/>t.95>.st GR16 GP-Rck bane regist r ume small dataa 2=v32v34ov onclick=LABI.tx#L96/spa L96/sBI.txt"tine/sarch">L96/>t.96>.st GR28 Curr 2= excepinpu frrch point r (__frrch)a 2=v32v34ov onclick=LABI.tx#L97/spa L97/sBI.txt"tine/sarch">L97/>t.97>.st GR29 Curr 2= task point r (curr 2=)a 2=v32v34ov onclick=LABI.tx#L98/spa L98/sBI.txt"tine/sarch">L98/>t.98>.st GR30 Destroyed by nclick mode entrya 2=v32v34ov onclick=LABI.tx#L99/spa L99/sBI.txt"tine/sarch">L99/>t.99>.st GR31 NOMMU Destroyed by debug mode entrya 2=v32v34ov onclick=LABI.tx#L100/spa L100/sBI.txt"tine/sarch">L100/>t100>.st GR31 MMU Destroyed by TLB miss nclick mode entrya 2=v32v34ov onclick=LABI.tx#L101/spa L101/sBI.txt"tine/sarch">L101/>t101>.st CCR.ICC2 Virtual int rrup= disable 2= rackinga 2=v32v34ov onclick=LABI.tx#L102/spa L102/sBI.txt"tine/sarch">L102/>t102>.st CCCR.CC3 Cleared by excepinpu prologue a 2=v32v34ov onclick=LABI.tx#L103/spa L103/sBI.txt"tine/sarch">L103/>t103>.st (atomic op emulv32v3)a 2=v32v34ov onclick=LABI.tx#L104/spa L104/sBI.txt"tine/sarch">L104/>t104>.st SCR0 MMU See mmu-layoutI.tx.a 2=v32v34ov onclick=LABI.tx#L105/spa L105/sBI.txt"tine/sarch">L105/>t105>.st SCR1 MMU See mmu-layoutI.tx.a 2=v32v34ov onclick=LABI.tx#L106/spa L106/sBI.txt"tine/sarch">L106/>t106>.st SCR2 MMU Savh ume EAR0 (destroyed by icache insns a 2=v32v34ov onclick=LABI.tx#L107/spa L107/sBI.txt"tine/sarch">L107/>t107>.st n debug mode)a 2=v32v34ov onclick=LABI.tx#L108/spa L108/sBI.txt"tine/sarch">L108/>t108>.st SCR3 MMU Savh ume GR31 during debug 11cepinpusa 2=v32v34ov onclick=LABI.tx#L109/spa L109/sBI.txt"tine/sarch">L109/>t109>.st DAMR/IAMR NOMMU Fixed memory prote3inpu layoutIa 2=v32v34ov onclick=LABI.tx#L110/spa L110/sBI.txt"tine/sarch">L110/>t110>.st DAMR/IAMR MMU See mmu-layoutI.tx.a 2=v32v34ov onclick=LABI.tx#L111/spa L111/sBI.txt"tine/sarch">L111/>t111>.sta 2=v32v34ov onclick=LABI.tx#L112/spa L112/sBI.txt"tine/sarch">L112/>t112>.sta 2=v32v34ov onclick=LABI.tx#L113/spa L113/sBI.txt"tine/sarch">L113/>t113>.stCertain regist rs are also used or modified across fun3inpu calls:a 2=v32v34ov onclick=LABI.tx#L114/spa L114/sBI.txt"tine/sarch">L114/>t114>.sta 2=v32v34ov onclick=LABI.tx#L115/spa L115/sBI.txt"tine/sarch">L115/>t115>.st REGISTER CALL RETURNa 2=v32v34ov onclick=LABI.tx#L116/spa L116/sBI.txt"tine/sarch">L116/>t116>.st =============== =============================== ======================a 2=v32v34ov onclick=LABI.tx#L117/spa L117/sBI.txt"tine/sarch">L117/>t117>.st GR0 Fixed Zero -a 2=v32v34ov onclick=LABI.tx#L118/spa L118/sBI.txt"tine/sarch">L118/>t118>.st GR2 Fun3inpu call frrch point ra 2=v32v34ov onclick=LABI.tx#L119/spa L119/sBI.txt"tine/sarch">L119/>t119>.st GR3 Special Preserveda 2=v32v34ov onclick=LABI.tx#L120/spa L120/sBI.txt"tine/sarch">L120/>t120>.st GR3-GR7 - Clobbereda 2=v32v34ov onclick=LABI.tx#L121/spa L121/sBI.txt"tine/sarch">L121/>t121>.st GR8 Fun3inpu call arg #1 Rtion">11 2=v32v34ov onclick=LABI.tx#L122/spa L122/sBI.txt"tine/sarch">L122/>t122>.st (me clobbered)a 2=v32v34ov onclick=LABI.tx#L123/spa L123/sBI.txt"tine/sarch">L123/>t123>.st GR9 Fun3inpu call arg #2 Rtion">11 2=v32v34ov onclick=LABI.tx#L124/spa L124/sBI.txt"tine/sarch">L124/>t124>.st (me clobbered)a 2=v32v34ov onclick=LABI.tx#L125/spa L125/sBI.txt"tine/sarch">L125/>t125>.st GR10-GR13 Fun3inpu call arg #3-#6 Clobbereda 2=v32v34ov onclick=LABI.tx#L126/spa L126/sBI.txt"tine/sarch">L126/>t126>.st GR14 - Clobbereda 2=v32v34ov onclick=LABI.tx#L127/spa L127/sBI.txt"tine/sarch">L127/>t127>.st GR15-GR16 Special Preserveda 2=v32v34ov onclick=LABI.tx#L128/spa L128/sBI.txt"tine/sarch">L128/>t128>.st GR17-GR27 - Preserveda 2=v32v34ov onclick=LABI.tx#L129/spa L129/sBI.txt"tine/sarch">L129/>t129>.st GR28-GR31 Special Only accessed a 2=v32v34ov onclick=LABI.tx#L130/spa L130/sBI.txt"tine/sarch">L130/>t130>.st explicitlya 2=v32v34ov onclick=LABI.tx#L131/spa L131/sBI.txt"tine/sarch">L131/>t131>.st LR Rtion">address aft r CALL Clobbereda 2=v32v34ov onclick=LABI.tx#L132/spa L132/sBI.txt"tine/sarch">L132/>t132>.st CCR/CCCR - Mosaly Clobbereda 2=v32v34ov onclick=LABI.tx#L133/spa L133/sBI.txt"tine/sarch">L133/>t133>.sta 2=v32v34ov onclick=LABI.tx#L134/spa L134/sBI.txt"tine/sarch">L134/>t134>.sta 2=v32v34ov onclick=LABI.tx#L135/spa L135/sBI.txt"tine/sarch">L135/>t135>.st================================a 2=v32v34ov onclick=LABI.tx#L136/spa L136/sBI.txt"tine/sarch">L136/>t136>.stINTERNAL DEBUG-MODE REGISTER LABa 2=v32v34ov onclick=LABI.tx#L137/spa L137/sBI.txt"tine/sarch">L137/>t137>.st================================a 2=v32v34ov onclick=LABI.tx#L138/spa L138/sBI.txt"tine/sarch">L138/>t138>.sta 2=v32v34ov onclick=LABI.tx#L139/spa L139/sBI.txt"tine/sarch">L139/>t139>.stThis is the srch as the nclick=mode regist r LAB ume fun3inpus calls. Thea 2=v32v34ov onclick=LABI.tx#L140/spa L140/sBI.txt"tine/sarch">L140/>t140>.stdifference is that n debug=mode there's a different stack and a differenta 2=v32v34ov onclick=LABI.tx#L141/spa L141/sBI.txt"tine/sarch">L141/>t1413.a>excepinpu frrch. Almonn all the global regist rs from nclick=modea 2=v32v34ov onclick=LABI.tx#L142/spa L142/sBI.txt"tine/sarch">L142/>t142>.st(including the stack point r) may be changed.a 2=v32v34ov onclick=LABI.tx#L143/spa L143/sBI.txt"tine/sarch">L143/>t143>.sta 2=v32v34ov onclick=LABI.tx#L144/spa L144/sBI.txt"tine/sarch">L144/>t144>.st REGISTER FLAVOUR USEa 2=v32v34ov onclick=LABI.tx#L145/spa L145/sBI.txt"tine/sarch">L145/>t145>.st =============== ======= ==============================================a 2=v32v34ov onclick=LABI.tx#L146/spa L146/sBI.txt"tine/sarch">L146/>t146>.st GR1 Debug stack point ra 2=v32v34ov onclick=LABI.tx#L147/spa L147/sBI.txt"tine/sarch">L147/>t147>.st GR16 GP-Rck bane regist r ume small dataa 2=v32v34ov onclick=LABI.tx#L148/spa L148/sBI.txt"tine/sarch">L148/>t148>.st GR31 Curr 2= debug 11cepinpu frrch point r a 2=v32v34ov onclick=LABI.tx#L149/spa L149/sBI.txt"tine/sarch">L149/>t149>.st (__debug_frrch)a 2=v32v34ov onclick=LABI.tx#L150/spa L150/sBI.txt"tine/sarch">L150/>t150>.st SCR3 MMU Savhd>11 2=v32v34ov onclick=LABI.tx#L151/spa L151/sBI.txt"tine/sarch">L151/>t151>.sta 2=v32v34ov onclick=LABI.tx#L152/spa L152/sBI.txt"tine/sarch">L152/>t152>.sta 2=v32v34ov onclick=LABI.tx#L153/spa L153/sBI.txt"tine/sarch">L153/>t153>.stNote that debug mode is able to int rfere wiut the nclick's emulv3ed atomica 2=v32v34ov onclick=LABI.tx#L154/spa L154/sBI.txt"tine/sarch">L154/>t154>.stops, so it must be 11ceedingly caurnul not to do any that would int racta 2=v32v34ov onclick=LABI.tx#L155/spa L155/sBI.txt"tine/sarch">L155/>t155>.stwiut the main nclick in ut t regard. Hence the debug mode code (gdbstub) ta 2=v32v34ov onclick=LABI.tx#L156/spa L156/sBI.txt"tine/sarch">L156/>t156>.stalmonn completely self-contained. The only 11 er3ak code used is thea 2=v32v34ov onclick=LABI.tx#L157/spa L157/sBI.txt"tine/sarch">L157/>t157>.stsprintf family of fun3inpus.a 2=v32v34ov onclick=LABI.tx#L158/spa L158/sBI.txt"tine/sarch">L158/>t158>.sta 2=v32v34ov onclick=LABI.tx#L159/spa L159/sBI.txt"tine/sarch">L159/>t159>.stFurthermore, break.S s so complicv3ed because ningle-st p mode does nota 2=v32v34ov onclick=LABI.tx#L160/spa L160/sBI.txt"tine/sarch">L160/>t160>.stswiuch off on entry to an e1cepinpu. That meaus unless manually disabled,a 2=v32v34ov onclick=LABI.tx#L161/spa L161/sBI.txt"tine/sarch">L161/>t161>.stningle-st pping will bliutely go on st pping into ut ngs like int rrup=s.a 2=v32v34ov onclick=LABI.tx#L162/spa L162/sBI.txt"tine/sarch">L162/>t162>.stSee gdbstubI.tx ume more informv32v3.a 2=v32v34ov onclick=LABI.tx#L163/spa L163/sBI.txt"tine/sarch">L163/>t163>.sta 2=v32v34ov onclick=LABI.tx#L164/spa L164/sBI.txt"tine/sarch">L164/>t164>.sta 2=v32v34ov onclick=LABI.tx#L165/spa L165/sBI.txt"tine/sarch">L165/>t165>.st==========================a 2=v32v34ov onclick=LABI.tx#L166/spa L166/sBI.txt"tine/sarch">L166/>t166>.stVIRTUAL INTERRUPT HANDLINGa 2=v32v34ov onclick=LABI.tx#L167/spa L167/sBI.txt"tine/sarch">L167/>t167>.st==========================a 2=v32v34ov onclick=LABI.tx#L168/spa L168/sBI.txt"tine/sarch">L168/>t168>.sta 2=v32v34ov onclick=LABI.tx#L169/spa L169/sBI.txt"tine/sarch">L169/>t169>.stBecause accesses to the PSR s so slow, and to disable int rrup=s we havha 2=v32v34ov onclick=LABI.tx#L170/spa L170/sBI.txt"tine/sarch">L170/>t170>.stto access it twice (once to read and once to write), we don't actuallya 2=v32v34ov onclick=LABI.tx#L171/spa L171/sBI.txt"tine/sarch">L171/>t171>.stdisable int rrup=s an all if we don't havh to. What we do instead s usea 2=v32v34ov onclick=LABI.tx#L172/spa L172/sBI.txt"tine/sarch">L172/>t172>.stthe ICC2 condi32v3 code flags to note virtual disable 2=, such that f wea 2=v32v34ov onclick=LABI.tx#L173/spa L173/sBI.txt"tine/sarch">L173/>t173>.stthen do takh an int rrup=, we note the flag, really disable int rrup=s, seta 2=v32v34ov onclick=LABI.tx#L174/spa L174/sBI.txt"tine/sarch">L174/>t174>.stanother flag and resume 11ecuinpu at the point the int rrup= happened.a 2=v32v34ov onclick=LABI.tx#L175/spa L175/sBI.txt"tine/sarch">L175/>t175>.stSet32ng condi32v3 flags as a side effe3i of au arithmetic or logicvka 2=v32v34ov onclick=LABI.tx#L176/spa L176/sBI.txt"tine/sarch">L176/>t176>.stinstru3inpu t really fast. Tt t use of the ICC2 only occurs wiut n thea 2=v32v34ov onclick=LABI.tx#L177/spa L177/sBI.txt"tine/sarch">L177/>t177>.stnclick - it does not affe3i user/gfce.a 2=v32v34ov onclick=LABI.tx#L178/spa L178/sBI.txt"tine/sarch">L178/>t178>.sta 2=v32v34ov onclick=LABI.tx#L179/spa L179/sBI.txt"tine/sarch">L179/>t179>.stThe flags we use are:a 2=v32v34ov onclick=LABI.tx#L180/spa L180/sBI.txt"tine/sarch">L180/>t180>.sta 2=v32v34ov onclick=LABI.tx#L181/spa L181/sBI.txt"tine/sarch">L181/>t1813.a> (*) CCR.ICC2.Z [Zero flag]a 2=v32v34ov onclick=LABI.tx#L182/spa L182/sBI.txt"tine/sarch">L182/>t182>.sta 2=v32v34ov onclick=LABI.tx#L183/spa L183/sBI.txt"tine/sarch">L183/>t183>.st Set to virtually disable int rrup=s, clear when int rrup=s area 2=v32v34ov onclick=LABI.tx#L184/spa L184/sBI.txt"tine/sarch">L184/>t184>.st virtually enabled. Cau be modified by logicvk instru3inpus wiutouta 2=v32v34ov onclick=LABI.tx#L185/spa L185/sBI.txt"tine/sarch">L185/>t185>.st affe3iing the Carry flag.a 2=v32v34ov onclick=LABI.tx#L186/spa L186/sBI.txt"tine/sarch">L186/>t186>.sta 2=v32v34ov onclick=LABI.tx#L187/spa L187/sBI.txt"tine/sarch">L187/>t187>.st (*) CCR.ICC2.C [Carry flag]a 2=v32v34ov onclick=LABI.tx#L188/spa L188/sBI.txt"tine/sarch">L188/>t188>.sta 2=v32v34ov onclick=LABI.tx#L189/spa L189/sBI.txt"tine/sarch">L189/>t189>.st Clear to indicv3e hardware int rrup=s are really disabled, set otherwise.a 2=v32v34ov onclick=LABI.tx#L190/spa L190/sBI.txt"tine/sarch">L190/>t190>.sta 2=v32v34ov onclick=LABI.tx#L191/spa L191/sBI.txt"tine/sarch">L191/>t191>.sta 2=v32v34ov onclick=LABI.tx#L192/spa L192/sBI.txt"tine/sarch">L192/>t192>.stWhat happens is this:a 2=v32v34ov onclick=LABI.tx#L193/spa L193/sBI.txt"tine/sarch">L193/>t193>.sta 2=v32v34ov onclick=LABI.tx#L194/spa L194/sBI.txt"tine/sarch">L194/>t194>.st (1) Normal nclick=mode operv32v3.a 2=v32v34ov onclick=LABI.tx#L195/spa L195/sBI.txt"tine/sarch">L195/>t195>.sta 2=v32v34ov onclick=LABI.tx#L196/spa L196/sBI.txt"tine/sarch">L196/>t196>.st ICC2.Z is 0, ICC2.C is 1.a 2=v32v34ov onclick=LABI.tx#L197/spa L197/sBI.txt"tine/sarch">L197/>t197>.sta 2=v32v34ov onclick=LABI.tx#L198/spa L198/sBI.txt"tine/sarch">L198/>t198>.st (2) An int rrup= occurs. The excepinpu prologue examines ICC2.Z anda 2=v32v34ov onclick=LABI.tx#L199/spa L199/sBI.txt"tine/sarch">L199/>t199>.st det rmines that nothing needs doing. Tt t is done nimply wiut aua 2=v32v34ov onclick=LABI.tx#L200/spa L200/sBI.txt"tine/sarch">L200/>t200>.st unlikely BEQ instru3inpu.a 2=v32v34ov onclick=LABI.tx#L201/spa L201/sBI.txt"tine/sarch">L201/>t201>.sta 2=v32v34ov onclick=LABI.tx#L202/spa L202/sBI.txt"tine/sarch">L202/>t202>.st (3) The int rrup=s are disabled (locvk_irq_disable)a 2=v32v34ov onclick=LABI.tx#L203/spa L203/sBI.txt"tine/sarch">L203/>t203>.sta 2=v32v34ov onclick=LABI.tx#L204/spa L204/sBI.txt"tine/sarch">L204/>t204>.st ICC2.Z is set to 1.a 2=v32v34ov onclick=LABI.tx#L205/spa L205/sBI.txt"tine/sarch">L205/>t205>.sta 2=v32v34ov onclick=LABI.tx#L206/spa L206/sBI.txt"tine/sarch">L206/>t206>.st (4) If int rrup=s were then re-enabled (locvk_irq_enable):a 2=v32v34ov onclick=LABI.tx#L207/spa L207/sBI.txt"tine/sarch">L207/>t207>.sta 2=v32v34ov onclick=LABI.tx#L208/spa L208/sBI.txt"tine/sarch">L208/>t208>.st ICC2.Z would be set to 0.a 2=v32v34ov onclick=LABI.tx#L209/spa L209/sBI.txt"tine/sarch">L209/>t209>.sta 2=v32v34ov onclick=LABI.tx#L210/spa L210/sBI.txt"tine/sarch">L210/>t210>.st A TIHI #2 instru3inpu (trap #2 if condi32v3 HI - Z==0 && C==0) woulda 2=v32v34ov onclick=LABI.tx#L211/spa L211/sBI.txt"tine/sarch">L211/>t211>.st be used to trap if int rrup=s were now virtually enabled, buta 2=v32v34ov onclick=LABI.tx#L212/spa L212/sBI.txt"tine/sarch">L212/>t212>.st physicvkly disabled - which they're not, so the trap isn't takhn. Thea 2=v32v34ov onclick=LABI.tx#L213/spa L213/sBI.txt"tine/sarch">L213/>t213>.st nclick would then be back to earce (1).a 2=v32v34ov onclick=LABI.tx#L214/spa L214/sBI.txt"tine/sarch">L214/>t214>.sta 2=v32v34ov onclick=LABI.tx#L215/spa L215/sBI.txt"tine/sarch">L215/>t215>.st (5) An int rrup= occurs. The excepinpu prologue examines ICC2.Z anda 2=v32v34ov onclick=LABI.tx#L216/spa L216/sBI.txt"tine/sarch">L216/>t216>.st det rmines that the int rrup= shouldn't actually havh happened. Ita 2=v32v34ov onclick=LABI.tx#L217/spa L217/sBI.txt"tine/sarch">L217/>t217>.st jumps aside, and there disabled int rrup=s by set32ng PSR.PIL to 14a 2=v32v34ov onclick=LABI.tx#L218/spa L218/sBI.txt"tine/sarch">L218/>t218>.st and then it clears ICC2.C.a 2=v32v34ov onclick=LABI.tx#L219/spa L219/sBI.txt"tine/sarch">L219/>t219>.sta 2=v32v34ov onclick=LABI.tx#L220/spa L220/sBI.txt"tine/sarch">L220/>t22v3.a> (6) If int rrup=s were then savhd>and disabled again (locvk_irq_savh):a 2=v32v34ov onclick=LABI.tx#L221/spa L221/sBI.txt"tine/sarch">L221/>t221>.sta 2=v32v34ov onclick=LABI.tx#L222/spa L222/sBI.txt"tine/sarch">L222/>t222>.st ICC2.Z would be shifted into the srvh variable and masked off a 2=v32v34ov onclick=LABI.tx#L223/spa L223/sBI.txt"tine/sarch">L223/>t223>.st (giving a 1).a 2=v32v34ov onclick=LABI.tx#L224/spa L224/sBI.txt"tine/sarch">L224/>t224>.sta 2=v32v34ov onclick=LABI.tx#L225/spa L225/sBI.txt"tine/sarch">L225/>t225>.st ICC2.Z would then be set to 1 (thus unchanged), and ICC2.C would bea 2=v32v34ov onclick=LABI.tx#L226/spa L226/sBI.txt"tine/sarch">L226/>t226>.st unaffe3ied (ie: 0).a 2=v32v34ov onclick=LABI.tx#L227/spa L227/sBI.txt"tine/sarch">L227/>t227>.sta 2=v32v34ov onclick=LABI.tx#L228/spa L228/sBI.txt"tine/sarch">L228/>t228>.st (7) If int rrup=s were then restored from earce (6) (locvk_irq_restore):a 2=v32v34ov onclick=LABI.tx#L229/spa L229/sBI.txt"tine/sarch">L229/>t229>.sta 2=v32v34ov onclick=LABI.tx#L230/spa L230/sBI.txt"tine/sarch">L230/>t230>.st ICC2.Z would be set to indicv3e the result of XOR'ing the saveda 2=v32v34ov onclick=LABI.tx#L231/spa L231/sBI.txt"tine/sarch">L231/>t231>.st 11 2=v32v34ov onclick=LABI.tx#L232/spa L232/sBI.txt"tine/sarch">L232/>t232>.st ICC2.Z set.a 2=v32v34ov onclick=LABI.tx#L233/spa L233/sBI.txt"tine/sarch">L233/>t233>.sta 2=v32v34ov onclick=LABI.tx#L234/spa L234/sBI.txt"tine/sarch">L234/>t234>.st ICC2.C would remain unaffe3ied (ie: 0).a 2=v32v34ov onclick=LABI.tx#L235/spa L235/sBI.txt"tine/sarch">L235/>t235>.sta 2=v32v34ov onclick=LABI.tx#L236/spa L236/sBI.txt"tine/sarch">L236/>t236>.st A TIHI #2 instru3inpu would be used to again .txay the curr 2= earce,a 2=v32v34ov onclick=LABI.tx#L237/spa L237/sBI.txt"tine/sarch">L237/>t237>.st bionst t would ti nothing as Z==1.a 2=v32v34ov onclick=LABI.tx#L238/spa L238/sBI.txt"tine/sarch">L238/>t238>.sta 2=v32v34ov onclick=LABI.tx#L239/spa L239/sBI.txt"tine/sarch">L239/>t239>.st (8) If int rrup=s were then enabled (locvk_irq_enable):a 2=v32v34ov onclick=LABI.tx#L240/spa L240/sBI.txt"tine/sarch">L240/>t240>.sta 2=v32v34ov onclick=LABI.tx#L241/spa L241/sBI.txt"tine/sarch">L241/>t241>.st ICC2.Z would be cleared. ICC2.C would be left unaffe3ied. Botha 2=v32v34ov onclick=LABI.tx#L242/spa L242/sBI.txt"tine/sarch">L242/>t242>.st flags would now be 0.a 2=v32v34ov onclick=LABI.tx#L243/spa L243/sBI.txt"tine/sarch">L243/>t243>.sta 2=v32v34ov onclick=LABI.tx#L244/spa L244/sBI.txt"tine/sarch">L244/>t244>.st A TIHI #2 instru3inpu again issued to atxay the curr 2= earce woulda 2=v32v34ov onclick=LABI.tx#L245/spa L245/sBI.txt"tine/sarch">L245/>t245>.st then trap as both Z==0 [int rrup=s virtually enabled] and C==0a 2=v32v34ov onclick=LABI.tx#L246/spa L246/sBI.txt"tine/sarch">L246/>t246>.st [int rrup=s really disabled] would then be true.a 2=v32v34ov onclick=LABI.tx#L247/spa L247/sBI.txt"tine/sarch">L247/>t247>.sta 2=v32v34ov onclick=LABI.tx#L248/spa L248/sBI.txt"tine/sarch">L248/>t248>.st (9) The trap #2 handter would nimply enable hardware int rrup=s a 2=v32v34ov onclick=LABI.tx#L249/spa L249/sBI.txt"tine/sarch">L249/>t249>.st (set PSR.PIL to 0), set ICC2.C to 1 and reion".a 2=v32v34ov onclick=LABI.tx#L250/spa L250/sBI.txt"tine/sarch">L250/>t250>.sta 2=v32v34ov onclick=LABI.tx#L251/spa L251/sBI.txt"tine/sarch">L251/>t251>.st(10) Immediately upon reion"ing, the pending int rrup= would be takhn.a 2=v32v34ov onclick=LABI.tx#L252/spa L252/sBI.txt"tine/sarch">L252/>t252>.sta 2=v32v34ov onclick=LABI.tx#L253/spa L253/sBI.txt"tine/sarch">L253/>t253>.st(11) The int rrup= handter would takh the path of actually processing thea 2=v32v34ov onclick=LABI.tx#L254/spa L254/sBI.txt"tine/sarch">L254/>t254>.st int rrup= (ICC2.Z is clear, BEQ fails as per st p (2)).a 2=v32v34ov onclick=LABI.tx#L255/spa L255/sBI.txt"tine/sarch">L255/>t255>.sta 2=v32v34ov onclick=LABI.tx#L256/spa L256/sBI.txt"tine/sarch">L256/>t256>.st(12) The int rrup= handter would then set ICC2.C to 1 since hardwarea 2=v32v34ov onclick=LABI.tx#L257/spa L257/sBI.txt"tine/sarch">L257/>t257>.st int rrup=s are definitely enabled - or else the nclick wouldn't be here.a 2=v32v34ov onclick=LABI.tx#L258/spa L258/sBI.txt"tine/sarch">L258/>t258>.sta 2=v32v34ov onclick=LABI.tx#L259/spa L259/sBI.txt"tine/sarch">L259/>t259>.st(13) On reion" from the int rrup= handter, ut ngs would be back to earce (1).a 2=v32v34ov onclick=LABI.tx#L260/spa L260/sBI.txt"tine/sarch">L260/>t260>.sta 2=v32v34ov onclick=LABI.tx#L261/spa L261/sBI.txt"tine/sarch">L261/>t261>.stTt t trap (#2) t only available in nclick mode. In user mode it willa 2=v32v34ov onclick=LABI.tx#L262/spa L262/sBI.txt"tine/sarch">L262/>t262>.stresult in SIGILL.a 2=v32v34ov onclick=LABI.tx#L263/spa L263/sBI.txt"tine/sarch">L263/>t263>.st
The origi3ak LXR software by the LXR community>.st,nst t experi 2=vl versnpu by lxr@tinux.no>.st.
lxr.tinux.no kindty hosted by Redpill Linpro AS>.st,nprovider of Linux consulting and operv32v3s services since 1995.