linux/include/linux/dmar.h
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   1/*
   2 * Copyright (c) 2006, Intel Corporation.
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms and conditions of the GNU General Public License,
   6 * version 2, as published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope it will be useful, but WITHOUT
   9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11 * more details.
  12 *
  13 * You should have received a copy of the GNU General Public License along with
  14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  15 * Place - Suite 330, Boston, MA 02111-1307 USA.
  16 *
  17 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
  18 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
  19 */
  20
  21#ifndef __DMAR_H__
  22#define __DMAR_H__
  23
  24#include <linux/acpi.h>
  25#include <linux/types.h>
  26#include <linux/msi.h>
  27#include <linux/irqreturn.h>
  28
  29struct acpi_dmar_header;
  30
  31/* DMAR Flags */
  32#define DMAR_INTR_REMAP         0x1
  33#define DMAR_X2APIC_OPT_OUT     0x2
  34
  35struct intel_iommu;
  36#ifdef CONFIG_DMAR_TABLE
  37extern struct acpi_table_header *dmar_tbl;
  38struct dmar_drhd_unit {
  39        struct list_head list;          /* list of drhd units   */
  40        struct  acpi_dmar_header *hdr;  /* ACPI header          */
  41        u64     reg_base_addr;          /* register base address*/
  42        struct  pci_dev **devices;      /* target device array  */
  43        int     devices_cnt;            /* target device count  */
  44        u16     segment;                /* PCI domain           */
  45        u8      ignored:1;              /* ignore drhd          */
  46        u8      include_all:1;
  47        struct intel_iommu *iommu;
  48};
  49
  50extern struct list_head dmar_drhd_units;
  51
  52#define for_each_drhd_unit(drhd) \
  53        list_for_each_entry(drhd, &dmar_drhd_units, list)
  54
  55#define for_each_active_iommu(i, drhd)                                  \
  56        list_for_each_entry(drhd, &dmar_drhd_units, list)               \
  57                if (i=drhd->iommu, drhd->ignored) {} else
  58
  59#define for_each_iommu(i, drhd)                                         \
  60        list_for_each_entry(drhd, &dmar_drhd_units, list)               \
  61                if (i=drhd->iommu, 0) {} else 
  62
  63extern int dmar_table_init(void);
  64extern int dmar_dev_scope_init(void);
  65
  66/* Intel IOMMU detection */
  67extern int detect_intel_iommu(void);
  68extern int enable_drhd_fault_handling(void);
  69
  70extern int parse_ioapics_under_ir(void);
  71extern int alloc_iommu(struct dmar_drhd_unit *);
  72#else
  73static inline int detect_intel_iommu(void)
  74{
  75        return -ENODEV;
  76}
  77
  78static inline int dmar_table_init(void)
  79{
  80        return -ENODEV;
  81}
  82static inline int enable_drhd_fault_handling(void)
  83{
  84        return -1;
  85}
  86#endif /* !CONFIG_DMAR_TABLE */
  87
  88struct irte {
  89        union {
  90                struct {
  91                        __u64   present         : 1,
  92                                fpd             : 1,
  93                                dst_mode        : 1,
  94                                redir_hint      : 1,
  95                                trigger_mode    : 1,
  96                                dlvry_mode      : 3,
  97                                avail           : 4,
  98                                __reserved_1    : 4,
  99                                vector          : 8,
 100                                __reserved_2    : 8,
 101                                dest_id         : 32;
 102                };
 103                __u64 low;
 104        };
 105
 106        union {
 107                struct {
 108                        __u64   sid             : 16,
 109                                sq              : 2,
 110                                svt             : 2,
 111                                __reserved_3    : 44;
 112                };
 113                __u64 high;
 114        };
 115};
 116
 117enum {
 118        IRQ_REMAP_XAPIC_MODE,
 119        IRQ_REMAP_X2APIC_MODE,
 120};
 121
 122/* Can't use the common MSI interrupt functions
 123 * since DMAR is not a pci device
 124 */
 125struct irq_data;
 126extern void dmar_msi_unmask(struct irq_data *data);
 127extern void dmar_msi_mask(struct irq_data *data);
 128extern void dmar_msi_read(int irq, struct msi_msg *msg);
 129extern void dmar_msi_write(int irq, struct msi_msg *msg);
 130extern int dmar_set_interrupt(struct intel_iommu *iommu);
 131extern irqreturn_t dmar_fault(int irq, void *dev_id);
 132extern int arch_setup_dmar_msi(unsigned int irq);
 133
 134#ifdef CONFIG_INTEL_IOMMU
 135extern int iommu_detected, no_iommu;
 136extern struct list_head dmar_rmrr_units;
 137struct dmar_rmrr_unit {
 138        struct list_head list;          /* list of rmrr units   */
 139        struct acpi_dmar_header *hdr;   /* ACPI header          */
 140        u64     base_address;           /* reserved base address*/
 141        u64     end_address;            /* reserved end address */
 142        struct pci_dev **devices;       /* target devices */
 143        int     devices_cnt;            /* target device count */
 144};
 145
 146#define for_each_rmrr_units(rmrr) \
 147        list_for_each_entry(rmrr, &dmar_rmrr_units, list)
 148
 149struct dmar_atsr_unit {
 150        struct list_head list;          /* list of ATSR units */
 151        struct acpi_dmar_header *hdr;   /* ACPI header */
 152        struct pci_dev **devices;       /* target devices */
 153        int devices_cnt;                /* target device count */
 154        u8 include_all:1;               /* include all ports */
 155};
 156
 157int dmar_parse_rmrr_atsr_dev(void);
 158extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header);
 159extern int dmar_parse_one_atsr(struct acpi_dmar_header *header);
 160extern int dmar_parse_dev_scope(void *start, void *end, int *cnt,
 161                                struct pci_dev ***devices, u16 segment);
 162extern int intel_iommu_init(void);
 163#else /* !CONFIG_INTEL_IOMMU: */
 164static inline int intel_iommu_init(void) { return -ENODEV; }
 165static inline int dmar_parse_one_rmrr(struct acpi_dmar_header *header)
 166{
 167        return 0;
 168}
 169static inline int dmar_parse_one_atsr(struct acpi_dmar_header *header)
 170{
 171        return 0;
 172}
 173static inline int dmar_parse_rmrr_atsr_dev(void)
 174{
 175        return 0;
 176}
 177#endif /* CONFIG_INTEL_IOMMU */
 178
 179#endif /* __DMAR_H__ */
 180
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