1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29#if defined(__i386__)
30# define BREAKPOINT() asm(" int $3");
31#else
32# define BREAKPOINT() { }
33#endif
34
35#define MAX_DEVICES 12
36
37#include <linux/module.h>
38#include <linux/errno.h>
39#include <linux/signal.h>
40#include <linux/sched.h>
41#include <linux/timer.h>
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/tty.h>
45#include <linux/tty_flip.h>
46#include <linux/serial.h>
47#include <linux/major.h>
48#include <linux/string.h>
49#include <linux/fcntl.h>
50#include <linux/ptrace.h>
51#include <linux/ioport.h>
52#include <linux/mm.h>
53#include <linux/seq_file.h>
54#include <linux/slab.h>
55#include <linux/netdevice.h>
56#include <linux/vmalloc.h>
57#include <linux/init.h>
58#include <linux/delay.h>
59#include <linux/ioctl.h>
60
61#include <asm/io.h>
62#include <asm/irq.h>
63#include <asm/dma.h>
64#include <linux/bitops.h>
65#include <asm/types.h>
66#include <linux/termios.h>
67#include <linux/workqueue.h>
68#include <linux/hdlc.h>
69#include <linux/synclink.h>
70
71#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72#define SYNCLINK_GENERIC_HDLC 1
73#else
74#define SYNCLINK_GENERIC_HDLC 0
75#endif
76
77#define GET_USER(error,value,addr) error = get_user(value,addr)
78#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79#define PUT_USER(error,value,addr) error = put_user(value,addr)
80#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82#include <asm/uaccess.h>
83
84static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC,
86 0,
87 HDLC_FLAG_UNDERRUN_ABORT15,
88 HDLC_ENCODING_NRZI_SPACE,
89 0,
90 0xff,
91 HDLC_CRC_16_CCITT,
92 HDLC_PREAMBLE_LENGTH_8BITS,
93 HDLC_PREAMBLE_PATTERN_NONE,
94 9600,
95 8,
96 1,
97 ASYNC_PARITY_NONE
98};
99
100
101#define SCABUFSIZE 1024
102#define SCA_MEM_SIZE 0x40000
103#define SCA_BASE_SIZE 512
104#define SCA_REG_SIZE 16
105#define SCA_MAX_PORTS 4
106#define SCAMAXDESC 128
107
108#define BUFFERLISTSIZE 4096
109
110
111typedef struct _SCADESC
112{
113 u16 next;
114 u16 buf_ptr;
115 u8 buf_base;
116 u8 pad1;
117 u16 length;
118 u8 status;
119 u8 pad2;
120} SCADESC, *PSCADESC;
121
122typedef struct _SCADESC_EX
123{
124
125 char *virt_addr;
126 u16 phys_entry;
127} SCADESC_EX, *PSCADESC_EX;
128
129
130
131#define BH_RECEIVE 1
132#define BH_TRANSMIT 2
133#define BH_STATUS 4
134
135#define IO_PIN_SHUTDOWN_LIMIT 100
136
137struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146};
147
148
149
150
151typedef struct _synclinkmp_info {
152 void *if_ptr;
153 int magic;
154 struct tty_port port;
155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait;
158
159 struct mgsl_icount icount;
160
161 int timeout;
162 int x_char;
163 u16 read_status_mask1;
164 u16 read_status_mask2;
165 unsigned char ignore_status_mask1;
166 unsigned char ignore_status_mask2;
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer;
175 struct _synclinkmp_info *next_device;
176 struct timer_list status_timer;
177
178 spinlock_t lock;
179 struct work_struct task;
180
181 u32 max_frame_size;
182
183 u32 pending_bh;
184
185 bool bh_running;
186 int isr_overflow;
187 bool bh_requested;
188
189 int dcd_chkcount;
190 int cts_chkcount;
191 int dsr_chkcount;
192 int ri_chkcount;
193
194 char *buffer_list;
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count;
198 SCADESC *rx_buf_list;
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC];
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count;
203 SCADESC *tx_buf_list;
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC];
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
210 bool rx_enabled;
211 bool rx_overflow;
212
213 bool tx_enabled;
214 bool tx_active;
215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25];
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type;
232
233 unsigned int irq_level;
234 unsigned long irq_flags;
235 bool irq_requested;
236
237 MGSL_PARAMS params;
238
239 unsigned char serial_signals;
240
241 bool irq_occurred;
242 unsigned int init_error;
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base;
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base;
250 u32 phys_sca_base;
251 u32 sca_offset;
252 bool sca_base_requested;
253
254 unsigned char* lcr_base;
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base;
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
262 bool sca_statctrl_requested;
263
264 u32 misc_ctrl_value;
265 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
266 char char_buf[MAX_ASYNC_BUFFER_SIZE];
267 bool drop_rts_on_tx_done;
268
269 struct _input_signal_events input_signal_events;
270
271
272 int netcount;
273 spinlock_t netlock;
274
275#if SYNCLINK_GENERIC_HDLC
276 struct net_device *netdev;
277#endif
278
279} SLMP_INFO;
280
281#define MGSL_MAGIC 0x5401
282
283
284
285
286#define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8)
287#define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8)
288#define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8)
289#define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8)
290
291
292#define LPR 0x00
293#define PABR0 0x02
294#define PABR1 0x03
295#define WCRL 0x04
296#define WCRM 0x05
297#define WCRH 0x06
298#define DPCR 0x08
299#define DMER 0x09
300#define ISR0 0x10
301#define ISR1 0x11
302#define ISR2 0x12
303#define IER0 0x14
304#define IER1 0x15
305#define IER2 0x16
306#define ITCR 0x18
307#define INTVR 0x1a
308#define IMVR 0x1c
309
310
311#define TRB 0x20
312#define TRBL 0x20
313#define TRBH 0x21
314#define SR0 0x22
315#define SR1 0x23
316#define SR2 0x24
317#define SR3 0x25
318#define FST 0x26
319#define IE0 0x28
320#define IE1 0x29
321#define IE2 0x2a
322#define FIE 0x2b
323#define CMD 0x2c
324#define MD0 0x2e
325#define MD1 0x2f
326#define MD2 0x30
327#define CTL 0x31
328#define SA0 0x32
329#define SA1 0x33
330#define IDL 0x34
331#define TMC 0x35
332#define RXS 0x36
333#define TXS 0x37
334#define TRC0 0x38
335#define TRC1 0x39
336#define RRC 0x3a
337#define CST0 0x3c
338#define CST1 0x3d
339
340
341#define TCNT 0x60
342#define TCNTL 0x60
343#define TCNTH 0x61
344#define TCONR 0x62
345#define TCONRL 0x62
346#define TCONRH 0x63
347#define TMCS 0x64
348#define TEPR 0x65
349
350
351#define DARL 0x80
352#define DARH 0x81
353#define DARB 0x82
354#define BAR 0x80
355#define BARL 0x80
356#define BARH 0x81
357#define BARB 0x82
358#define SAR 0x84
359#define SARL 0x84
360#define SARH 0x85
361#define SARB 0x86
362#define CPB 0x86
363#define CDA 0x88
364#define CDAL 0x88
365#define CDAH 0x89
366#define EDA 0x8a
367#define EDAL 0x8a
368#define EDAH 0x8b
369#define BFL 0x8c
370#define BFLL 0x8c
371#define BFLH 0x8d
372#define BCR 0x8e
373#define BCRL 0x8e
374#define BCRH 0x8f
375#define DSR 0x90
376#define DMR 0x91
377#define FCT 0x93
378#define DIR 0x94
379#define DCMD 0x95
380
381
382#define TIMER0 0x00
383#define TIMER1 0x08
384#define TIMER2 0x10
385#define TIMER3 0x18
386#define RXDMA 0x00
387#define TXDMA 0x20
388
389
390#define NOOP 0x00
391#define TXRESET 0x01
392#define TXENABLE 0x02
393#define TXDISABLE 0x03
394#define TXCRCINIT 0x04
395#define TXCRCEXCL 0x05
396#define TXEOM 0x06
397#define TXABORT 0x07
398#define MPON 0x08
399#define TXBUFCLR 0x09
400#define RXRESET 0x11
401#define RXENABLE 0x12
402#define RXDISABLE 0x13
403#define RXCRCINIT 0x14
404#define RXREJECT 0x15
405#define SEARCHMP 0x16
406#define RXCRCEXCL 0x17
407#define RXCRCCALC 0x18
408#define CHRESET 0x21
409#define HUNT 0x31
410
411
412#define SWABORT 0x01
413#define FEICLEAR 0x02
414
415
416#define TXINTE BIT7
417#define RXINTE BIT6
418#define TXRDYE BIT1
419#define RXRDYE BIT0
420
421
422#define UDRN BIT7
423#define IDLE BIT6
424#define SYNCD BIT4
425#define FLGD BIT4
426#define CCTS BIT3
427#define CDCD BIT2
428#define BRKD BIT1
429#define ABTD BIT1
430#define GAPD BIT1
431#define BRKE BIT0
432#define IDLD BIT0
433
434
435#define EOM BIT7
436#define PMP BIT6
437#define SHRT BIT6
438#define PE BIT5
439#define ABT BIT5
440#define FRME BIT4
441#define RBIT BIT4
442#define OVRN BIT3
443#define CRCE BIT2
444
445
446
447
448
449static SLMP_INFO *synclinkmp_device_list = NULL;
450static int synclinkmp_adapter_count = -1;
451static int synclinkmp_device_count = 0;
452
453
454
455
456
457
458static bool break_on_load = 0;
459
460
461
462
463
464static int ttymajor = 0;
465
466
467
468
469static int debug_level = 0;
470static int maxframe[MAX_DEVICES] = {0,};
471
472module_param(break_on_load, bool, 0);
473module_param(ttymajor, int, 0);
474module_param(debug_level, int, 0);
475module_param_array(maxframe, int, NULL, 0);
476
477static char *driver_name = "SyncLink MultiPort driver";
478static char *driver_version = "$Revision: 4.38 $";
479
480static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
481static void synclinkmp_remove_one(struct pci_dev *dev);
482
483static struct pci_device_id synclinkmp_pci_tbl[] = {
484 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
485 { 0, },
486};
487MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
488
489MODULE_LICENSE("GPL");
490
491static struct pci_driver synclinkmp_pci_driver = {
492 .name = "synclinkmp",
493 .id_table = synclinkmp_pci_tbl,
494 .probe = synclinkmp_init_one,
495 .remove = __devexit_p(synclinkmp_remove_one),
496};
497
498
499static struct tty_driver *serial_driver;
500
501
502#define WAKEUP_CHARS 256
503
504
505
506
507static int open(struct tty_struct *tty, struct file * filp);
508static void close(struct tty_struct *tty, struct file * filp);
509static void hangup(struct tty_struct *tty);
510static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
511
512static int write(struct tty_struct *tty, const unsigned char *buf, int count);
513static int put_char(struct tty_struct *tty, unsigned char ch);
514static void send_xchar(struct tty_struct *tty, char ch);
515static void wait_until_sent(struct tty_struct *tty, int timeout);
516static int write_room(struct tty_struct *tty);
517static void flush_chars(struct tty_struct *tty);
518static void flush_buffer(struct tty_struct *tty);
519static void tx_hold(struct tty_struct *tty);
520static void tx_release(struct tty_struct *tty);
521
522static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
523static int chars_in_buffer(struct tty_struct *tty);
524static void throttle(struct tty_struct * tty);
525static void unthrottle(struct tty_struct * tty);
526static int set_break(struct tty_struct *tty, int break_state);
527
528#if SYNCLINK_GENERIC_HDLC
529#define dev_to_port(D) (dev_to_hdlc(D)->priv)
530static void hdlcdev_tx_done(SLMP_INFO *info);
531static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
532static int hdlcdev_init(SLMP_INFO *info);
533static void hdlcdev_exit(SLMP_INFO *info);
534#endif
535
536
537
538static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
539static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
541static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
542static int set_txidle(SLMP_INFO *info, int idle_mode);
543static int tx_enable(SLMP_INFO *info, int enable);
544static int tx_abort(SLMP_INFO *info);
545static int rx_enable(SLMP_INFO *info, int enable);
546static int modem_input_wait(SLMP_INFO *info,int arg);
547static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
548static int tiocmget(struct tty_struct *tty);
549static int tiocmset(struct tty_struct *tty,
550 unsigned int set, unsigned int clear);
551static int set_break(struct tty_struct *tty, int break_state);
552
553static void add_device(SLMP_INFO *info);
554static void device_init(int adapter_num, struct pci_dev *pdev);
555static int claim_resources(SLMP_INFO *info);
556static void release_resources(SLMP_INFO *info);
557
558static int startup(SLMP_INFO *info);
559static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
560static int carrier_raised(struct tty_port *port);
561static void shutdown(SLMP_INFO *info);
562static void program_hw(SLMP_INFO *info);
563static void change_params(SLMP_INFO *info);
564
565static bool init_adapter(SLMP_INFO *info);
566static bool register_test(SLMP_INFO *info);
567static bool irq_test(SLMP_INFO *info);
568static bool loopback_test(SLMP_INFO *info);
569static int adapter_test(SLMP_INFO *info);
570static bool memory_test(SLMP_INFO *info);
571
572static void reset_adapter(SLMP_INFO *info);
573static void reset_port(SLMP_INFO *info);
574static void async_mode(SLMP_INFO *info);
575static void hdlc_mode(SLMP_INFO *info);
576
577static void rx_stop(SLMP_INFO *info);
578static void rx_start(SLMP_INFO *info);
579static void rx_reset_buffers(SLMP_INFO *info);
580static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
581static bool rx_get_frame(SLMP_INFO *info);
582
583static void tx_start(SLMP_INFO *info);
584static void tx_stop(SLMP_INFO *info);
585static void tx_load_fifo(SLMP_INFO *info);
586static void tx_set_idle(SLMP_INFO *info);
587static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
588
589static void get_signals(SLMP_INFO *info);
590static void set_signals(SLMP_INFO *info);
591static void enable_loopback(SLMP_INFO *info, int enable);
592static void set_rate(SLMP_INFO *info, u32 data_rate);
593
594static int bh_action(SLMP_INFO *info);
595static void bh_handler(struct work_struct *work);
596static void bh_receive(SLMP_INFO *info);
597static void bh_transmit(SLMP_INFO *info);
598static void bh_status(SLMP_INFO *info);
599static void isr_timer(SLMP_INFO *info);
600static void isr_rxint(SLMP_INFO *info);
601static void isr_rxrdy(SLMP_INFO *info);
602static void isr_txint(SLMP_INFO *info);
603static void isr_txrdy(SLMP_INFO *info);
604static void isr_rxdmaok(SLMP_INFO *info);
605static void isr_rxdmaerror(SLMP_INFO *info);
606static void isr_txdmaok(SLMP_INFO *info);
607static void isr_txdmaerror(SLMP_INFO *info);
608static void isr_io_pin(SLMP_INFO *info, u16 status);
609
610static int alloc_dma_bufs(SLMP_INFO *info);
611static void free_dma_bufs(SLMP_INFO *info);
612static int alloc_buf_list(SLMP_INFO *info);
613static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
614static int alloc_tmp_rx_buf(SLMP_INFO *info);
615static void free_tmp_rx_buf(SLMP_INFO *info);
616
617static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
618static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
619static void tx_timeout(unsigned long context);
620static void status_timeout(unsigned long context);
621
622static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
623static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
624static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
625static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
626static unsigned char read_status_reg(SLMP_INFO * info);
627static void write_control_reg(SLMP_INFO * info);
628
629
630static unsigned char rx_active_fifo_level = 16;
631static unsigned char tx_active_fifo_level = 16;
632static unsigned char tx_negate_fifo_level = 32;
633
634static u32 misc_ctrl_value = 0x007e4040;
635static u32 lcr1_brdr_value = 0x00800028;
636
637static u32 read_ahead_count = 8;
638
639
640
641
642
643
644
645
646
647
648
649
650static unsigned char dma_priority = 0x04;
651
652
653
654static u32 sca_pci_load_interval = 64;
655
656
657
658
659
660
661
662static void* synclinkmp_get_text_ptr(void);
663static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
664
665static inline int sanity_check(SLMP_INFO *info,
666 char *name, const char *routine)
667{
668#ifdef SANITY_CHECK
669 static const char *badmagic =
670 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
671 static const char *badinfo =
672 "Warning: null synclinkmp_struct for (%s) in %s\n";
673
674 if (!info) {
675 printk(badinfo, name, routine);
676 return 1;
677 }
678 if (info->magic != MGSL_MAGIC) {
679 printk(badmagic, name, routine);
680 return 1;
681 }
682#else
683 if (!info)
684 return 1;
685#endif
686 return 0;
687}
688
689
690
691
692
693
694
695
696
697
698static void ldisc_receive_buf(struct tty_struct *tty,
699 const __u8 *data, char *flags, int count)
700{
701 struct tty_ldisc *ld;
702 if (!tty)
703 return;
704 ld = tty_ldisc_ref(tty);
705 if (ld) {
706 if (ld->ops->receive_buf)
707 ld->ops->receive_buf(tty, data, flags, count);
708 tty_ldisc_deref(ld);
709 }
710}
711
712
713
714
715
716static int open(struct tty_struct *tty, struct file *filp)
717{
718 SLMP_INFO *info;
719 int retval, line;
720 unsigned long flags;
721
722 line = tty->index;
723 if (line >= synclinkmp_device_count) {
724 printk("%s(%d): open with invalid line #%d.\n",
725 __FILE__,__LINE__,line);
726 return -ENODEV;
727 }
728
729 info = synclinkmp_device_list;
730 while(info && info->line != line)
731 info = info->next_device;
732 if (sanity_check(info, tty->name, "open"))
733 return -ENODEV;
734 if ( info->init_error ) {
735 printk("%s(%d):%s device is not allocated, init error=%d\n",
736 __FILE__,__LINE__,info->device_name,info->init_error);
737 return -ENODEV;
738 }
739
740 tty->driver_data = info;
741 info->port.tty = tty;
742
743 if (debug_level >= DEBUG_LEVEL_INFO)
744 printk("%s(%d):%s open(), old ref count = %d\n",
745 __FILE__,__LINE__,tty->driver->name, info->port.count);
746
747
748 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
749 if (info->port.flags & ASYNC_CLOSING)
750 interruptible_sleep_on(&info->port.close_wait);
751 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
752 -EAGAIN : -ERESTARTSYS);
753 goto cleanup;
754 }
755
756 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
757
758 spin_lock_irqsave(&info->netlock, flags);
759 if (info->netcount) {
760 retval = -EBUSY;
761 spin_unlock_irqrestore(&info->netlock, flags);
762 goto cleanup;
763 }
764 info->port.count++;
765 spin_unlock_irqrestore(&info->netlock, flags);
766
767 if (info->port.count == 1) {
768
769 retval = startup(info);
770 if (retval < 0)
771 goto cleanup;
772 }
773
774 retval = block_til_ready(tty, filp, info);
775 if (retval) {
776 if (debug_level >= DEBUG_LEVEL_INFO)
777 printk("%s(%d):%s block_til_ready() returned %d\n",
778 __FILE__,__LINE__, info->device_name, retval);
779 goto cleanup;
780 }
781
782 if (debug_level >= DEBUG_LEVEL_INFO)
783 printk("%s(%d):%s open() success\n",
784 __FILE__,__LINE__, info->device_name);
785 retval = 0;
786
787cleanup:
788 if (retval) {
789 if (tty->count == 1)
790 info->port.tty = NULL;
791 if(info->port.count)
792 info->port.count--;
793 }
794
795 return retval;
796}
797
798
799
800
801static void close(struct tty_struct *tty, struct file *filp)
802{
803 SLMP_INFO * info = tty->driver_data;
804
805 if (sanity_check(info, tty->name, "close"))
806 return;
807
808 if (debug_level >= DEBUG_LEVEL_INFO)
809 printk("%s(%d):%s close() entry, count=%d\n",
810 __FILE__,__LINE__, info->device_name, info->port.count);
811
812 if (tty_port_close_start(&info->port, tty, filp) == 0)
813 goto cleanup;
814
815 mutex_lock(&info->port.mutex);
816 if (info->port.flags & ASYNC_INITIALIZED)
817 wait_until_sent(tty, info->timeout);
818
819 flush_buffer(tty);
820 tty_ldisc_flush(tty);
821 shutdown(info);
822 mutex_unlock(&info->port.mutex);
823
824 tty_port_close_end(&info->port, tty);
825 info->port.tty = NULL;
826cleanup:
827 if (debug_level >= DEBUG_LEVEL_INFO)
828 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
829 tty->driver->name, info->port.count);
830}
831
832
833
834
835static void hangup(struct tty_struct *tty)
836{
837 SLMP_INFO *info = tty->driver_data;
838 unsigned long flags;
839
840 if (debug_level >= DEBUG_LEVEL_INFO)
841 printk("%s(%d):%s hangup()\n",
842 __FILE__,__LINE__, info->device_name );
843
844 if (sanity_check(info, tty->name, "hangup"))
845 return;
846
847 mutex_lock(&info->port.mutex);
848 flush_buffer(tty);
849 shutdown(info);
850
851 spin_lock_irqsave(&info->port.lock, flags);
852 info->port.count = 0;
853 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
854 info->port.tty = NULL;
855 spin_unlock_irqrestore(&info->port.lock, flags);
856 mutex_unlock(&info->port.mutex);
857
858 wake_up_interruptible(&info->port.open_wait);
859}
860
861
862
863static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
864{
865 SLMP_INFO *info = tty->driver_data;
866 unsigned long flags;
867
868 if (debug_level >= DEBUG_LEVEL_INFO)
869 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
870 tty->driver->name );
871
872 change_params(info);
873
874
875 if (old_termios->c_cflag & CBAUD &&
876 !(tty->termios->c_cflag & CBAUD)) {
877 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
878 spin_lock_irqsave(&info->lock,flags);
879 set_signals(info);
880 spin_unlock_irqrestore(&info->lock,flags);
881 }
882
883
884 if (!(old_termios->c_cflag & CBAUD) &&
885 tty->termios->c_cflag & CBAUD) {
886 info->serial_signals |= SerialSignal_DTR;
887 if (!(tty->termios->c_cflag & CRTSCTS) ||
888 !test_bit(TTY_THROTTLED, &tty->flags)) {
889 info->serial_signals |= SerialSignal_RTS;
890 }
891 spin_lock_irqsave(&info->lock,flags);
892 set_signals(info);
893 spin_unlock_irqrestore(&info->lock,flags);
894 }
895
896
897 if (old_termios->c_cflag & CRTSCTS &&
898 !(tty->termios->c_cflag & CRTSCTS)) {
899 tty->hw_stopped = 0;
900 tx_release(tty);
901 }
902}
903
904
905
906
907
908
909
910
911
912
913
914static int write(struct tty_struct *tty,
915 const unsigned char *buf, int count)
916{
917 int c, ret = 0;
918 SLMP_INFO *info = tty->driver_data;
919 unsigned long flags;
920
921 if (debug_level >= DEBUG_LEVEL_INFO)
922 printk("%s(%d):%s write() count=%d\n",
923 __FILE__,__LINE__,info->device_name,count);
924
925 if (sanity_check(info, tty->name, "write"))
926 goto cleanup;
927
928 if (!info->tx_buf)
929 goto cleanup;
930
931 if (info->params.mode == MGSL_MODE_HDLC) {
932 if (count > info->max_frame_size) {
933 ret = -EIO;
934 goto cleanup;
935 }
936 if (info->tx_active)
937 goto cleanup;
938 if (info->tx_count) {
939
940
941 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
942 goto start;
943 }
944 ret = info->tx_count = count;
945 tx_load_dma_buffer(info, buf, count);
946 goto start;
947 }
948
949 for (;;) {
950 c = min_t(int, count,
951 min(info->max_frame_size - info->tx_count - 1,
952 info->max_frame_size - info->tx_put));
953 if (c <= 0)
954 break;
955
956 memcpy(info->tx_buf + info->tx_put, buf, c);
957
958 spin_lock_irqsave(&info->lock,flags);
959 info->tx_put += c;
960 if (info->tx_put >= info->max_frame_size)
961 info->tx_put -= info->max_frame_size;
962 info->tx_count += c;
963 spin_unlock_irqrestore(&info->lock,flags);
964
965 buf += c;
966 count -= c;
967 ret += c;
968 }
969
970 if (info->params.mode == MGSL_MODE_HDLC) {
971 if (count) {
972 ret = info->tx_count = 0;
973 goto cleanup;
974 }
975 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
976 }
977start:
978 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
979 spin_lock_irqsave(&info->lock,flags);
980 if (!info->tx_active)
981 tx_start(info);
982 spin_unlock_irqrestore(&info->lock,flags);
983 }
984
985cleanup:
986 if (debug_level >= DEBUG_LEVEL_INFO)
987 printk( "%s(%d):%s write() returning=%d\n",
988 __FILE__,__LINE__,info->device_name,ret);
989 return ret;
990}
991
992
993
994static int put_char(struct tty_struct *tty, unsigned char ch)
995{
996 SLMP_INFO *info = tty->driver_data;
997 unsigned long flags;
998 int ret = 0;
999
1000 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1001 printk( "%s(%d):%s put_char(%d)\n",
1002 __FILE__,__LINE__,info->device_name,ch);
1003 }
1004
1005 if (sanity_check(info, tty->name, "put_char"))
1006 return 0;
1007
1008 if (!info->tx_buf)
1009 return 0;
1010
1011 spin_lock_irqsave(&info->lock,flags);
1012
1013 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1014 !info->tx_active ) {
1015
1016 if (info->tx_count < info->max_frame_size - 1) {
1017 info->tx_buf[info->tx_put++] = ch;
1018 if (info->tx_put >= info->max_frame_size)
1019 info->tx_put -= info->max_frame_size;
1020 info->tx_count++;
1021 ret = 1;
1022 }
1023 }
1024
1025 spin_unlock_irqrestore(&info->lock,flags);
1026 return ret;
1027}
1028
1029
1030
1031static void send_xchar(struct tty_struct *tty, char ch)
1032{
1033 SLMP_INFO *info = tty->driver_data;
1034 unsigned long flags;
1035
1036 if (debug_level >= DEBUG_LEVEL_INFO)
1037 printk("%s(%d):%s send_xchar(%d)\n",
1038 __FILE__,__LINE__, info->device_name, ch );
1039
1040 if (sanity_check(info, tty->name, "send_xchar"))
1041 return;
1042
1043 info->x_char = ch;
1044 if (ch) {
1045
1046 spin_lock_irqsave(&info->lock,flags);
1047 if (!info->tx_enabled)
1048 tx_start(info);
1049 spin_unlock_irqrestore(&info->lock,flags);
1050 }
1051}
1052
1053
1054
1055static void wait_until_sent(struct tty_struct *tty, int timeout)
1056{
1057 SLMP_INFO * info = tty->driver_data;
1058 unsigned long orig_jiffies, char_time;
1059
1060 if (!info )
1061 return;
1062
1063 if (debug_level >= DEBUG_LEVEL_INFO)
1064 printk("%s(%d):%s wait_until_sent() entry\n",
1065 __FILE__,__LINE__, info->device_name );
1066
1067 if (sanity_check(info, tty->name, "wait_until_sent"))
1068 return;
1069
1070 if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags))
1071 goto exit;
1072
1073 orig_jiffies = jiffies;
1074
1075
1076
1077
1078
1079
1080
1081 if ( info->params.data_rate ) {
1082 char_time = info->timeout/(32 * 5);
1083 if (!char_time)
1084 char_time++;
1085 } else
1086 char_time = 1;
1087
1088 if (timeout)
1089 char_time = min_t(unsigned long, char_time, timeout);
1090
1091 if ( info->params.mode == MGSL_MODE_HDLC ) {
1092 while (info->tx_active) {
1093 msleep_interruptible(jiffies_to_msecs(char_time));
1094 if (signal_pending(current))
1095 break;
1096 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1097 break;
1098 }
1099 } else {
1100
1101
1102
1103
1104 while ( info->tx_active && info->tx_enabled) {
1105 msleep_interruptible(jiffies_to_msecs(char_time));
1106 if (signal_pending(current))
1107 break;
1108 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1109 break;
1110 }
1111 }
1112
1113exit:
1114 if (debug_level >= DEBUG_LEVEL_INFO)
1115 printk("%s(%d):%s wait_until_sent() exit\n",
1116 __FILE__,__LINE__, info->device_name );
1117}
1118
1119
1120
1121static int write_room(struct tty_struct *tty)
1122{
1123 SLMP_INFO *info = tty->driver_data;
1124 int ret;
1125
1126 if (sanity_check(info, tty->name, "write_room"))
1127 return 0;
1128
1129 if (info->params.mode == MGSL_MODE_HDLC) {
1130 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1131 } else {
1132 ret = info->max_frame_size - info->tx_count - 1;
1133 if (ret < 0)
1134 ret = 0;
1135 }
1136
1137 if (debug_level >= DEBUG_LEVEL_INFO)
1138 printk("%s(%d):%s write_room()=%d\n",
1139 __FILE__, __LINE__, info->device_name, ret);
1140
1141 return ret;
1142}
1143
1144
1145
1146static void flush_chars(struct tty_struct *tty)
1147{
1148 SLMP_INFO *info = tty->driver_data;
1149 unsigned long flags;
1150
1151 if ( debug_level >= DEBUG_LEVEL_INFO )
1152 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1153 __FILE__,__LINE__,info->device_name,info->tx_count);
1154
1155 if (sanity_check(info, tty->name, "flush_chars"))
1156 return;
1157
1158 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1159 !info->tx_buf)
1160 return;
1161
1162 if ( debug_level >= DEBUG_LEVEL_INFO )
1163 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1164 __FILE__,__LINE__,info->device_name );
1165
1166 spin_lock_irqsave(&info->lock,flags);
1167
1168 if (!info->tx_active) {
1169 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1170 info->tx_count ) {
1171
1172
1173
1174 tx_load_dma_buffer(info,
1175 info->tx_buf,info->tx_count);
1176 }
1177 tx_start(info);
1178 }
1179
1180 spin_unlock_irqrestore(&info->lock,flags);
1181}
1182
1183
1184
1185static void flush_buffer(struct tty_struct *tty)
1186{
1187 SLMP_INFO *info = tty->driver_data;
1188 unsigned long flags;
1189
1190 if (debug_level >= DEBUG_LEVEL_INFO)
1191 printk("%s(%d):%s flush_buffer() entry\n",
1192 __FILE__,__LINE__, info->device_name );
1193
1194 if (sanity_check(info, tty->name, "flush_buffer"))
1195 return;
1196
1197 spin_lock_irqsave(&info->lock,flags);
1198 info->tx_count = info->tx_put = info->tx_get = 0;
1199 del_timer(&info->tx_timer);
1200 spin_unlock_irqrestore(&info->lock,flags);
1201
1202 tty_wakeup(tty);
1203}
1204
1205
1206
1207static void tx_hold(struct tty_struct *tty)
1208{
1209 SLMP_INFO *info = tty->driver_data;
1210 unsigned long flags;
1211
1212 if (sanity_check(info, tty->name, "tx_hold"))
1213 return;
1214
1215 if ( debug_level >= DEBUG_LEVEL_INFO )
1216 printk("%s(%d):%s tx_hold()\n",
1217 __FILE__,__LINE__,info->device_name);
1218
1219 spin_lock_irqsave(&info->lock,flags);
1220 if (info->tx_enabled)
1221 tx_stop(info);
1222 spin_unlock_irqrestore(&info->lock,flags);
1223}
1224
1225
1226
1227static void tx_release(struct tty_struct *tty)
1228{
1229 SLMP_INFO *info = tty->driver_data;
1230 unsigned long flags;
1231
1232 if (sanity_check(info, tty->name, "tx_release"))
1233 return;
1234
1235 if ( debug_level >= DEBUG_LEVEL_INFO )
1236 printk("%s(%d):%s tx_release()\n",
1237 __FILE__,__LINE__,info->device_name);
1238
1239 spin_lock_irqsave(&info->lock,flags);
1240 if (!info->tx_enabled)
1241 tx_start(info);
1242 spin_unlock_irqrestore(&info->lock,flags);
1243}
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255static int ioctl(struct tty_struct *tty,
1256 unsigned int cmd, unsigned long arg)
1257{
1258 SLMP_INFO *info = tty->driver_data;
1259 void __user *argp = (void __user *)arg;
1260
1261 if (debug_level >= DEBUG_LEVEL_INFO)
1262 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1263 info->device_name, cmd );
1264
1265 if (sanity_check(info, tty->name, "ioctl"))
1266 return -ENODEV;
1267
1268 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1269 (cmd != TIOCMIWAIT)) {
1270 if (tty->flags & (1 << TTY_IO_ERROR))
1271 return -EIO;
1272 }
1273
1274 switch (cmd) {
1275 case MGSL_IOCGPARAMS:
1276 return get_params(info, argp);
1277 case MGSL_IOCSPARAMS:
1278 return set_params(info, argp);
1279 case MGSL_IOCGTXIDLE:
1280 return get_txidle(info, argp);
1281 case MGSL_IOCSTXIDLE:
1282 return set_txidle(info, (int)arg);
1283 case MGSL_IOCTXENABLE:
1284 return tx_enable(info, (int)arg);
1285 case MGSL_IOCRXENABLE:
1286 return rx_enable(info, (int)arg);
1287 case MGSL_IOCTXABORT:
1288 return tx_abort(info);
1289 case MGSL_IOCGSTATS:
1290 return get_stats(info, argp);
1291 case MGSL_IOCWAITEVENT:
1292 return wait_mgsl_event(info, argp);
1293 case MGSL_IOCLOOPTXDONE:
1294 return 0;
1295
1296
1297
1298 case TIOCMIWAIT:
1299 return modem_input_wait(info,(int)arg);
1300
1301
1302
1303
1304
1305
1306
1307 default:
1308 return -ENOIOCTLCMD;
1309 }
1310 return 0;
1311}
1312
1313static int get_icount(struct tty_struct *tty,
1314 struct serial_icounter_struct *icount)
1315{
1316 SLMP_INFO *info = tty->driver_data;
1317 struct mgsl_icount cnow;
1318 unsigned long flags;
1319
1320 spin_lock_irqsave(&info->lock,flags);
1321 cnow = info->icount;
1322 spin_unlock_irqrestore(&info->lock,flags);
1323
1324 icount->cts = cnow.cts;
1325 icount->dsr = cnow.dsr;
1326 icount->rng = cnow.rng;
1327 icount->dcd = cnow.dcd;
1328 icount->rx = cnow.rx;
1329 icount->tx = cnow.tx;
1330 icount->frame = cnow.frame;
1331 icount->overrun = cnow.overrun;
1332 icount->parity = cnow.parity;
1333 icount->brk = cnow.brk;
1334 icount->buf_overrun = cnow.buf_overrun;
1335
1336 return 0;
1337}
1338
1339
1340
1341
1342
1343static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1344{
1345 char stat_buf[30];
1346 unsigned long flags;
1347
1348 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1349 "\tIRQ=%d MaxFrameSize=%u\n",
1350 info->device_name,
1351 info->phys_sca_base,
1352 info->phys_memory_base,
1353 info->phys_statctrl_base,
1354 info->phys_lcr_base,
1355 info->irq_level,
1356 info->max_frame_size );
1357
1358
1359 spin_lock_irqsave(&info->lock,flags);
1360 get_signals(info);
1361 spin_unlock_irqrestore(&info->lock,flags);
1362
1363 stat_buf[0] = 0;
1364 stat_buf[1] = 0;
1365 if (info->serial_signals & SerialSignal_RTS)
1366 strcat(stat_buf, "|RTS");
1367 if (info->serial_signals & SerialSignal_CTS)
1368 strcat(stat_buf, "|CTS");
1369 if (info->serial_signals & SerialSignal_DTR)
1370 strcat(stat_buf, "|DTR");
1371 if (info->serial_signals & SerialSignal_DSR)
1372 strcat(stat_buf, "|DSR");
1373 if (info->serial_signals & SerialSignal_DCD)
1374 strcat(stat_buf, "|CD");
1375 if (info->serial_signals & SerialSignal_RI)
1376 strcat(stat_buf, "|RI");
1377
1378 if (info->params.mode == MGSL_MODE_HDLC) {
1379 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1380 info->icount.txok, info->icount.rxok);
1381 if (info->icount.txunder)
1382 seq_printf(m, " txunder:%d", info->icount.txunder);
1383 if (info->icount.txabort)
1384 seq_printf(m, " txabort:%d", info->icount.txabort);
1385 if (info->icount.rxshort)
1386 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1387 if (info->icount.rxlong)
1388 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1389 if (info->icount.rxover)
1390 seq_printf(m, " rxover:%d", info->icount.rxover);
1391 if (info->icount.rxcrc)
1392 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1393 } else {
1394 seq_printf(m, "\tASYNC tx:%d rx:%d",
1395 info->icount.tx, info->icount.rx);
1396 if (info->icount.frame)
1397 seq_printf(m, " fe:%d", info->icount.frame);
1398 if (info->icount.parity)
1399 seq_printf(m, " pe:%d", info->icount.parity);
1400 if (info->icount.brk)
1401 seq_printf(m, " brk:%d", info->icount.brk);
1402 if (info->icount.overrun)
1403 seq_printf(m, " oe:%d", info->icount.overrun);
1404 }
1405
1406
1407 seq_printf(m, " %s\n", stat_buf+1);
1408
1409 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1410 info->tx_active,info->bh_requested,info->bh_running,
1411 info->pending_bh);
1412}
1413
1414
1415
1416static int synclinkmp_proc_show(struct seq_file *m, void *v)
1417{
1418 SLMP_INFO *info;
1419
1420 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1421
1422 info = synclinkmp_device_list;
1423 while( info ) {
1424 line_info(m, info);
1425 info = info->next_device;
1426 }
1427 return 0;
1428}
1429
1430static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1431{
1432 return single_open(file, synclinkmp_proc_show, NULL);
1433}
1434
1435static const struct file_operations synclinkmp_proc_fops = {
1436 .owner = THIS_MODULE,
1437 .open = synclinkmp_proc_open,
1438 .read = seq_read,
1439 .llseek = seq_lseek,
1440 .release = single_release,
1441};
1442
1443
1444
1445static int chars_in_buffer(struct tty_struct *tty)
1446{
1447 SLMP_INFO *info = tty->driver_data;
1448
1449 if (sanity_check(info, tty->name, "chars_in_buffer"))
1450 return 0;
1451
1452 if (debug_level >= DEBUG_LEVEL_INFO)
1453 printk("%s(%d):%s chars_in_buffer()=%d\n",
1454 __FILE__, __LINE__, info->device_name, info->tx_count);
1455
1456 return info->tx_count;
1457}
1458
1459
1460
1461static void throttle(struct tty_struct * tty)
1462{
1463 SLMP_INFO *info = tty->driver_data;
1464 unsigned long flags;
1465
1466 if (debug_level >= DEBUG_LEVEL_INFO)
1467 printk("%s(%d):%s throttle() entry\n",
1468 __FILE__,__LINE__, info->device_name );
1469
1470 if (sanity_check(info, tty->name, "throttle"))
1471 return;
1472
1473 if (I_IXOFF(tty))
1474 send_xchar(tty, STOP_CHAR(tty));
1475
1476 if (tty->termios->c_cflag & CRTSCTS) {
1477 spin_lock_irqsave(&info->lock,flags);
1478 info->serial_signals &= ~SerialSignal_RTS;
1479 set_signals(info);
1480 spin_unlock_irqrestore(&info->lock,flags);
1481 }
1482}
1483
1484
1485
1486static void unthrottle(struct tty_struct * tty)
1487{
1488 SLMP_INFO *info = tty->driver_data;
1489 unsigned long flags;
1490
1491 if (debug_level >= DEBUG_LEVEL_INFO)
1492 printk("%s(%d):%s unthrottle() entry\n",
1493 __FILE__,__LINE__, info->device_name );
1494
1495 if (sanity_check(info, tty->name, "unthrottle"))
1496 return;
1497
1498 if (I_IXOFF(tty)) {
1499 if (info->x_char)
1500 info->x_char = 0;
1501 else
1502 send_xchar(tty, START_CHAR(tty));
1503 }
1504
1505 if (tty->termios->c_cflag & CRTSCTS) {
1506 spin_lock_irqsave(&info->lock,flags);
1507 info->serial_signals |= SerialSignal_RTS;
1508 set_signals(info);
1509 spin_unlock_irqrestore(&info->lock,flags);
1510 }
1511}
1512
1513
1514
1515
1516static int set_break(struct tty_struct *tty, int break_state)
1517{
1518 unsigned char RegValue;
1519 SLMP_INFO * info = tty->driver_data;
1520 unsigned long flags;
1521
1522 if (debug_level >= DEBUG_LEVEL_INFO)
1523 printk("%s(%d):%s set_break(%d)\n",
1524 __FILE__,__LINE__, info->device_name, break_state);
1525
1526 if (sanity_check(info, tty->name, "set_break"))
1527 return -EINVAL;
1528
1529 spin_lock_irqsave(&info->lock,flags);
1530 RegValue = read_reg(info, CTL);
1531 if (break_state == -1)
1532 RegValue |= BIT3;
1533 else
1534 RegValue &= ~BIT3;
1535 write_reg(info, CTL, RegValue);
1536 spin_unlock_irqrestore(&info->lock,flags);
1537 return 0;
1538}
1539
1540#if SYNCLINK_GENERIC_HDLC
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1553 unsigned short parity)
1554{
1555 SLMP_INFO *info = dev_to_port(dev);
1556 unsigned char new_encoding;
1557 unsigned short new_crctype;
1558
1559
1560 if (info->port.count)
1561 return -EBUSY;
1562
1563 switch (encoding)
1564 {
1565 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1566 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1567 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1568 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1569 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1570 default: return -EINVAL;
1571 }
1572
1573 switch (parity)
1574 {
1575 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1576 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1577 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1578 default: return -EINVAL;
1579 }
1580
1581 info->params.encoding = new_encoding;
1582 info->params.crc_type = new_crctype;
1583
1584
1585 if (info->netcount)
1586 program_hw(info);
1587
1588 return 0;
1589}
1590
1591
1592
1593
1594
1595
1596
1597static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1598 struct net_device *dev)
1599{
1600 SLMP_INFO *info = dev_to_port(dev);
1601 unsigned long flags;
1602
1603 if (debug_level >= DEBUG_LEVEL_INFO)
1604 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1605
1606
1607 netif_stop_queue(dev);
1608
1609
1610 info->tx_count = skb->len;
1611 tx_load_dma_buffer(info, skb->data, skb->len);
1612
1613
1614 dev->stats.tx_packets++;
1615 dev->stats.tx_bytes += skb->len;
1616
1617
1618 dev_kfree_skb(skb);
1619
1620
1621 dev->trans_start = jiffies;
1622
1623
1624 spin_lock_irqsave(&info->lock,flags);
1625 if (!info->tx_active)
1626 tx_start(info);
1627 spin_unlock_irqrestore(&info->lock,flags);
1628
1629 return NETDEV_TX_OK;
1630}
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640static int hdlcdev_open(struct net_device *dev)
1641{
1642 SLMP_INFO *info = dev_to_port(dev);
1643 int rc;
1644 unsigned long flags;
1645
1646 if (debug_level >= DEBUG_LEVEL_INFO)
1647 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1648
1649
1650 if ((rc = hdlc_open(dev)))
1651 return rc;
1652
1653
1654 spin_lock_irqsave(&info->netlock, flags);
1655 if (info->port.count != 0 || info->netcount != 0) {
1656 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1657 spin_unlock_irqrestore(&info->netlock, flags);
1658 return -EBUSY;
1659 }
1660 info->netcount=1;
1661 spin_unlock_irqrestore(&info->netlock, flags);
1662
1663
1664 if ((rc = startup(info)) != 0) {
1665 spin_lock_irqsave(&info->netlock, flags);
1666 info->netcount=0;
1667 spin_unlock_irqrestore(&info->netlock, flags);
1668 return rc;
1669 }
1670
1671
1672 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1673 program_hw(info);
1674
1675
1676 dev->trans_start = jiffies;
1677 netif_start_queue(dev);
1678
1679
1680 spin_lock_irqsave(&info->lock, flags);
1681 get_signals(info);
1682 spin_unlock_irqrestore(&info->lock, flags);
1683 if (info->serial_signals & SerialSignal_DCD)
1684 netif_carrier_on(dev);
1685 else
1686 netif_carrier_off(dev);
1687 return 0;
1688}
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698static int hdlcdev_close(struct net_device *dev)
1699{
1700 SLMP_INFO *info = dev_to_port(dev);
1701 unsigned long flags;
1702
1703 if (debug_level >= DEBUG_LEVEL_INFO)
1704 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1705
1706 netif_stop_queue(dev);
1707
1708
1709 shutdown(info);
1710
1711 hdlc_close(dev);
1712
1713 spin_lock_irqsave(&info->netlock, flags);
1714 info->netcount=0;
1715 spin_unlock_irqrestore(&info->netlock, flags);
1716
1717 return 0;
1718}
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1730{
1731 const size_t size = sizeof(sync_serial_settings);
1732 sync_serial_settings new_line;
1733 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1734 SLMP_INFO *info = dev_to_port(dev);
1735 unsigned int flags;
1736
1737 if (debug_level >= DEBUG_LEVEL_INFO)
1738 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1739
1740
1741 if (info->port.count)
1742 return -EBUSY;
1743
1744 if (cmd != SIOCWANDEV)
1745 return hdlc_ioctl(dev, ifr, cmd);
1746
1747 switch(ifr->ifr_settings.type) {
1748 case IF_GET_IFACE:
1749
1750 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1751 if (ifr->ifr_settings.size < size) {
1752 ifr->ifr_settings.size = size;
1753 return -ENOBUFS;
1754 }
1755
1756 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1757 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1758 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1759 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1760
1761 switch (flags){
1762 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1763 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1764 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1765 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1766 default: new_line.clock_type = CLOCK_DEFAULT;
1767 }
1768
1769 new_line.clock_rate = info->params.clock_speed;
1770 new_line.loopback = info->params.loopback ? 1:0;
1771
1772 if (copy_to_user(line, &new_line, size))
1773 return -EFAULT;
1774 return 0;
1775
1776 case IF_IFACE_SYNC_SERIAL:
1777
1778 if(!capable(CAP_NET_ADMIN))
1779 return -EPERM;
1780 if (copy_from_user(&new_line, line, size))
1781 return -EFAULT;
1782
1783 switch (new_line.clock_type)
1784 {
1785 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1786 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1787 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1788 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1789 case CLOCK_DEFAULT: flags = info->params.flags &
1790 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1791 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1792 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1793 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1794 default: return -EINVAL;
1795 }
1796
1797 if (new_line.loopback != 0 && new_line.loopback != 1)
1798 return -EINVAL;
1799
1800 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1801 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1802 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1803 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1804 info->params.flags |= flags;
1805
1806 info->params.loopback = new_line.loopback;
1807
1808 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1809 info->params.clock_speed = new_line.clock_rate;
1810 else
1811 info->params.clock_speed = 0;
1812
1813
1814 if (info->netcount)
1815 program_hw(info);
1816 return 0;
1817
1818 default:
1819 return hdlc_ioctl(dev, ifr, cmd);
1820 }
1821}
1822
1823
1824
1825
1826
1827
1828static void hdlcdev_tx_timeout(struct net_device *dev)
1829{
1830 SLMP_INFO *info = dev_to_port(dev);
1831 unsigned long flags;
1832
1833 if (debug_level >= DEBUG_LEVEL_INFO)
1834 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1835
1836 dev->stats.tx_errors++;
1837 dev->stats.tx_aborted_errors++;
1838
1839 spin_lock_irqsave(&info->lock,flags);
1840 tx_stop(info);
1841 spin_unlock_irqrestore(&info->lock,flags);
1842
1843 netif_wake_queue(dev);
1844}
1845
1846
1847
1848
1849
1850
1851
1852static void hdlcdev_tx_done(SLMP_INFO *info)
1853{
1854 if (netif_queue_stopped(info->netdev))
1855 netif_wake_queue(info->netdev);
1856}
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1867{
1868 struct sk_buff *skb = dev_alloc_skb(size);
1869 struct net_device *dev = info->netdev;
1870
1871 if (debug_level >= DEBUG_LEVEL_INFO)
1872 printk("hdlcdev_rx(%s)\n",dev->name);
1873
1874 if (skb == NULL) {
1875 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1876 dev->name);
1877 dev->stats.rx_dropped++;
1878 return;
1879 }
1880
1881 memcpy(skb_put(skb, size), buf, size);
1882
1883 skb->protocol = hdlc_type_trans(skb, dev);
1884
1885 dev->stats.rx_packets++;
1886 dev->stats.rx_bytes += size;
1887
1888 netif_rx(skb);
1889}
1890
1891static const struct net_device_ops hdlcdev_ops = {
1892 .ndo_open = hdlcdev_open,
1893 .ndo_stop = hdlcdev_close,
1894 .ndo_change_mtu = hdlc_change_mtu,
1895 .ndo_start_xmit = hdlc_start_xmit,
1896 .ndo_do_ioctl = hdlcdev_ioctl,
1897 .ndo_tx_timeout = hdlcdev_tx_timeout,
1898};
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908static int hdlcdev_init(SLMP_INFO *info)
1909{
1910 int rc;
1911 struct net_device *dev;
1912 hdlc_device *hdlc;
1913
1914
1915
1916 if (!(dev = alloc_hdlcdev(info))) {
1917 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1918 return -ENOMEM;
1919 }
1920
1921
1922 dev->mem_start = info->phys_sca_base;
1923 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1924 dev->irq = info->irq_level;
1925
1926
1927 dev->netdev_ops = &hdlcdev_ops;
1928 dev->watchdog_timeo = 10 * HZ;
1929 dev->tx_queue_len = 50;
1930
1931
1932 hdlc = dev_to_hdlc(dev);
1933 hdlc->attach = hdlcdev_attach;
1934 hdlc->xmit = hdlcdev_xmit;
1935
1936
1937 if ((rc = register_hdlc_device(dev))) {
1938 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1939 free_netdev(dev);
1940 return rc;
1941 }
1942
1943 info->netdev = dev;
1944 return 0;
1945}
1946
1947
1948
1949
1950
1951
1952
1953static void hdlcdev_exit(SLMP_INFO *info)
1954{
1955 unregister_hdlc_device(info->netdev);
1956 free_netdev(info->netdev);
1957 info->netdev = NULL;
1958}
1959
1960#endif
1961
1962
1963
1964
1965
1966static int bh_action(SLMP_INFO *info)
1967{
1968 unsigned long flags;
1969 int rc = 0;
1970
1971 spin_lock_irqsave(&info->lock,flags);
1972
1973 if (info->pending_bh & BH_RECEIVE) {
1974 info->pending_bh &= ~BH_RECEIVE;
1975 rc = BH_RECEIVE;
1976 } else if (info->pending_bh & BH_TRANSMIT) {
1977 info->pending_bh &= ~BH_TRANSMIT;
1978 rc = BH_TRANSMIT;
1979 } else if (info->pending_bh & BH_STATUS) {
1980 info->pending_bh &= ~BH_STATUS;
1981 rc = BH_STATUS;
1982 }
1983
1984 if (!rc) {
1985
1986 info->bh_running = false;
1987 info->bh_requested = false;
1988 }
1989
1990 spin_unlock_irqrestore(&info->lock,flags);
1991
1992 return rc;
1993}
1994
1995
1996
1997static void bh_handler(struct work_struct *work)
1998{
1999 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2000 int action;
2001
2002 if (!info)
2003 return;
2004
2005 if ( debug_level >= DEBUG_LEVEL_BH )
2006 printk( "%s(%d):%s bh_handler() entry\n",
2007 __FILE__,__LINE__,info->device_name);
2008
2009 info->bh_running = true;
2010
2011 while((action = bh_action(info)) != 0) {
2012
2013
2014 if ( debug_level >= DEBUG_LEVEL_BH )
2015 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2016 __FILE__,__LINE__,info->device_name, action);
2017
2018 switch (action) {
2019
2020 case BH_RECEIVE:
2021 bh_receive(info);
2022 break;
2023 case BH_TRANSMIT:
2024 bh_transmit(info);
2025 break;
2026 case BH_STATUS:
2027 bh_status(info);
2028 break;
2029 default:
2030
2031 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2032 __FILE__,__LINE__,info->device_name,action);
2033 break;
2034 }
2035 }
2036
2037 if ( debug_level >= DEBUG_LEVEL_BH )
2038 printk( "%s(%d):%s bh_handler() exit\n",
2039 __FILE__,__LINE__,info->device_name);
2040}
2041
2042static void bh_receive(SLMP_INFO *info)
2043{
2044 if ( debug_level >= DEBUG_LEVEL_BH )
2045 printk( "%s(%d):%s bh_receive()\n",
2046 __FILE__,__LINE__,info->device_name);
2047
2048 while( rx_get_frame(info) );
2049}
2050
2051static void bh_transmit(SLMP_INFO *info)
2052{
2053 struct tty_struct *tty = info->port.tty;
2054
2055 if ( debug_level >= DEBUG_LEVEL_BH )
2056 printk( "%s(%d):%s bh_transmit() entry\n",
2057 __FILE__,__LINE__,info->device_name);
2058
2059 if (tty)
2060 tty_wakeup(tty);
2061}
2062
2063static void bh_status(SLMP_INFO *info)
2064{
2065 if ( debug_level >= DEBUG_LEVEL_BH )
2066 printk( "%s(%d):%s bh_status() entry\n",
2067 __FILE__,__LINE__,info->device_name);
2068
2069 info->ri_chkcount = 0;
2070 info->dsr_chkcount = 0;
2071 info->dcd_chkcount = 0;
2072 info->cts_chkcount = 0;
2073}
2074
2075static void isr_timer(SLMP_INFO * info)
2076{
2077 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2078
2079
2080 write_reg(info, IER2, 0);
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092 write_reg(info, (unsigned char)(timer + TMCS), 0);
2093
2094 info->irq_occurred = true;
2095
2096 if ( debug_level >= DEBUG_LEVEL_ISR )
2097 printk("%s(%d):%s isr_timer()\n",
2098 __FILE__,__LINE__,info->device_name);
2099}
2100
2101static void isr_rxint(SLMP_INFO * info)
2102{
2103 struct tty_struct *tty = info->port.tty;
2104 struct mgsl_icount *icount = &info->icount;
2105 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2106 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2107
2108
2109 if (status)
2110 write_reg(info, SR1, status);
2111
2112 if (status2)
2113 write_reg(info, SR2, status2);
2114
2115 if ( debug_level >= DEBUG_LEVEL_ISR )
2116 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2117 __FILE__,__LINE__,info->device_name,status,status2);
2118
2119 if (info->params.mode == MGSL_MODE_ASYNC) {
2120 if (status & BRKD) {
2121 icount->brk++;
2122
2123
2124
2125
2126 if ( tty ) {
2127 if (!(status & info->ignore_status_mask1)) {
2128 if (info->read_status_mask1 & BRKD) {
2129 tty_insert_flip_char(tty, 0, TTY_BREAK);
2130 if (info->port.flags & ASYNC_SAK)
2131 do_SAK(tty);
2132 }
2133 }
2134 }
2135 }
2136 }
2137 else {
2138 if (status & (FLGD|IDLD)) {
2139 if (status & FLGD)
2140 info->icount.exithunt++;
2141 else if (status & IDLD)
2142 info->icount.rxidle++;
2143 wake_up_interruptible(&info->event_wait_q);
2144 }
2145 }
2146
2147 if (status & CDCD) {
2148
2149
2150
2151 get_signals( info );
2152 isr_io_pin(info,
2153 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2154 }
2155}
2156
2157
2158
2159
2160static void isr_rxrdy(SLMP_INFO * info)
2161{
2162 u16 status;
2163 unsigned char DataByte;
2164 struct tty_struct *tty = info->port.tty;
2165 struct mgsl_icount *icount = &info->icount;
2166
2167 if ( debug_level >= DEBUG_LEVEL_ISR )
2168 printk("%s(%d):%s isr_rxrdy\n",
2169 __FILE__,__LINE__,info->device_name);
2170
2171 while((status = read_reg(info,CST0)) & BIT0)
2172 {
2173 int flag = 0;
2174 bool over = false;
2175 DataByte = read_reg(info,TRB);
2176
2177 icount->rx++;
2178
2179 if ( status & (PE + FRME + OVRN) ) {
2180 printk("%s(%d):%s rxerr=%04X\n",
2181 __FILE__,__LINE__,info->device_name,status);
2182
2183
2184 if (status & PE)
2185 icount->parity++;
2186 else if (status & FRME)
2187 icount->frame++;
2188 else if (status & OVRN)
2189 icount->overrun++;
2190
2191
2192 if (status & info->ignore_status_mask2)
2193 continue;
2194
2195 status &= info->read_status_mask2;
2196
2197 if ( tty ) {
2198 if (status & PE)
2199 flag = TTY_PARITY;
2200 else if (status & FRME)
2201 flag = TTY_FRAME;
2202 if (status & OVRN) {
2203
2204
2205
2206
2207 over = true;
2208 }
2209 }
2210 }
2211
2212 if ( tty ) {
2213 tty_insert_flip_char(tty, DataByte, flag);
2214 if (over)
2215 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2216 }
2217 }
2218
2219 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2220 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2221 __FILE__,__LINE__,info->device_name,
2222 icount->rx,icount->brk,icount->parity,
2223 icount->frame,icount->overrun);
2224 }
2225
2226 if ( tty )
2227 tty_flip_buffer_push(tty);
2228}
2229
2230static void isr_txeom(SLMP_INFO * info, unsigned char status)
2231{
2232 if ( debug_level >= DEBUG_LEVEL_ISR )
2233 printk("%s(%d):%s isr_txeom status=%02x\n",
2234 __FILE__,__LINE__,info->device_name,status);
2235
2236 write_reg(info, TXDMA + DIR, 0x00);
2237 write_reg(info, TXDMA + DSR, 0xc0);
2238 write_reg(info, TXDMA + DCMD, SWABORT);
2239
2240 if (status & UDRN) {
2241 write_reg(info, CMD, TXRESET);
2242 write_reg(info, CMD, TXENABLE);
2243 } else
2244 write_reg(info, CMD, TXBUFCLR);
2245
2246
2247 info->ie0_value &= ~TXRDYE;
2248 info->ie1_value &= ~(IDLE + UDRN);
2249 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2250 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2251
2252 if ( info->tx_active ) {
2253 if (info->params.mode != MGSL_MODE_ASYNC) {
2254 if (status & UDRN)
2255 info->icount.txunder++;
2256 else if (status & IDLE)
2257 info->icount.txok++;
2258 }
2259
2260 info->tx_active = false;
2261 info->tx_count = info->tx_put = info->tx_get = 0;
2262
2263 del_timer(&info->tx_timer);
2264
2265 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2266 info->serial_signals &= ~SerialSignal_RTS;
2267 info->drop_rts_on_tx_done = false;
2268 set_signals(info);
2269 }
2270
2271#if SYNCLINK_GENERIC_HDLC
2272 if (info->netcount)
2273 hdlcdev_tx_done(info);
2274 else
2275#endif
2276 {
2277 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2278 tx_stop(info);
2279 return;
2280 }
2281 info->pending_bh |= BH_TRANSMIT;
2282 }
2283 }
2284}
2285
2286
2287
2288
2289
2290static void isr_txint(SLMP_INFO * info)
2291{
2292 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2293
2294
2295 write_reg(info, SR1, status);
2296
2297 if ( debug_level >= DEBUG_LEVEL_ISR )
2298 printk("%s(%d):%s isr_txint status=%02x\n",
2299 __FILE__,__LINE__,info->device_name,status);
2300
2301 if (status & (UDRN + IDLE))
2302 isr_txeom(info, status);
2303
2304 if (status & CCTS) {
2305
2306
2307
2308 get_signals( info );
2309 isr_io_pin(info,
2310 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2311
2312 }
2313}
2314
2315
2316
2317
2318static void isr_txrdy(SLMP_INFO * info)
2319{
2320 if ( debug_level >= DEBUG_LEVEL_ISR )
2321 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2322 __FILE__,__LINE__,info->device_name,info->tx_count);
2323
2324 if (info->params.mode != MGSL_MODE_ASYNC) {
2325
2326 info->ie0_value &= ~TXRDYE;
2327 info->ie1_value |= IDLE;
2328 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2329 return;
2330 }
2331
2332 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2333 tx_stop(info);
2334 return;
2335 }
2336
2337 if ( info->tx_count )
2338 tx_load_fifo( info );
2339 else {
2340 info->tx_active = false;
2341 info->ie0_value &= ~TXRDYE;
2342 write_reg(info, IE0, info->ie0_value);
2343 }
2344
2345 if (info->tx_count < WAKEUP_CHARS)
2346 info->pending_bh |= BH_TRANSMIT;
2347}
2348
2349static void isr_rxdmaok(SLMP_INFO * info)
2350{
2351
2352
2353
2354 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2355
2356
2357 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2358
2359 if ( debug_level >= DEBUG_LEVEL_ISR )
2360 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2361 __FILE__,__LINE__,info->device_name,status);
2362
2363 info->pending_bh |= BH_RECEIVE;
2364}
2365
2366static void isr_rxdmaerror(SLMP_INFO * info)
2367{
2368
2369
2370
2371 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2372
2373
2374 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2375
2376 if ( debug_level >= DEBUG_LEVEL_ISR )
2377 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2378 __FILE__,__LINE__,info->device_name,status);
2379
2380 info->rx_overflow = true;
2381 info->pending_bh |= BH_RECEIVE;
2382}
2383
2384static void isr_txdmaok(SLMP_INFO * info)
2385{
2386 unsigned char status_reg1 = read_reg(info, SR1);
2387
2388 write_reg(info, TXDMA + DIR, 0x00);
2389 write_reg(info, TXDMA + DSR, 0xc0);
2390 write_reg(info, TXDMA + DCMD, SWABORT);
2391
2392 if ( debug_level >= DEBUG_LEVEL_ISR )
2393 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2394 __FILE__,__LINE__,info->device_name,status_reg1);
2395
2396
2397 write_reg16(info, TRC0, 0);
2398 info->ie0_value |= TXRDYE;
2399 write_reg(info, IE0, info->ie0_value);
2400}
2401
2402static void isr_txdmaerror(SLMP_INFO * info)
2403{
2404
2405
2406
2407 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2408
2409
2410 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2411
2412 if ( debug_level >= DEBUG_LEVEL_ISR )
2413 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2414 __FILE__,__LINE__,info->device_name,status);
2415}
2416
2417
2418
2419static void isr_io_pin( SLMP_INFO *info, u16 status )
2420{
2421 struct mgsl_icount *icount;
2422
2423 if ( debug_level >= DEBUG_LEVEL_ISR )
2424 printk("%s(%d):isr_io_pin status=%04X\n",
2425 __FILE__,__LINE__,status);
2426
2427 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2428 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2429 icount = &info->icount;
2430
2431 if (status & MISCSTATUS_RI_LATCHED) {
2432 icount->rng++;
2433 if ( status & SerialSignal_RI )
2434 info->input_signal_events.ri_up++;
2435 else
2436 info->input_signal_events.ri_down++;
2437 }
2438 if (status & MISCSTATUS_DSR_LATCHED) {
2439 icount->dsr++;
2440 if ( status & SerialSignal_DSR )
2441 info->input_signal_events.dsr_up++;
2442 else
2443 info->input_signal_events.dsr_down++;
2444 }
2445 if (status & MISCSTATUS_DCD_LATCHED) {
2446 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2447 info->ie1_value &= ~CDCD;
2448 write_reg(info, IE1, info->ie1_value);
2449 }
2450 icount->dcd++;
2451 if (status & SerialSignal_DCD) {
2452 info->input_signal_events.dcd_up++;
2453 } else
2454 info->input_signal_events.dcd_down++;
2455#if SYNCLINK_GENERIC_HDLC
2456 if (info->netcount) {
2457 if (status & SerialSignal_DCD)
2458 netif_carrier_on(info->netdev);
2459 else
2460 netif_carrier_off(info->netdev);
2461 }
2462#endif
2463 }
2464 if (status & MISCSTATUS_CTS_LATCHED)
2465 {
2466 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2467 info->ie1_value &= ~CCTS;
2468 write_reg(info, IE1, info->ie1_value);
2469 }
2470 icount->cts++;
2471 if ( status & SerialSignal_CTS )
2472 info->input_signal_events.cts_up++;
2473 else
2474 info->input_signal_events.cts_down++;
2475 }
2476 wake_up_interruptible(&info->status_event_wait_q);
2477 wake_up_interruptible(&info->event_wait_q);
2478
2479 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2480 (status & MISCSTATUS_DCD_LATCHED) ) {
2481 if ( debug_level >= DEBUG_LEVEL_ISR )
2482 printk("%s CD now %s...", info->device_name,
2483 (status & SerialSignal_DCD) ? "on" : "off");
2484 if (status & SerialSignal_DCD)
2485 wake_up_interruptible(&info->port.open_wait);
2486 else {
2487 if ( debug_level >= DEBUG_LEVEL_ISR )
2488 printk("doing serial hangup...");
2489 if (info->port.tty)
2490 tty_hangup(info->port.tty);
2491 }
2492 }
2493
2494 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2495 (status & MISCSTATUS_CTS_LATCHED) ) {
2496 if ( info->port.tty ) {
2497 if (info->port.tty->hw_stopped) {
2498 if (status & SerialSignal_CTS) {
2499 if ( debug_level >= DEBUG_LEVEL_ISR )
2500 printk("CTS tx start...");
2501 info->port.tty->hw_stopped = 0;
2502 tx_start(info);
2503 info->pending_bh |= BH_TRANSMIT;
2504 return;
2505 }
2506 } else {
2507 if (!(status & SerialSignal_CTS)) {
2508 if ( debug_level >= DEBUG_LEVEL_ISR )
2509 printk("CTS tx stop...");
2510 info->port.tty->hw_stopped = 1;
2511 tx_stop(info);
2512 }
2513 }
2514 }
2515 }
2516 }
2517
2518 info->pending_bh |= BH_STATUS;
2519}
2520
2521
2522
2523
2524
2525
2526
2527
2528static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2529{
2530 SLMP_INFO *info = dev_id;
2531 unsigned char status, status0, status1=0;
2532 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2533 unsigned char timerstatus0, timerstatus1=0;
2534 unsigned char shift;
2535 unsigned int i;
2536 unsigned short tmp;
2537
2538 if ( debug_level >= DEBUG_LEVEL_ISR )
2539 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2540 __FILE__, __LINE__, info->irq_level);
2541
2542 spin_lock(&info->lock);
2543
2544 for(;;) {
2545
2546
2547 tmp = read_reg16(info, ISR0);
2548 status0 = (unsigned char)tmp;
2549 dmastatus0 = (unsigned char)(tmp>>8);
2550 timerstatus0 = read_reg(info, ISR2);
2551
2552 if ( debug_level >= DEBUG_LEVEL_ISR )
2553 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2554 __FILE__, __LINE__, info->device_name,
2555 status0, dmastatus0, timerstatus0);
2556
2557 if (info->port_count == 4) {
2558
2559 tmp = read_reg16(info->port_array[2], ISR0);
2560 status1 = (unsigned char)tmp;
2561 dmastatus1 = (unsigned char)(tmp>>8);
2562 timerstatus1 = read_reg(info->port_array[2], ISR2);
2563
2564 if ( debug_level >= DEBUG_LEVEL_ISR )
2565 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2566 __FILE__,__LINE__,info->device_name,
2567 status1,dmastatus1,timerstatus1);
2568 }
2569
2570 if (!status0 && !dmastatus0 && !timerstatus0 &&
2571 !status1 && !dmastatus1 && !timerstatus1)
2572 break;
2573
2574 for(i=0; i < info->port_count ; i++) {
2575 if (info->port_array[i] == NULL)
2576 continue;
2577 if (i < 2) {
2578 status = status0;
2579 dmastatus = dmastatus0;
2580 } else {
2581 status = status1;
2582 dmastatus = dmastatus1;
2583 }
2584
2585 shift = i & 1 ? 4 :0;
2586
2587 if (status & BIT0 << shift)
2588 isr_rxrdy(info->port_array[i]);
2589 if (status & BIT1 << shift)
2590 isr_txrdy(info->port_array[i]);
2591 if (status & BIT2 << shift)
2592 isr_rxint(info->port_array[i]);
2593 if (status & BIT3 << shift)
2594 isr_txint(info->port_array[i]);
2595
2596 if (dmastatus & BIT0 << shift)
2597 isr_rxdmaerror(info->port_array[i]);
2598 if (dmastatus & BIT1 << shift)
2599 isr_rxdmaok(info->port_array[i]);
2600 if (dmastatus & BIT2 << shift)
2601 isr_txdmaerror(info->port_array[i]);
2602 if (dmastatus & BIT3 << shift)
2603 isr_txdmaok(info->port_array[i]);
2604 }
2605
2606 if (timerstatus0 & (BIT5 | BIT4))
2607 isr_timer(info->port_array[0]);
2608 if (timerstatus0 & (BIT7 | BIT6))
2609 isr_timer(info->port_array[1]);
2610 if (timerstatus1 & (BIT5 | BIT4))
2611 isr_timer(info->port_array[2]);
2612 if (timerstatus1 & (BIT7 | BIT6))
2613 isr_timer(info->port_array[3]);
2614 }
2615
2616 for(i=0; i < info->port_count ; i++) {
2617 SLMP_INFO * port = info->port_array[i];
2618
2619
2620
2621
2622
2623
2624
2625
2626 if ( port && (port->port.count || port->netcount) &&
2627 port->pending_bh && !port->bh_running &&
2628 !port->bh_requested ) {
2629 if ( debug_level >= DEBUG_LEVEL_ISR )
2630 printk("%s(%d):%s queueing bh task.\n",
2631 __FILE__,__LINE__,port->device_name);
2632 schedule_work(&port->task);
2633 port->bh_requested = true;
2634 }
2635 }
2636
2637 spin_unlock(&info->lock);
2638
2639 if ( debug_level >= DEBUG_LEVEL_ISR )
2640 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2641 __FILE__, __LINE__, info->irq_level);
2642 return IRQ_HANDLED;
2643}
2644
2645
2646
2647static int startup(SLMP_INFO * info)
2648{
2649 if ( debug_level >= DEBUG_LEVEL_INFO )
2650 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2651
2652 if (info->port.flags & ASYNC_INITIALIZED)
2653 return 0;
2654
2655 if (!info->tx_buf) {
2656 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2657 if (!info->tx_buf) {
2658 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2659 __FILE__,__LINE__,info->device_name);
2660 return -ENOMEM;
2661 }
2662 }
2663
2664 info->pending_bh = 0;
2665
2666 memset(&info->icount, 0, sizeof(info->icount));
2667
2668
2669 reset_port(info);
2670
2671 change_params(info);
2672
2673 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2674
2675 if (info->port.tty)
2676 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2677
2678 info->port.flags |= ASYNC_INITIALIZED;
2679
2680 return 0;
2681}
2682
2683
2684
2685static void shutdown(SLMP_INFO * info)
2686{
2687 unsigned long flags;
2688
2689 if (!(info->port.flags & ASYNC_INITIALIZED))
2690 return;
2691
2692 if (debug_level >= DEBUG_LEVEL_INFO)
2693 printk("%s(%d):%s synclinkmp_shutdown()\n",
2694 __FILE__,__LINE__, info->device_name );
2695
2696
2697
2698 wake_up_interruptible(&info->status_event_wait_q);
2699 wake_up_interruptible(&info->event_wait_q);
2700
2701 del_timer(&info->tx_timer);
2702 del_timer(&info->status_timer);
2703
2704 kfree(info->tx_buf);
2705 info->tx_buf = NULL;
2706
2707 spin_lock_irqsave(&info->lock,flags);
2708
2709 reset_port(info);
2710
2711 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2712 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2713 set_signals(info);
2714 }
2715
2716 spin_unlock_irqrestore(&info->lock,flags);
2717
2718 if (info->port.tty)
2719 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2720
2721 info->port.flags &= ~ASYNC_INITIALIZED;
2722}
2723
2724static void program_hw(SLMP_INFO *info)
2725{
2726 unsigned long flags;
2727
2728 spin_lock_irqsave(&info->lock,flags);
2729
2730 rx_stop(info);
2731 tx_stop(info);
2732
2733 info->tx_count = info->tx_put = info->tx_get = 0;
2734
2735 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2736 hdlc_mode(info);
2737 else
2738 async_mode(info);
2739
2740 set_signals(info);
2741
2742 info->dcd_chkcount = 0;
2743 info->cts_chkcount = 0;
2744 info->ri_chkcount = 0;
2745 info->dsr_chkcount = 0;
2746
2747 info->ie1_value |= (CDCD|CCTS);
2748 write_reg(info, IE1, info->ie1_value);
2749
2750 get_signals(info);
2751
2752 if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2753 rx_start(info);
2754
2755 spin_unlock_irqrestore(&info->lock,flags);
2756}
2757
2758
2759
2760static void change_params(SLMP_INFO *info)
2761{
2762 unsigned cflag;
2763 int bits_per_char;
2764
2765 if (!info->port.tty || !info->port.tty->termios)
2766 return;
2767
2768 if (debug_level >= DEBUG_LEVEL_INFO)
2769 printk("%s(%d):%s change_params()\n",
2770 __FILE__,__LINE__, info->device_name );
2771
2772 cflag = info->port.tty->termios->c_cflag;
2773
2774
2775
2776 if (cflag & CBAUD)
2777 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2778 else
2779 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2780
2781
2782
2783 switch (cflag & CSIZE) {
2784 case CS5: info->params.data_bits = 5; break;
2785 case CS6: info->params.data_bits = 6; break;
2786 case CS7: info->params.data_bits = 7; break;
2787 case CS8: info->params.data_bits = 8; break;
2788
2789 default: info->params.data_bits = 7; break;
2790 }
2791
2792 if (cflag & CSTOPB)
2793 info->params.stop_bits = 2;
2794 else
2795 info->params.stop_bits = 1;
2796
2797 info->params.parity = ASYNC_PARITY_NONE;
2798 if (cflag & PARENB) {
2799 if (cflag & PARODD)
2800 info->params.parity = ASYNC_PARITY_ODD;
2801 else
2802 info->params.parity = ASYNC_PARITY_EVEN;
2803#ifdef CMSPAR
2804 if (cflag & CMSPAR)
2805 info->params.parity = ASYNC_PARITY_SPACE;
2806#endif
2807 }
2808
2809
2810
2811
2812 bits_per_char = info->params.data_bits +
2813 info->params.stop_bits + 1;
2814
2815
2816
2817
2818
2819 if (info->params.data_rate <= 460800) {
2820 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2821 }
2822
2823 if ( info->params.data_rate ) {
2824 info->timeout = (32*HZ*bits_per_char) /
2825 info->params.data_rate;
2826 }
2827 info->timeout += HZ/50;
2828
2829 if (cflag & CRTSCTS)
2830 info->port.flags |= ASYNC_CTS_FLOW;
2831 else
2832 info->port.flags &= ~ASYNC_CTS_FLOW;
2833
2834 if (cflag & CLOCAL)
2835 info->port.flags &= ~ASYNC_CHECK_CD;
2836 else
2837 info->port.flags |= ASYNC_CHECK_CD;
2838
2839
2840
2841 info->read_status_mask2 = OVRN;
2842 if (I_INPCK(info->port.tty))
2843 info->read_status_mask2 |= PE | FRME;
2844 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2845 info->read_status_mask1 |= BRKD;
2846 if (I_IGNPAR(info->port.tty))
2847 info->ignore_status_mask2 |= PE | FRME;
2848 if (I_IGNBRK(info->port.tty)) {
2849 info->ignore_status_mask1 |= BRKD;
2850
2851
2852
2853 if (I_IGNPAR(info->port.tty))
2854 info->ignore_status_mask2 |= OVRN;
2855 }
2856
2857 program_hw(info);
2858}
2859
2860static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2861{
2862 int err;
2863
2864 if (debug_level >= DEBUG_LEVEL_INFO)
2865 printk("%s(%d):%s get_params()\n",
2866 __FILE__,__LINE__, info->device_name);
2867
2868 if (!user_icount) {
2869 memset(&info->icount, 0, sizeof(info->icount));
2870 } else {
2871 mutex_lock(&info->port.mutex);
2872 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2873 mutex_unlock(&info->port.mutex);
2874 if (err)
2875 return -EFAULT;
2876 }
2877
2878 return 0;
2879}
2880
2881static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2882{
2883 int err;
2884 if (debug_level >= DEBUG_LEVEL_INFO)
2885 printk("%s(%d):%s get_params()\n",
2886 __FILE__,__LINE__, info->device_name);
2887
2888 mutex_lock(&info->port.mutex);
2889 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2890 mutex_unlock(&info->port.mutex);
2891 if (err) {
2892 if ( debug_level >= DEBUG_LEVEL_INFO )
2893 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2894 __FILE__,__LINE__,info->device_name);
2895 return -EFAULT;
2896 }
2897
2898 return 0;
2899}
2900
2901static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2902{
2903 unsigned long flags;
2904 MGSL_PARAMS tmp_params;
2905 int err;
2906
2907 if (debug_level >= DEBUG_LEVEL_INFO)
2908 printk("%s(%d):%s set_params\n",
2909 __FILE__,__LINE__,info->device_name );
2910 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2911 if (err) {
2912 if ( debug_level >= DEBUG_LEVEL_INFO )
2913 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2914 __FILE__,__LINE__,info->device_name);
2915 return -EFAULT;
2916 }
2917
2918 mutex_lock(&info->port.mutex);
2919 spin_lock_irqsave(&info->lock,flags);
2920 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2921 spin_unlock_irqrestore(&info->lock,flags);
2922
2923 change_params(info);
2924 mutex_unlock(&info->port.mutex);
2925
2926 return 0;
2927}
2928
2929static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2930{
2931 int err;
2932
2933 if (debug_level >= DEBUG_LEVEL_INFO)
2934 printk("%s(%d):%s get_txidle()=%d\n",
2935 __FILE__,__LINE__, info->device_name, info->idle_mode);
2936
2937 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2938 if (err) {
2939 if ( debug_level >= DEBUG_LEVEL_INFO )
2940 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2941 __FILE__,__LINE__,info->device_name);
2942 return -EFAULT;
2943 }
2944
2945 return 0;
2946}
2947
2948static int set_txidle(SLMP_INFO * info, int idle_mode)
2949{
2950 unsigned long flags;
2951
2952 if (debug_level >= DEBUG_LEVEL_INFO)
2953 printk("%s(%d):%s set_txidle(%d)\n",
2954 __FILE__,__LINE__,info->device_name, idle_mode );
2955
2956 spin_lock_irqsave(&info->lock,flags);
2957 info->idle_mode = idle_mode;
2958 tx_set_idle( info );
2959 spin_unlock_irqrestore(&info->lock,flags);
2960 return 0;
2961}
2962
2963static int tx_enable(SLMP_INFO * info, int enable)
2964{
2965 unsigned long flags;
2966
2967 if (debug_level >= DEBUG_LEVEL_INFO)
2968 printk("%s(%d):%s tx_enable(%d)\n",
2969 __FILE__,__LINE__,info->device_name, enable);
2970
2971 spin_lock_irqsave(&info->lock,flags);
2972 if ( enable ) {
2973 if ( !info->tx_enabled ) {
2974 tx_start(info);
2975 }
2976 } else {
2977 if ( info->tx_enabled )
2978 tx_stop(info);
2979 }
2980 spin_unlock_irqrestore(&info->lock,flags);
2981 return 0;
2982}
2983
2984
2985
2986static int tx_abort(SLMP_INFO * info)
2987{
2988 unsigned long flags;
2989
2990 if (debug_level >= DEBUG_LEVEL_INFO)
2991 printk("%s(%d):%s tx_abort()\n",
2992 __FILE__,__LINE__,info->device_name);
2993
2994 spin_lock_irqsave(&info->lock,flags);
2995 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2996 info->ie1_value &= ~UDRN;
2997 info->ie1_value |= IDLE;
2998 write_reg(info, IE1, info->ie1_value);
2999 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
3000
3001 write_reg(info, TXDMA + DSR, 0);
3002 write_reg(info, TXDMA + DCMD, SWABORT);
3003
3004 write_reg(info, CMD, TXABORT);
3005 }
3006 spin_unlock_irqrestore(&info->lock,flags);
3007 return 0;
3008}
3009
3010static int rx_enable(SLMP_INFO * info, int enable)
3011{
3012 unsigned long flags;
3013
3014 if (debug_level >= DEBUG_LEVEL_INFO)
3015 printk("%s(%d):%s rx_enable(%d)\n",
3016 __FILE__,__LINE__,info->device_name,enable);
3017
3018 spin_lock_irqsave(&info->lock,flags);
3019 if ( enable ) {
3020 if ( !info->rx_enabled )
3021 rx_start(info);
3022 } else {
3023 if ( info->rx_enabled )
3024 rx_stop(info);
3025 }
3026 spin_unlock_irqrestore(&info->lock,flags);
3027 return 0;
3028}
3029
3030
3031
3032static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3033{
3034 unsigned long flags;
3035 int s;
3036 int rc=0;
3037 struct mgsl_icount cprev, cnow;
3038 int events;
3039 int mask;
3040 struct _input_signal_events oldsigs, newsigs;
3041 DECLARE_WAITQUEUE(wait, current);
3042
3043 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3044 if (rc) {
3045 return -EFAULT;
3046 }
3047
3048 if (debug_level >= DEBUG_LEVEL_INFO)
3049 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3050 __FILE__,__LINE__,info->device_name,mask);
3051
3052 spin_lock_irqsave(&info->lock,flags);
3053
3054
3055 get_signals(info);
3056 s = info->serial_signals;
3057
3058 events = mask &
3059 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3060 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3061 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3062 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3063 if (events) {
3064 spin_unlock_irqrestore(&info->lock,flags);
3065 goto exit;
3066 }
3067
3068
3069 cprev = info->icount;
3070 oldsigs = info->input_signal_events;
3071
3072
3073 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3074 unsigned char oldval = info->ie1_value;
3075 unsigned char newval = oldval +
3076 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3077 (mask & MgslEvent_IdleReceived ? IDLD:0);
3078 if ( oldval != newval ) {
3079 info->ie1_value = newval;
3080 write_reg(info, IE1, info->ie1_value);
3081 }
3082 }
3083
3084 set_current_state(TASK_INTERRUPTIBLE);
3085 add_wait_queue(&info->event_wait_q, &wait);
3086
3087 spin_unlock_irqrestore(&info->lock,flags);
3088
3089 for(;;) {
3090 schedule();
3091 if (signal_pending(current)) {
3092 rc = -ERESTARTSYS;
3093 break;
3094 }
3095
3096
3097 spin_lock_irqsave(&info->lock,flags);
3098 cnow = info->icount;
3099 newsigs = info->input_signal_events;
3100 set_current_state(TASK_INTERRUPTIBLE);
3101 spin_unlock_irqrestore(&info->lock,flags);
3102
3103
3104 if (newsigs.dsr_up == oldsigs.dsr_up &&
3105 newsigs.dsr_down == oldsigs.dsr_down &&
3106 newsigs.dcd_up == oldsigs.dcd_up &&
3107 newsigs.dcd_down == oldsigs.dcd_down &&
3108 newsigs.cts_up == oldsigs.cts_up &&
3109 newsigs.cts_down == oldsigs.cts_down &&
3110 newsigs.ri_up == oldsigs.ri_up &&
3111 newsigs.ri_down == oldsigs.ri_down &&
3112 cnow.exithunt == cprev.exithunt &&
3113 cnow.rxidle == cprev.rxidle) {
3114 rc = -EIO;
3115 break;
3116 }
3117
3118 events = mask &
3119 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3120 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3121 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3122 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3123 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3124 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3125 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3126 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3127 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3128 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3129 if (events)
3130 break;
3131
3132 cprev = cnow;
3133 oldsigs = newsigs;
3134 }
3135
3136 remove_wait_queue(&info->event_wait_q, &wait);
3137 set_current_state(TASK_RUNNING);
3138
3139
3140 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3141 spin_lock_irqsave(&info->lock,flags);
3142 if (!waitqueue_active(&info->event_wait_q)) {
3143
3144 info->ie1_value &= ~(FLGD|IDLD);
3145 write_reg(info, IE1, info->ie1_value);
3146 }
3147 spin_unlock_irqrestore(&info->lock,flags);
3148 }
3149exit:
3150 if ( rc == 0 )
3151 PUT_USER(rc, events, mask_ptr);
3152
3153 return rc;
3154}
3155
3156static int modem_input_wait(SLMP_INFO *info,int arg)
3157{
3158 unsigned long flags;
3159 int rc;
3160 struct mgsl_icount cprev, cnow;
3161 DECLARE_WAITQUEUE(wait, current);
3162
3163
3164 spin_lock_irqsave(&info->lock,flags);
3165 cprev = info->icount;
3166 add_wait_queue(&info->status_event_wait_q, &wait);
3167 set_current_state(TASK_INTERRUPTIBLE);
3168 spin_unlock_irqrestore(&info->lock,flags);
3169
3170 for(;;) {
3171 schedule();
3172 if (signal_pending(current)) {
3173 rc = -ERESTARTSYS;
3174 break;
3175 }
3176
3177
3178 spin_lock_irqsave(&info->lock,flags);
3179 cnow = info->icount;
3180 set_current_state(TASK_INTERRUPTIBLE);
3181 spin_unlock_irqrestore(&info->lock,flags);
3182
3183
3184 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3185 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3186 rc = -EIO;
3187 break;
3188 }
3189
3190
3191 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3192 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3193 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3194 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3195 rc = 0;
3196 break;
3197 }
3198
3199 cprev = cnow;
3200 }
3201 remove_wait_queue(&info->status_event_wait_q, &wait);
3202 set_current_state(TASK_RUNNING);
3203 return rc;
3204}
3205
3206
3207
3208static int tiocmget(struct tty_struct *tty)
3209{
3210 SLMP_INFO *info = tty->driver_data;
3211 unsigned int result;
3212 unsigned long flags;
3213
3214 spin_lock_irqsave(&info->lock,flags);
3215 get_signals(info);
3216 spin_unlock_irqrestore(&info->lock,flags);
3217
3218 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3219 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3220 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3221 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3222 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3223 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3224
3225 if (debug_level >= DEBUG_LEVEL_INFO)
3226 printk("%s(%d):%s tiocmget() value=%08X\n",
3227 __FILE__,__LINE__, info->device_name, result );
3228 return result;
3229}
3230
3231
3232
3233static int tiocmset(struct tty_struct *tty,
3234 unsigned int set, unsigned int clear)
3235{
3236 SLMP_INFO *info = tty->driver_data;
3237 unsigned long flags;
3238
3239 if (debug_level >= DEBUG_LEVEL_INFO)
3240 printk("%s(%d):%s tiocmset(%x,%x)\n",
3241 __FILE__,__LINE__,info->device_name, set, clear);
3242
3243 if (set & TIOCM_RTS)
3244 info->serial_signals |= SerialSignal_RTS;
3245 if (set & TIOCM_DTR)
3246 info->serial_signals |= SerialSignal_DTR;
3247 if (clear & TIOCM_RTS)
3248 info->serial_signals &= ~SerialSignal_RTS;
3249 if (clear & TIOCM_DTR)
3250 info->serial_signals &= ~SerialSignal_DTR;
3251
3252 spin_lock_irqsave(&info->lock,flags);
3253 set_signals(info);
3254 spin_unlock_irqrestore(&info->lock,flags);
3255
3256 return 0;
3257}
3258
3259static int carrier_raised(struct tty_port *port)
3260{
3261 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3262 unsigned long flags;
3263
3264 spin_lock_irqsave(&info->lock,flags);
3265 get_signals(info);
3266 spin_unlock_irqrestore(&info->lock,flags);
3267
3268 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3269}
3270
3271static void dtr_rts(struct tty_port *port, int on)
3272{
3273 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3274 unsigned long flags;
3275
3276 spin_lock_irqsave(&info->lock,flags);
3277 if (on)
3278 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3279 else
3280 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3281 set_signals(info);
3282 spin_unlock_irqrestore(&info->lock,flags);
3283}
3284
3285
3286
3287static int block_til_ready(struct tty_struct *tty, struct file *filp,
3288 SLMP_INFO *info)
3289{
3290 DECLARE_WAITQUEUE(wait, current);
3291 int retval;
3292 bool do_clocal = false;
3293 bool extra_count = false;
3294 unsigned long flags;
3295 int cd;
3296 struct tty_port *port = &info->port;
3297
3298 if (debug_level >= DEBUG_LEVEL_INFO)
3299 printk("%s(%d):%s block_til_ready()\n",
3300 __FILE__,__LINE__, tty->driver->name );
3301
3302 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3303
3304
3305 port->flags |= ASYNC_NORMAL_ACTIVE;
3306 return 0;
3307 }
3308
3309 if (tty->termios->c_cflag & CLOCAL)
3310 do_clocal = true;
3311
3312
3313
3314
3315
3316
3317
3318
3319 retval = 0;
3320 add_wait_queue(&port->open_wait, &wait);
3321
3322 if (debug_level >= DEBUG_LEVEL_INFO)
3323 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3324 __FILE__,__LINE__, tty->driver->name, port->count );
3325
3326 spin_lock_irqsave(&info->lock, flags);
3327 if (!tty_hung_up_p(filp)) {
3328 extra_count = true;
3329 port->count--;
3330 }
3331 spin_unlock_irqrestore(&info->lock, flags);
3332 port->blocked_open++;
3333
3334 while (1) {
3335 if (tty->termios->c_cflag & CBAUD)
3336 tty_port_raise_dtr_rts(port);
3337
3338 set_current_state(TASK_INTERRUPTIBLE);
3339
3340 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3341 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3342 -EAGAIN : -ERESTARTSYS;
3343 break;
3344 }
3345
3346 cd = tty_port_carrier_raised(port);
3347
3348 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3349 break;
3350
3351 if (signal_pending(current)) {
3352 retval = -ERESTARTSYS;
3353 break;
3354 }
3355
3356 if (debug_level >= DEBUG_LEVEL_INFO)
3357 printk("%s(%d):%s block_til_ready() count=%d\n",
3358 __FILE__,__LINE__, tty->driver->name, port->count );
3359
3360 tty_unlock();
3361 schedule();
3362 tty_lock();
3363 }
3364
3365 set_current_state(TASK_RUNNING);
3366 remove_wait_queue(&port->open_wait, &wait);
3367
3368 if (extra_count)
3369 port->count++;
3370 port->blocked_open--;
3371
3372 if (debug_level >= DEBUG_LEVEL_INFO)
3373 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3374 __FILE__,__LINE__, tty->driver->name, port->count );
3375
3376 if (!retval)
3377 port->flags |= ASYNC_NORMAL_ACTIVE;
3378
3379 return retval;
3380}
3381
3382static int alloc_dma_bufs(SLMP_INFO *info)
3383{
3384 unsigned short BuffersPerFrame;
3385 unsigned short BufferCount;
3386
3387
3388
3389
3390
3391
3392 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3393
3394
3395
3396
3397
3398
3399 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3400 if ( info->max_frame_size % SCABUFSIZE )
3401 BuffersPerFrame++;
3402
3403
3404
3405
3406
3407 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3408
3409
3410 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3411 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3412
3413
3414 info->tx_buf_count = BuffersPerFrame + 1;
3415
3416
3417 if (info->tx_buf_count > (BufferCount/2))
3418 info->tx_buf_count = BufferCount/2;
3419
3420 if (info->tx_buf_count > SCAMAXDESC)
3421 info->tx_buf_count = SCAMAXDESC;
3422
3423
3424 info->rx_buf_count = BufferCount - info->tx_buf_count;
3425
3426 if (info->rx_buf_count > SCAMAXDESC)
3427 info->rx_buf_count = SCAMAXDESC;
3428
3429 if ( debug_level >= DEBUG_LEVEL_INFO )
3430 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3431 __FILE__,__LINE__, info->device_name,
3432 info->tx_buf_count,info->rx_buf_count);
3433
3434 if ( alloc_buf_list( info ) < 0 ||
3435 alloc_frame_bufs(info,
3436 info->rx_buf_list,
3437 info->rx_buf_list_ex,
3438 info->rx_buf_count) < 0 ||
3439 alloc_frame_bufs(info,
3440 info->tx_buf_list,
3441 info->tx_buf_list_ex,
3442 info->tx_buf_count) < 0 ||
3443 alloc_tmp_rx_buf(info) < 0 ) {
3444 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3445 __FILE__,__LINE__, info->device_name);
3446 return -ENOMEM;
3447 }
3448
3449 rx_reset_buffers( info );
3450
3451 return 0;
3452}
3453
3454
3455
3456static int alloc_buf_list(SLMP_INFO *info)
3457{
3458 unsigned int i;
3459
3460
3461 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3462 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3463 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3464
3465 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3466
3467
3468
3469
3470 info->rx_buf_list = (SCADESC *)info->buffer_list;
3471
3472 info->tx_buf_list = (SCADESC *)info->buffer_list;
3473 info->tx_buf_list += info->rx_buf_count;
3474
3475
3476
3477
3478
3479
3480
3481 for ( i = 0; i < info->rx_buf_count; i++ ) {
3482
3483 info->rx_buf_list_ex[i].phys_entry =
3484 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3485
3486
3487
3488 info->rx_buf_list[i].next = info->buffer_list_phys;
3489 if ( i < info->rx_buf_count - 1 )
3490 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3491
3492 info->rx_buf_list[i].length = SCABUFSIZE;
3493 }
3494
3495 for ( i = 0; i < info->tx_buf_count; i++ ) {
3496
3497 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3498 ((info->rx_buf_count + i) * sizeof(SCADESC));
3499
3500
3501
3502
3503 info->tx_buf_list[i].next = info->buffer_list_phys +
3504 info->rx_buf_count * sizeof(SCADESC);
3505
3506 if ( i < info->tx_buf_count - 1 )
3507 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3508 }
3509
3510 return 0;
3511}
3512
3513
3514
3515static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3516{
3517 int i;
3518 unsigned long phys_addr;
3519
3520 for ( i = 0; i < count; i++ ) {
3521 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3522 phys_addr = info->port_array[0]->last_mem_alloc;
3523 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3524
3525 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3526 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3527 }
3528
3529 return 0;
3530}
3531
3532static void free_dma_bufs(SLMP_INFO *info)
3533{
3534 info->buffer_list = NULL;
3535 info->rx_buf_list = NULL;
3536 info->tx_buf_list = NULL;
3537}
3538
3539
3540
3541
3542static int alloc_tmp_rx_buf(SLMP_INFO *info)
3543{
3544 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3545 if (info->tmp_rx_buf == NULL)
3546 return -ENOMEM;
3547 return 0;
3548}
3549
3550static void free_tmp_rx_buf(SLMP_INFO *info)
3551{
3552 kfree(info->tmp_rx_buf);
3553 info->tmp_rx_buf = NULL;
3554}
3555
3556static int claim_resources(SLMP_INFO *info)
3557{
3558 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3559 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3560 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3561 info->init_error = DiagStatus_AddressConflict;
3562 goto errout;
3563 }
3564 else
3565 info->shared_mem_requested = true;
3566
3567 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3568 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3569 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3570 info->init_error = DiagStatus_AddressConflict;
3571 goto errout;
3572 }
3573 else
3574 info->lcr_mem_requested = true;
3575
3576 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3577 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3578 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3579 info->init_error = DiagStatus_AddressConflict;
3580 goto errout;
3581 }
3582 else
3583 info->sca_base_requested = true;
3584
3585 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3586 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3587 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3588 info->init_error = DiagStatus_AddressConflict;
3589 goto errout;
3590 }
3591 else
3592 info->sca_statctrl_requested = true;
3593
3594 info->memory_base = ioremap_nocache(info->phys_memory_base,
3595 SCA_MEM_SIZE);
3596 if (!info->memory_base) {
3597 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3598 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3599 info->init_error = DiagStatus_CantAssignPciResources;
3600 goto errout;
3601 }
3602
3603 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3604 if (!info->lcr_base) {
3605 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3606 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3607 info->init_error = DiagStatus_CantAssignPciResources;
3608 goto errout;
3609 }
3610 info->lcr_base += info->lcr_offset;
3611
3612 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3613 if (!info->sca_base) {
3614 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3615 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3616 info->init_error = DiagStatus_CantAssignPciResources;
3617 goto errout;
3618 }
3619 info->sca_base += info->sca_offset;
3620
3621 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3622 PAGE_SIZE);
3623 if (!info->statctrl_base) {
3624 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3625 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3626 info->init_error = DiagStatus_CantAssignPciResources;
3627 goto errout;
3628 }
3629 info->statctrl_base += info->statctrl_offset;
3630
3631 if ( !memory_test(info) ) {
3632 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3633 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3634 info->init_error = DiagStatus_MemoryError;
3635 goto errout;
3636 }
3637
3638 return 0;
3639
3640errout:
3641 release_resources( info );
3642 return -ENODEV;
3643}
3644
3645static void release_resources(SLMP_INFO *info)
3646{
3647 if ( debug_level >= DEBUG_LEVEL_INFO )
3648 printk( "%s(%d):%s release_resources() entry\n",
3649 __FILE__,__LINE__,info->device_name );
3650
3651 if ( info->irq_requested ) {
3652 free_irq(info->irq_level, info);
3653 info->irq_requested = false;
3654 }
3655
3656 if ( info->shared_mem_requested ) {
3657 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3658 info->shared_mem_requested = false;
3659 }
3660 if ( info->lcr_mem_requested ) {
3661 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3662 info->lcr_mem_requested = false;
3663 }
3664 if ( info->sca_base_requested ) {
3665 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3666 info->sca_base_requested = false;
3667 }
3668 if ( info->sca_statctrl_requested ) {
3669 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3670 info->sca_statctrl_requested = false;
3671 }
3672
3673 if (info->memory_base){
3674 iounmap(info->memory_base);
3675 info->memory_base = NULL;
3676 }
3677
3678 if (info->sca_base) {
3679 iounmap(info->sca_base - info->sca_offset);
3680 info->sca_base=NULL;
3681 }
3682
3683 if (info->statctrl_base) {
3684 iounmap(info->statctrl_base - info->statctrl_offset);
3685 info->statctrl_base=NULL;
3686 }
3687
3688 if (info->lcr_base){
3689 iounmap(info->lcr_base - info->lcr_offset);
3690 info->lcr_base = NULL;
3691 }
3692
3693 if ( debug_level >= DEBUG_LEVEL_INFO )
3694 printk( "%s(%d):%s release_resources() exit\n",
3695 __FILE__,__LINE__,info->device_name );
3696}
3697
3698
3699
3700
3701static void add_device(SLMP_INFO *info)
3702{
3703 info->next_device = NULL;
3704 info->line = synclinkmp_device_count;
3705 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3706
3707 if (info->line < MAX_DEVICES) {
3708 if (maxframe[info->line])
3709 info->max_frame_size = maxframe[info->line];
3710 }
3711
3712 synclinkmp_device_count++;
3713
3714 if ( !synclinkmp_device_list )
3715 synclinkmp_device_list = info;
3716 else {
3717 SLMP_INFO *current_dev = synclinkmp_device_list;
3718 while( current_dev->next_device )
3719 current_dev = current_dev->next_device;
3720 current_dev->next_device = info;
3721 }
3722
3723 if ( info->max_frame_size < 4096 )
3724 info->max_frame_size = 4096;
3725 else if ( info->max_frame_size > 65535 )
3726 info->max_frame_size = 65535;
3727
3728 printk( "SyncLink MultiPort %s: "
3729 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3730 info->device_name,
3731 info->phys_sca_base,
3732 info->phys_memory_base,
3733 info->phys_statctrl_base,
3734 info->phys_lcr_base,
3735 info->irq_level,
3736 info->max_frame_size );
3737
3738#if SYNCLINK_GENERIC_HDLC
3739 hdlcdev_init(info);
3740#endif
3741}
3742
3743static const struct tty_port_operations port_ops = {
3744 .carrier_raised = carrier_raised,
3745 .dtr_rts = dtr_rts,
3746};
3747
3748
3749
3750
3751
3752static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3753{
3754 SLMP_INFO *info;
3755
3756 info = kzalloc(sizeof(SLMP_INFO),
3757 GFP_KERNEL);
3758
3759 if (!info) {
3760 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3761 __FILE__,__LINE__, adapter_num, port_num);
3762 } else {
3763 tty_port_init(&info->port);
3764 info->port.ops = &port_ops;
3765 info->magic = MGSL_MAGIC;
3766 INIT_WORK(&info->task, bh_handler);
3767 info->max_frame_size = 4096;
3768 info->port.close_delay = 5*HZ/10;
3769 info->port.closing_wait = 30*HZ;
3770 init_waitqueue_head(&info->status_event_wait_q);
3771 init_waitqueue_head(&info->event_wait_q);
3772 spin_lock_init(&info->netlock);
3773 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3774 info->idle_mode = HDLC_TXIDLE_FLAGS;
3775 info->adapter_num = adapter_num;
3776 info->port_num = port_num;
3777
3778
3779 info->irq_level = pdev->irq;
3780 info->phys_lcr_base = pci_resource_start(pdev,0);
3781 info->phys_sca_base = pci_resource_start(pdev,2);
3782 info->phys_memory_base = pci_resource_start(pdev,3);
3783 info->phys_statctrl_base = pci_resource_start(pdev,4);
3784
3785
3786
3787
3788
3789 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3790 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3791
3792 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3793 info->phys_sca_base &= ~(PAGE_SIZE-1);
3794
3795 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3796 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3797
3798 info->bus_type = MGSL_BUS_TYPE_PCI;
3799 info->irq_flags = IRQF_SHARED;
3800
3801 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3802 setup_timer(&info->status_timer, status_timeout,
3803 (unsigned long)info);
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814 info->misc_ctrl_value = 0x087e4546;
3815
3816
3817
3818
3819
3820
3821
3822 info->init_error = -1;
3823 }
3824
3825 return info;
3826}
3827
3828static void device_init(int adapter_num, struct pci_dev *pdev)
3829{
3830 SLMP_INFO *port_array[SCA_MAX_PORTS];
3831 int port;
3832
3833
3834 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3835 port_array[port] = alloc_dev(adapter_num,port,pdev);
3836 if( port_array[port] == NULL ) {
3837 for ( --port; port >= 0; --port )
3838 kfree(port_array[port]);
3839 return;
3840 }
3841 }
3842
3843
3844 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3845 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3846 add_device( port_array[port] );
3847 spin_lock_init(&port_array[port]->lock);
3848 }
3849
3850
3851 if ( !claim_resources(port_array[0]) ) {
3852
3853 alloc_dma_bufs(port_array[0]);
3854
3855
3856 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3857 port_array[port]->lock = port_array[0]->lock;
3858 port_array[port]->irq_level = port_array[0]->irq_level;
3859 port_array[port]->memory_base = port_array[0]->memory_base;
3860 port_array[port]->sca_base = port_array[0]->sca_base;
3861 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3862 port_array[port]->lcr_base = port_array[0]->lcr_base;
3863 alloc_dma_bufs(port_array[port]);
3864 }
3865
3866 if ( request_irq(port_array[0]->irq_level,
3867 synclinkmp_interrupt,
3868 port_array[0]->irq_flags,
3869 port_array[0]->device_name,
3870 port_array[0]) < 0 ) {
3871 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3872 __FILE__,__LINE__,
3873 port_array[0]->device_name,
3874 port_array[0]->irq_level );
3875 }
3876 else {
3877 port_array[0]->irq_requested = true;
3878 adapter_test(port_array[0]);
3879 }
3880 }
3881}
3882
3883static const struct tty_operations ops = {
3884 .open = open,
3885 .close = close,
3886 .write = write,
3887 .put_char = put_char,
3888 .flush_chars = flush_chars,
3889 .write_room = write_room,
3890 .chars_in_buffer = chars_in_buffer,
3891 .flush_buffer = flush_buffer,
3892 .ioctl = ioctl,
3893 .throttle = throttle,
3894 .unthrottle = unthrottle,
3895 .send_xchar = send_xchar,
3896 .break_ctl = set_break,
3897 .wait_until_sent = wait_until_sent,
3898 .set_termios = set_termios,
3899 .stop = tx_hold,
3900 .start = tx_release,
3901 .hangup = hangup,
3902 .tiocmget = tiocmget,
3903 .tiocmset = tiocmset,
3904 .get_icount = get_icount,
3905 .proc_fops = &synclinkmp_proc_fops,
3906};
3907
3908
3909static void synclinkmp_cleanup(void)
3910{
3911 int rc;
3912 SLMP_INFO *info;
3913 SLMP_INFO *tmp;
3914
3915 printk("Unloading %s %s\n", driver_name, driver_version);
3916
3917 if (serial_driver) {
3918 if ((rc = tty_unregister_driver(serial_driver)))
3919 printk("%s(%d) failed to unregister tty driver err=%d\n",
3920 __FILE__,__LINE__,rc);
3921 put_tty_driver(serial_driver);
3922 }
3923
3924
3925 info = synclinkmp_device_list;
3926 while(info) {
3927 reset_port(info);
3928 info = info->next_device;
3929 }
3930
3931
3932 info = synclinkmp_device_list;
3933 while(info) {
3934#if SYNCLINK_GENERIC_HDLC
3935 hdlcdev_exit(info);
3936#endif
3937 free_dma_bufs(info);
3938 free_tmp_rx_buf(info);
3939 if ( info->port_num == 0 ) {
3940 if (info->sca_base)
3941 write_reg(info, LPR, 1);
3942 release_resources(info);
3943 }
3944 tmp = info;
3945 info = info->next_device;
3946 kfree(tmp);
3947 }
3948
3949 pci_unregister_driver(&synclinkmp_pci_driver);
3950}
3951
3952
3953
3954
3955static int __init synclinkmp_init(void)
3956{
3957 int rc;
3958
3959 if (break_on_load) {
3960 synclinkmp_get_text_ptr();
3961 BREAKPOINT();
3962 }
3963
3964 printk("%s %s\n", driver_name, driver_version);
3965
3966 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3967 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3968 return rc;
3969 }
3970
3971 serial_driver = alloc_tty_driver(128);
3972 if (!serial_driver) {
3973 rc = -ENOMEM;
3974 goto error;
3975 }
3976
3977
3978
3979 serial_driver->driver_name = "synclinkmp";
3980 serial_driver->name = "ttySLM";
3981 serial_driver->major = ttymajor;
3982 serial_driver->minor_start = 64;
3983 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3984 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3985 serial_driver->init_termios = tty_std_termios;
3986 serial_driver->init_termios.c_cflag =
3987 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3988 serial_driver->init_termios.c_ispeed = 9600;
3989 serial_driver->init_termios.c_ospeed = 9600;
3990 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3991 tty_set_operations(serial_driver, &ops);
3992 if ((rc = tty_register_driver(serial_driver)) < 0) {
3993 printk("%s(%d):Couldn't register serial driver\n",
3994 __FILE__,__LINE__);
3995 put_tty_driver(serial_driver);
3996 serial_driver = NULL;
3997 goto error;
3998 }
3999
4000 printk("%s %s, tty major#%d\n",
4001 driver_name, driver_version,
4002 serial_driver->major);
4003
4004 return 0;
4005
4006error:
4007 synclinkmp_cleanup();
4008 return rc;
4009}
4010
4011static void __exit synclinkmp_exit(void)
4012{
4013 synclinkmp_cleanup();
4014}
4015
4016module_init(synclinkmp_init);
4017module_exit(synclinkmp_exit);
4018
4019
4020
4021
4022
4023static void enable_loopback(SLMP_INFO *info, int enable)
4024{
4025 if (enable) {
4026
4027
4028
4029 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4030
4031
4032 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4033 write_control_reg(info);
4034
4035
4036
4037
4038
4039
4040 write_reg(info, RXS, 0x40);
4041 write_reg(info, TXS, 0x40);
4042
4043 } else {
4044
4045
4046
4047 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4048
4049
4050
4051
4052
4053
4054 write_reg(info, RXS, 0x00);
4055 write_reg(info, TXS, 0x00);
4056 }
4057
4058
4059 if (info->params.clock_speed)
4060 set_rate(info, info->params.clock_speed);
4061 else
4062 set_rate(info, 3686400);
4063}
4064
4065
4066
4067
4068
4069
4070static void set_rate( SLMP_INFO *info, u32 data_rate )
4071{
4072 u32 TMCValue;
4073 unsigned char BRValue;
4074 u32 Divisor=0;
4075
4076
4077
4078 if (data_rate != 0) {
4079 Divisor = 14745600/data_rate;
4080 if (!Divisor)
4081 Divisor = 1;
4082
4083 TMCValue = Divisor;
4084
4085 BRValue = 0;
4086 if (TMCValue != 1 && TMCValue != 2) {
4087
4088
4089
4090
4091 BRValue = 1;
4092 TMCValue >>= 1;
4093 }
4094
4095
4096
4097
4098 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4099 TMCValue >>= 1;
4100
4101 write_reg(info, TXS,
4102 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4103 write_reg(info, RXS,
4104 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4105 write_reg(info, TMC, (unsigned char)TMCValue);
4106 }
4107 else {
4108 write_reg(info, TXS,0);
4109 write_reg(info, RXS,0);
4110 write_reg(info, TMC, 0);
4111 }
4112}
4113
4114
4115
4116static void rx_stop(SLMP_INFO *info)
4117{
4118 if (debug_level >= DEBUG_LEVEL_ISR)
4119 printk("%s(%d):%s rx_stop()\n",
4120 __FILE__,__LINE__, info->device_name );
4121
4122 write_reg(info, CMD, RXRESET);
4123
4124 info->ie0_value &= ~RXRDYE;
4125 write_reg(info, IE0, info->ie0_value);
4126
4127 write_reg(info, RXDMA + DSR, 0);
4128 write_reg(info, RXDMA + DCMD, SWABORT);
4129 write_reg(info, RXDMA + DIR, 0);
4130
4131 info->rx_enabled = false;
4132 info->rx_overflow = false;
4133}
4134
4135
4136
4137static void rx_start(SLMP_INFO *info)
4138{
4139 int i;
4140
4141 if (debug_level >= DEBUG_LEVEL_ISR)
4142 printk("%s(%d):%s rx_start()\n",
4143 __FILE__,__LINE__, info->device_name );
4144
4145 write_reg(info, CMD, RXRESET);
4146
4147 if ( info->params.mode == MGSL_MODE_HDLC ) {
4148
4149 info->ie0_value &= ~RXRDYE;
4150 write_reg(info, IE0, info->ie0_value);
4151
4152
4153 write_reg(info, RXDMA + DSR, 0);
4154 write_reg(info, RXDMA + DCMD, SWABORT);
4155
4156 for (i = 0; i < info->rx_buf_count; i++) {
4157 info->rx_buf_list[i].status = 0xff;
4158
4159
4160
4161 if (!(i % 4))
4162 read_status_reg(info);
4163 }
4164 info->current_rx_buf = 0;
4165
4166
4167 write_reg16(info, RXDMA + CDA,
4168 info->rx_buf_list_ex[0].phys_entry);
4169
4170
4171 write_reg16(info, RXDMA + EDA,
4172 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4173
4174
4175 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4176
4177 write_reg(info, RXDMA + DIR, 0x60);
4178 write_reg(info, RXDMA + DSR, 0xf2);
4179 } else {
4180
4181 info->ie0_value |= RXRDYE;
4182 write_reg(info, IE0, info->ie0_value);
4183 }
4184
4185 write_reg(info, CMD, RXENABLE);
4186
4187 info->rx_overflow = false;
4188 info->rx_enabled = true;
4189}
4190
4191
4192
4193
4194static void tx_start(SLMP_INFO *info)
4195{
4196 if (debug_level >= DEBUG_LEVEL_ISR)
4197 printk("%s(%d):%s tx_start() tx_count=%d\n",
4198 __FILE__,__LINE__, info->device_name,info->tx_count );
4199
4200 if (!info->tx_enabled ) {
4201 write_reg(info, CMD, TXRESET);
4202 write_reg(info, CMD, TXENABLE);
4203 info->tx_enabled = true;
4204 }
4205
4206 if ( info->tx_count ) {
4207
4208
4209
4210
4211
4212 info->drop_rts_on_tx_done = false;
4213
4214 if (info->params.mode != MGSL_MODE_ASYNC) {
4215
4216 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4217 get_signals( info );
4218 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4219 info->serial_signals |= SerialSignal_RTS;
4220 set_signals( info );
4221 info->drop_rts_on_tx_done = true;
4222 }
4223 }
4224
4225 write_reg16(info, TRC0,
4226 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4227
4228 write_reg(info, TXDMA + DSR, 0);
4229 write_reg(info, TXDMA + DCMD, SWABORT);
4230
4231
4232 write_reg16(info, TXDMA + CDA,
4233 info->tx_buf_list_ex[0].phys_entry);
4234
4235
4236 write_reg16(info, TXDMA + EDA,
4237 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4238
4239
4240 info->ie1_value &= ~IDLE;
4241 info->ie1_value |= UDRN;
4242 write_reg(info, IE1, info->ie1_value);
4243 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4244
4245 write_reg(info, TXDMA + DIR, 0x40);
4246 write_reg(info, TXDMA + DSR, 0xf2);
4247
4248 mod_timer(&info->tx_timer, jiffies +
4249 msecs_to_jiffies(5000));
4250 }
4251 else {
4252 tx_load_fifo(info);
4253
4254 info->ie0_value |= TXRDYE;
4255 write_reg(info, IE0, info->ie0_value);
4256 }
4257
4258 info->tx_active = true;
4259 }
4260}
4261
4262
4263
4264static void tx_stop( SLMP_INFO *info )
4265{
4266 if (debug_level >= DEBUG_LEVEL_ISR)
4267 printk("%s(%d):%s tx_stop()\n",
4268 __FILE__,__LINE__, info->device_name );
4269
4270 del_timer(&info->tx_timer);
4271
4272 write_reg(info, TXDMA + DSR, 0);
4273 write_reg(info, TXDMA + DCMD, SWABORT);
4274
4275 write_reg(info, CMD, TXRESET);
4276
4277 info->ie1_value &= ~(UDRN + IDLE);
4278 write_reg(info, IE1, info->ie1_value);
4279 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4280
4281 info->ie0_value &= ~TXRDYE;
4282 write_reg(info, IE0, info->ie0_value);
4283
4284 info->tx_enabled = false;
4285 info->tx_active = false;
4286}
4287
4288
4289
4290
4291static void tx_load_fifo(SLMP_INFO *info)
4292{
4293 u8 TwoBytes[2];
4294
4295
4296
4297 if ( !info->tx_count && !info->x_char )
4298 return;
4299
4300
4301
4302 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4303
4304
4305
4306
4307 if ( (info->tx_count > 1) && !info->x_char ) {
4308
4309 TwoBytes[0] = info->tx_buf[info->tx_get++];
4310 if (info->tx_get >= info->max_frame_size)
4311 info->tx_get -= info->max_frame_size;
4312 TwoBytes[1] = info->tx_buf[info->tx_get++];
4313 if (info->tx_get >= info->max_frame_size)
4314 info->tx_get -= info->max_frame_size;
4315
4316 write_reg16(info, TRB, *((u16 *)TwoBytes));
4317
4318 info->tx_count -= 2;
4319 info->icount.tx += 2;
4320 } else {
4321
4322
4323 if (info->x_char) {
4324
4325 write_reg(info, TRB, info->x_char);
4326 info->x_char = 0;
4327 } else {
4328 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4329 if (info->tx_get >= info->max_frame_size)
4330 info->tx_get -= info->max_frame_size;
4331 info->tx_count--;
4332 }
4333 info->icount.tx++;
4334 }
4335 }
4336}
4337
4338
4339
4340static void reset_port(SLMP_INFO *info)
4341{
4342 if (info->sca_base) {
4343
4344 tx_stop(info);
4345 rx_stop(info);
4346
4347 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4348 set_signals(info);
4349
4350
4351 info->ie0_value = 0;
4352 info->ie1_value = 0;
4353 info->ie2_value = 0;
4354 write_reg(info, IE0, info->ie0_value);
4355 write_reg(info, IE1, info->ie1_value);
4356 write_reg(info, IE2, info->ie2_value);
4357
4358 write_reg(info, CMD, CHRESET);
4359 }
4360}
4361
4362
4363
4364static void reset_adapter(SLMP_INFO *info)
4365{
4366 int i;
4367
4368 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4369 if (info->port_array[i])
4370 reset_port(info->port_array[i]);
4371 }
4372}
4373
4374
4375
4376static void async_mode(SLMP_INFO *info)
4377{
4378
4379 unsigned char RegValue;
4380
4381 tx_stop(info);
4382 rx_stop(info);
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394 RegValue = 0x00;
4395 if (info->params.stop_bits != 1)
4396 RegValue |= BIT1;
4397 write_reg(info, MD0, RegValue);
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408 RegValue = 0x40;
4409 switch (info->params.data_bits) {
4410 case 7: RegValue |= BIT4 + BIT2; break;
4411 case 6: RegValue |= BIT5 + BIT3; break;
4412 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4413 }
4414 if (info->params.parity != ASYNC_PARITY_NONE) {
4415 RegValue |= BIT1;
4416 if (info->params.parity == ASYNC_PARITY_ODD)
4417 RegValue |= BIT0;
4418 }
4419 write_reg(info, MD1, RegValue);
4420
4421
4422
4423
4424
4425
4426
4427
4428 RegValue = 0x00;
4429 if (info->params.loopback)
4430 RegValue |= (BIT1 + BIT0);
4431 write_reg(info, MD2, RegValue);
4432
4433
4434
4435
4436
4437
4438
4439 RegValue=BIT6;
4440 write_reg(info, RXS, RegValue);
4441
4442
4443
4444
4445
4446
4447
4448 RegValue=BIT6;
4449 write_reg(info, TXS, RegValue);
4450
4451
4452
4453
4454
4455 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4456 write_control_reg(info);
4457
4458 tx_set_idle(info);
4459
4460
4461
4462
4463
4464
4465 write_reg(info, RRC, 0x00);
4466
4467
4468
4469
4470
4471
4472 write_reg(info, TRC0, 0x10);
4473
4474
4475
4476
4477
4478
4479 write_reg(info, TRC1, 0x1e);
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493 RegValue = 0x10;
4494 if (!(info->serial_signals & SerialSignal_RTS))
4495 RegValue |= 0x01;
4496 write_reg(info, CTL, RegValue);
4497
4498
4499 info->ie0_value |= TXINTE + RXINTE;
4500 write_reg(info, IE0, info->ie0_value);
4501
4502
4503 info->ie1_value = BRKD;
4504 write_reg(info, IE1, info->ie1_value);
4505
4506
4507 info->ie2_value = OVRN;
4508 write_reg(info, IE2, info->ie2_value);
4509
4510 set_rate( info, info->params.data_rate * 16 );
4511}
4512
4513
4514
4515static void hdlc_mode(SLMP_INFO *info)
4516{
4517 unsigned char RegValue;
4518 u32 DpllDivisor;
4519
4520
4521
4522
4523
4524 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4525
4526
4527 write_reg(info, TXDMA + DIR, 0);
4528 write_reg(info, RXDMA + DIR, 0);
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541 RegValue = 0x81;
4542 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4543 RegValue |= BIT4;
4544 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4545 RegValue |= BIT4;
4546 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4547 RegValue |= BIT2 + BIT1;
4548 write_reg(info, MD0, RegValue);
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559 RegValue = 0x00;
4560 write_reg(info, MD1, RegValue);
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572 RegValue = 0x00;
4573 switch(info->params.encoding) {
4574 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4575 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break;
4576 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break;
4577 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;
4578#if 0
4579 case HDLC_ENCODING_NRZB:
4580 case HDLC_ENCODING_NRZI_MARK:
4581 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4582#endif
4583 }
4584 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4585 DpllDivisor = 16;
4586 RegValue |= BIT3;
4587 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4588 DpllDivisor = 8;
4589 } else {
4590 DpllDivisor = 32;
4591 RegValue |= BIT4;
4592 }
4593 write_reg(info, MD2, RegValue);
4594
4595
4596
4597
4598
4599
4600
4601
4602 RegValue=0;
4603 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4604 RegValue |= BIT6;
4605 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4606 RegValue |= BIT6 + BIT5;
4607 write_reg(info, RXS, RegValue);
4608
4609
4610
4611
4612
4613
4614
4615 RegValue=0;
4616 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4617 RegValue |= BIT6;
4618 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4619 RegValue |= BIT6 + BIT5;
4620 write_reg(info, TXS, RegValue);
4621
4622 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4623 set_rate(info, info->params.clock_speed * DpllDivisor);
4624 else
4625 set_rate(info, info->params.clock_speed);
4626
4627
4628
4629
4630
4631 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4632 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4633 else
4634 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4635 write_control_reg(info);
4636
4637
4638
4639
4640
4641
4642 write_reg(info, RRC, rx_active_fifo_level);
4643
4644
4645
4646
4647
4648
4649 write_reg(info, TRC0, tx_active_fifo_level);
4650
4651
4652
4653
4654
4655
4656 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669 write_reg(info, TXDMA + DMR, 0x14);
4670 write_reg(info, RXDMA + DMR, 0x14);
4671
4672
4673 write_reg(info, RXDMA + CPB,
4674 (unsigned char)(info->buffer_list_phys >> 16));
4675
4676
4677 write_reg(info, TXDMA + CPB,
4678 (unsigned char)(info->buffer_list_phys >> 16));
4679
4680
4681
4682
4683 info->ie0_value |= TXINTE + RXINTE;
4684 write_reg(info, IE0, info->ie0_value);
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698 RegValue = 0x10;
4699 if (!(info->serial_signals & SerialSignal_RTS))
4700 RegValue |= 0x01;
4701 write_reg(info, CTL, RegValue);
4702
4703
4704
4705 tx_set_idle(info);
4706 tx_stop(info);
4707 rx_stop(info);
4708
4709 set_rate(info, info->params.clock_speed);
4710
4711 if (info->params.loopback)
4712 enable_loopback(info,1);
4713}
4714
4715
4716
4717static void tx_set_idle(SLMP_INFO *info)
4718{
4719 unsigned char RegValue = 0xff;
4720
4721
4722 switch(info->idle_mode) {
4723 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4724 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4725 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4726 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4727 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4728 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4729 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4730 }
4731
4732 write_reg(info, IDL, RegValue);
4733}
4734
4735
4736
4737static void get_signals(SLMP_INFO *info)
4738{
4739 u16 status = read_reg(info, SR3);
4740 u16 gpstatus = read_status_reg(info);
4741 u16 testbit;
4742
4743
4744 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4745
4746
4747
4748 if (!(status & BIT3))
4749 info->serial_signals |= SerialSignal_CTS;
4750
4751 if ( !(status & BIT2))
4752 info->serial_signals |= SerialSignal_DCD;
4753
4754 testbit = BIT1 << (info->port_num * 2);
4755 if (!(gpstatus & testbit))
4756 info->serial_signals |= SerialSignal_RI;
4757
4758 testbit = BIT0 << (info->port_num * 2);
4759 if (!(gpstatus & testbit))
4760 info->serial_signals |= SerialSignal_DSR;
4761}
4762
4763
4764
4765
4766static void set_signals(SLMP_INFO *info)
4767{
4768 unsigned char RegValue;
4769 u16 EnableBit;
4770
4771 RegValue = read_reg(info, CTL);
4772 if (info->serial_signals & SerialSignal_RTS)
4773 RegValue &= ~BIT0;
4774 else
4775 RegValue |= BIT0;
4776 write_reg(info, CTL, RegValue);
4777
4778
4779 EnableBit = BIT1 << (info->port_num*2);
4780 if (info->serial_signals & SerialSignal_DTR)
4781 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4782 else
4783 info->port_array[0]->ctrlreg_value |= EnableBit;
4784 write_control_reg(info);
4785}
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795static void rx_reset_buffers(SLMP_INFO *info)
4796{
4797 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4798}
4799
4800
4801
4802
4803
4804
4805
4806static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4807{
4808 bool done = false;
4809
4810 while(!done) {
4811
4812 info->rx_buf_list[first].status = 0xff;
4813
4814 if (first == last) {
4815 done = true;
4816
4817 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4818 }
4819
4820 first++;
4821 if (first == info->rx_buf_count)
4822 first = 0;
4823 }
4824
4825
4826 info->current_rx_buf = first;
4827}
4828
4829
4830
4831
4832
4833
4834static bool rx_get_frame(SLMP_INFO *info)
4835{
4836 unsigned int StartIndex, EndIndex;
4837 unsigned short status;
4838 unsigned int framesize = 0;
4839 bool ReturnCode = false;
4840 unsigned long flags;
4841 struct tty_struct *tty = info->port.tty;
4842 unsigned char addr_field = 0xff;
4843 SCADESC *desc;
4844 SCADESC_EX *desc_ex;
4845
4846CheckAgain:
4847
4848 framesize = 0;
4849 addr_field = 0xff;
4850
4851
4852
4853
4854
4855
4856
4857 StartIndex = EndIndex = info->current_rx_buf;
4858
4859 for ( ;; ) {
4860 desc = &info->rx_buf_list[EndIndex];
4861 desc_ex = &info->rx_buf_list_ex[EndIndex];
4862
4863 if (desc->status == 0xff)
4864 goto Cleanup;
4865
4866 if (framesize == 0 && info->params.addr_filter != 0xff)
4867 addr_field = desc_ex->virt_addr[0];
4868
4869 framesize += desc->length;
4870
4871
4872 if (desc->status)
4873 break;
4874
4875 EndIndex++;
4876 if (EndIndex == info->rx_buf_count)
4877 EndIndex = 0;
4878
4879 if (EndIndex == info->current_rx_buf) {
4880
4881
4882 if ( info->rx_enabled ){
4883 spin_lock_irqsave(&info->lock,flags);
4884 rx_start(info);
4885 spin_unlock_irqrestore(&info->lock,flags);
4886 }
4887 goto Cleanup;
4888 }
4889
4890 }
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904 status = desc->status;
4905
4906
4907
4908 if (info->params.crc_type == HDLC_CRC_NONE)
4909 status &= ~BIT2;
4910
4911 if (framesize == 0 ||
4912 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4913
4914
4915
4916 rx_free_frame_buffers(info, StartIndex, EndIndex);
4917 goto CheckAgain;
4918 }
4919
4920 if (framesize < 2)
4921 status |= BIT6;
4922
4923 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4924
4925
4926
4927 if (status & BIT6)
4928 info->icount.rxshort++;
4929 else if (status & BIT5)
4930 info->icount.rxabort++;
4931 else if (status & BIT3)
4932 info->icount.rxover++;
4933 else
4934 info->icount.rxcrc++;
4935
4936 framesize = 0;
4937#if SYNCLINK_GENERIC_HDLC
4938 {
4939 info->netdev->stats.rx_errors++;
4940 info->netdev->stats.rx_frame_errors++;
4941 }
4942#endif
4943 }
4944
4945 if ( debug_level >= DEBUG_LEVEL_BH )
4946 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4947 __FILE__,__LINE__,info->device_name,status,framesize);
4948
4949 if ( debug_level >= DEBUG_LEVEL_DATA )
4950 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4951 min_t(unsigned int, framesize, SCABUFSIZE), 0);
4952
4953 if (framesize) {
4954 if (framesize > info->max_frame_size)
4955 info->icount.rxlong++;
4956 else {
4957
4958 int copy_count = framesize;
4959 int index = StartIndex;
4960 unsigned char *ptmp = info->tmp_rx_buf;
4961 info->tmp_rx_buf_count = framesize;
4962
4963 info->icount.rxok++;
4964
4965 while(copy_count) {
4966 int partial_count = min(copy_count,SCABUFSIZE);
4967 memcpy( ptmp,
4968 info->rx_buf_list_ex[index].virt_addr,
4969 partial_count );
4970 ptmp += partial_count;
4971 copy_count -= partial_count;
4972
4973 if ( ++index == info->rx_buf_count )
4974 index = 0;
4975 }
4976
4977#if SYNCLINK_GENERIC_HDLC
4978 if (info->netcount)
4979 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4980 else
4981#endif
4982 ldisc_receive_buf(tty,info->tmp_rx_buf,
4983 info->flag_buf, framesize);
4984 }
4985 }
4986
4987 rx_free_frame_buffers( info, StartIndex, EndIndex );
4988
4989 ReturnCode = true;
4990
4991Cleanup:
4992 if ( info->rx_enabled && info->rx_overflow ) {
4993
4994
4995
4996 if (info->rx_buf_list[EndIndex].status == 0xff) {
4997 spin_lock_irqsave(&info->lock,flags);
4998 rx_start(info);
4999 spin_unlock_irqrestore(&info->lock,flags);
5000 }
5001 }
5002
5003 return ReturnCode;
5004}
5005
5006
5007
5008static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5009{
5010 unsigned short copy_count;
5011 unsigned int i = 0;
5012 SCADESC *desc;
5013 SCADESC_EX *desc_ex;
5014
5015 if ( debug_level >= DEBUG_LEVEL_DATA )
5016 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5017
5018
5019
5020
5021 for(i=0;;)
5022 {
5023 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5024
5025 desc = &info->tx_buf_list[i];
5026 desc_ex = &info->tx_buf_list_ex[i];
5027
5028 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5029
5030 desc->length = copy_count;
5031 desc->status = 0;
5032
5033 buf += copy_count;
5034 count -= copy_count;
5035
5036 if (!count)
5037 break;
5038
5039 i++;
5040 if (i >= info->tx_buf_count)
5041 i = 0;
5042 }
5043
5044 info->tx_buf_list[i].status = 0x81;
5045 info->last_tx_buf = ++i;
5046}
5047
5048static bool register_test(SLMP_INFO *info)
5049{
5050 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5051 static unsigned int count = ARRAY_SIZE(testval);
5052 unsigned int i;
5053 bool rc = true;
5054 unsigned long flags;
5055
5056 spin_lock_irqsave(&info->lock,flags);
5057 reset_port(info);
5058
5059
5060 info->init_error = DiagStatus_AddressFailure;
5061
5062
5063
5064
5065 for (i = 0 ; i < count ; i++) {
5066 write_reg(info, TMC, testval[i]);
5067 write_reg(info, IDL, testval[(i+1)%count]);
5068 write_reg(info, SA0, testval[(i+2)%count]);
5069 write_reg(info, SA1, testval[(i+3)%count]);
5070
5071 if ( (read_reg(info, TMC) != testval[i]) ||
5072 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5073 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5074 (read_reg(info, SA1) != testval[(i+3)%count]) )
5075 {
5076 rc = false;
5077 break;
5078 }
5079 }
5080
5081 reset_port(info);
5082 spin_unlock_irqrestore(&info->lock,flags);
5083
5084 return rc;
5085}
5086
5087static bool irq_test(SLMP_INFO *info)
5088{
5089 unsigned long timeout;
5090 unsigned long flags;
5091
5092 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5093
5094 spin_lock_irqsave(&info->lock,flags);
5095 reset_port(info);
5096
5097
5098 info->init_error = DiagStatus_IrqFailure;
5099 info->irq_occurred = false;
5100
5101
5102
5103
5104 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5105
5106 write_reg(info, (unsigned char)(timer + TEPR), 0);
5107 write_reg16(info, (unsigned char)(timer + TCONR), 1);
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5121
5122 spin_unlock_irqrestore(&info->lock,flags);
5123
5124 timeout=100;
5125 while( timeout-- && !info->irq_occurred ) {
5126 msleep_interruptible(10);
5127 }
5128
5129 spin_lock_irqsave(&info->lock,flags);
5130 reset_port(info);
5131 spin_unlock_irqrestore(&info->lock,flags);
5132
5133 return info->irq_occurred;
5134}
5135
5136
5137
5138static bool sca_init(SLMP_INFO *info)
5139{
5140
5141 write_reg(info, PABR0, 0);
5142 write_reg(info, PABR1, 0);
5143 write_reg(info, WCRL, 0);
5144 write_reg(info, WCRM, 0);
5145 write_reg(info, WCRH, 0);
5146
5147
5148
5149
5150
5151
5152
5153
5154