linux/drivers/pinctrl/pinctrl-coh901.c
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   1/*
   2 * U300 GPIO module.
   3 *
   4 * Copyright (C) 2007-2011 ST-Ericsson AB
   5 * License terms: GNU General Public License (GPL) version 2
   6 * This can driver either of the two basic GPIO cores
   7 * available in the U300 platforms:
   8 * COH 901 335   - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
   9 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
  10 * Author: Linus Walleij <linus.walleij@linaro.org>
  11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
  12 */
  13#include <linux/module.h>
  14#include <linux/irq.h>
  15#include <linux/interrupt.h>
  16#include <linux/delay.h>
  17#include <linux/errno.h>
  18#include <linux/io.h>
  19#include <linux/clk.h>
  20#include <linux/err.h>
  21#include <linux/platform_device.h>
  22#include <linux/gpio.h>
  23#include <linux/list.h>
  24#include <linux/slab.h>
  25#include <linux/pinctrl/consumer.h>
  26#include <linux/pinctrl/pinconf-generic.h>
  27#include <mach/gpio-u300.h>
  28#include "pinctrl-coh901.h"
  29
  30/*
  31 * Register definitions for COH 901 335 variant
  32 */
  33#define U300_335_PORT_STRIDE                            (0x1C)
  34/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
  35#define U300_335_PXPDIR                                 (0x00)
  36#define U300_335_PXPDOR                                 (0x00)
  37/* Port X Pin Config Register 32bit (R/W) */
  38#define U300_335_PXPCR                                  (0x04)
  39/* This register layout is the same in both blocks */
  40#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK              (0x0000FFFFUL)
  41#define U300_GPIO_PXPCR_PIN_MODE_MASK                   (0x00000003UL)
  42#define U300_GPIO_PXPCR_PIN_MODE_SHIFT                  (0x00000002UL)
  43#define U300_GPIO_PXPCR_PIN_MODE_INPUT                  (0x00000000UL)
  44#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL       (0x00000001UL)
  45#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN      (0x00000002UL)
  46#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE     (0x00000003UL)
  47/* Port X Interrupt Event Register 32bit (R/W) */
  48#define U300_335_PXIEV                                  (0x08)
  49/* Port X Interrupt Enable Register 32bit (R/W) */
  50#define U300_335_PXIEN                                  (0x0C)
  51/* Port X Interrupt Force Register 32bit (R/W) */
  52#define U300_335_PXIFR                                  (0x10)
  53/* Port X Interrupt Config Register 32bit (R/W) */
  54#define U300_335_PXICR                                  (0x14)
  55/* This register layout is the same in both blocks */
  56#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK             (0x000000FFUL)
  57#define U300_GPIO_PXICR_IRQ_CONFIG_MASK                 (0x00000001UL)
  58#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE         (0x00000000UL)
  59#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE          (0x00000001UL)
  60/* Port X Pull-up Enable Register 32bit (R/W) */
  61#define U300_335_PXPER                                  (0x18)
  62/* This register layout is the same in both blocks */
  63#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK        (0x000000FFUL)
  64#define U300_GPIO_PXPER_PULL_UP_DISABLE                 (0x00000001UL)
  65/* Control Register 32bit (R/W) */
  66#define U300_335_CR                                     (0x54)
  67#define U300_335_CR_BLOCK_CLOCK_ENABLE                  (0x00000001UL)
  68
  69/*
  70 * Register definitions for COH 901 571 / 3 variant
  71 */
  72#define U300_571_PORT_STRIDE                            (0x30)
  73/*
  74 * Control Register 32bit (R/W)
  75 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
  76 * gives the number of GPIO pins.
  77 * bit 8-2  (mask 0x000001FC) contains the core version ID.
  78 */
  79#define U300_571_CR                                     (0x00)
  80#define U300_571_CR_SYNC_SEL_ENABLE                     (0x00000002UL)
  81#define U300_571_CR_BLOCK_CLKRQ_ENABLE                  (0x00000001UL)
  82/*
  83 * These registers have the same layout and function as the corresponding
  84 * COH 901 335 registers, just at different offset.
  85 */
  86#define U300_571_PXPDIR                                 (0x04)
  87#define U300_571_PXPDOR                                 (0x08)
  88#define U300_571_PXPCR                                  (0x0C)
  89#define U300_571_PXPER                                  (0x10)
  90#define U300_571_PXIEV                                  (0x14)
  91#define U300_571_PXIEN                                  (0x18)
  92#define U300_571_PXIFR                                  (0x1C)
  93#define U300_571_PXICR                                  (0x20)
  94
  95/* 8 bits per port, no version has more than 7 ports */
  96#define U300_GPIO_PINS_PER_PORT 8
  97#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
  98
  99struct u300_gpio {
 100        struct gpio_chip chip;
 101        struct list_head port_list;
 102        struct clk *clk;
 103        struct resource *memres;
 104        void __iomem *base;
 105        struct device *dev;
 106        int irq_base;
 107        u32 stride;
 108        /* Register offsets */
 109        u32 pcr;
 110        u32 dor;
 111        u32 dir;
 112        u32 per;
 113        u32 icr;
 114        u32 ien;
 115        u32 iev;
 116};
 117
 118struct u300_gpio_port {
 119        struct list_head node;
 120        struct u300_gpio *gpio;
 121        char name[8];
 122        int irq;
 123        int number;
 124        u8 toggle_edge_mode;
 125};
 126
 127/*
 128 * Macro to expand to read a specific register found in the "gpio"
 129 * struct. It requires the struct u300_gpio *gpio variable to exist in
 130 * its context. It calculates the port offset from the given pin
 131 * offset, muliplies by the port stride and adds the register offset
 132 * so it provides a pointer to the desired register.
 133 */
 134#define U300_PIN_REG(pin, reg) \
 135        (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
 136
 137/*
 138 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
 139 * register.
 140 */
 141#define U300_PIN_BIT(pin) \
 142        (1 << (pin & 0x07))
 143
 144struct u300_gpio_confdata {
 145        u16 bias_mode;
 146        bool output;
 147        int outval;
 148};
 149
 150/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
 151#define BS335_GPIO_NUM_PORTS 7
 152/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
 153#define BS365_GPIO_NUM_PORTS 5
 154
 155#define U300_FLOATING_INPUT { \
 156        .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
 157        .output = false, \
 158}
 159
 160#define U300_PULL_UP_INPUT { \
 161        .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
 162        .output = false, \
 163}
 164
 165#define U300_OUTPUT_LOW { \
 166        .output = true, \
 167        .outval = 0, \
 168}
 169
 170#define U300_OUTPUT_HIGH { \
 171        .output = true, \
 172        .outval = 1, \
 173}
 174
 175
 176/* Initial configuration */
 177static const struct __initconst u300_gpio_confdata
 178bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
 179        /* Port 0, pins 0-7 */
 180        {
 181                U300_FLOATING_INPUT,
 182                U300_OUTPUT_HIGH,
 183                U300_FLOATING_INPUT,
 184                U300_OUTPUT_LOW,
 185                U300_OUTPUT_LOW,
 186                U300_OUTPUT_LOW,
 187                U300_OUTPUT_LOW,
 188                U300_OUTPUT_LOW,
 189        },
 190        /* Port 1, pins 0-7 */
 191        {
 192                U300_OUTPUT_LOW,
 193                U300_OUTPUT_LOW,
 194                U300_OUTPUT_LOW,
 195                U300_PULL_UP_INPUT,
 196                U300_FLOATING_INPUT,
 197                U300_OUTPUT_HIGH,
 198                U300_OUTPUT_LOW,
 199                U300_OUTPUT_LOW,
 200        },
 201        /* Port 2, pins 0-7 */
 202        {
 203                U300_FLOATING_INPUT,
 204                U300_FLOATING_INPUT,
 205                U300_FLOATING_INPUT,
 206                U300_FLOATING_INPUT,
 207                U300_OUTPUT_LOW,
 208                U300_PULL_UP_INPUT,
 209                U300_OUTPUT_LOW,
 210                U300_PULL_UP_INPUT,
 211        },
 212        /* Port 3, pins 0-7 */
 213        {
 214                U300_PULL_UP_INPUT,
 215                U300_OUTPUT_LOW,
 216                U300_FLOATING_INPUT,
 217                U300_FLOATING_INPUT,
 218                U300_FLOATING_INPUT,
 219                U300_FLOATING_INPUT,
 220                U300_FLOATING_INPUT,
 221                U300_FLOATING_INPUT,
 222        },
 223        /* Port 4, pins 0-7 */
 224        {
 225                U300_FLOATING_INPUT,
 226                U300_FLOATING_INPUT,
 227                U300_FLOATING_INPUT,
 228                U300_FLOATING_INPUT,
 229                U300_FLOATING_INPUT,
 230                U300_FLOATING_INPUT,
 231                U300_FLOATING_INPUT,
 232                U300_FLOATING_INPUT,
 233        },
 234        /* Port 5, pins 0-7 */
 235        {
 236                U300_FLOATING_INPUT,
 237                U300_FLOATING_INPUT,
 238                U300_FLOATING_INPUT,
 239                U300_FLOATING_INPUT,
 240                U300_FLOATING_INPUT,
 241                U300_FLOATING_INPUT,
 242                U300_FLOATING_INPUT,
 243                U300_FLOATING_INPUT,
 244        },
 245        /* Port 6, pind 0-7 */
 246        {
 247                U300_FLOATING_INPUT,
 248                U300_FLOATING_INPUT,
 249                U300_FLOATING_INPUT,
 250                U300_FLOATING_INPUT,
 251                U300_FLOATING_INPUT,
 252                U300_FLOATING_INPUT,
 253                U300_FLOATING_INPUT,
 254                U300_FLOATING_INPUT,
 255        }
 256};
 257
 258static const struct __initconst u300_gpio_confdata
 259bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
 260        /* Port 0, pins 0-7 */
 261        {
 262                U300_FLOATING_INPUT,
 263                U300_OUTPUT_LOW,
 264                U300_FLOATING_INPUT,
 265                U300_OUTPUT_LOW,
 266                U300_OUTPUT_LOW,
 267                U300_OUTPUT_LOW,
 268                U300_PULL_UP_INPUT,
 269                U300_FLOATING_INPUT,
 270        },
 271        /* Port 1, pins 0-7 */
 272        {
 273                U300_OUTPUT_LOW,
 274                U300_FLOATING_INPUT,
 275                U300_OUTPUT_LOW,
 276                U300_FLOATING_INPUT,
 277                U300_FLOATING_INPUT,
 278                U300_OUTPUT_HIGH,
 279                U300_OUTPUT_LOW,
 280                U300_OUTPUT_LOW,
 281        },
 282        /* Port 2, pins 0-7 */
 283        {
 284                U300_FLOATING_INPUT,
 285                U300_PULL_UP_INPUT,
 286                U300_OUTPUT_LOW,
 287                U300_OUTPUT_LOW,
 288                U300_PULL_UP_INPUT,
 289                U300_PULL_UP_INPUT,
 290                U300_PULL_UP_INPUT,
 291                U300_PULL_UP_INPUT,
 292        },
 293        /* Port 3, pins 0-7 */
 294        {
 295                U300_PULL_UP_INPUT,
 296                U300_PULL_UP_INPUT,
 297                U300_PULL_UP_INPUT,
 298                U300_PULL_UP_INPUT,
 299                U300_PULL_UP_INPUT,
 300                U300_PULL_UP_INPUT,
 301                U300_PULL_UP_INPUT,
 302                U300_PULL_UP_INPUT,
 303        },
 304        /* Port 4, pins 0-7 */
 305        {
 306                U300_PULL_UP_INPUT,
 307                U300_PULL_UP_INPUT,
 308                U300_PULL_UP_INPUT,
 309                U300_PULL_UP_INPUT,
 310                /* These 4 pins doesn't exist on DB3210 */
 311                U300_OUTPUT_LOW,
 312                U300_OUTPUT_LOW,
 313                U300_OUTPUT_LOW,
 314                U300_OUTPUT_LOW,
 315        }
 316};
 317
 318/**
 319 * to_u300_gpio() - get the pointer to u300_gpio
 320 * @chip: the gpio chip member of the structure u300_gpio
 321 */
 322static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
 323{
 324        return container_of(chip, struct u300_gpio, chip);
 325}
 326
 327static int u300_gpio_request(struct gpio_chip *chip, unsigned offset)
 328{
 329        /*
 330         * Map back to global GPIO space and request muxing, the direction
 331         * parameter does not matter for this controller.
 332         */
 333        int gpio = chip->base + offset;
 334
 335        return pinctrl_request_gpio(gpio);
 336}
 337
 338static void u300_gpio_free(struct gpio_chip *chip, unsigned offset)
 339{
 340        int gpio = chip->base + offset;
 341
 342        pinctrl_free_gpio(gpio);
 343}
 344
 345static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
 346{
 347        struct u300_gpio *gpio = to_u300_gpio(chip);
 348
 349        return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
 350}
 351
 352static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 353{
 354        struct u300_gpio *gpio = to_u300_gpio(chip);
 355        unsigned long flags;
 356        u32 val;
 357
 358        local_irq_save(flags);
 359
 360        val = readl(U300_PIN_REG(offset, dor));
 361        if (value)
 362                writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
 363        else
 364                writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
 365
 366        local_irq_restore(flags);
 367}
 368
 369static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 370{
 371        struct u300_gpio *gpio = to_u300_gpio(chip);
 372        unsigned long flags;
 373        u32 val;
 374
 375        local_irq_save(flags);
 376        val = readl(U300_PIN_REG(offset, pcr));
 377        /* Mask out this pin, note 2 bits per setting */
 378        val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
 379        writel(val, U300_PIN_REG(offset, pcr));
 380        local_irq_restore(flags);
 381        return 0;
 382}
 383
 384static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 385                                      int value)
 386{
 387        struct u300_gpio *gpio = to_u300_gpio(chip);
 388        unsigned long flags;
 389        u32 oldmode;
 390        u32 val;
 391
 392        local_irq_save(flags);
 393        val = readl(U300_PIN_REG(offset, pcr));
 394        /*
 395         * Drive mode must be set by the special mode set function, set
 396         * push/pull mode by default if no mode has been selected.
 397         */
 398        oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
 399                         ((offset & 0x07) << 1));
 400        /* mode = 0 means input, else some mode is already set */
 401        if (oldmode == 0) {
 402                val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
 403                         ((offset & 0x07) << 1));
 404                val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
 405                        << ((offset & 0x07) << 1));
 406                writel(val, U300_PIN_REG(offset, pcr));
 407        }
 408        u300_gpio_set(chip, offset, value);
 409        local_irq_restore(flags);
 410        return 0;
 411}
 412
 413static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 414{
 415        struct u300_gpio *gpio = to_u300_gpio(chip);
 416        int retirq = gpio->irq_base + offset;
 417
 418        dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d\n", offset,
 419                retirq);
 420        return retirq;
 421}
 422
 423/* Returning -EINVAL means "supported but not available" */
 424int u300_gpio_config_get(struct gpio_chip *chip,
 425                         unsigned offset,
 426                         unsigned long *config)
 427{
 428        struct u300_gpio *gpio = to_u300_gpio(chip);
 429        enum pin_config_param param = (enum pin_config_param) *config;
 430        bool biasmode;
 431        u32 drmode;
 432
 433        /* One bit per pin, clamp to bool range */
 434        biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
 435
 436        /* Mask out the two bits for this pin and shift to bits 0,1 */
 437        drmode = readl(U300_PIN_REG(offset, pcr));
 438        drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
 439        drmode >>= ((offset & 0x07) << 1);
 440
 441        switch(param) {
 442        case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 443                *config = 0;
 444                if (biasmode)
 445                        return 0;
 446                else
 447                        return -EINVAL;
 448                break;
 449        case PIN_CONFIG_BIAS_PULL_UP:
 450                *config = 0;
 451                if (!biasmode)
 452                        return 0;
 453                else
 454                        return -EINVAL;
 455                break;
 456        case PIN_CONFIG_DRIVE_PUSH_PULL:
 457                *config = 0;
 458                if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
 459                        return 0;
 460                else
 461                        return -EINVAL;
 462                break;
 463        case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 464                *config = 0;
 465                if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
 466                        return 0;
 467                else
 468                        return -EINVAL;
 469                break;
 470        case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 471                *config = 0;
 472                if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
 473                        return 0;
 474                else
 475                        return -EINVAL;
 476                break;
 477        default:
 478                break;
 479        }
 480        return -ENOTSUPP;
 481}
 482
 483int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
 484                         enum pin_config_param param)
 485{
 486        struct u300_gpio *gpio = to_u300_gpio(chip);
 487        unsigned long flags;
 488        u32 val;
 489
 490        local_irq_save(flags);
 491        switch (param) {
 492        case PIN_CONFIG_BIAS_DISABLE:
 493        case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 494                val = readl(U300_PIN_REG(offset, per));
 495                writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
 496                break;
 497        case PIN_CONFIG_BIAS_PULL_UP:
 498                val = readl(U300_PIN_REG(offset, per));
 499                writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
 500                break;
 501        case PIN_CONFIG_DRIVE_PUSH_PULL:
 502                val = readl(U300_PIN_REG(offset, pcr));
 503                val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 504                         << ((offset & 0x07) << 1));
 505                val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
 506                        << ((offset & 0x07) << 1));
 507                writel(val, U300_PIN_REG(offset, pcr));
 508                break;
 509        case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 510                val = readl(U300_PIN_REG(offset, pcr));
 511                val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 512                         << ((offset & 0x07) << 1));
 513                val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
 514                        << ((offset & 0x07) << 1));
 515                writel(val, U300_PIN_REG(offset, pcr));
 516                break;
 517        case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 518                val = readl(U300_PIN_REG(offset, pcr));
 519                val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 520                         << ((offset & 0x07) << 1));
 521                val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
 522                        << ((offset & 0x07) << 1));
 523                writel(val, U300_PIN_REG(offset, pcr));
 524                break;
 525        default:
 526                local_irq_restore(flags);
 527                dev_err(gpio->dev, "illegal configuration requested\n");
 528                return -EINVAL;
 529        }
 530        local_irq_restore(flags);
 531        return 0;
 532}
 533
 534static struct gpio_chip u300_gpio_chip = {
 535        .label                  = "u300-gpio-chip",
 536        .owner                  = THIS_MODULE,
 537        .request                = u300_gpio_request,
 538        .free                   = u300_gpio_free,
 539        .get                    = u300_gpio_get,
 540        .set                    = u300_gpio_set,
 541        .direction_input        = u300_gpio_direction_input,
 542        .direction_output       = u300_gpio_direction_output,
 543        .to_irq                 = u300_gpio_to_irq,
 544};
 545
 546static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
 547{
 548        u32 val;
 549
 550        val = readl(U300_PIN_REG(offset, icr));
 551        /* Set mode depending on state */
 552        if (u300_gpio_get(&gpio->chip, offset)) {
 553                /* High now, let's trigger on falling edge next then */
 554                writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 555                dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
 556                        offset);
 557        } else {
 558                /* Low now, let's trigger on rising edge next then */
 559                writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 560                dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
 561                        offset);
 562        }
 563}
 564
 565static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
 566{
 567        struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
 568        struct u300_gpio *gpio = port->gpio;
 569        int offset = d->irq - gpio->irq_base;
 570        u32 val;
 571
 572        if ((trigger & IRQF_TRIGGER_RISING) &&
 573            (trigger & IRQF_TRIGGER_FALLING)) {
 574                /*
 575                 * The GPIO block can only trigger on falling OR rising edges,
 576                 * not both. So we need to toggle the mode whenever the pin
 577                 * goes from one state to the other with a special state flag
 578                 */
 579                dev_dbg(gpio->dev,
 580                        "trigger on both rising and falling edge on pin %d\n",
 581                        offset);
 582                port->toggle_edge_mode |= U300_PIN_BIT(offset);
 583                u300_toggle_trigger(gpio, offset);
 584        } else if (trigger & IRQF_TRIGGER_RISING) {
 585                dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
 586                        offset);
 587                val = readl(U300_PIN_REG(offset, icr));
 588                writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 589                port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
 590        } else if (trigger & IRQF_TRIGGER_FALLING) {
 591                dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
 592                        offset);
 593                val = readl(U300_PIN_REG(offset, icr));
 594                writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 595                port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
 596        }
 597
 598        return 0;
 599}
 600
 601static void u300_gpio_irq_enable(struct irq_data *d)
 602{
 603        struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
 604        struct u300_gpio *gpio = port->gpio;
 605        int offset = d->irq - gpio->irq_base;
 606        u32 val;
 607        unsigned long flags;
 608
 609        local_irq_save(flags);
 610        val = readl(U300_PIN_REG(offset, ien));
 611        writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
 612        local_irq_restore(flags);
 613}
 614
 615static void u300_gpio_irq_disable(struct irq_data *d)
 616{
 617        struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
 618        struct u300_gpio *gpio = port->gpio;
 619        int offset = d->irq - gpio->irq_base;
 620        u32 val;
 621        unsigned long flags;
 622
 623        local_irq_save(flags);
 624        val = readl(U300_PIN_REG(offset, ien));
 625        writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
 626        local_irq_restore(flags);
 627}
 628
 629static struct irq_chip u300_gpio_irqchip = {
 630        .name                   = "u300-gpio-irqchip",
 631        .irq_enable             = u300_gpio_irq_enable,
 632        .irq_disable            = u300_gpio_irq_disable,
 633        .irq_set_type           = u300_gpio_irq_type,
 634
 635};
 636
 637static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 638{
 639        struct u300_gpio_port *port = irq_get_handler_data(irq);
 640        struct u300_gpio *gpio = port->gpio;
 641        int pinoffset = port->number << 3; /* get the right stride */
 642        unsigned long val;
 643
 644        desc->irq_data.chip->irq_ack(&desc->irq_data);
 645        /* Read event register */
 646        val = readl(U300_PIN_REG(pinoffset, iev));
 647        /* Mask relevant bits */
 648        val &= 0xFFU; /* 8 bits per port */
 649        /* ACK IRQ (clear event) */
 650        writel(val, U300_PIN_REG(pinoffset, iev));
 651
 652        /* Call IRQ handler */
 653        if (val != 0) {
 654                int irqoffset;
 655
 656                for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
 657                        int pin_irq = gpio->irq_base + (port->number << 3)
 658                                + irqoffset;
 659                        int offset = pinoffset + irqoffset;
 660
 661                        dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
 662                                pin_irq, offset);
 663                        generic_handle_irq(pin_irq);
 664                        /*
 665                         * Triggering IRQ on both rising and falling edge
 666                         * needs mockery
 667                         */
 668                        if (port->toggle_edge_mode & U300_PIN_BIT(offset))
 669                                u300_toggle_trigger(gpio, offset);
 670                }
 671        }
 672
 673        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 674}
 675
 676static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
 677                                      int offset,
 678                                      const struct u300_gpio_confdata *conf)
 679{
 680        /* Set mode: input or output */
 681        if (conf->output) {
 682                u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
 683
 684                /* Deactivate bias mode for output */
 685                u300_gpio_config_set(&gpio->chip, offset,
 686                                     PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
 687
 688                /* Set drive mode for output */
 689                u300_gpio_config_set(&gpio->chip, offset,
 690                                     PIN_CONFIG_DRIVE_PUSH_PULL);
 691
 692                dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
 693                        offset, conf->outval);
 694        } else {
 695                u300_gpio_direction_input(&gpio->chip, offset);
 696
 697                /* Always set output low on input pins */
 698                u300_gpio_set(&gpio->chip, offset, 0);
 699
 700                /* Set bias mode for input */
 701                u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
 702
 703                dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
 704                        offset, conf->bias_mode);
 705        }
 706}
 707
 708static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
 709                                     struct u300_gpio_platform *plat)
 710{
 711        int i, j;
 712
 713        /* Write default config and values to all pins */
 714        for (i = 0; i < plat->ports; i++) {
 715                for (j = 0; j < 8; j++) {
 716                        const struct u300_gpio_confdata *conf;
 717                        int offset = (i*8) + j;
 718
 719                        if (plat->variant == U300_GPIO_COH901571_3_BS335)
 720                                conf = &bs335_gpio_config[i][j];
 721                        else if (plat->variant == U300_GPIO_COH901571_3_BS365)
 722                                conf = &bs365_gpio_config[i][j];
 723                        else
 724                                break;
 725
 726                        u300_gpio_init_pin(gpio, offset, conf);
 727                }
 728        }
 729}
 730
 731static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
 732{
 733        struct u300_gpio_port *port;
 734        struct list_head *p, *n;
 735
 736        list_for_each_safe(p, n, &gpio->port_list) {
 737                port = list_entry(p, struct u300_gpio_port, node);
 738                list_del(&port->node);
 739                kfree(port);
 740        }
 741}
 742
 743static int __init u300_gpio_probe(struct platform_device *pdev)
 744{
 745        struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
 746        struct u300_gpio *gpio;
 747        int err = 0;
 748        int portno;
 749        u32 val;
 750        u32 ifr;
 751        int i;
 752
 753        gpio = kzalloc(sizeof(struct u300_gpio), GFP_KERNEL);
 754        if (gpio == NULL) {
 755                dev_err(&pdev->dev, "failed to allocate memory\n");
 756                return -ENOMEM;
 757        }
 758
 759        gpio->chip = u300_gpio_chip;
 760        gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
 761        gpio->irq_base = plat->gpio_irq_base;
 762        gpio->chip.dev = &pdev->dev;
 763        gpio->chip.base = plat->gpio_base;
 764        gpio->dev = &pdev->dev;
 765
 766        /* Get GPIO clock */
 767        gpio->clk = clk_get(gpio->dev, NULL);
 768        if (IS_ERR(gpio->clk)) {
 769                err = PTR_ERR(gpio->clk);
 770                dev_err(gpio->dev, "could not get GPIO clock\n");
 771                goto err_no_clk;
 772        }
 773        err = clk_prepare_enable(gpio->clk);
 774        if (err) {
 775                dev_err(gpio->dev, "could not enable GPIO clock\n");
 776                goto err_no_clk_enable;
 777        }
 778
 779        gpio->memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 780        if (!gpio->memres) {
 781                dev_err(gpio->dev, "could not get GPIO memory resource\n");
 782                err = -ENODEV;
 783                goto err_no_resource;
 784        }
 785
 786        if (!request_mem_region(gpio->memres->start,
 787                                resource_size(gpio->memres),
 788                                "GPIO Controller")) {
 789                err = -ENODEV;
 790                goto err_no_ioregion;
 791        }
 792
 793        gpio->base = ioremap(gpio->memres->start, resource_size(gpio->memres));
 794        if (!gpio->base) {
 795                err = -ENOMEM;
 796                goto err_no_ioremap;
 797        }
 798
 799        if (plat->variant == U300_GPIO_COH901335) {
 800                dev_info(gpio->dev,
 801                         "initializing GPIO Controller COH 901 335\n");
 802                gpio->stride = U300_335_PORT_STRIDE;
 803                gpio->pcr = U300_335_PXPCR;
 804                gpio->dor = U300_335_PXPDOR;
 805                gpio->dir = U300_335_PXPDIR;
 806                gpio->per = U300_335_PXPER;
 807                gpio->icr = U300_335_PXICR;
 808                gpio->ien = U300_335_PXIEN;
 809                gpio->iev = U300_335_PXIEV;
 810                ifr = U300_335_PXIFR;
 811
 812                /* Turn on the GPIO block */
 813                writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
 814                       gpio->base + U300_335_CR);
 815        } else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
 816                   plat->variant == U300_GPIO_COH901571_3_BS365) {
 817                dev_info(gpio->dev,
 818                         "initializing GPIO Controller COH 901 571/3\n");
 819                gpio->stride = U300_571_PORT_STRIDE;
 820                gpio->pcr = U300_571_PXPCR;
 821                gpio->dor = U300_571_PXPDOR;
 822                gpio->dir = U300_571_PXPDIR;
 823                gpio->per = U300_571_PXPER;
 824                gpio->icr = U300_571_PXICR;
 825                gpio->ien = U300_571_PXIEN;
 826                gpio->iev = U300_571_PXIEV;
 827                ifr = U300_571_PXIFR;
 828
 829                val = readl(gpio->base + U300_571_CR);
 830                dev_info(gpio->dev, "COH901571/3 block version: %d, " \
 831                         "number of cores: %d totalling %d pins\n",
 832                         ((val & 0x000001FC) >> 2),
 833                         ((val & 0x0000FE00) >> 9),
 834                         ((val & 0x0000FE00) >> 9) * 8);
 835                writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
 836                       gpio->base + U300_571_CR);
 837                u300_gpio_init_coh901571(gpio, plat);
 838        } else {
 839                dev_err(gpio->dev, "unknown block variant\n");
 840                err = -ENODEV;
 841                goto err_unknown_variant;
 842        }
 843
 844        /* Add each port with its IRQ separately */
 845        INIT_LIST_HEAD(&gpio->port_list);
 846        for (portno = 0 ; portno < plat->ports; portno++) {
 847                struct u300_gpio_port *port =
 848                        kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
 849
 850                if (!port) {
 851                        dev_err(gpio->dev, "out of memory\n");
 852                        err = -ENOMEM;
 853                        goto err_no_port;
 854                }
 855
 856                snprintf(port->name, 8, "gpio%d", portno);
 857                port->number = portno;
 858                port->gpio = gpio;
 859
 860                port->irq = platform_get_irq_byname(pdev,
 861                                                    port->name);
 862
 863                dev_dbg(gpio->dev, "register IRQ %d for %s\n", port->irq,
 864                        port->name);
 865
 866                irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
 867                irq_set_handler_data(port->irq, port);
 868
 869                /* For each GPIO pin set the unique IRQ handler */
 870                for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
 871                        int irqno = gpio->irq_base + (portno << 3) + i;
 872
 873                        dev_dbg(gpio->dev, "handler for IRQ %d on %s\n",
 874                                irqno, port->name);
 875                        irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
 876                                                 handle_simple_irq);
 877                        set_irq_flags(irqno, IRQF_VALID);
 878                        irq_set_chip_data(irqno, port);
 879                }
 880
 881                /* Turns off irq force (test register) for this port */
 882                writel(0x0, gpio->base + portno * gpio->stride + ifr);
 883
 884                list_add_tail(&port->node, &gpio->port_list);
 885        }
 886        dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
 887
 888        err = gpiochip_add(&gpio->chip);
 889        if (err) {
 890                dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
 891                goto err_no_chip;
 892        }
 893
 894        /* Spawn pin controller device as child of the GPIO, pass gpio chip */
 895        plat->pinctrl_device->dev.platform_data = &gpio->chip;
 896        err = platform_device_register(plat->pinctrl_device);
 897        if (err)
 898                goto err_no_pinctrl;
 899
 900        platform_set_drvdata(pdev, gpio);
 901
 902        return 0;
 903
 904err_no_pinctrl:
 905        err = gpiochip_remove(&gpio->chip);
 906err_no_chip:
 907err_no_port:
 908        u300_gpio_free_ports(gpio);
 909err_unknown_variant:
 910        iounmap(gpio->base);
 911err_no_ioremap:
 912        release_mem_region(gpio->memres->start, resource_size(gpio->memres));
 913err_no_ioregion:
 914err_no_resource:
 915        clk_disable_unprepare(gpio->clk);
 916err_no_clk_enable:
 917        clk_put(gpio->clk);
 918err_no_clk:
 919        kfree(gpio);
 920        dev_info(&pdev->dev, "module ERROR:%d\n", err);
 921        return err;
 922}
 923
 924static int __exit u300_gpio_remove(struct platform_device *pdev)
 925{
 926        struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
 927        struct u300_gpio *gpio = platform_get_drvdata(pdev);
 928        int err;
 929
 930        /* Turn off the GPIO block */
 931        if (plat->variant == U300_GPIO_COH901335)
 932                writel(0x00000000U, gpio->base + U300_335_CR);
 933        if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
 934            plat->variant == U300_GPIO_COH901571_3_BS365)
 935                writel(0x00000000U, gpio->base + U300_571_CR);
 936
 937        err = gpiochip_remove(&gpio->chip);
 938        if (err < 0) {
 939                dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
 940                return err;
 941        }
 942        u300_gpio_free_ports(gpio);
 943        iounmap(gpio->base);
 944        release_mem_region(gpio->memres->start,
 945                           resource_size(gpio->memres));
 946        clk_disable_unprepare(gpio->clk);
 947        clk_put(gpio->clk);
 948        platform_set_drvdata(pdev, NULL);
 949        kfree(gpio);
 950        return 0;
 951}
 952
 953static struct platform_driver u300_gpio_driver = {
 954        .driver         = {
 955                .name   = "u300-gpio",
 956        },
 957        .remove         = __exit_p(u300_gpio_remove),
 958};
 959
 960static int __init u300_gpio_init(void)
 961{
 962        return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
 963}
 964
 965static void __exit u300_gpio_exit(void)
 966{
 967        platform_driver_unregister(&u300_gpio_driver);
 968}
 969
 970arch_initcall(u300_gpio_init);
 971module_exit(u300_gpio_exit);
 972
 973MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
 974MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
 975MODULE_LICENSE("GPL");
 976
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