linux/drivers/pci/msi.c
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   1/*
   2 * File:        msi.c
   3 * Purpose:     PCI Message Signaled Interrupt (MSI)
   4 *
   5 * Copyright (C) 2003-2004 Intel
   6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   7 */
   8
   9#include <linux/err.h>
  10#include <linux/mm.h>
  11#include <linux/irq.h>
  12#include <linux/interrupt.h>
  13#include <linux/init.h>
  14#include <linux/export.h>
  15#include <linux/ioport.h>
  16#include <linux/pci.h>
  17#include <linux/proc_fs.h>
  18#include <linux/msi.h>
  19#include <linux/smp.h>
  20#include <linux/errno.h>
  21#include <linux/io.h>
  22#include <linux/slab.h>
  23
  24#include "pci.h"
  25#include "msi.h"
  26
  27static int pci_msi_enable = 1;
  28
  29/* Arch hooks */
  30
  31#ifndef arch_msi_check_device
  32int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
  33{
  34        return 0;
  35}
  36#endif
  37
  38#ifndef arch_setup_msi_irqs
  39# define arch_setup_msi_irqs default_setup_msi_irqs
  40# define HAVE_DEFAULT_MSI_SETUP_IRQS
  41#endif
  42
  43#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS
  44int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
  45{
  46        struct msi_desc *entry;
  47        int ret;
  48
  49        /*
  50         * If an architecture wants to support multiple MSI, it needs to
  51         * override arch_setup_msi_irqs()
  52         */
  53        if (type == PCI_CAP_ID_MSI && nvec > 1)
  54                return 1;
  55
  56        list_for_each_entry(entry, &dev->msi_list, list) {
  57                ret = arch_setup_msi_irq(dev, entry);
  58                if (ret < 0)
  59                        return ret;
  60                if (ret > 0)
  61                        return -ENOSPC;
  62        }
  63
  64        return 0;
  65}
  66#endif
  67
  68#ifndef arch_teardown_msi_irqs
  69# define arch_teardown_msi_irqs default_teardown_msi_irqs
  70# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
  71#endif
  72
  73#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS
  74void default_teardown_msi_irqs(struct pci_dev *dev)
  75{
  76        struct msi_desc *entry;
  77
  78        list_for_each_entry(entry, &dev->msi_list, list) {
  79                int i, nvec;
  80                if (entry->irq == 0)
  81                        continue;
  82                nvec = 1 << entry->msi_attrib.multiple;
  83                for (i = 0; i < nvec; i++)
  84                        arch_teardown_msi_irq(entry->irq + i);
  85        }
  86}
  87#endif
  88
  89#ifndef arch_restore_msi_irqs
  90# define arch_restore_msi_irqs default_restore_msi_irqs
  91# define HAVE_DEFAULT_MSI_RESTORE_IRQS
  92#endif
  93
  94#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS
  95void default_restore_msi_irqs(struct pci_dev *dev, int irq)
  96{
  97        struct msi_desc *entry;
  98
  99        entry = NULL;
 100        if (dev->msix_enabled) {
 101                list_for_each_entry(entry, &dev->msi_list, list) {
 102                        if (irq == entry->irq)
 103                                break;
 104                }
 105        } else if (dev->msi_enabled)  {
 106                entry = irq_get_msi_desc(irq);
 107        }
 108
 109        if (entry)
 110                write_msi_msg(irq, &entry->msg);
 111}
 112#endif
 113
 114static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
 115{
 116        u16 control;
 117
 118        BUG_ON(!pos);
 119
 120        pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
 121        control &= ~PCI_MSI_FLAGS_ENABLE;
 122        if (enable)
 123                control |= PCI_MSI_FLAGS_ENABLE;
 124        pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
 125}
 126
 127static void msix_set_enable(struct pci_dev *dev, int enable)
 128{
 129        int pos;
 130        u16 control;
 131
 132        pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 133        if (pos) {
 134                pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
 135                control &= ~PCI_MSIX_FLAGS_ENABLE;
 136                if (enable)
 137                        control |= PCI_MSIX_FLAGS_ENABLE;
 138                pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 139        }
 140}
 141
 142static inline __attribute_const__ u32 msi_mask(unsigned x)
 143{
 144        /* Don't shift by >= width of type */
 145        if (x >= 5)
 146                return 0xffffffff;
 147        return (1 << (1 << x)) - 1;
 148}
 149
 150static inline __attribute_const__ u32 msi_capable_mask(u16 control)
 151{
 152        return msi_mask((control >> 1) & 7);
 153}
 154
 155static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
 156{
 157        return msi_mask((control >> 4) & 7);
 158}
 159
 160/*
 161 * PCI 2.3 does not specify mask bits for each MSI interrupt.  Attempting to
 162 * mask all MSI interrupts by clearing the MSI enable bit does not work
 163 * reliably as devices without an INTx disable bit will then generate a
 164 * level IRQ which will never be cleared.
 165 */
 166static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 167{
 168        u32 mask_bits = desc->masked;
 169
 170        if (!desc->msi_attrib.maskbit)
 171                return 0;
 172
 173        mask_bits &= ~mask;
 174        mask_bits |= flag;
 175        pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
 176
 177        return mask_bits;
 178}
 179
 180static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 181{
 182        desc->masked = __msi_mask_irq(desc, mask, flag);
 183}
 184
 185/*
 186 * This internal function does not flush PCI writes to the device.
 187 * All users must ensure that they read from the device before either
 188 * assuming that the device state is up to date, or returning out of this
 189 * file.  This saves a few milliseconds when initialising devices with lots
 190 * of MSI-X interrupts.
 191 */
 192static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
 193{
 194        u32 mask_bits = desc->masked;
 195        unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
 196                                                PCI_MSIX_ENTRY_VECTOR_CTRL;
 197        mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
 198        if (flag)
 199                mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
 200        writel(mask_bits, desc->mask_base + offset);
 201
 202        return mask_bits;
 203}
 204
 205static void msix_mask_irq(struct msi_desc *desc, u32 flag)
 206{
 207        desc->masked = __msix_mask_irq(desc, flag);
 208}
 209
 210static void msi_set_mask_bit(struct irq_data *data, u32 flag)
 211{
 212        struct msi_desc *desc = irq_data_get_msi(data);
 213
 214        if (desc->msi_attrib.is_msix) {
 215                msix_mask_irq(desc, flag);
 216                readl(desc->mask_base);         /* Flush write to device */
 217        } else {
 218                unsigned offset = data->irq - desc->dev->irq;
 219                msi_mask_irq(desc, 1 << offset, flag << offset);
 220        }
 221}
 222
 223void mask_msi_irq(struct irq_data *data)
 224{
 225        msi_set_mask_bit(data, 1);
 226}
 227
 228void unmask_msi_irq(struct irq_data *data)
 229{
 230        msi_set_mask_bit(data, 0);
 231}
 232
 233void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 234{
 235        BUG_ON(entry->dev->current_state != PCI_D0);
 236
 237        if (entry->msi_attrib.is_msix) {
 238                void __iomem *base = entry->mask_base +
 239                        entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 240
 241                msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
 242                msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
 243                msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
 244        } else {
 245                struct pci_dev *dev = entry->dev;
 246                int pos = entry->msi_attrib.pos;
 247                u16 data;
 248
 249                pci_read_config_dword(dev, msi_lower_address_reg(pos),
 250                                        &msg->address_lo);
 251                if (entry->msi_attrib.is_64) {
 252                        pci_read_config_dword(dev, msi_upper_address_reg(pos),
 253                                                &msg->address_hi);
 254                        pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
 255                } else {
 256                        msg->address_hi = 0;
 257                        pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
 258                }
 259                msg->data = data;
 260        }
 261}
 262
 263void read_msi_msg(unsigned int irq, struct msi_msg *msg)
 264{
 265        struct msi_desc *entry = irq_get_msi_desc(irq);
 266
 267        __read_msi_msg(entry, msg);
 268}
 269
 270void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 271{
 272        /* Assert that the cache is valid, assuming that
 273         * valid messages are not all-zeroes. */
 274        BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
 275                 entry->msg.data));
 276
 277        *msg = entry->msg;
 278}
 279
 280void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
 281{
 282        struct msi_desc *entry = irq_get_msi_desc(irq);
 283
 284        __get_cached_msi_msg(entry, msg);
 285}
 286
 287void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 288{
 289        if (entry->dev->current_state != PCI_D0) {
 290                /* Don't touch the hardware now */
 291        } else if (entry->msi_attrib.is_msix) {
 292                void __iomem *base;
 293                base = entry->mask_base +
 294                        entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 295
 296                writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
 297                writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
 298                writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
 299        } else {
 300                struct pci_dev *dev = entry->dev;
 301                int pos = entry->msi_attrib.pos;
 302                u16 msgctl;
 303
 304                pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
 305                msgctl &= ~PCI_MSI_FLAGS_QSIZE;
 306                msgctl |= entry->msi_attrib.multiple << 4;
 307                pci_write_config_word(dev, msi_control_reg(pos), msgctl);
 308
 309                pci_write_config_dword(dev, msi_lower_address_reg(pos),
 310                                        msg->address_lo);
 311                if (entry->msi_attrib.is_64) {
 312                        pci_write_config_dword(dev, msi_upper_address_reg(pos),
 313                                                msg->address_hi);
 314                        pci_write_config_word(dev, msi_data_reg(pos, 1), &dev,  260<="line" name="L260"> 260<="line" bits 197cl2u  197cl23c, );
/* Flush write to3devic31t;< 4;
 314                        pci_write_config_word(dev, msi_data_reg( 217dev,  260<="line" name="L260"> 260<="line" bits 197cl2u  197cl23c#L308" idirq;
o3fset);
3220);
 311     msi.c#L277" id="L277" clas class="sref">entry, struct  197cl23#L221" id3"L221" class="line" name3"L2213> 221(<="L222" class="line" nam3="L2232gctl;
dataget_cached_msi_msg(unsigned int irq, struct ms3#L224" id3"L224" class="line" name3"L2243> 224da32lag);
 282        struct msi_desc *entry = irq_get_msi3#L226" id3"L226" class="line" name3"L2263> 226}
 282        struct __get_cached_msi_msg(e3ta *<3 href="+code=data" class3"sref3>data;
da3a,
,  300                struct ms3#L231" id3"L231" class="line" name3"L2313> 231 282        struct  282 tmp  struct  197cl23_msg 3 234{
 282        struct msi        if ((__geteista>(msi_attribP33>dev;
__getnve id="L282" classnve ef="197cl2u  197cl23_L226" id3="L236" class="line" nam3="L2333t;< 4;
 311   a href="+code=irq_get_msi_97cl2u  197cl23_#L227" i3code=is_msix" class="sre3">is_3six) {
 197cl23_a *<3e=mask_base" class="sref3>mask3base +
__getnve id="L282" classnve ef="msik_irq" class="sref">msi_ma                msgctl |= entry-> 197cl23X_ENTRY_S3ZE" class="sref">PCI_MSI3_ENTR34pos),
msi_manve id="L282" classnve ef="1rs/pci/msi.c#L24 * 197cl23c#L240" i3="L240" class="line" nam3="L243"> 240
__getci/msi.c#L235" id="L235" class="line" name="L23de=ehas_aL186"> * 282        struct offset =  *m3_ADDR" cl3ss="sref">PCI_MSIX_ENTRY3LOWER3ADDR);
PCI_MSIX_ENTRY3UPPER34gctl;
PCI_MSIX3ENTRY34> 283
, m3_L234" id3ine" name="L244"> 244;
dev;
 282        struct __gettmp  struct msi        if ((__geteista>(msi_attrib3pos;
 291        } else if (entry->msi_attrib3u16 <3 href="+code=data" class3"sref34ix) {
(ms91" id="L291" class="line" name="L291"> 291  eista>(msi        if (( 197cl23ca *<3="L248" class="line" nam3="L243"> 248
__getiolassp  struct  282        struct readl( 197cl23_reg(3a href="+code=pos" class3"sref3>pos),
);
i3_64) {
                


                 255       3     3  } elpan>
                ad3ress_3i pan>
);
 291  kobjd="L291" class=kobjry" class="sref">entpacode0" class="line" acode_attrib" class="sref">msi_attrib3 class="l3ne" name="L258"> 2583     3         }
 291  kobject_d8" id="L298" claskobject_d8"="L28reg" class="sref">ms91" id="L291" class="line" name="L291"> 291  kobjd="L291" class=kobjry" c"97cl2u  197cl23a = <3 href="+code=data" class3"sref36pos),
 291  kobject_pue0" class="line"kobject_pue="L28reg" class="sref">ms91" id="L291" class="line" name="L291"> 291  kobjd="L291" class=kobjry" c"97cl2u  197cl23af="+code3lass="line" name="L260">3260 240
 261}
ms91" id="L291" class="line" name="L291"> 291  eista>( 197cl23aENTRY_DA3 282        struct  197cl23aL234" id3"L264" class="line" name3"L2643> 264{
->3a href="+code=irq" class3"sref36, 1);
, 3a href="+code=msg" class3"sref3>msg
 282 allocne" n       struct  300                struct ms3#L268" id3"L268" class="line" name3"L26836data)
 212        struct  212        struct  197cl23_msg 3 197cl23_L261" id3"L271" class="line" name3"L2713764) {
 197cl23ssert tha3 the cache is valid, ass3ming 37gctl;
msss="sref">data->( 197cl23ef="+code3address_lo" class="sref"3addre37 234{
data->irq - dev = entrg.3ata));
 276
data->entrgry, 3msg;
 278}
 279
 300                struct  197cl23_msg 3msg)
 281{
dev->ms="sINTX_DISABLE_BUGa>, ms="sINTX_DISABLE_BUGode=)_97cl2u  197cl23desc(3a href="+code=irq" class3"sref38base;
entrc#L283" i3="L283" class="line" nam3="L283"> 283/a>;
;
 285<
-> 300                struct ms3c#L286" i3="L286" class="line" nam3="L283"> 286/a>)
entrcL278" id3"L288" class="line" name3"L2883> 288{
entr= PC39pos),
 212        struct entr=msg 3on't touch the hardw3re no39set);
is_39 281{
msi        if ( 3de=denab-&"ef="+code=msi_msg" class="sref">ms3em *<3 href="+code=base" class3"sref3>base;
entr=#L283" i3e=mask_base" class="sref3>mask39 203}
PCI_MSI3_ENTR39 234{
msi_desc *entry =         if (irq_get_msi3c#L295" i3="L295" class="line" nam3="L2939>dev;
 301                int pos = entry->msi_a_ADDR" cl3ss="sref">PCI_MSIX_ENTRY3LOWER39 226}
PCI_MSIX_ENTRY3UPPER39 167{
irq_get_msi3cL278" id3A" class="sref">PCI_MSIX3ENTRY39 288{
irq_get_msi4" class="4ine" name="L299"> 299 282 arch_4"storine" nget/a>, irq_get_msi4y->44pos;
 304                p1" id="L301" class="line" f="+code=data" class="srsref">a>, _word"reg" class="sref">mscode=de02" id="L302" ccode=deine"_desc" class="sref">irq_get_msi4y3rib4403288{
 282        struct pci_wriapab-&nef="ref="+code=irq_e" niapab-&nef="="L28L282"> 282 code=de02" id="L302" ccode=deine"_l_reg" class="sreen     struct  3d="s&"ine"_desc" class="sref">irq_get_msi4y4rib4<=mask_base" class="sref4="L3040*/
 305                msgctl &= ~m40 234{
 291        } else if (entry->mENABLE"+code=msgctl" class="sref">mENABLE &= ~dev;
 314                        pc1" id="L301" class="line" f="+code=data" class="srsref">a>, _word"class="sref">mscode=de02" id="L302" ccode=deine"_desc" class="sref">irq_get_msi4y7;PCI_MSIX_ENTRY4 4lt;</a>;
m4gctl);
 308
-> 300                struct ms4_reg(4a href="+code=pos" class4"sref4>pos)
);
ent4/a>.i41 281{
 282        struct ent4/3rib4a href="+code=pos" class4"sref413288{
ent4ef="+code4address_hi" class="sref"4addre41 203}
pos, 1)4 &4msi        if ( 3de=xdenab-&"ef="+code=msi_msg" class="sref">ms4c, );
ent4 class="c4mment">/* Flush write to4devic41t;< 4;
msss/a>        if ((ent4 ,  217{
msss/a>        if ((get_cached_msi_msg(82" id="L282" class="line" namelass="sref">__geteista>(ent4 #L308" i4 301                int pos = entry->msi_4t; o42 } else {
 282  nam4" id="L304" class="line" name="L304"> 304                p1" id="L301" class="line" f="+code=data" class="srXsref">a>, _word"reg" class="sref">mscode=de02" id="L302" ccode=deine"_desc" class="sref">irq_get_msi4d="L220" 4lass="line" name="L220">4220);
{
                irq_get_msi4ta *<4 href="+code=data" class4"sref42*/
 306t;mENABLE"+code=msgctl" class="Xsref">mENABLE=msg" class="sref"class="Xsref">mMASKALL   struct mMASKALLcode=msi_attrib" class="sref">msi_4tode=pos"4"L224" class="line" name4"L22442 234{
 314                        pc1" id="L301" class="line" f="+code=data" class="srXsref">a>, _word"class="sref">mscode=de02" id="L302" ccode=deine"_desc" class="sref">irq_get_msi4d, da42ta));
 282        struct msi        if ((__geteista>(,  311   a href="+code=irq_get_msi_desc" class="sref">irq_get_msi4d#L308" i4 href="+code=data" class4"sref42ase +
__getde=xdef="+a href="+code=irq_e" xnef="+a h="L28L282"> 282        struct pcen     struct  3d="s&"ine"_desc" class="sref">irq_get_msi4#L229" id4"L229" class="line" name4"L22943set);
(da43set);
pos;
 305            Xsref">mMASKALL   struct mMASKALLcode=msi_attrib" class="sref">msi_4c#L232" i4="L232" class="line" nam4="L23433288{
 314                        pc1" id="L301" class="line" f="+code=data" class="srXsref">a>, _word"class="sref">mscode=de02" id="L302" ccode=deine"_desi_attrib" class="sref">msi_4ca *<4;
P43>dev< href="drivers/pci/m nam4"storine" nstry-> 300                struct ms4_L226" id4="L236" class="line" nam4="L2343> 286/a>)
is_43 167{
->msi_4c#L308" i4e=mask_base" class="sref4>mask43 288{
->msi_4X_ENTRY_S4ZE" class="sref">PCI_MSI4_ENTR44pos;
 240 300       EXPORT_SYMBOL_GPL   struct ->msi_4XL231" id4ss="sref">PCI_MSIX_ENTRY4LOWER44 261}
PCI_MSIX_ENTRY4UPPER44gctl;
PCI_MSIX4ENTRY44> 283#defef"ass="sref">__getto_"+code=e/a>->       objd="L291" class=objry" c"class="sref">mscodeaef"r_of02" id="L302" ccodeaef"r_of="L28 300       objd="L291" class=objry" ref">get_cached_msi_msg(de=entuy->(de=entuy<_word"class="sref">msde=e/a>->ms4_L234" id4ine" name="L244"> 244__getto_"+co82" id="L282" classto_"+co82" ="L28 300       objd="L291" class=objry" c"class="sref">mscodeaef"r_of02" id="L302" ccodeaef"r_of="L28 300       objd="L291" class=objry" ref">get_cached_msi_msg(82" id="L282" class="line" namelass="sref">__getkobjd="L291" class=kobjry" ccode=msi_msg" class="sref">ms4_= 4posget_cached_msi_msg(de=entuy->(de=entuy<_worattrib" c href="drivers/pci/msi4u16 <4 href="+code=data" class4"sref44ix) {
get_cached_msi_msg->->msi_4X#L308" i4="L248" class="line" nam4="L2444 288{
( 212 showa>( 287void __write_msi_msg(struct msi_dde=entuy->(de=entuy<_wora"L282"> 282 ae=e/a>->msi_data_reg(pos),
 292      uf02" id="L302" c uf="L2+desi_attrib" class="sref">msi_4ef="+code4address_lo" class="sref"4addre45_lo);
( 212 storia>( 287void __write_msi_msg(struct msi_dde=entuy->(de=entuy<_wora"L282"> 282 ae=e/a>->msi_data_reg(i4_64) {
 292      uf02" id="L302" c uf="L2lass="sref">__getiize_ta>(mscoude0" class="line"coude="L2+desi_attrib" class="sref">msi_4eADDR" cl4a href="+code=pos" class4"sref45atmsi_4eENTRY_DA4address_hi" class="sref"4addre45 203}

( 212 show_"+com/a>a>(="L28ivers/pci/msi.c#L300" f="+code=__write_msi_msg" class="sref">__write_msi_msg(struct msi_dde=entuy->(de=entuy<_wora"L282"> 282 aee/a>->msi_data_reg( 255       4     45lag);
 292      uf02" id="L302" c uf="L2+f">msi_data_reg(ad4ress_45> 286/a>)
);
"%s\n"0  " class="sref">pcen     struct entry->"=msi"0   :asref="driversi_ding">"=ms"0  +desi_attrib" class="sref">msi_4e#L308" i4ne" name="L258"> 2584     45data = <4 href="+code=data" class4"sref46SIZE;
4260
( 212 e" ngetode=e_showa>( 282 kobjd="L291" class=kobjry" ef">msi_data_reg() {
get_cached_msi_msg-> 282 ae=e/a>-> 292      uf02" id="L302" c uf="L2+f">msi_data_reg(msi_dde=entuy->(de=entuy<_wora"L282"> 282 ae=entuy-> 306to_"+code=e/a>->       de=e/a>->msi_4aL234" id4"L264" class="line" name4"L2644> 264{
 282        struct  197cl24#->4a href="+code=irq" class4"sref46ta));
msae=entuy->));
);
msi_4#L268" id4"L268" class="line" name4"L26846 278}
 282        struct pcae=entuy->pc uf02" id="L302" c uf="L2+desi_attrib" class="sref">msi_4_msg 4}
 212 e" ngetosysfs_op id="L301" classe" ngetosysfs_op ode=msi/a>)
entshowa>((msi_data_reg(msi_4g.4ata));
msi_dde=entuy->(de=entuy<_wora class="sref">msf">dde=entuy->dde=entuy));
-> 282 m/a>a>(pcS_IRUGO   struct __getihow_"+com/a>a>(="L2lass="sref">__getNULL   struct msi_4_L268" id4"L278" class="line" name4"L2784> 278}
 4get_cached_msi_msg-> 282 e" ngetodefaultdde=e id="L301" classe" ngetodefaultdde=e _wor[]msi/a>)
 281{
mssf">dde=entuy->dde=entuyentae=e/a>->msi_data_reg({
msi_data_reg( 283/desi_attrib" class="sref">msi_4try, 4a href="+code=msg" class4"sref48SIZE;
dev< href="drivers/pci/me" nkobj_relef">readl(="L28ivers/pci/msi.c#L300" kobjectd="L291" class=kobject_wora"L282"> 282 kobjd="L291" class=kobjry" c>));
 286/a>)
get_cached_msi_msg 282        struct  197cl24cL278" id4"L288" class="line" name4"L28848 278}
PC49 } else {
 282  nams="_pue0" class="line" nams="_puery" 8L282"> 282        struct irq -  197cl24=msg 4on't touch the hardw4re no49> 240href="drivers/pci/msi.c#L220" 4is_49 261}

readl(288 212 e" ngetoktyp>readl(ode=msi/a>)
entrelef">readl(="L2msi_desc" class="se" nkobj_relef">readl(="L2ef">msi_data_reg(PCI_MSI4_ENTR49 234{
entsysfs_op id="L301" classsysfs_op 288mss" ngetosysfs_op id="L301" classe" ngetosysfs_op ode=ef">msi_data_reg(entdefaultdde=e id="L301" classdefaultdde=e _wormsi_desc" class="se" ngetodefaultdde=e id="L301" classe" ngetodefaultdde=e _woref">msi_data_reg(PCI_MSIX_ENTRY4LOWER49 226msi_4_ADDR" cl4ss="sref">PCI_MSIX_ENTRY4UPPER49ctl);
PCI_MSIX4ENTRY49> 308
 300       pL300" class="line"  href="+code=msi_msg" class="sref">ms5" class="5ine" name="L299"> 299)
get_cached_msi_msg 282        struct msi_5ttrib5 282 kobjd="L291" class=kobjry" desi_attrib" class="sref">msi_5t3rib5503288{
msi_5t4rib5<=mask_base" class="sref5="L3050*/
msi_5t5rib5PCI_MSI5ef">m50SIZE;
dev;
 3kset_crealinand_ad"ry" 8Lref="driversi_ding">"=msnget/"0  " class="sref">pcNULL   struct ms1L300" class="line"  href="code=offset" class="s="sref">irq - entkobjd="L291" class=kobjry" c"97cl2u  197cl25y7;PCI_MSIX_ENTRY5 50t;< 4;
ms1L300" class="line"  href="code=offset" class="s   ksetd="L291" class=s   kset_wor+code=msi_msg" class="sref">ms5"8;PCI_MSIX_ENTRY5ef">m50DDR);
msi_5t9;PCI_MSIX5="L3050 278}
 282 list_for_each_       struct  282        struct ms1L300" class="line"  href="code=offset" class="s   eista>(__geteista>( 240
entkobjd="L291" class=kobjry" /= reg" class="sref">ms91" id="L291" class="line" name="L291"> 291  kobjd="L291" class=kobjry" desi_attrib" class="sref">msi_5/a>.i5164) {
 291  kobjd="L291" class=kobjry" me="L291"> 291  ksetd="L291" class=kset_wormsi_desc" class="s1L300" class="line"  href="code=offset" class="s   ksetd="L291" class=s   kset_wordesi_attrib" class="sref">msi_5/3rib5a href="+code=pos" class5"sref513288{
 282  nams="_getd="L291" class= nams="_get="L28L282"> 282 pL300" class="line"  href="+desi_attrib" class="sref">msi_5/4rib5address_hi" class="sref"5addre51> 303
 3kobject_initnand_ad"="L28 300       kobjd="L291" class=kobjry" lareg" class="sref">mse" ngetoktyp>readl(ode=" class="sref">pcNULL   struct msi_5/5rib5class="sref">pos, 1)5 &5"%u"0  " class="sref">pcen     struct irq_get_msi5c, );
ms5 class="c5mment">/* Flush write to5devic51>pos;
pcout_unrole02" id="L302" cout_unrole_wordesi_attrib" class="sref">msi_5/8; 217);
__getcoude0" class="line"coude="L2++desi_attrib" class="sref">msi_5t; o52set);
5220);
{
msi_5dreg(5="L222" class="line" nam5="L2252gctl;
pcout_unrole02" id="L302" cout_unrole_wor:/a>;
{
 282        struct ms1L300" class="line"  href="code=offset" class="s   eista>(__geteista>(da52lag);
mscoude0" class="line"coude="L2+trib"pos;
msi_5d8;ms91" id="L291" class="line" name="L291"> 291  kobjd="L291" class=kobjry" c"97cl2u  197cl25d#L308" i5 href="+code=data" class5"sref52ase +
__getkobject_pue0" class="line"kobject_pue="L28reg" class="sref">ms91" id="L291" class="line" name="L291"> 291  kobjd="L291" class=kobjry" c"97cl2u  197cl25#L229" id5"L229" class="line" name5"L22953pos),
mscoude0" class="line"coude="L2--"97cl2u  197cl25#="L220" 5f="+code=data" class="sr5f">da531et);
{
msi_5c#L232" i5="L232" class="line" nam5="L23533288 *<5P53>dev
                                is_53 167
                PCI_MSI5_ENTR54pos
                 240 an>
                PCI_MSIX_ENTRY5LOWER54 261< an>
                PCI_MSIX_ENTRY5UPPER54gctl< an>

d a posit  < return_valui indicry                PCI_MSIX5ENTRY54> 283 an>
 244 300                struct  <5 href="+code=data" class5"sref54ix) {
get_cached_msi_msg 282        struct msi_5X#L308" i5="L248" class="line" nam5="L2454 288{
__getretd="L291" class=retry" desi_attrib" class="sref">msi_5_reg(5a href="+code=pos" class5"sref55 } else {
 282 #L302" id="L302" class="line" name="L302"code=de02" id="L302" ccode=deine""+code=entry" class="sref">ent5ef="+code5address_lo" class="sref"5addre55_lo);
ent5eL231" id5f="+code=is_64" class="s5ef">i55 261}
{
 301< namfinddiapability0" class="line" namfinddiapability="L28L282"> 282 ode=pci_write_config_word" class="sref">pct; 197cl25eENTRY_DA5address_hi" class="sref"5addre55*/
;
 255       5     55>dev;
 304                pde=diode=de04"ga>( 282 p, mscode=de02" id="L302" ccode=deine"_desc" class="sref">irq_get_msi5_trib5ress_hi" class="sref">ad5ress_55t;< 4;
 <5href="+code=data" class=5sref"55 167{
irq_get_msi5_#L308" i5ne" name="L258"> 2585     55 288{
ms       struct ),
msi_5af="+code5lass="line" name="L260">5260);
pos;
entry->msi_5c#L262" i5="L262" class="line" nam5="L26563288{
entry< 303
irq_get_msi5aENTRY_DA5entf="+c_ne/a>->msi_5cL234" id5"L264" class="line" name5"L26456 234{
 291        } else if (entrf="bita>(entry(irq_get_msi5a= dev;
 291        } else if (entdefaultda href="+code=irq_defaultda hdev class="sref">enti        if (                                int pos = entry-> 301< y->msi_5c &);
{
->( 282 p, pcen     struct entry< 303_desc" class="sref">irq_get_msi5c#L269" i5="L269" class="line" nam5="L2657pos),
                 291        } else if (entrf="bita>() {
 291  "L304"> 304 d class="line" name="L304"> 304 d               pen     struct ->msen     struct  3d="s&"ine"_desc" class="sref">irq_get_msi5ssert tha5 the cache is valid, ass5ming 573288{
 282 code=de02" id="L302" ccode=deine"_desc" class="sref">irq_get_msi5sENTRY_DA5id messages are not all-5eroes57*/
 282        struct pcef="ref="+code=irq_ef="="L2" class="sref">pcef="ref="+code=irq_ef="="L2_desc" class="sref">irq_get_msi5sL234" id5address_lo" class="sref"5addre57SIZE;
57>dev;
ms91" id="L291" class="line" name="L291"> 291  eista>(msi        if ((irq_get_msi5s#L266" i5="L276" class="line" nam5="L27577ctlirq_get_msi5s &{
pnvec      struct pct; 197cl25c#L279" i5="L279" class="line" nam5="L2758pos),
ente" nef="+a href="+code=irq_e" nef="+a h="L28L282"> 282        struct pcef="ref="+code=irq_ef="="L2" 5"> 305     ef="ref="+code=irq_ef="="L2_desc" class="sref">irq_get_msi5#L281" id5"L281" class="line" name5"L2815864) {
 291  freine" nget/a>, irq_get_msi5desc(5a href="+code=irq" class5"sref583288{
msi_5d    * va5="L283" class="line" nam5="L2858*/
, 5a href="+code=msg" class5"sref58SIZE;
dev;
irq_get_msi5d#L266" i5="L286" class="line" nam5="L2858t;< 4;
 282        struct pcef="ref="+code=irq_ef="="L2" 5"> 305     ef="ref="+code=irq_ef="="L2_desc" class="sref">irq_get_msi5#L268" id5"L288" class="line" name5"L28858ase +
__getfreine" nget/a>, irq_get_msi5= PC59pos),
msi_5=msg 5on't touch the hardw5re no591et);
is_59 261}
{
irq_get_msi5X_ENTRY_S5ZE" class="sref">PCI_MSI5_ENTR59 234{
irq_get_msi5XL285" id5="L295" class="line" nam5="L2959>dev;
irq_get_msi5X#L266" i5ss="sref">PCI_MSIX_ENTRY5LOWER597ctlirq_get_msi5_ADDR" cl5ss="sref">PCI_MSIX_ENTRY5UPPER59 167{
irq_get_msi5XL268" id5A" class="sref">PCI_MSIX5ENTRY59ase +
msi_6" class="6ine" name="L299"> 299;
6 282 m" xnefp_4"giongt; 300                struct , 6603288{
PCI_MSI6ef">m60 234{
, irq_get_msi6m6;dev;
irq_get_msi6m7;PCI_MSIX_ENTRY6 60t;< 4;
irq_get_msi6m8;PCI_MSIX_ENTRY6ef">m60ctl);
PCI_MSIX6="L3060 288{
 304 d class="line" name="L304"> 304 d               pe" xntab-&noffset_4"ga>( 282 p, mstab-&noffsetd="L291" class=tab-&noffset_msi_desc" class="sref">irq_get_msi6_reg(6a href="+code=pos" class6"sref61 } else {
 282 bira>,  282 u8231" clas302" cl8271<)8L282"> 282 tab-&noffsetd="L291" class=tab-&noffset_msi"reg"  class="sref">pct;_BIRMASK=pci_write_conft;_BIRMASK_msi_desc" class="sref">irq_get_msi6_->6address_lo" class="sref"6addre61_lo);
 305     t;_BIRMASK=pci_write_conft;_BIRMASK_msidesc" class="sref">irq_get_msi6_trib6f="+code=is_64" class="s6ef">i61>pos;
 301< namresource_itarta>(pbira>, irq_get_msi6/3rib6a href="+code=pos" class6"sref61gctl;
 303
 282 physnaddra>, pnrn    ie/a>, pct;irq_get_msi6_5rib6class="sref">pos, 1)6 &6;
));
/* Flush write to6devic617ctl<
,  300                struct ,  217);
 282 bf">readl(="L2e f">get_cached_msi_msg 282     ie/a>, o62pos)
6220) {
get_cached_msi_msg 282        struct msi_6#L221" id6"L221" class="line" name6"L22162 271{
msi_6#3rib6="L222" class="line" nam6="L2262gctl;
 303
 282 i0" class="line"iode=< clars/pci/msi.c#L24i0" class="line"iode= <ars/pci/msi.c#L24nvec      struct  282        struct irq_get_msi6t, da62lag);
ms       struct pos;
msi0" class="line"iode=+trib" 282 iound=pgt;readl(="L2_desc" class="sref">irq_get_msi6t9; +
irq_get_msi6#L229" id6"L229" class="line" name6"L22963pos),
 282 freine" nget/a>, irq_get_msi6#="L220" 6f="+code=data" class="sr6f">da63> 240
                ) {
msi_6c#L232" i6="L232" class="line" nam6="L23633288{
;
 282        struct entry->irq_get_msi6!= P63lag);
 282        struct entry< 303
irq_get_msi6!class="c6="L236" class="line" nam6="L2363>pos;
 282        struct entf="+c_ne/a>-> 282     ie/a>, msi0" class="line"iode=]class="sref">entf="+c  struct msi_6!8;is_63DDR);
 291        } else if (entdefaultda href="+code=irq_defaultda hdev class="sref">enti        if (msi_6!9;__get/a>                int pos = entry-> 301< y->msi_6X_ENTRY_S6ZE" class="sref">PCI_MSI6_ENTR64pos),
msen     struct readl(os),
 301readl(="L2=msi_attrib" class="sref">msi_6X="L220" 6="L240" class="line" nam6="L2464set);
PCI_MSIX_ENTRY6LOWER6464) {
 291  list_add_taie02" id="L302" clist_add_taie="L28reg" class="sref">ms91" id="L291" class="line" name="L291"> 291  eista>(msi        if ((PCI_MSIX_ENTRY6UPPER643288{
;
PCI_MSIX6ENTRY64 203}
 244msi_6_= irq_get_msi6u16 <6 href="+code=data" class6"sref64ix
 300                struct irq_get_msi6u9;get_cached_msi_msg 282     ie/a>, )
) {
get_cached_msi_msg 282        struct msi_6eL231" id6f="+code=is_64" class="s6ef">i65 271{
msi_6eADDR" cl6a href="+code=pos" class6"sref65gctl;

 282        struct msi        if ((__geteista>( 282     ie/a>, msi0" class="line"iode=]class="sref">entf="+c  struct pct; 255       6     65lag);
pct;msi_6eclass="c6ress_hi" class="sref">ad6ress_657ctlirq_get_msi6_16 <6href="+code=data" class=6sref"65DDR);
, msi0" class="line"iode=]class="sref">entvectoe/a>-> 282        struct irq_get_msi6_#L308" i6ne" name="L258"> 2586     65ase +
__getgetoset_c#L282" id="L282" classgetoset_c#L282" ="L28L282"> 282        struct pen     struct  = <6 href="+code=data" class6"sref66pos),
msen     struct  3d="s&"ine"" cL282"> 282 4"> e02" id="L302" c4"> e="L28L282"> 282        struct readl(os6260 240
ente" xnef="+a href="+code=irq_e" xnef="+a h="L28L282"> 282        struct irq_get_msi6#L261" id6"L261" class="line" name6"L2616664) {
 291  i0" class="line"iode=++desc" class="sref">irq_get_msi6#ADDR" cl6="L262" class="line" nam6="L26663288{
;
;
dev
 <6a href="+code=msg" class6"sref66 167
                
get_c#Lxn          ie/  /a>                                                

                                .67 285<
 300                struct get_cached_msi_msg 282     ie/a>, {
__getretd="L291" class=retry" desi_attrib" class="sref">msi_6c#L279" i6="L279" class="line" nam6="L2768 } else {
 282 #L302" id="L302" class="line" name="L302"code=de02" id="L302" ccode=deine""+code=entry" class="sref">ent6_msg 6 282 bf">readl(="L2"+code=entry" class="sref">ent6_L261" id6"L281" class="line" name6"L28168 261}
{
entry-> 301< namfinddiapability0" class="line" namfinddiapability="L28L282"> 282 ode=pci_write_config_word" class="sref">pct; 304                pry->   struct ode=lareg" class="sref">mscode=de02" id="L302" ccode=deine"_desc" class="sref">irq_get_msi6try, 6a href="+code=msg" class6"sref68SIZE;
dev;
                 305     t;_ENABLE=pci_write_conft;_ENABLE="L2"+code=entry" class="sref">ent6_ &pry->   struct ode=laclass="sref">mscode=de02" id="L302" ccode=deine"_desc" class="sref">irq_get_msi6tL268" id6"L288" class="line" name6"L28868aseirq_get_msi6= PC69pos),
                readl(="L2msi_desc" class="s"+cxnefp_4"giongt;pry->peulti_e" xniapab->irq_get_msi6is_69 271{
msbf">readl(="L2_esc" class="sref">irq_get_msi6(6 href="+code=base" class6"sref693288{
       ENOMEM   struct msi_6=#L283" i6e=mask_base" class="sref6>mask69 203}
PCI_MSI6_ENTR69 234{
pry->pbf">readl(="L2e L282"> 282     ie/a>, msi_6=L285" id6="L295" class="line" nam6="L2969>dev;
msi_6=#L266" i6ss="sref">PCI_MSIX_ENTRY6LOWER69>pos;
msi_6_ADDR" cl6ss="sref">PCI_MSIX_ENTRY6UPPER69ctl);
PCI_MSIX6ENTRY69ase +
pnvec      struct pct; 299),
 240
 282  rroe/a>->msi_7ttrib77703288{
7<=mask_base" class="sref7="L3070> 283 an>
                PCI_MSI7ef">m70SIZE                dev
                PCI_MSIX_ENTRY7 70> 286pan>
PCI_MSIX_ENTRY7ef">m70 167{
_MASKALL   struct _MASKALLine""|i_desc" class="st;_ENABLE=pci_write_conft;_ENABLE="L2"+code=entry" class="sref">ent7t9;PCI_MSIX7="L3070 288{
pry->   struct ode=laclass="sref">mscode=de02" id="L302" ccode=deine"_decode=entry" class="sref">ent7_reg(7a href="+code=pos" class7"sref71 } elecode=entry" class="sref">ent7_1class="7address_lo" class="sref"7addre71_lo);
, p    ie/a>, ent7_trib7f="+code=is_64" class="s7ef">i71 261}
{
entretd="L291" class=retry" msi_desc" class="s1"pulaline" nsysfs0" class="line" "pulaline" nsysfs="L28      irq_get_msi7/4rib7address_hi" class="sref"7addre71> 303
pos, 1)7 &71a href="+cdevvvvvvvvvL282"> 282 retd="L291" class=retry" msilaesi_attrib" class="sref">msi_7c, );
 282  rroe/a>->msi_7 class="c7mment">/* Flush write to7devic71>pos;
;
 217);
                o72 } else {
 282 pL30intx_for_pci0" class="line" namintx_for_pci="L28    irq_get_msi7d="L220" 7lass="line" name="L220">7220);
        if (irq_get_msi7#L221" id7"L221" class="line" name7"L22172 261}
entcode=de02" id="L302" ccode=deine""reg" = 5"> 305     t;_MASKALL   struct _MASKALLine"desc" class="sref">irq_get_msi7#4rib7 href="+code=data" class7"sref72*/
pry->   struct ode=laclass="sref">mscode=de02" id="L302" ccode=deine"_desc" class="sref">irq_get_msi7#5rib7"L224" class="line" name7"L22472SIZE;
da72lag);
msi_7tclass="c7"L226" class="line" name7"L226727ctlirq_get_msi7t8; 282  rroe/a>->irq_get_msi7t9; +
),
                da73> 240 an>
                
                get_cached_msi_msg 282        struct msi_7#L234" id7"L234" class="line" name7"L23473a href="+cdevvvvvvvvvivers/pci/msi.c#L30avaie02" id="L302" cavaiery" msilaesi_attrib" class="sref">msi_7!= P73ta));
 282 list_for_each_       struct  282        struct msi        if ((__geteista>(is_73DDR);
;
 282 avaie02" id="L302" cavaiery" ++desc" class="sref">irq_get_msi7X_ENTRY_S7ZE" class="sref">PCI_MSI7_ENTR74pos),
PCI_MSIX_ENTRY7LOWER7464) {
 282 retd="L291" class=retry" msi_desc" class="savaie02" id="L302" cavaiery" desc" class="sref">irq_get_msi7X#L232" i7ss="sref">PCI_MSIX_ENTRY7UPPER743288{
;
PCI_MSIX7ENTRY74 203}
 244{
, irq_get_msi7_= msi_7u16 <7 href="+code=data" class7"sref74ix;
irq_get_msi7_reg(7a href="+code=pos" class7"sref75pos
 240 an>
                i75 261< an>
                
                 283 an>
                 255       7     75>dev
                ad7ress_75> 286pan>
                

< rroe c#L3.in/a>                 2587     75 288
 = <7 href="+code=data" class7"sref76pos
 300                struct 7260 240ttrib") {
 300       bus0" class="line"busL300desi_attrib" class="sref">msi_7#ADDR" cl7="L262" class="line" nam7="L26763288{
msi_7aENTRY_DA7{
                dev;
ms"L30e" nenab->ms         struct msi        if (       EINVAL   struct msi_7a16 <7a href="+code=msg" class7"sref76ctl);
 +

't ="s no have 0 orilessLMSIs       ured.in/a>                                

 303
msi_7g.77ta));
                                
                                                
                
 282 bus0" class="line"busL300> class="sref">enti        if (pbus0" class="line"busL300d" class="sref">pbus0" class="line"busL300rname="L301"> 301, 7a href="+code=msg" class7"sref78a href="+cdevvvvvvvvviverrs/pci/msi.c#L2bus0" class="line"busL300"+code=entry" class=bus_flags0" class="line"bus_flagsine""reg" /href="drivers/pt;_NOa"sr   struct _NOa"srry" +esc" class="="drivers/pci/msi7t.);
msi_7d#L266" i7="L286" class="line" nam7="L28787ctlirq_get_msi7_ &pnvec      struct pctype      struct msi_7dL268" id7"L288" class="line" name7"L28878ase +
PC79pos),
msi_7=msg 7on't touch the hardw7re no79set);
is_79 271{
mspnamfinddiapability0" class="line" namfinddiapability="L28L282"> 282 ode=pci_write_config_word" class="sref">pctype      struct {
       EINVAL   struct msi_7=#L283" i7e=mask_base" class="sref7>mask79 203}
PCI_MSI7_ENTR79 234{
msi_7=L285" id7="L295" class="line" nam7="L2979 285;
PCI_MSIX_ENTRY7LOWER797ctlirq_get_msi7_ADDR" cl7ss="sref">PCI_MSIX_ENTRY7UPPER79 167
PCI_MSIX7ENTRY79 288
 299
 240 an>

80gctl< an>
                 283 an>
8PCI_MSI8ef">m80SIZEllocry< ne" number of gnterrupts request&", it returns0                dev
llocry<.  If is successfully="/a>                PCI_MSIX_ENTRY8 80> 286pan>
PCI_MSIX_ENTRY8ef">m80 167
                PCI_MSIX8="L3080 288
                
 300                struct i81 261{
us0" class="line"usword" class="sref">pcry->peaxvec      struct msi_8/4rib8address_hi" class="sref"8addre81*/
msi_8/5rib8class="sref">pos, 1)8 &81SIZE;
);
pcry-> 301< namfinddiapability0" class="line" namfinddiapability="L28L282"> 282 ode=pci_write_config_word" class="sref">pct;msi_8 class="c8mment">/* Flush write to8devic81>pos;
mspy-> 217);
msi_8/9; 304                pry->   struct ode=lareg" class="sref">msmsgcte02" id="L302" cmsgctery" +desi_attrib" class="sref">msi_8t; o82 } else {
 282 eaxvec      struct _QMASK   struct _QMASKry" + +cod+cod 1_desc" class="sref">irq_get_msi8d="L220" 8lass="line" name="L220">8220);
 282 eaxvec      struct ) {
msi_8#3rib8="L222" class="line" nam8="L2282gctl;

usword 301< name" ncheck_ hricess="line" name="L30e" ncheck_ hrice           pnvec      struct pct;msi_8#5rib8"L224" class="line" name8"L224825lo);
us0" class="line"usword+trib"da82lag);
usworddesi_attrib" class="sref">msi_8#class="c8"L226" class="line" name8"L226827ctlirq_get_msi8t8;ms         struct msi_8#9;irq_get_msi8#L229" id8"L229" class="line" name8"L22983pos),
 y request&" MSI-X gets *90                da83_lo);
        if () {
 291  a h_infoa>        if (msi        if ("c>
't enab-& MSI "0                "(MSI-X al4"> y enab-&d)\n"0  +desi_attrib" class="sref">msi_8#a *<8       EINVAL   struct msi_8#L234" id8"L234" class="line" name8"L23483a href="+cdev/a>;
P83ta));
us0" class="line"usword 301pnvec      struct msi_8#8;is_83DDR);
us0" class="line"usworddesi_attrib" class="sref">msi_8!9;PCI_MSI8_ENTR84pos       EXPORT_SYMBOL   struct msi_8X="L220" 8="L240" class="line" nam8="L2484set);
PCI_MSIX_ENTRY8LOWER8464 300                struct PCI_MSIX_ENTRY8UPPER843288PCI_MSIX8ENTRY844os),
get_cached_msi_msg 282 82" id="L282" classne" namedesi_attrib" class="sref">msi_8XL234" id8ine" name="L244"> 244{
s/pci/msi.c#L30eask0" class="line"easknamedesi_attrib" class="sref">msi_8X= pc#L302" id="L302" class="line" name="L302"ctre02" id="L302" cctrenamedesi_attrib" class="sref">msi_8Xclass="c8pry->msi_8X8;);
ms"L30e" nenab->ms         struct ms         struct );
),
msi_8ef="+code8address_lo" class="sref"8addre85set);
i852ag);
pcBUG_ON0" class="line"BUG_ON="L28      msi        if ((irq_get_msi8eADDR" cl8a href="+code=pos" class8"sref853288{
ent82" id="L282" classne" name 301msi        if ((get_cached_msi_msg__geteista>(irq_get_msi8ea *<8address_hi" class="sref"8addre85*/
-> 301<82" id="L282" classne" name"+code=entry" class=me=datveibid="L282" class="liatveibname. class="sref">pry->msi_8eL234" id8href="+code=data" class=8sref"85SIZE;
 255       8     85lag);
pce" nsetnenab->pry->irq_get_msi8eclass="c8ress_hi" class="sref">ad8ress_85t;< 4;
irq_get_msi8e16 <8href="+code=data" class=8sref"85 167{
msi_8_#L308" i8ne" name="L258"> 2588     85aseirq_get_msi8a = <8 href="+code=data" class8"sref86pos),
8260);
 304                pry->   struct ode=lareg" class="sref">msctre02" id="L302" cctrename_desc" class="sref">irq_get_msi8#L261" id8"L261" class="line" name8"L261862ag);
pceask0" class="line"easkname 301irq_get_msi8#ADDR" cl8="L262" class="line" nam8="L26863288{
 *<8peask0" class="line"easkname, 5"> 305     eask0" class="line"easkname_desc" class="sref">irq_get_msi8#L234" id8"L264" class="line" name8"L26486SIZE;
dev;
                 301<82" id="L282" classne" name"+code=entry" class=me=datveibid="L282" class="liatveibname. class="sref">pdefault_a href="+code=irq_default_a hcodedesi_attrib" class="sref">msi_8a16 <8a href="+code=msg" class8"sref86ix;
irq_get_msi8c#L269" i8="L269" class="line" nam8="L2687pos 300                struct {
mspname" nenab->ms         struct ms         struct );
{
msi_8cENTRY_DA8id messages are not all-8eroes87 203}
{
                struct msi_8c= 87lag);
pcfreine" nget/a>, irq_get_msi8g#L266" i8="L276" class="line" nam8="L2787t;< 4;
irq_get_msi8g16 <8 301msi_8cL268" id8"L278" class="line" name8"L27887ase;
irq_get_msi8_msg 8

                                . 300                struct msi_8dL268" id8"L288" class="line" name8"L28888 288{
msi_8= PC89 } elecode=entry" class="sref">ent8=msg 8on't touch the hardw8re no89_lo);
-> 301< namfinddiapability0" class="line" namfinddiapability="L28L282"> 282 ode=pci_write_config_word" class="sref">pct;is_89 271{
mspy->{
msi_8=#L283" i8e=mask_base" class="sref8>mask89 203}
PCI_MSI8_ENTR89 234{
 304                pe" ncode=de04"g0" class="line"e" ncode=de04"g="L28      mscode=de02" id="L302" ccode=deine"_desc" class="sref">irq_get_msi8=L285" id8="L295" class="line" nam8="L2989lag);
peult30e" x_capab-&0" class="line"eult30e" x_capab-&           irq_get_msi8=#L266" i8ss="sref">PCI_MSIX_ENTRY8LOWER897ctl;
PCI_MSIX_ENTRY8UPPER89ctl);
PCI_MSIX8ENTRY89 288
 299
 240 an>
                
90gctl< an>
                 283 an>
9PCI_MSI9ef">m90SIZE                dev
9PCI_MSIX_ENTRY9 90> 286pan>
9PCI_MSIX_ENTRY9ef">m90 167
9<" class="sref">PCI_MSIX9="L3090 288
(9a href="+code=pos" class9"sref91pos
                 240 an>
                i91 261< an>

9address_hi" class="sref"9addre91*/ 300                struct get_cached_msi_msg 300           ie/  struct pos, 1)9 &91SIZE);
us0" class="line"usword" class="sref">pcnr_    ie/  struct msi_9 class="c9mment">/* Flush write to9devic91>pos;
pcj0" class="line"jine"desi_attrib" class="sref">msi_9 8rib9ine" name="L217"> 217);
ms    ie/  struct o92pos),
msi_9d="L220" 9lass="line" name="L220">9220);
);
pcus0" class="line"usword 301< name" ncheck_ hricess="line" name="L30e" ncheck_ hrice           pnvec      struct pct;9="L222" class="line" nam9="L22923se +
pcus0" class="line"usword+trib"),
pcus0" class="line"usworddesc" class="="drivers/pci/msi9#5rib9"L224" class="line" name9"L22492SIZE;
da92lag);
pcnr_    ie/  struct  301< name" x_tab-&_sizegt;irq_get_msi9#class="c9"L226" class="line" name9"L22692>pos;
pnvec      struct  282 nr_    ie/  struct pcnr_    ie/  struct msi_9#9;irq_get_msi9#L229" id9"L229" class="line" name9"L22993pos),
da93_lo);
 282 i0" class="line"iwordmsilars/pci/msi.c#L24i0" class="line"iword <ar class="sref">pnvec      struct ) {
p       struct  282 nr_    ie/  struct        EINVAL   struct                  282 j0" class="line"jine" 301pnvec      struct p       struct  301<    ie/  struct p       struct P93lag);
       EINVAL   struct ;
is_93DDR);
;
ms         struct msi_9X_ENTRY_S9ZE" class="sref">PCI_MSI9_ENTR94 } elecode=entry" class="sref">ent9X="L220" 9="L240" class="line" nam9="L2494_lo);
 y request&" foriMSI irq *90                PCI_MSIX_ENTRY9LOWER94 271{
ms         struct PCI_MSIX_ENTRY9UPPER943288{
ms   _infoa>        if (msi        if ("c>
't enab-& MSI-X "0                PCI_MSIX9ENTRY944os),
"(MSI IRQ al4"> y iveign  +desi_attrib" class="sref">msi_9XL234" id9ine" name="L244"> 244msi_9X= us0" class="line"usword 301p    ie/  struct msi_9X8;);
us0" class="line"usworddesi_attrib" class="sref">msi_9X9;(9a href="+code=pos" class9"sref95pos       EXPORT_SYMBOL   struct msi_9ef="+code9address_lo" class="sref"9addre95set);
i9564 300                struct ),
get_cached_msi_msg 282        struct msi_9eL234" id9href="+code=data" class=9sref"95SIZE;
 255       9     95lag);
mspname" nenab->ms         struct ms         struct ;
ad9ress_95>pos;
msi_9e8;);
 2589     95ase +
 = <9 href="+code=data" class9"sref96 } else {
 282 list_for_each_e      struct msi        if (( 282 list  struct 9260);
 +
) {
 291  _0e" xneask_a href="+code=irq__0e" xneask_a h           irq_get_msi9#ADDR" cl9="L262" class="line" nam9="L26963288{
;
{
irq_get_msi9a= );
pcpL30intx_for_pci0" class="line" namintx_for_pci="L28    irq_get_msi9aclass="c9="L266" class="line" nam9="L2696t;< 4;
msi_9a16 <9a href="+code=msg" class9"sref96ix;
irq_get_msi9c#L269" i9="L269" class="line" nam9="L2697pos 300                struct {
mspname" nenab->ms         struct ms         struct ;
{
msi_9cENTRY_DA9id messages are not all-9eroes97 203}
{
irq_get_msi9c= 97lag);
pcfreine" nget/a>, irq_get_msi9g#L266" i9="L276" class="line" nam9="L2797t;< 4;
irq_get_msi9g16 <9 301msi_9cL268" id9"L278" class="line" name9"L27897ase;
irq_get_msi9_msg 9

e0                                dev
                                e,ry/a>                
PC99pos
 9on't touch the hardw9re no99_lo 300                struct is_99 261 +
mspname" nenab->ms         struct irq_get_msi9X_ENTRY_S9ZE" class="sref">PCI_MSI9_ENTR99SIZE;
ms         struct ms         struct ;
PCI_MSIX_ENTRY9LOWER99>pos;
pcfreine" nget/a>, irq_get_msi9_ADDR" cl9ss="sref">PCI_MSIX_ENTRY9UPPER99ix;
PCI_MSIX9ENTRY99aseirq_get_msi10" class="10" cllass="sref">PCI_MSIX10" c>10" osPass=69/5b/00a957881625aa85e2de98s8ba9a1dfc3ad8_3/10" c>sc" class="sref">irq_get_msi10"1class="10"n't touch the hardw10"n&>10"> 240ttrib"10"2ag);
pcpname" nenab->msi_10"3class="10"href="+code=base" class10"hr>10"3x;
10" 203}
PCI_MSI10"E">10"SIZE                10">dev
                PCI_MSIX_ENTRY10"s=>10"> 286pan>
PCI_MSIX_ENTRY10"s=>10" 167
                PCI_MSIX10"" >10" 288
10a os
10a> 240ivers/pci/msi.c#L30 name" denab-&dgt;10a 26110a3se +
msi_1014class="10address_hi" class="sref"10add>10a4x;
pos, 1)10cla>10a5os       EXPORT_SYMBOL   struct irq_get_msi10a6class="10href="+code=flag" class=10hre>10ata));
/* Flush write to10mme>10a74 300                struct  21710a826110aase +
->msi_102 class="10="+code=offset" class="s10="+>10="ag);
pcINIT_LIST_HEAD/a>->msi        if ((msi_1021class="10lass="line" name="L220">10las>10=set);
10=2ag);
 hrefscreaming interrupt/  /a>                                10=> 283 an>
10=SIZE                10=lag);
pcpy-> 301< namfinddiapability0" class="line" namfinddiapability="L28L282"> 282 ode=pci_write_config_word" class="sref">pct;msi_1027class="10"L226" class="line" name10"L2>10=>pos;
ppy->pry->irq_get_msi10=9class="10 href="+code=data" class10 hr>10= 288{
irq_get_msi103 class="10"L229" class="line" name10"L2>10"Lx;
10"> 240 /prh>
Te" original LXR software by ne" >; LXR /pciunity="L2,inegs experii/msal drivion by >; lxr@ta"ux.no="L2. lxr.ta"ux.no kindlyihost&" by >; Redpill LI_pro A>ode=laprovider of La"ux sult3ng and operryions serrices since 1995.