linux/drivers/mfd/rc5t583.c
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   1/*
   2 * Core driver access RC5T583 power management chip.
   3 *
   4 * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   5 * Author: Laxman dewangan <ldewangan@nvidia.com>
   6 *
   7 * Based on code
   8 *      Copyright (C) 2011 RICOH COMPANY,LTD
   9 *
  10 * This program is free software; you can redistribute it and/or modify it
  11 * under the terms and conditions of the GNU General Public License,
  12 * version 2, as published by the Free Software Foundation.
  13 *
  14 * This program is distributed in the hope it will be useful, but WITHOUT
  15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17 * more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21 *
  22 */
  23#include <linux/interrupt.h>
  24#include <linux/irq.h>
  25#include <linux/kernel.h>
  26#include <linux/module.h>
  27#include <linux/init.h>
  28#include <linux/err.h>
  29#include <linux/slab.h>
  30#include <linux/i2c.h>
  31#include <linux/mfd/core.h>
  32#include <linux/mfd/rc5t583.h>
  33#include <linux/regmap.h>
  34
  35#define RICOH_ONOFFSEL_REG      0x10
  36#define RICOH_SWCTL_REG         0x5E
  37
  38struct deepsleep_control_data {
  39        u8 reg_add;
  40        u8 ds_pos_bit;
  41};
  42
  43#define DEEPSLEEP_INIT(_id, _reg, _pos)         \
  44        {                                       \
  45                .reg_add = RC5T583_##_reg,      \
  46                .ds_pos_bit = _pos,             \
  47        }
  48
  49static struct deepsleep_control_data deepsleep_data[] = {
  50        DEEPSLEEP_INIT(DC0, SLPSEQ1, 0),
  51        DEEPSLEEP_INIT(DC1, SLPSEQ1, 4),
  52        DEEPSLEEP_INIT(DC2, SLPSEQ2, 0),
  53        DEEPSLEEP_INIT(DC3, SLPSEQ2, 4),
  54        DEEPSLEEP_INIT(LDO0, SLPSEQ3, 0),
  55        DEEPSLEEP_INIT(LDO1, SLPSEQ3, 4),
  56        DEEPSLEEP_INIT(LDO2, SLPSEQ4, 0),
  57        DEEPSLEEP_INIT(LDO3, SLPSEQ4, 4),
  58        DEEPSLEEP_INIT(LDO4, SLPSEQ5, 0),
  59        DEEPSLEEP_INIT(LDO5, SLPSEQ5, 4),
  60        DEEPSLEEP_INIT(LDO6, SLPSEQ6, 0),
  61        DEEPSLEEP_INIT(LDO7, SLPSEQ6, 4),
  62        DEEPSLEEP_INIT(LDO8, SLPSEQ7, 0),
  63        DEEPSLEEP_INIT(LDO9, SLPSEQ7, 4),
  64        DEEPSLEEP_INIT(PSO0, SLPSEQ8, 0),
  65        DEEPSLEEP_INIT(PSO1, SLPSEQ8, 4),
  66        DEEPSLEEP_INIT(PSO2, SLPSEQ9, 0),
  67        DEEPSLEEP_INIT(PSO3, SLPSEQ9, 4),
  68        DEEPSLEEP_INIT(PSO4, SLPSEQ10, 0),
  69        DEEPSLEEP_INIT(PSO5, SLPSEQ10, 4),
  70        DEEPSLEEP_INIT(PSO6, SLPSEQ11, 0),
  71        DEEPSLEEP_INIT(PSO7, SLPSEQ11, 4),
  72};
  73
  74#define EXT_PWR_REQ             \
  75        (RC5T583_EXT_PWRREQ1_CONTROL | RC5T583_EXT_PWRREQ2_CONTROL)
  76
  77static struct mfd_cell rc5t583_subdevs[] = {
  78        {.name = "rc5t583-gpio",},
  79        {.name = "rc5t583-regulator",},
  80        {.name = "rc5t583-rtc",      },
  81        {.name = "rc5t583-key",      }
  82};
  83
  84static int __rc5t583_set_ext_pwrreq1_control(struct device *dev,
  85        int id, int ext_pwr, int slots)
  86{
  87        int ret;
  88        uint8_t sleepseq_val;
  89        unsigned int en_bit;
  90        unsigned int slot_bit;
  91
  92        if (id == RC5T583_DS_DC0) {
  93                dev_err(dev, "PWRREQ1 is invalid control for rail %d\n", id);
  94                return -EINVAL;
  95        }
  96
  97        en_bit = deepsleep_data[id].ds_pos_bit;
  98        slot_bit = en_bit + 1;
  99        ret = rc5t583_read(dev, deepsleep_data[id].reg_add, &sleepseq_val);
 100        if (ret < 0) {
 101                dev_err(dev, "Error in reading reg 0x%x\n",
 102                                deepsleep_data[id].reg_add);
 103                return ret;
 104        }
 105
 106        sleepseq_val &= ~(0xF << en_bit);
 107        sleepseq_val |= BIT(en_bit);
 108        sleepseq_val |= ((slots & 0x7) << slot_bit);
 109        ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(1));
 110        if (ret < 0) {
 111                dev_err(dev, "Error in updating the 0x%02x register\n",
 112                                RICOH_ONOFFSEL_REG);
 113                return ret;
 114        }
 115
 116        ret = rc5t583_write(dev, deepsleep_data[id].reg_add, sleepseq_val);
 117        if (ret < 0) {
 118                dev_err(dev, "Error in writing reg 0x%x\n",
 119                                deepsleep_data[id].reg_add);
 120                return ret;
 121        }
 122
 123        if (id == RC5T583_DS_LDO4) {
 124                ret = rc5t583_write(dev, RICOH_SWCTL_REG, 0x1);
 12"L120"> 120      jL77" id="L77" cl"L120"> 120      jL77" id="L77" cl"L1ass="line" name="ame="L34">  34
 id="L1 href="+code=deepsleep_data" class="sref/L1assref="d11" cla127code=dev" class="sref">dev, );
 120        v_err" clers/mfd/rc5t583.c#L28" i1d="L212+code=dev" clf="+code=id" class="sref">id].reg_addf="driver1s/mfd/rc5t583.c#L29" id=1"L29"1class=="line" name="L120"> 120       ref="driv1ers/mfd/rc5t583.c#L30" i1d="L31390" class="line" name="L90">  90  1rs/mfd/rc15t583.c#L31" id="L31" cl1ass="1ine" nne" name="L82">  82};
  82
  84static int  121device *dev,
"sref">RICOH_SWCTL_REG, 0x1);
(struct id].reg_addf href="dr83.c#L35" id="L35" class1="lin13ss="sref">EINVAL;
="drivers/mfd/rc5t583.c#!83.c#L91" id="L91" class="line" name="L91">  91
13id="L117" class="line" name="L117"> 117        if (ret < 0) {
  7d="L93" class="line" name="L93">  93                dev_err(id);
1583.c#L391" id="L39" class="line" 1name=1L39">  39 ="line" name="L120"> 120       L40" id="1L40" class="line" name="1L40">1490" class="line" name="L90">  90  1sref">u8<1/a>  & 0x7) << slot_bit);
 109        ret = rc5t583_set_bits( 121        }
RICOH_SWCTL_REG, 0x1);
(1id =110        if (ret < 0) {
 name"L111"> 111         f">rc5t583_set_bits(id].reg_adde="L45"> 1 45                .1 120       Ls/mfd/rc1  46                1.  36#define  = 1posdevne" _  8fi3.c#L43" id="L43e);
devne" _  8fi3href="drivers/mfd/rc5t583.c#L84" id="L84" class="line" name="L84">  84static int   42
dsme=ode=__rc5t583_set_ext_pwrreq1_control"1/mfd/rc5t1583.c#L47" id="L47" clas1s="li14+code=dev" clvice *dev        if (a>,
"sref">RICOH_SWCTL_REG, 0x1);
< DEEP1LEEP_INIT(a>  drivers/mfd/rc5t5code=d_  8ev" class="sref">devu8<1SLEEP_INIT" class="sref"1>DEEP15lass="sref">dev, nvalid control for rail %d\n", id);
1code=DEEP1SLEEP_INIT" class="sref"1>DEEP15583-key",      }
DEEP1LEEP_INIT(a>        }
dev#define EXT_PWR_REQ        )s/mfd/rc5t583.c#L92" id="L92" cla1c;D1EEPSL15"+code=dev" class="srf="+code=id" class="sr  83
  42
dsme=ode=__rc5t583_set_ext_pwrreq1_control"1de=DEEPSL1EEP_INIT" class="sref">D1EEPSL1525" class="line" name="L125">" class="sref">id =+code=d_  8ev" class="sref">dev        if (a>,
"="+code=id" class="sref">id);
1cs/mfd/rc1EEP_INIT" class="sref">D1EEPSL15ne" name="L36">  36#define D1EEPSL1EP_INIT(        }
dev#define   75        (D1EEPSL15+code=dev" class="srenvalid 82">  82};
  82
  84static int D1EEPSL16sleep_data[id =1sme="L42">  42
dsme=ode=_="sref">id =+code=d_  8ev" class="sref">devid);
1de=DEEPSL1EEP_INIT" class="sref">D1EEPSL1EP_INIT(id);
1dref">u8<1EEP_INIT" class="sref">D1EEPSL1EP_INI="line" name="L120"> 120       de=DEEPSL1EEP_INIT" class="sref">D1EEPSL1EP_INI2" id="L122" cl ;PORT_SYMBid="L75" class="l ;PORT_SYMBidhref="L84">  84se);
devne" _  8fi3.c#L43" id="L43e);
devne" _  8fi3href"="+code=id" class="sref">id);
1dode=DEEP1EEP_INIT" class="sref">D1EEPSL16="line" name="L33">  33#include &l1de=DEEPSL1EEP_INIT" class="sref">D1EEPSL1EP_INIne" name="L82">  82};
e);
devne" _  8.c#L43" id="L43e);
devne" _  8href="drivers/mfd/rc5t583.ce);
  84se);
  84spror in writing reg pror  nam (D1EEPSL1EP_INIrs/mfd/rc5t583.c#L92" id="L92" cla1de=DEEPSL1EEP_INIT" class="sref">D1EEPSL1EP_INIT(id].reg_add=DEEPSLEE1P_INIT" class="sref">DEE1PSLEE16+code=dev" clvice *reg_add=DEEPSLEE1P_INIT" class="sref">DEE1PSLEE1_INIT(  87        int ,lt; id);
1=DEEPSLEE1P_INIT" class="sref">DEE1PSLEE1790" class="line" name="L90">  90  1=DEEPSLEE1P_INIT" class="sref">DEE1PSLEE17P_INIT(

L111"> 13.c#L21" id="L21" class="line" name="L21"> 1f">PSO7, 121 } id =+nable_shutdownev" class="sref"nable_shutdown nam (id =on_off/a>, ret; RC5T583_1EXT_P17"L114"> 114 } 115 id =109" id="L109" class="line" name="L109"> 109 ret = ,lt; "="+code=id" class="sref">id); 1583_EXT_P1WRREQ2_CONTROL" class="s1ref">17ef="+code=reg_add" class="sref">reg_add, id); 15e=DEEPSL1static struct 117id =109" id="L109" class="line" name="ame="L34"> 34 9 ea hr:93"> 93 "+code=id" class="sref">id); 15DEEPSLEE1ss="line" name="L78"> 71817+code=dev" class="sref">dev, 09 ret = id); 1 class="l1ine" name="L79"> 791 1 {.id); 1 DEEPSLEE1ine" name="L80"> 801 18INIT( 115 id =109" id="L109" class="line" name="L109"> 109 0"="+code=id" class="sref">id); 1 DEEPSLEE1line" name="L81"> 81 18it" class="sref">slot_bit; , id); 1me = 1&qu1ot;rc18(id warnev" class="sref117id =109" id="L109" class="line" name="ame="L34"> 34 9 ea hr:93"> 93 "+code=id" class="sref">id); 1drivers/m1fd/rc5t583.c#L82" id="L812" cl18ref="+code=id" class=f">dev, 09 , id); 1 "drivers1ref">__rc5t583_set_ext_p1wrreq18"sref">ret; i18"L114"> 114
13.c#L21" id="L21" class="line" name="L21"> 1"sref">ex1t_pwr, int =e=dev_err" class+cod t583.c#L51" id="L51" c t583.c#+codee * * 1 86{ href="drivers/mfd/rc5t583.c#L115" id="L115" class="line" name="L115"> 115 id =109" id="L109" class="line" name="L109"> 1ie=dev_err" class+codef">0"="+code=id" class="sref">id); 1 DEEPSLEE1ne" name="L88"> 88 1 18+code=dev" class="sreef">slot_bit; , id); 1>; [id =1a> warnev" class="sref117id =109" id="L109" class="line"+code=id" class="sref">id); 1>DEEPSLEE1rivers/mfd/rc5t583.c#L901" id=19id="L110" class="line>[ 34 93 "+code=id" class="sref">id); 1 uns1igned int dev, "Erroie=dev_err" class+codefid); 1ss="line"1 name="L92"> 92 1 i1 ( 120 class="sr1ef">dev, "PWRRnvalid 0="+code=id" class="sref">id); 1 120 cint EINVAL; 84static int 89 583.c#L43" id="L43583hrefp"+code=id" class="sref">id); 1>="L86"> 1sleep_data" class="sref"1>deep1leep_drs/mfd/rc5t583.c#L92" id="L92" cla198" class1="line" name="L98"> 98<1/a> 1
1s3.c#L21" id="L21" class="line" name="L21"> 2"+code=id2 class="sref">id].slot_bit; ); 35#define < INT_EN_SYS#L51" id="L51" c INT_EN_SYS#d="L:s/mfd/rc5t583.c#L92" id="L92" cla2a2); 35#define < INT_EN_SYSPSEQ8, 4), << INT_EN_SYSPd="L:s/mfd/rc5t583.c#L92" id="L92" cla2a3); 92 2f">de2psleep_data 35#define < INT_EN_DCDCSEQ8, 4), << INT_EN_DCDCd="L:s/mfd/rc5t583.c#L92" id="L92" cla2a4); dev, 35#define < INT_EN_RTCSEQ8, 4), << INT_EN_RTCd="L:s/mfd/rc5t583.c#L92" id="L92" cla2a5); 35#define < INT_EN_A>SLPSEQ1, 0), < INT_EN_A>SLd="L:s/mfd/rc5t583.c#L92" id="L92" cla2a6); 104 35#define < INT_EN_A>SPSEQ8, 4), << INT_EN_Asl2epseq_val cas> 35#define < GPIO GPEDGELPSEQ1, 0), < GPIO GPEDGELhref:s/mfd/rc5t583.c#L92" id="L92" cla2a9); 98<2ef="+2ode=slots" clacas> 35#define < GPIO GPEDGEPSEQ8, 4), << GPIO GPEDGEPhref:s/mfd/rc5t583.c#L92" id="L92" cla2de=dev" c2ass="sref">dev, ); 82}; fals id="L84" class=fals +code=reg_add" class="sref">reg_add2ev_err(ret; 35#define < GPIO MON_IOINSEQ8, 4), << GPIO MON_IOINhref:s/mfd/rc5t583.c#L92" id="L92" cla2d4);
13.c#L21" id="L21" class="line" name="L21"> 2 2eturn reg_addEINVAL; id
1s3.c#L21" id="L21" class="line" name="L21"> 2ev_err" c2ass="sref">dev_err(<2 href2"+code=dev" class="srea> drivers/mfd/rc5tre3.c#L43" id="L43583href ION. GPIO IOSEd="L75" class="line" namGPIO IOSEdhrefpe/mfd//mfd/d="L21" class="line" name="L21"> 2f="+code=2eepsleep_data" class="sr2f">de2psleep_data[id); 2); 82}; fals id="L84" class=fals +code=reg_add" class="sref">reg_addret;
1s3.c#L21" id="L21" class="line" name="L21"> 2line" nam2="L123"> 123 2f ( drivers/mfd/rc5tre3.c#L43" id="L43583href ION. t583.c#L51" id="L51" c t583.c#+codpe/mfd//mfd/edrivers/mfd/rc5tre3.c#L43" id="L43583href I=sl t583.c##L51" id="L51" c t583.c##+codpp"+code=id" class="sref">id); 2) 2sref">rc5t583_write(2a hre2="+code=dev" class="sr>[ 82}; fals id="L84" class=fals +code=reg_add" class="sref">reg_addEINVAL;
1s3.c#L21" id="L21" class="line" name="L21"> 2l8); id); 2)v_err" c2ers/mfd/rc5t583.c#L28" i2d="L222+code=dev" class="sref">dev 82}; fals id="L84" class=fals +code=reg_add" class="sref">reg_add[ drivers/mfd/rc5tre3.c#L43" id="L43583href ION. REGrLDOEN#L51" id="L51" c REGrLDOEN#hrefpe/mfd//mfd/d="L21" class="line" name="L21"> 2ref="driv2ers/mfd/rc5t583.c#L30" i2d="L323id="L110" class="line>[id); 2rs/mfd/rc25t583.c#L31" id="L31" cl2ass="23lass="sref">dev, 82}; fals id="L84" class=fals +code=reg_add" class="sref">reg_add, } reg_add 94 2f href="d283.c#L35" id="L35" class2="lin23ss="sref">EINVAL; reg_add23id="Line" name="L94"> 94 2fv_err" c2583.c#L38" id="L38" clas2s="li23+codene" name="L94"> 94 2583.c#L392" id="L39" class="line" 2name=2L39"> _EXT_PWconsta"drivers/mfd/rc5t583.ceegmapfi3.c#L43" id="L43eegmapfi3 int 24id="L110" cla19" id="L119" class=="sref">slot_bitss=="srt583.c#8 "+code=id" class="sref">id); 2sref">u8<2/a> slot_bitid); 2st583.c#L2fd/rc5t583.c#L41" id="L421" cl24"L121"> 121id); 2sivers/mf2 1.c#L43" id="L43max_L111"> 1+cod MAX REGSL51" id="L51" c MAX REGShref "+code=id" class="sref">id); 2s 2>) \ id); 2s href="d2 45 .2id); 2ss/mfd/rc2 46 2.na2> = 2posna2>v_err" c2583.c#L47" id="L47" clas2s="li24+codene" name="L82"> 82}; 1 115 84ss2c==dev_err" class2chref "+code=id" class="sref">id); 2 [ 42 s2c_"line"me= name="L84"> 84ssde=dev_err" class="sref"+code=id" class="sref">id); 2 40" id="2SLEEP_INIT" class="sref"2>DEEP2LEEP_Irs/mfd/rc5t583.c#L92" id="L92" cla2cref">u8<2SLEEP_INIT" class="sref"2>DEEP25lass="sref">d"drivers/mfd/rc5t583.ce); 84se); na2code=DEEP2SLEEP_INIT" class="sref"2>DEEP253ass="sref">d"drivers/mfd/rc5t583.ce); 84spror in writing reg pror nam s2c==dev_err" class2chref-ION. sref">id =109" id="L109" class="linode=name" class=plat Prerror in writing reg plat Prerror nam href="+code=name" class="sref">na2civers/mf2SLEEP_INIT" class="sref"2>DEEP2LEEP_INIT(aruct id].reg_addD2EEPSL25"+code=dev" cslot_bitreg_addD2EEPSL25ss="sref">EINVAL; D2EEPSL25ef="+code=reg_add!"L84"> 84spror in writing reg pror nampers/mfd/rc5t583.c#L92" id="L92" cla2de=DEEPSL2EEP_INIT" class="sref">D2EEPSL25id="L117" class="line" name="L117"> 117 if (ds2c==dev_err" class2chref-ION. sref">id =109" id="L109" class="line" name="ame="L34"> 34 "="+code=id" class="sref">id); 2de=DEEPSL2EEP_INIT" class="sref">D2EEPSL25+code=dev" class="srenvalid control for rail %d\n", id); 2de=DEEPSL2EEP_INIT" class="sref">D2EEPSL2639"> 39 ="line" name="L120"> 120 2de=DEEPSL2EEP_INIT" class="sref">D2EEPSL2690" class="line" name="L90"> 90 2dref">u8<2EEP_INIT" class="sref">D2EEPSL26P_INIT(ds2c==dev_err" class2chref-ION. sref">id =109" id="L109" class="line"sizeof="drivers/mfd/rc5t583.ce); id); 2dode=DEEP2EEP_INIT" class="sref">D2EEPSL26"L121"> 121 !"L84"> 84se); D2EEPSL26ref="+code=id" class="sref">id =110 if (ds2c==dev_err" class2chref-ION. sref">id =109" id="L109" class="line" name="ame="L34"> 34 Memory alloc" non faile93 "="+code=id" class="sref">id); 2de=DEEPSL2EEP_INIT" class="sref">D2EEPSL26"+code=dev" class="srf="+codcontrol for rail NOMEMd\n"NOMEMhref="+code=id" class="sref">id); 2de=DEEPSL2LL15" class="line" name=2LEPSL2EP_INIT( 120 2ds/mfd/rc2EEP_INIT" class="sref">D2EEPSL26ne" name="L36"> 36#define D2EEPSL26pseq_val |= id =109" id="L109" class="linec#=dev" class="sref">ds2c==dev_err" class2chref-ION. sref">id =109" id="L109" class="lin="+code=id" class="sref">id); 2de=DEEPSL2P_INIT" class="sref">DEE2PSLEE26de=slots" class="sref">slotss2c_namecli idror in writing reg s2c_namecli idror code="L84"> 84ss2c==dev_err" class2chref rs/mfd/rc5t583.ce); id); 2=DEEPSLEE2P_INIT" class="sref">DEE2PSLEE27 {.id); 2=DEEPSLEE2P_INIT" class="sref">DEE2PSLEE27INIT(id =eegmap.c#L43" id="L43eegmap namec#L96" id="L96" clavm_eegmap 84ss2c==dev_err" class2chref r=dev" class="sref">d15 fi3.c#L43" id="L43e5 fi3t583)="+code=id" class="sref">id); 2=ref">u8<2P_INIT" class="sref">DEE2PSLEE27it" class="sref">slot_bit; 84sh); id =eegmap.c#L43" id="L43eegmap nam))ers/mfd/rc5t583.c#L92" id="L92" cla2f">PSO7, id]. 84sh); id =eegmap.c#L43" id="L43eegmap nam)="+code=id" class="sref">id); 2=ode=DEEP2fd/rc5t583.c#L72" id="L722" cl27ref="+code=id" class="sref">id =110 if (ds2c==dev_err" class2chref-ION. sref">id =109" id="L109" class="line" name="ame="L34"> 34 eegmap nne"ializ" non faile9:93"> 93 fid); 2="drivers2/mfd/rc5t583.c#L74" id="2L74" 27"+code=dev" class="srf="+code=id" class="sref">id].reg_addRC5T583_2EXT_P27P_INIT( 120 2583_EXT_P2WRREQ2_CONTROL" class="s2ref">27ne" name="L36"> 36#define static struct devne" _ 8.c#L43" id="L43e); devne" _ 8href="L84"> 84sh); reg_add 72827+code=dev" clef">slot_bit; , id); 2 class="l2ine" name="L79"> 792 28sleep_data[id].reg_add 802 2890" class="line" name="L90"> 90 2 DEEPSLEE2line" name="L81"> 81 28it" class="sref">slot_bit; id =ir8.c#L43" id="L43ir8 nam)ers/mfd/rc5t583.c#L92" id="L92" cla2me = 2&qu2ot;rc28(id 115 84sh); id =ir8.c#L43" id="L43ir8 nam fid =ir8_bas id="L84" class=ir8_bas nampe=reg_add" class="sref">reg_add
2 "drivers2ref">__rc5t583_set_ext_p2wrreq28"+code=dev" class="sref">dev, id); 2 1_CONTRO2ref="+code=id" class="sr2ef">i2825" class="line" name="L125">"sref">id =110ds2c==dev_err" class2chref-ION. sref">id =109" id="L109" class="line" name="ame="L34"> 34 IRQ nne" faile9:93"> 93 fid); 2"sref">ex2t_pwr, int id); 2"e=DEEPSL2 86{ "sref">id =irq_nne"_succesref">slot_bitreg_add 88 2 28+code=dev" cl="line" name="L120"> 120 2>; id); 2>DEEPSLEE2rivers/mfd/rc5t583.c#L902" id=29INIT(slot_bit 84sh); id =109" id="L109" class="line"-1 rs/mfd/rc5t583.ce); slot_bit); id); 2 uns2igned int dev, 84sh); slot_bit); id); 2ss="line"2 name="L92"> 92 2 i29"L121"> 121 dev, id =110 if (ds2c==dev_err" class2chref-ION. sref">id =109" id="L109" class="line" name="ame="L34"> 34 9 93 fid); 2id =+rr19slot_bitreg_add( 120 2/mfd/rc5t2583.c#L95" id="L95" clas2s="li29ne" name="L36"> 36#define ="L86"> 2sleep_data" class="sref"2>deep29id="L117" clanvalid 0="+code=id" class="sref">id); 298" class2="line" name="L98"> 98<2/a> 29+codene" name="L94"> 94 3"+code=id3 class="sref">id].id =+rr19slot_bit); slot_bit; slot_bitid); 3a2); dev, L115" id="L115" class="irq_exe" name="L115"> 115 84sh); id); 3a3); 92 3f">de3psleep_dataid].reg_adddev, 120 3a5); ret; 82}; 1 115 84ss2c==dev_err" class2chrefp"+code=id" class="sref">id); 3a7); sl3epseq_val "drivers/mfd/rc5t583.ce); 84se); 84ss2c==dev_err" class2chref"="+code=id" class="sref">id); 3a9); 98<3ef="+30+codene" name="L94"> 94 3de=dev" c3ass="sref">dev, slot_bit 84sh); id =109" id="L109" class="lin"="+code=id" class="sref">id); 3d>); 115 84sh); id); 3s="sref">3ev_err(id); 3id="L112"3class="line" name="L112"3 112<31sleep="line" name="L120"> 120 3d4); 33#include &l3 3eturn 42 s2c_"line"me= nameL115" id="L115" class="i2c_e="L42"> 42 class="i2c_e= nam[].c#rs/mfd/rc5t583.c#L92" id="L92" cla3s6); ( 42 "s=" nam name="ame="L34"> 34 e="L92"/a> fode=name" class=583.c#rror in writing reg 583.c#rror nam 0} "+code=id" class="sref">id); 3href="+co3e=id" class="sref">id 120 3d8); na3ev_err" c3ass="sref">dev_err(<3 href31+codene" name="L94"> 94 3f="+code=3eepsleep_data" class="sr3f">de32code="sref">id =MODULE_DEVICE_TABLEL51" id="L51" cMODULE_DEVICE_TABLEcode="L84"> 84ss2c==dev_err" class2chref rL115" id="L115" class="i2c_e="L42"> 42 class="i2c_e= nam"="+code=id" class="sref">id); 3); 90 3 3eturn 42 s2c_" name nameL115" id="L115" class="i2c_" name"L42"> 42 class="i2c_" name nam rs/mfd/rc5t583.c#L92" id="L92" cla35t583.c#L321" id="L121" class="lin3" nam32( 123 3f ( 42 "s=" nam name="ame="L34"> 34 e="L92"/a> s/mfd/rc5t583.c#L92" id="L92" cla35 3sref">rc5t583_write(3a hre3="+code=dev" class="sr>[id); 3 6); id); 3eep_data"3class="sref/L1assref="d13" cla327code=dev" clode=name" class=prob" name="L115"> 1prob"href.c#L115" id="L115" class="i2c_prob" name="L115"> 115 id); 3e8); 11emov"code.c#L115" id="L115" 84sh); 115 id); 3ev_err" c3ers/mfd/rc5t583.c#L28" i3d="L232+code=dev" cl19" id="L119" clid_table"L42"> 42 sd_tablehref.c#L115" id="L115" class="i2c_e="L42"> 42 class="i2c_e= nam "+code=id" class="sref">id); 3f="driver3s/mfd/rc5t583.c#L29" id=3"L29"33sleepa href="+code=name" class="sref">na3ref="driv3ers/mfd/rc5t583.c#L30" i3d="L33390" class="line" name="L90"> 90 3rs/mfd/rc35t583.c#L31" id="L31" cl3ass="33"srefne" name="L82"> 82}; 1 115 id); 3ft583.c#L3c#L32" id="L32" class="l3ine" 33583-krs/mfd/rc5t583.c#L92" id="L92" cla3rivers/mf3d/rc5t583.c#L33" id="L333" cla33ref="+code=idf="+code=id" class="sri2c_9 42 s2c_9d class="i2c_" name"L42"> 42 class="i2c_" name nam"="+code=id" class="sref">id); 3f 3="include/linux/regmap.h3" cla33L94" ="line" name="L120"> 120 3f href="d383.c#L35" id="L35" class3="lin33ss="s class="sref">dsubsys_nne"cal83" id="L83" clasubsys_nne"cal8code="L84"> 84sh); 115 id); 3fep_data"35t583.c#L36" id="L36" cl3ass="33ne" name="L36"> 36#define 33id="Lne" namvoidL82"> 82}; 1 115 id); 3fv_err" c3583.c#L38" id="L38" clas3s="li33+coders/mfd/rc5t583.c#L92" id="L92" cla3583.c#L393" id="L39" class="line" 3name=34INIT( 42 s2c_"ll_" namecode==dev" class="sref">d class="i2c_" name"L42"> 42 class="i2c_" name nam"="+code=id" class="sref">id); 3L40" id="3L40" class="line" name="3L40">34id="L="line" name="L120"> 120 3sref">u8<3/a> ret; 1module_exe"code="L84"> 84sh); 115 id); 3Livers/mf3 33#include &l3s 3>) \ id =MODULE_AUTHOR.c#L43" id="L43MODULE_AUTHORcode=" name="ame="L34"> 34 LaxmameDewangamee=slldewangam@nvidia.comION./a> "="+code=id" class="sref">id); 3s href="d3 45 .3dMODULE_DESCRIPTIONSEQ8, 4), 34 code= vne" mamagev id system "line" class/a> "="+code=id" class="sref">id); 3sep_data"3 46 3.dMODULE_LICENSEL51" id="L51" cMODULE_LICENSEcode=" name="ame="L34"> 34 GPL v2/a> "="+code=id" class="sref">id); 3s"+code=R3ef="+code=_pos" class="s3ref">3pos
1.> The original LXR software by th> 35#dhttp://sourceforge.net/projects/lx1.>LXR lx1@posux.nohref.
1.> lx1.posux.no kindly hosted by 35#dhttp://www.redpill-pospro.no">Redpill Lospro AShref provid" of Losuxmconsulvers/and oper" nons serine"r since 1995.