linux/drivers/mfd/dbx500-prcmu-regs.h
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   1/*
   2 * Copyright (C) STMicroelectronics 2009
   3 * Copyright (C) ST-Ericsson SA 2010
   4 *
   5 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
   6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
   7 *
   8 * License Terms: GNU General Public License v2
   9 *
  10 * PRCM Unit registers
  11 */
  12
  13#ifndef __DB8500_PRCMU_REGS_H
  14#define __DB8500_PRCMU_REGS_H
  15
  16#include <mach/hardware.h>
  17
  18#define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
  19
  20#define PRCM_CLK_MGT(_offset) (void __iomem *)(IO_ADDRESS(U8500_PRCMU_BASE) \
  21        + _offset)
  22#define PRCM_ACLK_MGT           PRCM_CLK_MGT(0x004)
  23#define PRCM_SVACLK_MGT         PRCM_CLK_MGT(0x008)
  24#define PRCM_SIACLK_MGT         PRCM_CLK_MGT(0x00C)
  25#define PRCM_SGACLK_MGT         PRCM_CLK_MGT(0x014)
  26#define PRCM_UARTCLK_MGT        PRCM_CLK_MGT(0x018)
  27#define PRCM_MSP02CLK_MGT       PRCM_CLK_MGT(0x01C)
  28#define PRCM_I2CCLK_MGT         PRCM_CLK_MGT(0x020)
  29#define PRCM_SDMMCCLK_MGT       PRCM_CLK_MGT(0x024)
  30#define PRCM_SLIMCLK_MGT        PRCM_CLK_MGT(0x028)
  31#define PRCM_PER1CLK_MGT        PRCM_CLK_MGT(0x02C)
  32#define PRCM_PER2CLK_MGT        PRCM_CLK_MGT(0x030)
  33#define PRCM_PER3CLK_MGT        PRCM_CLK_MGT(0x034)
  34#define PRCM_PER5CLK_MGT        PRCM_CLK_MGT(0x038)
  35#define PRCM_PER6CLK_MGT        PRCM_CLK_MGT(0x03C)
  36#define PRCM_PER7CLK_MGT        PRCM_CLK_MGT(0x040)
  37#define PRCM_LCDCLK_MGT         PRCM_CLK_MGT(0x044)
  38#define PRCM_BMLCLK_MGT         PRCM_CLK_MGT(0x04C)
  39#define PRCM_HSITXCLK_MGT       PRCM_CLK_MGT(0x050)
  40#define PRCM_HSIRXCLK_MGT       PRCM_CLK_MGT(0x054)
  41#define PRCM_HDMICLK_MGT        PRCM_CLK_MGT(0x058)
  42#define PRCM_APEATCLK_MGT       PRCM_CLK_MGT(0x05C)
  43#define PRCM_APETRACECLK_MGT    PRCM_CLK_MGT(0x060)
  44#define PRCM_MCDECLK_MGT        PRCM_CLK_MGT(0x064)
  45#define PRCM_IPI2CCLK_MGT       PRCM_CLK_MGT(0x068)
  46#define PRCM_DSIALTCLK_MGT      PRCM_CLK_MGT(0x06C)
  47#define PRCM_DMACLK_MGT         PRCM_CLK_MGT(0x074)
  48#define PRCM_B2R2CLK_MGT        PRCM_CLK_MGT(0x078)
  49#define PRCM_TVCLK_MGT          PRCM_CLK_MGT(0x07C)
  50#define PRCM_UNIPROCLK_MGT      PRCM_CLK_MGT(0x278)
  51#define PRCM_SSPCLK_MGT         PRCM_CLK_MGT(0x280)
  52#define PRCM_RNGCLK_MGT         PRCM_CLK_MGT(0x284)
  53#define PRCM_UICCCLK_MGT        PRCM_CLK_MGT(0x27C)
  54#define PRCM_MSP1CLK_MGT        PRCM_CLK_MGT(0x288)
  55
  56#define PRCM_ARM_PLLDIVPS       (_PRCMU_BASE + 0x118)
  57#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE          0x3f
  58#define PRCM_ARM_PLLDIVPS_MAX_MASK              0xf
  59
  60#define PRCM_PLLARM_LOCKP       (_PRCMU_BASE + 0x0a8)
  61#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3    0x2
  62
  63#define PRCM_ARM_CHGCLKREQ      (_PRCMU_BASE + 0x114)
  64#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ   0x1
  65
  66#define PRCM_PLLARM_ENABLE      (_PRCMU_BASE + 0x98)
  67#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE   0x1
  68#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON  0x100
  69
  70#define PRCM_ARMCLKFIX_MGT      (_PRCMU_BASE + 0x0)
  71#define PRCM_A9PL_FORCE_CLKEN   (_PRCMU_BASE + 0x19C)
  72#define PRCM_A9_RESETN_CLR      (_PRCMU_BASE + 0x1f4)
  73#define PRCM_A9_RESETN_SET      (_PRCMU_BASE + 0x1f0)
  74#define PRCM_ARM_LS_CLAMP       (_PRCMU_BASE + 0x30c)
  75#define PRCM_SRAM_A9            (_PRCMU_BASE + 0x308)
  76
  77#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0)
  78#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1)
  79
  80/* ARM WFI Standby signal register */
  81#define PRCM_ARM_WFI_STANDBY    (_PRCMU_BASE + 0x130)
  82#define PRCM_ARM_WFI_STANDBY_WFI0               0x08
  83#define PRCM_ARM_WFI_STANDBY_WFI1               0x10
  84#define PRCM_IOCR               (_PRCMU_BASE + 0x310)
  85#define PRCM_IOCR_IOFORCE                       0x1
  86
  87/* CPU mailbox registers */
  88#define PRCM_MBOX_CPU_VAL       (_PRCMU_BASE + 0x0fc)
  89#define PRCM_MBOX_CPU_SET       (_PRCMU_BASE + 0x100)
  90#define PRCM_MBOX_CPU_CLR       (_PRCMU_BASE + 0x104)
  91
  92/* Dual A9 core interrupt management unit registers */
  93#define PRCM_A9_MASK_REQ        (_PRCMU_BASE + 0x328)
  94#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ       0x1
  95
  96#define PRCM_A9_MASK_ACK        (_PRCMU_BASE + 0x32c)
  97#define PRCM_ARMITMSK31TO0      (_PRCMU_BASE + 0x11c)
  98#define PRCM_ARMITMSK63TO32     (_PRCMU_BASE + 0x120)
  99#define PRCM_ARMITMSK95TO64     (_PRCMU_BASE + 0x124)
 100#define PRCM_ARMITMSK127TO96    (_PRCMU_BASE + 0x128)
 101#define PRCM_POWER_STATE_VAL    (_PRCMU_BASE + 0x25C)
 102#define PRCM_ARMITVAL31TO0      (_PRCMU_BASE + 0x260)
 103#define PRCM_ARMITVAL63TO32     (_PRCMU_BASE + 0x264)
 104#define PRCM_ARMITVAL95TO64     (_PRCMU_BASE + 0x268)
 105#define PRCM_ARMITVAL127TO96    (_PRCMU_BASE + 0x26C)
 106
 107#define PRCM_HOSTACCESS_REQ     (_PRCMU_BASE + 0x334)
 108#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1
 109#define PRCM_HOSTACCESS_REQ_WAKE_REQ    BIT(16)
 110#define ARM_WAKEUP_MODEM        0x1
 111
 112#define PRCM_ARM_IT1_CLR        (_PRCMU_BASE + 0x48C)
 113#define PRCM_ARM_IT1_VAL        (_PRCMU_BASE + 0x494)
 114#define PRCM_HOLD_EVT           (_PRCMU_BASE + 0x174)
 115
 116#define PRCM_MOD_AWAKE_STATUS   (_PRCMU_BASE + 0x4A0)
 117#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE     BIT(0)
 118#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE       BIT(1)
 119#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO   BIT(2)
 120
 121#define PRCM_ITSTATUS0          (_PRCMU_BASE + 0x148)
 122#define PRCM_ITSTATUS1          (_PRCMU_BASE + 0x150)
 123#define PRCM_ITSTATUS2          (_PRCMU_BASE + 0x158)
 124#define PRCM_ITSTATUS3          (_PRCMU_BASE + 0x160)
 125#define PRCM_ITSTATUS4          (_PRCMU_BASE + 0x168)
 126#define PRCM_ITSTATUS5          (_PRCMU_BASE + 0x484)
 127#define PRCM_ITCLEAR5           (_PRCMU_BASE + 0x488)
 128#define PRCM_ARMIT_MASKXP70_IT  (_PRCMU_BASE + 0x1018)
 129
 130/* System reset register */
 131#define PRCM_APE_SOFTRST        (_PRCMU_BASE + 0x228)
 132
 133/* Level shifter and clamp control registers */
 134#define PRCM_MMIP_LS_CLAMP_SET     (_PRCMU_BASE + 0x420)
 135#define PRCM_MMIP_LS_CLAMP_CLR     (_PRCMU_BASE + 0x424)
 136
 137#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP         BIT(11)
 138#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI        BIT(22)
 139
 140/* PRCMU clock/PLL/reset registers */
 141#define PRCM_PLLSOC0_FREQ          (_PRCMU_BASE + 0x080)
 142#define PRCM_PLLSOC1_FREQ          (_PRCMU_BASE + 0x084)
 143#define PRCM_PLLDDR_FREQ           (_PRCMU_BASE + 0x08C)
 144#define PRCM_PLL_FREQ_D_SHIFT   0
 145#define PRCM_PLL_FREQ_D_MASK    BITS(0, 7)
 146#define PRCM_PLL_FREQ_N_SHIFT   8
 147#define PRCM_PLL_FREQ_N_MASK    BITS(8, 13)
 148#define PRCM_PLL_FREQ_R_SHIFT   16
 149#define PRCM_PLL_FREQ_R_MASK    BITS(16, 18)
 150#define PRCM_PLL_FREQ_SELDIV2   BIT(24)
 151#define PRCM_PLL_FREQ_DIV2EN    BIT(25)
 152
 153#define PRCM_PLLDSI_FREQ           (_PRCMU_BASE + 0x500)
 154#define PRCM_PLLDSI_ENABLE         (_PRCMU_BASE + 0x504)
 155#define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)
 156#define PRCM_DSI_PLLOUT_SEL        (_PRCMU_BASE + 0x530)
 157#define PRCM_DSITVCLK_DIV          (_PRCMU_BASE + 0x52C)
 158#define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)
 159#define PRCM_APE_RESETN_SET        (_PRCMU_BASE + 0x1E4)
 160#define PRCM_APE_RESETN_CLR        (_PRCMU_BASE + 0x1E8)
 161
 162#define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0)
 163
 164#define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10   BIT(0)
 165#define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3    BIT(1)
 166
 167#define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT    0
 168#define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK     BITS(0, 2)
 169#define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT    8
 170#define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK     BITS(8, 10)
 171
 172#define PRCM_DSI_PLLOUT_SEL_OFF         0
 173#define PRCM_DSI_PLLOUT_SEL_PHI         1
 174#define PRCM_DSI_PLLOUT_SEL_PHI_2       2
 175#define PRCM_DSI_PLLOUT_SEL_PHI_4       3
 176
 177#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT        0
 178#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK         BITS(0, 7)
 179#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT        8
 180#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK         BITS(8, 15)
 181#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT        16
 182#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK         BITS(16, 23)
 183#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN               BIT(24)
 184#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN               BIT(25)
 185#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN               BIT(26)
 186
 187#define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14)
 188
 189#define PRCM_CLKOCR                (_PRCMU_BASE + 0x1CC)
 190#define PRCM_CLKOCR_CLKOUT0_REF_CLK     (1 << 0)
 191#define PRCM_CLKOCR_CLKOUT0_MASK        BITS(0, 13)
 192#define PRCM_CLKOCR_CLKOUT1_REF_CLK     (1 << 16)
 193#define PRCM_CLKOCR_CLKOUT1_MASK        BITS(16, 29)
 194
 195/* ePOD and memory power signal control registers */
 196#define PRCM_EPOD_C_SET            (_PRCMU_BASE + 0x410)
 197#define PRCM_SRAM_LS_SLEEP         (_PRCMU_BASE + 0x304)
 198
 199/* Debug power control unit registers */
 200#define PRCM_POWER_STATE_SET       (_PRCMU_BASE + 0x254)
 201
 202/* Miscellaneous unit registers */
 203#define PRCM_DSI_SW_RESET          (_PRCMU_BASE + 0x324)
 204#define PRCM_GPIOCR                (_PRCMU_BASE + 0x138)
 205#define PRCM_GPIOCR_DBG_STM_MOD_CMD1            0x800
 206#define PRCM_GPIOCR_DBG_UARTMOD_CMD0            0x1
 207
 208/* PRCMU HW semaphore */
 209#define PRCM_SEM                   (_PRCMU_BASE + 0x400)
 210#define PRCM_SEM_PRCM_SEM BIT(0)
 211
 212#define PRCM_TCR                   (_PRCMU_BASE + 0x1C8)
 213#define PRCM_TCR_TENSEL_MASK       BITS(0, 7)
 214#define PRCM_TCR_STOP_TIMERS       BIT(16)
 215#define PRCM_TCR_DOZE_MODE         BIT(17)
 216
 217#define PRCM_CLKOCR_CLKODIV0_SHIFT      0
 218#define PRCM_CLKOCR_CLKODIV0_MASK       BITS(0, 5)
 219#define PRCM_CLKOCR_CLKOSEL0_SHIFT      6
 220#define PRCM_CLKOCR_CLKOSEL0_MASK       BITS(6, 8)
 221#define PRCM_CLKOCR_CLKODIV1_SHIFT      16
 222#define PRCM_CLKOCR_CLKODIV1_MASK       BITS(16, 21)
 223#define PRCM_CLKOCR_CLKOSEL1_SHIFT      22
 224#define PRCM_CLKOCR_CLKOSEL1_MASK       BITS(22, 24)
 225#define PRCM_CLKOCR_CLK1TYPE            BIT(28)
 226
 227#define PRCM_CLK_MGT_CLKPLLDIV_MASK             BITS(0, 4)
 228#define PRCM_CLK_MGT_CLKPLLSW_SOC0              BIT(5)
 229#define PRCM_CLK_MGT_CLKPLLSW_SOC1              BIT(6)
 230#define PRCM_CLK_MGT_CLKPLLSW_DDR               BIT(7)
 231#define PRCM_CLK_MGT_CLKPLLSW_MASK              BITS(5, 7)
 232#define PRCM_CLK_MGT_CLKEN                      BIT(8)
 233#define PRCM_CLK_MGT_CLK38                      BIT(9)
 234#define PRCM_CLK_MGT_CLK38DIV                   BIT(11)
 235#define PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN     BIT(12)
 236
 237/* GPIOCR register */
 238#define PRCM_GPIOCR_SPI2_SELECT BIT(23)
 239
 240#define PRCM_DDR_SUBSYS_APE_MINBW       (_PRCMU_BASE + 0x438)
 241#define PRCM_CGATING_BYPASS             (_PRCMU_BASE + 0x134)
 242#define PRCM_CGATING_BYPASS_ICN2        BIT(6)
 243
 244/* Miscellaneous unit registers */
 245#define PRCM_RESOUTN_SET                (_PRCMU_BASE + 0x214)
 246#define PRCM_RESOUTN_CLR                (_PRCMU_BASE + 0x218)
 247
 248/* System reset register */
 249#define PRCM_APE_SOFTRST                (_PRCMU_BASE + 0x228)
 250
 251#endif /* __DB8500_PRCMU_REGS_H */
 252
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