linux/drivers/memory/tegra30-mc.c
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   1/*
   2 * Tegra30 Memory Controller
   3 *
   4 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along with
  16 * this program; if not, write to the Free Software Foundation, Inc.,
  17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18 */
  19
  20#include <linux/kernel.h>
  21#include <linux/module.h>
  22#include <linux/ratelimit.h>
  23#include <linux/platform_device.h>
  24#include <linux/interrupt.h>
  25#include <linux/io.h>
  26
  27#define DRV_NAME "tegra30-mc"
  28
  29#define MC_INTSTATUS                    0x0
  30#define MC_INTMASK                      0x4
  31
  32#define MC_INT_ERR_SHIFT                6
  33#define MC_INT_ERR_MASK                 (0x1f << MC_INT_ERR_SHIFT)
  34#define MC_INT_DECERR_EMEM              BIT(MC_INT_ERR_SHIFT)
  35#define MC_INT_SECURITY_VIOLATION       BIT(MC_INT_ERR_SHIFT + 2)
  36#define MC_INT_ARBITRATION_EMEM         BIT(MC_INT_ERR_SHIFT + 3)
  37#define MC_INT_INVALID_SMMU_PAGE        BIT(MC_INT_ERR_SHIFT + 4)
  38
  39#define MC_ERR_STATUS                   0x8
  40#define MC_ERR_ADR                      0xc
  41
  42#define MC_ERR_TYPE_SHIFT               28
  43#define MC_ERR_TYPE_MASK                (7 << MC_ERR_TYPE_SHIFT)
  44#define MC_ERR_TYPE_DECERR_EMEM         2
  45#define MC_ERR_TYPE_SECURITY_TRUSTZONE  3
  46#define MC_ERR_TYPE_SECURITY_CARVEOUT   4
  47#define MC_ERR_TYPE_INVALID_SMMU_PAGE   6
  48
  49#define MC_ERR_INVALID_SMMU_PAGE_SHIFT  25
  50#define MC_ERR_INVALID_SMMU_PAGE_MASK   (7 << MC_ERR_INVALID_SMMU_PAGE_SHIFT)
  51#define MC_ERR_RW_SHIFT                 16
  52#define MC_ERR_RW                       BIT(MC_ERR_RW_SHIFT)
  53#define MC_ERR_SECURITY                 BIT(MC_ERR_RW_SHIFT + 1)
  54
  55#define SECURITY_VIOLATION_TYPE         BIT(30) /* 0=TRUSTZONE, 1=CARVEOUT */
  56
  57#define MC_EMEM_ARB_CFG                 0x90
  58#define MC_EMEM_ARB_OUTSTANDING_REQ     0x94
  59#define MC_EMEM_ARB_TIMING_RCD          0x98
  60#define MC_EMEM_ARB_TIMING_RP           0x9c
  61#define MC_EMEM_ARB_TIMING_RC           0xa0
  62#define MC_EMEM_ARB_TIMING_RAS          0xa4
  63#define MC_EMEM_ARB_TIMING_FAW          0xa8
  64#define MC_EMEM_ARB_TIMING_RRD          0xac
  65#define MC_EMEM_ARB_TIMING_RAP2PRE      0xb0
  66#define MC_EMEM_ARB_TIMING_WAP2PRE      0xb4
  67#define MC_EMEM_ARB_TIMING_R2R          0xb8
  68#define MC_EMEM_ARB_TIMING_W2W          0xbc
  69#define MC_EMEM_ARB_TIMING_R2W          0xc0
  70#define MC_EMEM_ARB_TIMING_W2R          0xc4
  71
  72#define MC_EMEM_ARB_DA_TURNS            0xd0
  73#define MC_EMEM_ARB_DA_COVERS           0xd4
  74#define MC_EMEM_ARB_MISC0               0xd8
  75#define MC_EMEM_ARB_MISC1               0xdc
  76
  77#define MC_EMEM_ARB_RING3_THROTTLE      0xe4
  78#define MC_EMEM_ARB_OVERRIDE            0xe8
  79
  80#define MC_TIMING_CONTROL               0xfc
  81
  82#define MC_CLIENT_ID_MASK               0x7f
  83
  84#define NUM_MC_REG_BANKS                4
  85
  86struct tegra30_mc {
  87        void __iomem *regs[NUM_MC_REG_BANKS];
  88        struct device *dev;
  89        u32 ctx[0];
  90};
  91
  92static inline u32 mc_readl(struct tegra30_mc *mc, u32 offs)
  93{
  94        u32 val = 0;
  95
  96        if (offs < 0x10)
  97                val = readl(mc->regs[0] + offs);
  98        if (offs < 0x1f0)
  99                val = readl(mc->regs[1] + offs - 0x3c);
 100        if (offs < 0x228)
 101                val = readl(mc->regs[2] + offs - 0x200);
 102        if (offs < 0x400)
 103                val = readl(mc->regs[3] + offs - 0x284);
 104
 105        return val;
 106}
 107
 108static inline void mc_writel(struct tegra30_mc *mc, u32 val, u32 offs)
 109{
 110        if (offs < 0x10) {
 111                writel(val, mc->regs[0] + offs);
 112                return;
 113        }
 114        if (offs < 0x1f0) {
 115                writel(val, mc->regs[1] + offs - 0x3c);
 116                return;
 117        }
 118        if (offs < 0x228) {
 119                writel(val, mc->regs[2] + offs - 0x200);
 120                return;
 121        }
 122        if (offs < 0x400) {
 123                writel(val, mc->regs[3] + offs - 0x284);
 124                return;
 125        }
 126}
 127
 128static const char * const tegra30_mc_client[] = {
 129        "csr_ptcr",
 130        "cbr_display0a",
 131        "cbr_display0ab",
 132        "cbr_display0b",
 133        "cbr_display0bb",
 134        "cbr_display0c",
 135        "cbr_display0cb",
 136        "cbr_display1b",
 137        "cbr_display1bb",
 138        "cbr_eppup",
 139        "cbr_g2pr",
 140        "cbr_g2sr",
 141        "cbr_mpeunifbr",
 142        "cbr_viruv",
 143        "csr_afir",
 144        "csr_avpcarm7r",
 145        "csr_displayhc",
 146        "csr_displayhcb",
 147        "csr_fdcdrd",
 148        "csr_fdcdrd2",
 149        "csr_g2dr",
 150        "csr_hdar",
 151        "csr_host1xdmar",
 152        "csr_host1xr",
 153        "csr_idxsrd",
 154        "csr_idxsrd2",
 155        "csr_mpe_ipred",
 156        "csr_mpeamemrd",
 157        "csr_mpecsrd",
 158        "csr_ppcsahbdmar",
 159        "csr_ppcsahbslvr",
 160        "csr_satar",
 161        "csr_texsrd",
 162        "csr_texsrd2",
 163        "csr_vdebsevr",
 164        "csr_vdember",
 165        "csr_vdemcer",
 166        "csr_vdetper",
 167        "csr_mpcorelpr",
 168        "csr_mpcorer",
 169        "cbw_eppu",
 170        "cbw_eppv",
 171        "cbw_eppy",
 172        "cbw_mpeunifbw",
 173        "cbw_viwsb",
 174        "cbw_viwu",
 175        "cbw_viwv",
 176        "cbw_viwy",
 177        "ccw_g2dw",
 178        "csw_afiw",
 179        "csw_avpcarm7w",
 180        "csw_fdcdwr",
 181        "csw_fdcdwr2",
 182        "csw_hdaw",
 183        "csw_host1xw",
 184        "csw_ispw",
 185        "csw_mpcorelpw",
 186        "csw_mpcorew",
 187        "csw_mpecswr",
 188        "csw_ppcsahbdmaw",
 189        "csw_ppcsahbslvw",
 190        "csw_sataw",
 191        "csw_vdebsevw",
 192        "csw_vdedbgw",
 193        "csw_vdembew",
 194        "csw_vdetpmw",
 195};
 196
 197static void tegra30_mc_decode(struct tegra30_mc *mc, int n)
 198{
 199        u32 err, addr;
 200        const char * const mc_int_err[] = {
 201                "MC_DECERR",
 202                "Unknown",
 203                "MC_SECURITY_ERR",
 204                "MC_ARBITRATION_EMEM",
 205                "MC_SMMU_ERR",
 206        };
 207        const char * const err_type[] = {
 208                "Unknown",
 209                "Unknown",
 210                "DECERR_EMEM",
 211                "SECURITY_TRUSTZONE",
 212                "SECURITY_CARVEOUT",
 213                "Unknown",
 214                "INVALID_SMMU_PAGE",
 215                "Unknown",
 216        };
 217        char attr[6];
 218        int cid, perm, type, idx;
 219        const char *client = "Unknown";
 220
 221        idx = n - MC_INT_ERR_SHIFT;
 222        if ((idx < 0) || (idx >= ARRAY_SIZE(mc_int_err)) || (idx == 1)) {
 223                dev_err_ratelimited(mc->dev, "Unknown interrupt status %08lx\n",
 224                                    BIT(n));
 225                return;
 226        }
 227
 228        err = readl(mc + MC_ERR_STATUS);
 229
 230        type = (err & MC_ERR_TYPE_MASK) >> MC_ERR_TYPE_SHIFT;
 231        perm = (err & MC_ERR_INVALID_SMMU_PAGE_MASK) >>
 232                MC_ERR_INVALID_SMMU_PAGE_SHIFT;
 233        if (type == MC_ERR_TYPE_INVALID_SMMU_PAGE)
 234                sprintf(attr, "%c-%c-%c",
 235                        (perm & BIT(2)) ? 'R' : '-',
 236                        (perm & BIT(1)) ? 'W' : '-',
 237                        (perm & BIT(0)) ? 'S' : '-');
 238        else
 239                attr[0] = '\0';
 240
 241        cid = err & MC_CLIENT_ID_MASK;
 242        if (cid < ARRAY_SIZE(tegra30_mc_client))
 243                client = tegra30_mc_client[cid];
 244
 245        addr = readl(mc + MC_ERR_ADR);
 246
 247        dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s %s %s)\n",
 248                           mc_int_err[idx], err, addr, client,
 249                           (err & MC_ERR_SECURITY) ? "secure" : "non-secure",
 250                           (err & MC_ERR_RW) ? "write" : "read",
 251                           err_type[type], attr);
 252}
 253
 254static const u32 tegra30_mc_ctx[] = {
 255        MC_EMEM_ARB_CFG,
 256        MC_EMEM_ARB_OUTSTANDING_REQ,
 257        MC_EMEM_ARB_TIMING_RCD,
 258        MC_EMEM_ARB_TIMING_RP,
 259        MC_EMEM_ARB_TIMING_RC,
 260        MC_EMEM_ARB_TIMING_RAS,
 261        MC_EMEM_ARB_TIMING_FAW,
 262        MC_EMEM_ARB_TIMING_RRD,
 263        MC_EMEM_ARB_TIMING_RAP2PRE,
 264        MC_EMEM_ARB_TIMING_WAP2PRE,
 265        MC_EMEM_ARB_TIMING_R2R,
 266        MC_EMEM_ARB_TIMING_W2W,
 267        MC_EMEM_ARB_TIMING_R2W,
 268        MC_EMEM_ARB_TIMING_W2R,
 269        MC_EMEM_ARB_DA_TURNS,
 270        MC_EMEM_ARB_DA_COVERS,
 271        MC_EMEM_ARB_MISC0,
 272        MC_EMEM_ARB_MISC1,
 273        MC_EMEM_ARB_RING3_THROTTLE,
 274        MC_EMEM_ARB_OVERRIDE,
 275        MC_INTMASK,
 276};
 277
 278static int tegra30_mc_suspend(struct device *dev)
 279{
 280        int i;
 281        struct tegra30_mc *mc = dev_get_drvdata(dev);
 282
 283        for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++)
 284                mc->ctx[i] = mc_readl(mc, tegra30_mc_ctx[i]);
 285        return 0;
 286}
 287
 288static int tegra30_mc_resume(struct device *dev)
 289{
 290        int i;
 291        struct tegra30_mc *mc = dev_get_drvdata(dev);
 292
 293        for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++)
 294                mc_writel(mc, mc->ctx[i], tegra30_mc_ctx[i]);
 295
 296        mc_writel(mc, 1, MC_TIMING_CONTROL);
 297        /* Read-back to ensure that write reached */
 298        mc_readl(mc, MC_TIMING_CONTROL);
 299        return 0;
 300}
 301
 302static UNIVERSAL_DEV_PM_OPS(tegra30_mc_pm,
 303                            tegra30_mc_suspend,
 304                            tegra30_mc_resume, NULL);
 305
 306static const struct of_device_id tegra30_mc_of_match[] __devinitconst = {
 307        { .compatible = "nvidia,tegra30-mc", },
 308        {},
 309};
 310
 311static irqreturn_t tegra30_mc_isr(int irq, void *data)
 312{
 313        u32 stat, mask, bit;
 314        struct tegra30_mc *mc = data;
 315
 316        stat = mc_readl(mc, MC_INTSTATUS);
 317        mask = mc_readl(mc, MC_INTMASK);
 318        mask &= stat;
 319        if (!mask)
 320                return IRQ_NONE;
 321        while ((bit = ffs(mask)) != 0)
 322                tegra30_mc_decode(mc, bit - 1);
 323        mc_writel(mc, stat, MC_INTSTATUS);
 324        return IRQ_HANDLED;
 325}
 326
 327static int __devinit tegra30_mc_probe(struct platform_device *pdev)
 328{
 329        struct resource *irq;
 330        struct tegra30_mc *mc;
 331        size_t bytes;
 332        int err, i;
 333        u32 intmask;
 334
 335        bytes = sizeof(*mc) + sizeof(u32) * ARRAY_SIZE(tegra30_mc_ctx);
 336        mc = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
 337        if (!mc)
 338                return -ENOMEM;
 339        mc->dev = &pdev->dev;
 340
 341        for (i = 0; i < ARRAY_SIZE(mc->regs); i++) {
 342                struct resource *res;
 343
 344                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 345                if (!res)
 346                        return -ENODEV;
 347                mc->regs[i] = devm_request_and_ioremap(&pdev->dev, res);
 348                if (!mc->regs[i])
 349                        return -EBUSY;
 350        }
 351
 352        irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 353        if (!irq)
 354                return -ENODEV;
 355        err = devm_request_irq(&pdev->dev, irq->start, tegra30_mc_isr,
 356                               IRQF_SHARED, dev_name(&pdev->dev), mc);
 357        if (err)
 358                return -ENODEV;
 359
 360        platform_set_drvdata(pdev, mc);
 361
 362        intmask = MC_INT_INVALID_SMMU_PAGE |
 363                MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION;
 364        mc_writel(mc, intmask, MC_INTMASK);
 365        return 0;
 366}
 367
 368static struct platform_driver tegra30_mc_driver = {
 369        .probe = tegra30_mc_probe,
 370        .driver = {
 371                .name = DRV_NAME,
 372                .owner = THIS_MODULE,
 373                .of_match_table = tegra30_mc_of_match,
 374                .pm = &tegra30_mc_pm,
 375        },
 376};
 377module_platform_driver(tegra30_mc_driver);
 378
 379MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
 380MODULE_DESCRIPTION("Tegra30 MC driver");
 381MODULE_LICENSE("GPL v2");
 382MODULE_ALIAS("platform:" DRV_NAME);
 383
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