linux/drivers/ide/hpt366.c
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   1/*
   2 * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   3 * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   4 * Portions Copyright (C) 2003          Red Hat Inc
   5 * Portions Copyright (C) 2007          Bartlomiej Zolnierkiewicz
   6 * Portions Copyright (C) 2005-2009     MontaVista Software, Inc.
   7 *
   8 * Thanks to HighPoint Technologies for their assistance, and hardware.
   9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
  11 * development and support.
  12 *
  13 *
  14 * HighPoint has its own drivers (open source except for the RAID part)
  15 * available from http://www.highpoint-tech.com/USA_new/service_support.htm 
  16 * This may be useful to anyone wanting to work on this driver, however  do not
  17 * trust  them too much since the code tends to become less and less meaningful
  18 * as the time passes... :-/
  19 *
  20 * Note that final HPT370 support was done by force extraction of GPL.
  21 *
  22 * - add function for getting/setting power status of drive
  23 * - the HPT370's state machine can get confused. reset it before each dma 
  24 *   xfer to prevent that from happening.
  25 * - reset state engine whenever we get an error.
  26 * - check for busmaster state at end of dma. 
  27 * - use new highpoint timings.
  28 * - detect bus speed using highpoint register.
  29 * - use pll if we don't have a clock table. added a 66MHz table that's
  30 *   just 2x the 33MHz table.
  31 * - removed turnaround. NOTE: we never want to switch between pll and
  32 *   pci clocks as the chip can glitch in those cases. the highpoint
  33 *   approved workaround slows everything down too much to be useful. in
  34 *   addition, we would have to serialize access to each chip.
  35 *      Adrian Sun <a.sun@sun.com>
  36 *
  37 * add drive timings for 66MHz PCI bus,
  38 * fix ATA Cable signal detection, fix incorrect /proc info
  39 * add /proc display for per-drive PIO/DMA/UDMA mode and
  40 * per-channel ATA-33/66 Cable detect.
  41 *      Duncan Laurie <void@sun.com>
  42 *
  43 * fixup /proc output for multiple controllers
  44 *      Tim Hockin <thockin@sun.com>
  45 *
  46 * On hpt366: 
  47 * Reset the hpt366 on error, reset on dma
  48 * Fix disabling Fast Interrupt hpt366.
  49 *      Mike Waychison <crlf@sun.com>
  50 *
  51 * Added support for 372N clocking and clock switching. The 372N needs
  52 * different clocks on read/write. This requires overloading rw_disk and
  53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  54 * keeping me sane. 
  55 *              Alan Cox <alan@lxorguk.ukuu.org.uk>
  56 *
  57 * - fix the clock turnaround code: it was writing to the wrong ports when
  58 *   called for the secondary channel, caching the current clock mode per-
  59 *   channel caused the cached register value to get out of sync with the
  60 *   actual one, the channels weren't serialized, the turnaround shouldn't
  61 *   be done on 66 MHz PCI bus
  62 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
  63 *   does not allow for this speed anyway
  64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
  65 *   their primary channel is kind of virtual, it isn't tied to any pins)
  66 * - fix/remove bad/unused timing tables and use one set of tables for the whole
  67 *   HPT37x chip family; save space by introducing the separate transfer mode
  68 *   table in which the mode lookup is done
  69 * - use f_CNT value saved by  the HighPoint BIOS as reading it directly gives
  70 *   the wrong PCI frequency since DPLL has already been calibrated by BIOS;
  71 *   read it only from the function 0 of HPT374 chips
  72 * - fix the hotswap code:  it caused RESET- to glitch when tristating the bus,
  73 *   and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
  74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
  75 *   they tamper with its fields
  76 * - pass  to the init_setup handlers a copy of the ide_pci_device_t structure
  77 *   since they may tamper with its fields
  78 * - prefix the driver startup messages with the real chip name
  79 * - claim the extra 240 bytes of I/O space for all chips
  80 * - optimize the UltraDMA filtering and the drive list lookup code
  81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
  82 * - cache offset of the channel's misc. control registers (MCRs) being used
  83 *   throughout the driver
  84 * - only touch the relevant MCR when detecting the cable type on HPT374's
  85 *   function 1
  86 * - rename all the register related variables consistently
  87 * - move all the interrupt twiddling code from the speedproc handlers into
  88 *   init_hwif_hpt366(), also grouping all the DMA related code together there
  89 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
  90 *   separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
  91 *   when setting an UltraDMA mode
  92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
  93 *   the best possible one
  94 * - clean up DMA timeout handling for HPT370
  95 * - switch to using the enumeration type to differ between the numerous chip
  96 *   variants, matching PCI device/revision ID with the chip type early, at the
  97 *   init_setup stage
  98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
  99 *   stop duplicating it for each channel by storing the pointer in the pci_dev
 100 *   structure: first, at the init_setup stage, point it to a static "template"
 101 *   with only the chip type and its specific base DPLL frequency, the highest
 102 *   UltraDMA mode, and the chip settings table pointer filled,  then, at the
 103 *   init_chipset stage, allocate per-chip instance  and fill it with the rest
 104 *   of the necessary information
 105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
 106 *   switch  to calculating  PCI clock frequency based on the chip's base DPLL
 107 *   frequency
 108 * - switch to using the  DPLL clock and enable UltraATA/133 mode by default on
 109 *   anything  newer than HPT370/A (except HPT374 that is not capable of this
 110 *   mode according to the manual)
 111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
 112 *   also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
 113 *   unify HPT36x/37x timing setup code and the speedproc handlers by joining
 114 *   the register setting lists into the table indexed by the clock selected
 115 * - set the correct hwif->ultra_mask for each individual chip
 116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
 117 * - stop resetting HPT370's state machine before each DMA transfer as that has
 118 *   caused more harm than good
 119 *      Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
 120 */
 121
 122#include <linux/types.h>
 123#include <linux/module.h>
 124#include <linux/kernel.h>
 125#include <linux/delay.h>
 126#include <linux/blkdev.h>
 127#include <linux/interrupt.h>
 128#include <linux/pci.h>
 129#include <linux/init.h>
 130#include <linux/ide.h>
 131#include <linux/slab.h>
 132
 133#include <asm/uaccess.h>
 134#include <asm/io.h>
 135
 136#define DRV_NAME "hpt366"
 137
 138/* various tuning parameters */
 139#undef  HPT_RESET_STATE_ENGINE
 140#undef  HPT_DELAY_INTERRUPT
 141
 142static const char *bad_ata100_5[] = {
 143        "IBM-DTLA-307075",
 144        "IBM-DTLA-307060",
 145        "IBM-DTLA-307045",
 146        "IBM-DTLA-307030",
 147        "IBM-DTLA-307020",
 148        "IBM-DTLA-307015",
 149        "IBM-DTLA-305040",
 150        "IBM-DTLA-305030",
 151        "IBM-DTLA-305020",
 152        "IC35L010AVER07-0",
 153        "IC35L020AVER07-0",
 154        "IC35L030AVER07-0",
 155        "IC35L040AVER07-0",
 156        "IC35L060AVER07-0",
 157        "WDC AC310200R",
 158        NULL
 159};
 160
 161static const char *bad_ata66_4[] = {
 162        "IBM-DTLA-307075",
 163        "IBM-DTLA-307060",
 164        "IBM-DTLA-307045",
 165        "IBM-DTLA-307030",
 166        "IBM-DTLA-307020",
 167        "IBM-DTLA-307015",
 168        "IBM-DTLA-305040",
 169        "IBM-DTLA-305030",
 170        "IBM-DTLA-305020",
 171        "IC35L010AVER07-0",
 172        "IC35L020AVER07-0",
 173        "IC35L030AVER07-0",
 174        "IC35L040AVER07-0",
 175        "IC35L060AVER07-0",
 176        "WDC AC310200R",
 177        "MAXTOR STM3320620A",
 178        NULL
 179};
 180
 181static const char *bad_ata66_3[] = {
 182        "WDC AC310200R",
 183        NULL
 184};
 185
 186static const char *bad_ata33[] = {
 187        "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 188        "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 189        "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 190        "Maxtor 90510D4",
 191        "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 192        "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 193        "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 194        NULL
 195};
 196
 197static u8 xfer_speeds[] = {
 198        XFER_UDMA_6,
 199        XFER_UDMA_5,
 200        XFER_UDMA_4,
 201        XFER_UDMA_3,
 202        XFER_UDMA_2,
 203        XFER_UDMA_1,
 204        XFER_UDMA_0,
 205
 206        XFER_MW_DMA_2,
 207        XFER_MW_DMA_1,
 208        XFER_MW_DMA_0,
 209
 210        XFER_PIO_4,
 211        XFER_PIO_3,
 212        XFER_PIO_2,
 213        XFER_PIO_1,
 214        XFER_PIO_0
 215};
 216
 217/* Key for bus clock timings
 218 * 36x   37x
 219 * bits  bits
 220 * 0:3   0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 221 *              cycles = value + 1
 222 * 4:7   4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 223 *              cycles = value + 1
 224 * 8:11  9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 225 *              register access.
 226 * 12:15 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 227 *              register access.
 228 * 16:18 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
 229 * -     21     CLK frequency: 0=ATA clock, 1=dual ATA clock.
 230 * 19:21 22:24  pre_high_time. Time to initialize the 1st cycle for PIO and
 231 *              MW DMA xfer.
 232 * 22:24 25:27  cmd_pre_high_time. Time to initialize the 1st PIO cycle for
 233 *              task file register access.
 234 * 28    28     UDMA enable.
 235 * 29    29     DMA  enable.
 236 * 30    30     PIO MST enable. If set, the chip is in bus master mode during
 237 *              PIO xfer.
 238 * 31    31     FIFO enable.
 239 */
 240
 241static u32 forty_base_hpt36x[] = {
 242        /* XFER_UDMA_6 */       0x900fd943,
 243        /* XFER_UDMA_5 */       0x900fd943,
 244        /* XFER_UDMA_4 */       0x900fd943,
 245        /* XFER_UDMA_3 */       0x900ad943,
 246        /* XFER_UDMA_2 */       0x900bd943,
 247        /* XFER_UDMA_1 */       0x9008d943,
 248        /* XFER_UDMA_0 */       0x9008d943,
 249
 250        /* XFER_MW_DMA_2 */     0xa008d943,
 251        /* XFER_MW_DMA_1 */     0xa010d955,
 252        /* XFER_MW_DMA_0 */     0xa010d9fc,
 253
 254        /* XFER_PIO_4 */        0xc008d963,
 255        /* XFER_PIO_3 */        0xc010d974,
 256        /* XFER_PIO_2 */        0xc010d997,
 257        /* XFER_PIO_1 */        0xc010d9c7,
 258        /* XFER_PIO_0 */        0xc018d9d9
 259};
 260
 261static u32 thirty_three_base_hpt36x[] = {
 262        /* XFER_UDMA_6 */       0x90c9a731,
 263        /* XFER_UDMA_5 */       0x90c9a731,
 264        /* XFER_UDMA_4 */       0x90c9a731,
 265        /* XFER_UDMA_3 */       0x90cfa731,
 266        /* XFER_UDMA_2 */       0x90caa731,
 267        /* XFER_UDMA_1 */       0x90cba731,
 268        /* XFER_UDMA_0 */       0x90c8a731,
 269
 270        /* XFER_MW_DMA_2 */     0xa0c8a731,
 271        /* XFER_MW_DMA_1 */     0xa0c8a732,     /* 0xa0c8a733 */
 272        /* XFER_MW_DMA_0 */     0xa0c8a797,
 273
 274        /* XFER_PIO_4 */        0xc0c8a731,
 275        /* XFER_PIO_3 */        0xc0c8a742,
 276        /* XFER_PIO_2 */        0xc0d0a753,
 277        /* XFER_PIO_1 */        0xc0d0a7a3,     /* 0xc0d0a793 */
 278        /* XFER_PIO_0 */        0xc0d0a7aa      /* 0xc0d0a7a7 */
 279};
 280
 281static u32 twenty_five_base_hpt36x[] = {
 282        /* XFER_UDMA_6 */       0x90c98521,
 283        /* XFER_UDMA_5 */       0x90c98521,
 284        /* XFER_UDMA_4 */       0x90c98521,
 285        /* XFER_UDMA_3 */       0x90cf8521,
 286        /* XFER_UDMA_2 */       0x90cf8521,
 287        /* XFER_UDMA_1 */       0x90cb8521,
 288        /* XFER_UDMA_0 */       0x90cb8521,
 289
 290        /* XFER_MW_DMA_2 */     0xa0ca8521,
 291        /* XFER_MW_DMA_1 */     0xa0ca8532,
 292        /* XFER_MW_DMA_0 */     0xa0ca8575,
 293
 294        /* XFER_PIO_4 */        0xc0ca8521,
 295        /* XFER_PIO_3 */        0xc0ca8532,
 296        /* XFER_PIO_2 */        0xc0ca8542,
 297        /* XFER_PIO_1 */        0xc0d08572,
 298        /* XFER_PIO_0 */        0xc0d08585
 299};
 300
 301/*
 302 * The following are the new timing tables with PIO mode data/taskfile transfer
 303 * overclocking fixed...
 304 */
 305
 306/* This table is taken from the HPT370 data manual rev. 1.02 */
 307static u32 thirty_three_base_hpt37x[] = {
 308        /* XFER_UDMA_6 */       0x16455031,     /* 0x16655031 ?? */
 309        /* XFER_UDMA_5 */       0x16455031,
 310        /* XFER_UDMA_4 */       0x16455031,
 311        /* XFER_UDMA_3 */       0x166d5031,
 312        /* XFER_UDMA_2 */       0x16495031,
 313        /* XFER_UDMA_1 */       0x164d5033,
 314        /* XFER_UDMA_0 */       0x16515097,
 315
 316        /* XFER_MW_DMA_2 */     0x26515031,
 317        /* XFER_MW_DMA_1 */     0x26515033,
 318        /* XFER_MW_DMA_0 */     0x26515097,
 319
 320        /* XFER_PIO_4 */        0x06515021,
 321        /* XFER_PIO_3 */        0x06515022,
 322        /* XFER_PIO_2 */        0x06515033,
 323        /* XFER_PIO_1 */        0x06915065,
 324        /* XFER_PIO_0 */        0x06d1508a
 325};
 326
 327static u32 fifty_base_hpt37x[] = {
 328        /* XFER_UDMA_6 */       0x1a861842,
 329        /* XFER_UDMA_5 */       0x1a861842,
 330        /* XFER_UDMA_4 */       0x1aae1842,
 331        /* XFER_UDMA_3 */       0x1a8e1842,
 332        /* XFER_UDMA_2 */       0x1a0e1842,
 333        /* XFER_UDMA_1 */       0x1a161854,
 334        /* XFER_UDMA_0 */       0x1a1a18ea,
 335
 336        /* XFER_MW_DMA_2 */     0x2a821842,
 337        /* XFER_MW_DMA_1 */     0x2a821854,
 338        /* XFER_MW_DMA_0 */     0x2a8218ea,
 339
 340        /* XFER_PIO_4 */        0x0a821842,
 341        /* XFER_PIO_3 */        0x0a821843,
 342        /* XFER_PIO_2 */        0x0a821855,
 343        /* XFER_PIO_1 */        0x0ac218a8,
 344        /* XFER_PIO_0 */        0x0b02190c
 345};
 346
 347static u32 sixty_six_base_hpt37x[] = {
 348        /* XFER_UDMA_6 */       0x1c86fe62,
 349        /* XFER_UDMA_5 */       0x1caefe62,     /* 0x1c8afe62 */
 350        /* XFER_UDMA_4 */       0x1c8afe62,
 351        /* XFER_UDMA_3 */       0x1c8efe62,
 352        /* XFER_UDMA_2 */       0x1c92fe62,
 353        /* XFER_UDMA_1 */       0x1c9afe62,
 354        /* XFER_UDMA_0 */       0x1c82fe62,
 355
 356        /* XFER_MW_DMA_2 */     0x2c82fe62,
 357        /* XFER_MW_DMA_1 */     0x2c82fe66,
 358        /* XFER_MW_DMA_0 */     0x2c82ff2e,
 359
 360        /* XFER_PIO_4 */        0x0c82fe62,
 361        /* XFER_PIO_3 */        0x0c82fe84,
 362        /* XFER_PIO_2 */        0x0c82fea6,
 363        /* XFER_PIO_1 */        0x0d02ff26,
 364        /* XFER_PIO_0 */        0x0d42ff7f
 365};
 366
 367#define HPT371_ALLOW_ATA133_6           1
 368#define HPT302_ALLOW_ATA133_6           1
 369#define HPT372_ALLOW_ATA133_6           1
 370#define HPT370_ALLOW_ATA100_5           0
 371#define HPT366_ALLOW_ATA66_4            1
 372#define HPT366_ALLOW_ATA66_3            1
 373
 374/* Supported ATA clock frequencies */
 375enum ata_clock {
 376        ATA_CLOCK_25MHZ,
 377        ATA_CLOCK_33MHZ,
 378        ATA_CLOCK_40MHZ,
 379        ATA_CLOCK_50MHZ,
 380        ATA_CLOCK_66MHZ,
 381        NUM_ATA_CLOCKS
 382};
 383
 384struct hpt_timings {
 385        u32 pio_mask;
 386        u32 dma_mask;
 387        u32 ultra_mask;
 388        u32 *clock_table[NUM_ATA_CLOCKS];
 389};
 390
 391/*
 392 *      Hold all the HighPoint chip information in one place.
 393 */
 394
 395struct hpt_info {
 396        char *chip_name;        /* Chip name */
 397        u8 chip_type;           /* Chip type */
 398        u8 udma_mask;           /* Allowed UltraDMA modes mask. */
 399        u8 dpll_clk;            /* DPLL clock in MHz */
 400        u8 pci_clk;             /* PCI  clock in MHz */
 401        struct hpt_timings *timings; /* Chipset timing data */
 402        u8 clock;               /* ATA clock selected */
 403};
 404
 405/* Supported HighPoint chips */
 406enum {
 407        HPT36x,
 408        HPT370,
 409        HPT370A,
 410        HPT374,
 411        HPT372,
 412        HPT372A,
 413        HPT302,
 414        HPT371,
 415        HPT372N,
 416        HPT302N,
 417        HPT371N
 418};
 419
 420static struct hpt_timings hpt36x_timings = {
 421        .pio_mask       = 0xc1f8ffff,
 422        .dma_mask       = 0x303800ff,
 423        .ultra_mask     = 0x30070000,
 424        .clock_table    = {
 425                [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
 426                [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
 427                [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
 428                [ATA_CLOCK_50MHZ] = NULL,
 429                [ATA_CLOCK_66MHZ] = NULL
 430        }
 431};
 432
 433static struct hpt_timings hpt37x_timings = {
 434        .pio_mask       = 0xcfc3ffff,
 435        .dma_mask       = 0x31c001ff,
 436        .ultra_mask     = 0x303c0000,
 437        .clock_table    = {
 438                [ATA_CLOCK_25MHZ] = NULL,
 439                [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
 440                [ATA_CLOCK_40MHZ] = NULL,
 441                [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
 442                [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
 443        }
 444};
 445
 446static const struct hpt_info hpt36x __devinitdata = {
 447        .chip_name      = "HPT36x",
 448        .chip_type      = HPT36x,
 449        .udma_mask      = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
 450        .dpll_clk       = 0,    /* no DPLL */
 451        .timings        = &hpt36x_timings
 452};
 453
 454static const struct hpt_info hpt370 __devinitdata = {
 455        .chip_name      = "HPT370",
 456        .chip_type      = HPT370,
 457        .udma_mask      = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
 458        .dpll_clk       = 48,
 459        .timings        = &hpt37x_timings
 460};
 461
 462static const struct hpt_info hpt370a __devinitdata = {
 463        .chip_name      = "HPT370A",
 464        .chip_type      = HPT370A,
 465        .udma_mask      = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
 466        .dpll_clk       = 48,
 467        .timings        = &hpt37x_timings
 468};
 469
 470static const struct hpt_info hpt374 __devinitdata = {
 471        .chip_name      = "HPT374",
 472        .chip_type      = HPT374,
 473        .udma_mask      = ATA_UDMA5,
 474        .dpll_clk       = 48,
 475        .timings        = &hpt37x_timings
 476};
 477
 478static const struct hpt_info hpt372 __devinitdata = {
 479        .chip_name      = "HPT372",
 480        .chip_type      = HPT372,
 481        .udma_mask      = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 482        .dpll_clk       = 55,
 483        .timings        = &hpt37x_timings
 484};
 485
 486static const struct hpt_info hpt372a __devinitdata = {
 487        .chip_name      = "HPT372A",
 488        .chip_type      = HPT372A,
 489        .udma_mask      = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 490        .dpll_clk       = 66,
 491        .timings        = &hpt37x_timings
 492};
 493
 494static const struct hpt_info hpt302 __devinitdata = {
 495        .chip_name      = "HPT302",
 496        .chip_type      = HPT302,
 497        .udma_mask      = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 498        .dpll_clk       = 66,
 499        .timings        = &hpt37x_timings
 500};
 501
 502static const struct hpt_info hpt371 __devinitdata = {
 503        .chip_name      = "HPT371",
 504        .chip_type      = HPT371,
 505        .udma_mask      = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 506        .dpll_clk       = 66,
 507        .timings        = &hpt37x_timings
 508};
 509
 510static const struct hpt_info hpt372n __devinitdata = {
 511        .chip_name      = "HPT372N",
 512        .chip_type      = HPT372N,
 513        .udma_mask      = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 514        .dpll_clk       = 77,
 515        .timings        = &hpt37x_timings
 516};
 517
 518static const struct hpt_info hpt302n __devinitdata = {
 519        .chip_name      = "HPT302N",
 520        .chip_type      = HPT302N,
 521        .udma_mask      = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 522        .dpll_clk       = 77,
 523        .timings        = &hpt37x_timings
 524};
 525
 526static const struct hpt_info hpt371n __devinitdata = {
 527        .chip_name      = "HPT371N",
 528        .chip_type      = HPT371N,
 529        .udma_mask      = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 530        .dpll_clk       = 77,
 531        .timings        = &hpt37x_timings
 532};
 533
 534static int check_in_drive_list(ide_drive_t *drive, const char **list)
 535{
 536        char *m = (char *)&drive->id[ATA_ID_PROD];
 537
 538        while (*list)
 539                if (!strcmp(*list++, m))
 540                        return 1;
 541        return 0;
 542}
 543
 544static struct hpt_info *hpt3xx_get_info(struct device *dev)
 545{
 546        struct ide_host *host   = dev_get_drvdata(dev);
 547        struct hpt_info *info   = (struct hpt_info *)host->host_priv;
 548
 549        return dev == host->dev[1] ? info + 1 : info;
 550}
 551
 552/*
 553 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
 554 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
 555 */
 556
 557static u8 hpt3xx_udma_filter(ide_drive_t *drive)
 558{
 559        ide_hwif_t *hwif        = drive->hwif;
 560        struct hpt_info *info   = hpt3xx_get_info(hwif->dev);
 561        u8 mask                 = hwif->ultra_mask;
 562
 563        switch (info->chip_type) {
 564        case HPT36x:
 565                if (!HPT366_ALLOW_ATA66_4 ||
 566                    check_in_drive_list(drive, bad_ata66_4))
 567                        mask = ATA_UDMA3;
 568
 569                if (!HPT366_ALLOW_ATA66_3 ||
 570                    check_in_drive_list(drive, bad_ata66_3))
 571                        mask = ATA_UDMA2;
 572                break;
 573        case HPT370:
 574                if (!HPT370_ALLOW_ATA100_5 ||
 575                    check_in_drive_list(drive, bad_ata100_5))
 576                        mask = ATA_UDMA4;
 577                break;
 578        case HPT370A:
 579                if (!HPT370_ALLOW_ATA100_5 ||
 580                    check_in_drive_list(drive, bad_ata100_5))
 581                        return ATA_UDMA4;
 582        case HPT372 :
 583        case HPT372A:
 584        case HPT372N:
 585        case HPT374 :
 586                if (ata_id_is_sata(drive->id))
 587                        mask &= ~0x0e;
 588                /* Fall thru */
 589        default:
 590                return mask;
 591        }
 592
 593        return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
 594}
 595
 596static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
 597{
 598        ide_hwif_t *hwif        = drive->hwif;
 599        struct hpt_info *info   = hpt3xx_get_info(hwif->dev);
 600
 601        switch (info->chip_type) {
 602        case HPT372 :
 603        case HPT372A:
 604        case HPT372N:
 605        case HPT374 :
 606                if (ata_id_is_sata(drive->id))
 607                        return 0x00;
 608                /* Fall thru */
 609        default:
 610                return 0x07;
 611        }
 612}
 613
 614static u32 get_speed_setting(u8 speed, struct hpt_info *info)
 615{
 616        int i;
 617
 618        /*
 619         * Lookup the transfer mode table to get the index into
 620         * the timing table.
 621         *
 622         * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
 623         */
 624        for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
 625                if (xfer_speeds[i] == speed)
 626                        break;
 627
 628        return info->timings->clock_table[info->clock][i];
 629}
 630
 631static void hpt3xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 632{
 633        struct pci_dev *dev     = to_pci_dev(hwif->dev);
 634        struct hpt_info *info   = hpt3xx_get_info(hwif->dev);
 635        struct hpt_timings *t   = info->timings;
 636        u8  itr_addr            = 0x40 + (drive->dn * 4);
 637        u32 old_itr             = 0;
 638        const u8 speed          = drive->dma_mode;
 639        u32 new_itr             = get_speed_setting(speed, info);
 640        u32 itr_mask            = speed < XFER_MW_DMA_0 ? t->pio_mask :
 641                                 (speed < XFER_UDMA_0   ? t->dma_mask :
 642                                                          t->ultra_mask);
 643
 644        pci_read_config_dword(dev, itr_addr, &old_itr);
 645        new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
 646        /*
 647         * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
 648         * to avoid problems handling I/O errors later
 649         */
 650        new_itr &= ~0xc0000000;
 651
 652        pci_write_config_dword(dev, itr_addr, new_itr);
 653}
 654
 655static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 656{
 657        drive->dma_mode = drive->pio_mode;
 658        hpt3xx_set_mode(hwif, drive);
 659}
 660
 661static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
 662{
 663        ide_hwif_t *hwif        = drive->hwif;
 664        struct pci_dev  *dev    = to_pci_dev(hwif->dev);
 665        struct hpt_info *info   = hpt3xx_get_info(hwif->dev);
 666
 667        if ((drive->dev_flags & IDE_DFLAG_NIEN_QUIRK) == 0)
 668                return;
 669
 670        if (info->chip_type >= HPT370) {
 671                u8 scr1 = 0;
 672
 673                pci_read_config_byte(dev, 0x5a, &scr1);
 674                if (((scr1 & 0x10) >> 4) != mask) {
 675                        if (mask)
 676                                scr1 |=  0x10;
 677                        else
 678                                scr1 &= ~0x10;
 679                        pci_write_config_byte(dev, 0x5a, scr1);
 680                }
 681        } else if (mask)
 682                disable_irq(hwif->irq);
 683        else
 684                enable_irq(hwif->irq);
 685}
 686
 687/*
 688 * This is specific to the HPT366 UDMA chipset
 689 * by HighPoint|Triones Technologies, Inc.
 690 */
 691static void hpt366_dma_lost_irq(ide_drive_t *drive)
 692{
 693        struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
 694        u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
 695
 696        pci_read_config_byte(dev, 0x50, &mcr1);
 697        pci_read_config_byte(dev, 0x52, &mcr3);
 698        pci_read_config_byte(dev, 0x5a, &scr1);
 699        printk("%s: (%s)  mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
 700                drive->name, __func__, mcr1, mcr3, scr1);
 701        if (scr1 & 0x10)
 702                pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
 703        ide_dma_lost_irq(drive);
 704}
 705
 706static void hpt370_clear_engine(ide_drive_t *drive)
 707{
 708        ide_hwif_t *hwif = drive->hwif;
 709        struct pci_dev *dev = to_pci_dev(hwif->dev);
 710
 711        pci_write_config_byte(dev, hwif->select_data, 0x37);
 712        udelay(10);
 713}
 714
 715static void hpt370_irq_timeout(ide_drive_t *drive)
 716{
 717        ide_hwif_t *hwif        = drive->hwif;
 718        struct pci_dev *dev     = to_pci_dev(hwif->dev);
 719        u16 bfifo               = 0;
 720        u8  dma_cmd;
 721
 722        pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
 723        printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
 724
 725        /* get DMA command mode */
 726        dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
 727        /* stop DMA */
 728        outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
 729        hpt370_clear_engine(drive);
 730}
 731
 732static void hpt370_dma_start(ide_drive_t *drive)
 733{
 734#ifdef HPT_RESET_STATE_ENGINE
 735        hpt370_clear_engine(drive);
 736#endif
 737        ide_dma_start(drive);
 738}
 739
 740static int hpt370_dma_end(ide_drive_t *drive)
 741{
 742        ide_hwif_t *hwif        = drive->hwif;
 743        u8  dma_stat            = inb(hwif->dma_base + ATA_DMA_STATUS);
 744
 745        if (dma_stat & ATA_DMA_ACTIVE) {
 746                /* wait a little */
 747                udelay(20);
 748                dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
 749                if (dma_stat & ATA_DMA_ACTIVE)
 750                        hpt370_irq_timeout(drive);
 751        }
 752        return ide_dma_end(drive);
 753}
 754
 755/* returns 1 if DMA IRQ issued, 0 otherwise */
 756static int hpt374_dma_test_irq(ide_drive_t *drive)
 757{
 758        ide_hwif_t *hwif        = drive->hwif;
 759        struct pci_dev *dev     = to_pci_dev(hwif->dev);
 760        u16 bfifo               = 0;
 761        u8  dma_stat;
 762
 763        pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
 764        if (bfifo & 0x1FF) {
 765//              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 766                return 0;
 767        }
 768
 769        dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
 770        /* return 1 if INTR asserted */
 771        if (dma_stat & ATA_DMA_INTR)
 772                return 1;
 773
 774        return 0;
 775}
 776
 777static int hpt374_dma_end(ide_drive_t *drive)
 778{
 779        ide_hwif_t *hwif        = drive->hwif;
 780        struct pci_dev *dev     = to_pci_dev(hwif->dev);
 781        u8 mcr  = 0, mcr_addr   = hwif->select_data;
 782        u8 bwsr = 0, mask       = hwif->channel ? 0x02 : 0x01;
 783
 784        pci_read_config_byte(dev, 0x6a, &bwsr);
 785        pci_read_config_byte(dev, mcr_addr, &mcr);
 786        if (bwsr & mask)
 787                pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
 788        return ide_dma_end(drive);
 789}
 790
 791/**
 792 *      hpt3xxn_set_clock       -       perform clock switching dance
 793 *      @hwif: hwif to switch
 794 *      @mode: clocking mode (0x21 for write, 0x23 otherwise)
 795 *
 796 *      Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
 797 */
 798
 799static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
 800{
 801        unsigned long base = hwif->extra_base;
 802        u8 scr2 = inb(base + 0x6b);
 803
 804        if ((scr2 & 0x7f) == mode)
 805                return;
 806
 807        /* Tristate the bus */
 808        outb(0x80, base + 0x63);
 809        outb(0x80, base + 0x67);
 810
 811        /* Switch clock and reset channels */
 812        outb(mode, base + 0x6b);
 813        outb(0xc0, base + 0x69);
 814
 815        /*
 816         * Reset the state machines.
 817         * NOTE: avoid accidentally enabling the disabled channels.
 818         */
 819        outb(inb(base + 0x60) | 0x32, base + 0x60);
 820        outb(inb(base + 0x64) | 0x32, base + 0x64);
 821
 822        /* Complete reset */
 823        outb(0x00, base + 0x69);
 824
 825        /* Reconnect channels to bus */
 826        outb(0x00, base + 0x63);
 827        outb(0x00, base + 0x67);
 828}
 829
 830/**
 831 *      hpt3xxn_rw_disk         -       prepare for I/O
 832 *      @drive: drive for command
 833 *      @rq: block request structure
 834 *
 835 *      This is called when a disk I/O is issued to HPT3xxN.
 836 *      We need it because of the clock switching.
 837 */
 838
 839static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
 840{
 841        hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x21 : 0x23);
 842}
 843
 844/**
 845 *      hpt37x_calibrate_dpll   -       calibrate the DPLL
 846 *      @dev: PCI device
 847 *
 848 *      Perform a calibration cycle on the DPLL.
 849 *      Returns 1 if this succeeds
 850 */
 851static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
 852{
 853        u32 dpll = (f_high << 16) | f_low | 0x100;
 854        u8  scr2;
 855        int i;
 856
 857        pci_write_config_dword(dev, 0x5c, dpll);
 858
 859        /* Wait for oscillator ready */
 860        for(i = 0; i < 0x5000; ++i) {
 861                udelay(50);
 862                pci_read_config_byte(dev, 0x5b, &scr2);
 863                if (scr2 & 0x80)
 864                        break;
 865        }
 866        /* See if it stays ready (we'll just bail out if it's not yet) */
 867        for(i = 0; i < 0x1000; ++i) {
 868                pci_read_config_byte(dev, 0x5b, &scr2);
 869                /* DPLL destabilized? */
 870                if(!(scr2 & 0x80))
 871                        return 0;
 872        }
 873        /* Turn off tuning, we have the DPLL set */
 874        pci_read_config_dword (dev, 0x5c, &dpll);
 875        pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
 876        return 1;
 877}
 878
 879static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
 880{
 881        struct ide_host *host   = pci_get_drvdata(dev);
 882        struct hpt_info *info   = host->host_priv + (&dev->dev == host->dev[1]);
 883        u8  chip_type           = info->chip_type;
 884        u8  new_mcr, old_mcr    = 0;
 885
 886        /*
 887         * Disable the "fast interrupt" prediction.  Don't hold off
 888         * on interrupts. (== 0x01 despite what the docs say)
 889         */
 890        pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
 891
 892        if (chip_type >= HPT374)
 893                new_mcr = old_mcr & ~0x07;
 894        else if (chip_type >= HPT370) {
 895                new_mcr = old_mcr;
 896                new_mcr &= ~0x02;
 897#ifdef HPT_DELAY_INTERRUPT
 898                new_mcr &= ~0x01;
 899#else
 900                new_mcr |=  0x01;
 901#endif
 902        } else                                  /* HPT366 and HPT368  */
 903                new_mcr = old_mcr & ~0x80;
 904
 905        if (new_mcr != old_mcr)
 906                pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
 907}
 908
 909static int init_chipset_hpt366(struct pci_dev *dev)
 910{
 911        unsigned long io_base   = pci_resource_start(dev, 4);
 912        struct hpt_info *info   = hpt3xx_get_info(&dev->dev);
 913        const char *name        = DRV_NAME;
 914        u8 pci_clk,  dpll_clk   = 0;    /* PCI and DPLL clock in MHz */
 915        u8 chip_type;
 916        enum ata_clock  clock;
 917
 918        chip_type = info->chip_type;
 919
 920        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 921        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 922        pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 923        pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 924
 925        /*
 926         * First, try to estimate the PCI clock frequency...
 927         */
 928        if (chip_type >= HPT370) {
 929                u8  scr1  = 0;
 930                u16 f_cnt = 0;
 931                u32 temp  = 0;
 932
 933                /* Interrupt force enable. */
 934                pci_read_config_byte(dev, 0x5a, &scr1);
 935                if (scr1 & 0x10)
 936                        pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
 937
 938                /*
 939                 * HighPoint does this for HPT372A.
 940                 * NOTE: This register is only writeable via I/O space.
 941                 */
 942                if (chip_type == HPT372A)
 943                        outb(0x0e, io_base + 0x9c);
 944
 945                /*
 946                 * Default to PCI clock. Make sure MA15/16 are set to output
 947                 * to prevent drives having problems with 40-pin cables.
 948                 */
 949                pci_write_config_byte(dev, 0x5b, 0x23);
 950
 951                /*
 952                 * We'll have to read f_CNT value in order to determine
 953                 * the PCI clock frequency according to the following ratio:
 954                 *
 955                 * f_CNT = Fpci * 192 / Fdpll
 956                 *
 957                 * First try reading the register in which the HighPoint BIOS
 958                 * saves f_CNT value before  reprogramming the DPLL from its
 959                 * default setting (which differs for the various chips).
 960                 *
 961                 * NOTE: This register is only accessible via I/O space;
 962                 * HPT374 BIOS only saves it for the function 0, so we have to
 963                 * always read it from there -- no need to check the result of
 964                 * pci_get_slot() for the function 0 as the whole device has
 965                 * been already "pinned" (via function 1) in init_setup_hpt374()
 966                 */
 967                if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
 968                        struct pci_dev  *dev1 = pci_get_slot(dev->bus,
 969                                                             dev->devfn - 1);
 970                        unsigned long io_base = pci_resource_start(dev1, 4);
 971
 972                        temp =  inl(io_base + 0x90);
 973                        pci_dev_put(dev1);
 974                } else
 975                        temp =  inl(io_base + 0x90);
 976
 977                /*
 978                 * In case the signature check fails, we'll have to
 979                 * resort to reading the f_CNT register itself in hopes
 980                 * that nobody has touched the DPLL yet...
 981                 */
 982                if ((temp & 0xFFFFF000) != 0xABCDE000) {
 983                        int i;
 984
 985                        printk(KERN_WARNING "%s %s: no clock data saved by "
 986                                "BIOS\n", name, pci_name(dev));
 987
 988                        /* Calculate the average value of f_CNT. */
 989                        for (temp = i = 0; i < 128; i++) {
 990                                pci_read_config_word(dev, 0x78, &f_cnt);
 991                                temp += f_cnt & 0x1ff;
 992                                mdelay(1);
 993                        }
 994                        f_cnt = temp / 128;
 995                } else
 996                        f_cnt = temp & 0x1ff;
 997
 998                dpll_clk = info->dpll_clk;
 999                pci_clk  = (f_cnt * dpll_clk) / 192;
1000
1001                /* Clamp PCI clock to bands. */
1002                if (pci_clk < 40)
1003                        pci_clk = 33;
1004                else if(pci_clk < 45)
1005                        pci_clk = 40;
1006                else if(pci_clk < 55)
1007                        pci_clk = 50;
1008                else
1009                        pci_clk = 66;
1010
1011                printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1012                        "assuming %d MHz PCI\n", name, pci_name(dev),
1013                        dpll_clk, f_cnt, pci_clk);
1014        } else {
1015                u32 itr1 = 0;
1016
1017                pci_read_config_dword(dev, 0x40, &itr1);
1018
1019                /* Detect PCI clock by looking at cmd_high_time. */
1020                switch((itr1 >> 8) & 0x07) {
1021                        case 0x09:
1022                                pci_clk = 40;
1023                                break;
1024                        case 0x05:
1025                                pci_clk = 25;
1026                                break;
1027                        case 0x07:
1028                        default:
1029                                pci_clk = 33;
1030                                break;
1031                }
1032        }
1033
1034        /* Let's assume we'll use PCI clock for the ATA clock... */
1035        switch (pci_clk) {
1036                case 25:
1037                        clock = ATA_CLOCK_25MHZ;
1038                        break;
1039                case 33:
1040                default:
1041                        clock = ATA_CLOCK_33MHZ;
1042                        break;
1043                case 40:
1044                        clock = ATA_CLOCK_40MHZ;
1045                        break;
1046                case 50:
1047                        clock = ATA_CLOCK_50MHZ;
1048                        break;
1049                case 66:
1050                        clock = ATA_CLOCK_66MHZ;
1051                        break;
1052        }
1053
1054        /*
1055         * Only try the DPLL if we don't have a table for the PCI clock that
1056         * we are running at for HPT370/A, always use it  for anything newer...
1057         *
1058         * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1059         * We also  don't like using  the DPLL because this causes glitches
1060         * on PRST-/SRST- when the state engine gets reset...
1061         */
1062        if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
1063                u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1064                int adjust;
1065
1066                 /*
1067                  * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1068                  * supported/enabled, use 50 MHz DPLL clock otherwise...
1069                  */
1070                if (info->udma_mask == ATA_UDMA6) {
1071                        dpll_clk = 66;
1072                        clock = ATA_CLOCK_66MHZ;
1073                } else if (dpll_clk) {  /* HPT36x chips don't have DPLL */
1074                        dpll_clk = 50;
1075                        clock = ATA_CLOCK_50MHZ;
1076                }
1077
1078                if (info->timings->clock_table[clock] == NULL) {
1079                        printk(KERN_ERR "%s %s: unknown bus timing!\n",
1080                                name, pci_name(dev));
1081                        return -EIO;
1082                }
1083
1084                /* Select the DPLL clock. */
1085                pci_write_config_byte(dev, 0x5b, 0x21);
1086
1087                /*
1088                 * Adjust the DPLL based upon PCI clock, enable it,
1089                 * and wait for stabilization...
1090                 */
1091                f_low = (pci_clk * 48) / dpll_clk;
1092
1093                for (adjust = 0; adjust < 8; adjust++) {
1094                        if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1095                                break;
1096
1097                        /*
1098                         * See if it'll settle at a fractionally different clock
1099                         */
1100                        if (adjust & 1)
1101                                f_low -= adjust >> 1;
1102                        else
1103                                f_low += adjust >> 1;
1104                }
1105                if (adjust == 8) {
1106                        printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
1107                                name, pci_name(dev));
1108                        return -EIO;
1109                }
1110
1111                printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1112                        name, pci_name(dev), dpll_clk);
1113        } else {
1114                /* Mark the fact that we're not using the DPLL. */
1115                dpll_clk = 0;
1116
1117                printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1118                        name, pci_name(dev), pci_clk);
1119        }
1120
1121        /* Store the clock frequencies. */
1122        info->dpll_clk  = dpll_clk;
1123        info->pci_clk   = pci_clk;
1124        info->clock     = clock;
1125
1126        if (chip_type >= HPT370) {
1127                u8  mcr1, mcr4;
1128
1129                /*
1130                 * Reset the state engines.
1131                 * NOTE: Avoid accidentally enabling the disabled channels.
1132                 */
1133                pci_read_config_byte (dev, 0x50, &mcr1);
1134                pci_read_config_byte (dev, 0x54, &mcr4);
1135                pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1136                pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1137                udelay(100);
1138        }
1139
1140        /*
1141         * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1142         * the MISC. register to stretch the UltraDMA Tss timing.
1143         * NOTE: This register is only writeable via I/O space.
1144         */
1145        if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1146                outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1147
1148        hpt3xx_disable_fast_irq(dev, 0x50);
1149        hpt3xx_disable_fast_irq(dev, 0x54);
1150
1151        return 0;
1152}
1153
1154static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
1155{
1156        struct pci_dev  *dev    = to_pci_dev(hwif->dev);
1157        struct hpt_info *info   = hpt3xx_get_info(hwif->dev);
1158        u8 chip_type            = info->chip_type;
1159        u8 scr1 = 0, ata66      = hwif->channel ? 0x01 : 0x02;
1160
1161        /*
1162         * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1163         * address lines to access an external EEPROM.  To read valid
1164         * cable detect state the pins must be enabled as inputs.
1165         */
1166        if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1167                /*
1168                 * HPT374 PCI function 1
1169                 * - set bit 15 of reg 0x52 to enable TCBLID as input
1170                 * - set bit 15 of reg 0x56 to enable FCBLID as input
1171                 */
1172                u8  mcr_addr = hwif->select_data + 2;
1173                u16 mcr;
1174
1175                pci_read_config_word(dev, mcr_addr, &mcr);
1176                pci_write_config_word(dev, mcr_addr, mcr | 0x8000);
1177                /* Debounce, then read cable ID register */
1178                udelay(10);
1179                pci_read_config_byte(dev, 0x5a, &scr1);
1180                pci_write_config_word(dev, mcr_addr, mcr);
1181        } else if (chip_type >= HPT370) {
1182                /*
1183                 * HPT370/372 and 374 pcifn 0
1184                 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1185                 */
1186                u8 scr2 = 0;
1187
1188                pci_read_config_byte(dev, 0x5b, &scr2);
1189                pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1190                /* Debounce, then read cable ID register */
1191                udelay(10);
1192                pci_read_config_byte(dev, 0x5a, &scr1);
1193                pci_write_config_byte(dev, 0x5b, scr2);
1194        } else
1195                pci_read_config_byte(dev, 0x5a, &scr1);
1196
1197        return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1198}
1199
1200static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1201{
1202        struct hpt_info *info   = hpt3xx_get_info(hwif->dev);
1203        u8  chip_type           = info->chip_type;
1204
1205        /* Cache the channel's MISC. control registers' offset */
1206        hwif->select_data       = hwif->channel ? 0x54 : 0x50;
1207
1208        /*
1209         * HPT3xxN chips have some complications:
1210         *
1211         * - on 33 MHz PCI we must clock switch
1212         * - on 66 MHz PCI we must NOT use the PCI clock
1213         */
1214        if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1215                /*
1216                 * Clock is shared between the channels,
1217                 * so we'll have to serialize them... :-(
1218                 */
1219                hwif->host->host_flags |= IDE_HFLAG_SERIALIZE;
1220                hwif->rw_disk = &hpt3xxn_rw_disk;
1221        }
1222}
1223
1224static int __devinit init_dma_hpt366(ide_hwif_t *hwif,
1225                                     const struct ide_port_info *d)
1226{
1227        struct pci_dev *dev = to_pci_dev(hwif->dev);
1228        unsigned long flags, base = ide_pci_dma_base(hwif, d);
1229        u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
1230
1231        if (base == 0)
1232                return -1;
1233
1234        hwif->dma_base = base;
1235
1236        if (ide_pci_check_simplex(hwif, d) < 0)
1237                return -1;
1238
1239        if (ide_pci_set_master(dev, d->name) < 0)
1240                return -1;
1241
1242        dma_old = inb(base + 2);
1243
1244        local_irq_save(flags);
1245
1246        dma_new = dma_old;
1247        pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1248        pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47,  &slavedma);
1249
1250        if (masterdma & 0x30)   dma_new |= 0x20;
1251        if ( slavedma & 0x30)   dma_new |= 0x40;
1252        if (dma_new != dma_old)
1253                outb(dma_new, base + 2);
1254
1255        local_irq_restore(flags);
1256
1257        printk(KERN_INFO "    %s: BM-DMA at 0x%04lx-0x%04lx\n",
1258                         hwif->name, base, base + 7);
1259
1260        hwif->extra_base = base + (hwif->channel ? 8 : 16);
1261
1262        if (ide_allocate_dma_engine(hwif))
1263                return -1;
1264
1265        return 0;
1266}
1267
1268static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
1269{
1270        if (dev2->irq != dev->irq) {
1271                /* FIXME: we need a core pci_set_interrupt() */
1272                dev2->irq = dev->irq;
1273                printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
1274                        "fixed\n", pci_name(dev2));
1275        }
1276}
1277
1278static void __devinit hpt371_init(struct pci_dev *dev)
1279{
1280        u8 mcr1 = 0;
1281
1282        /*
1283         * HPT371 chips physically have only one channel, the secondary one,
1284         * but the primary channel registers do exist!  Go figure...
1285         * So,  we manually disable the non-existing channel here
1286         * (if the BIOS hasn't done this already).
1287         */
1288        pci_read_config_byte(dev, 0x50, &mcr1);
1289        if (mcr1 & 0x04)
1290                pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1291}
1292
1293static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
1294{
1295        u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1296
1297        /*
1298         * Now we'll have to force both channels enabled if
1299         * at least one of them has been enabled by BIOS...
1300         */
1301        pci_read_config_byte(dev, 0x50, &mcr1);
1302        if (mcr1 & 0x30)
1303                pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1304
1305        pci_read_config_byte(dev,  PCI_INTERRUPT_PIN, &pin1);
1306        pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1307
1308        if (pin1 != pin2 && dev->irq == dev2->irq) {
1309                printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
1310                        "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
1311                return 1;
1312        }
1313
1314        return 0;
1315}
1316
1317#define IDE_HFLAGS_HPT3XX \
1318        (IDE_HFLAG_NO_ATAPI_DMA | \
1319         IDE_HFLAG_OFF_BOARD)
1320
1321static const struct ide_port_ops hpt3xx_port_ops = {
1322        .set_pio_mode           = hpt3xx_set_pio_mode,
1323        .set_dma_mode           = hpt3xx_set_mode,
1324        .maskproc               = hpt3xx_maskproc,
1325        .mdma_filter            = hpt3xx_mdma_filter,
1326        .udma_filter            = hpt3xx_udma_filter,
1327        .cable_detect           = hpt3xx_cable_detect,
1328};
1329
1330static const struct ide_dma_ops hpt37x_dma_ops = {
1331        .dma_host_set           = ide_dma_host_set,
1332        .dma_setup              = ide_dma_setup,
1333        .dma_start              = ide_dma_start,
1334        .dma_end                = hpt374_dma_end,
1335        .dma_test_irq           = hpt374_dma_test_irq,
1336        .dma_lost_irq           = ide_dma_lost_irq,
1337        .dma_timer_expiry       = ide_dma_sff_timer_expiry,
1338        .dma_sff_read_status    = ide_dma_sff_read_status,
1339};
1340
1341static const struct ide_dma_ops hpt370_dma_ops = {
1342        .dma_host_set           = ide_dma_host_set,
1343        .dma_setup              = ide_dma_setup,
1344        .dma_start              = hpt370_dma_start,
1345        .dma_end                = hpt370_dma_end,
1346        .dma_test_irq           = ide_dma_test_irq,
1347        .dma_lost_irq           = ide_dma_lost_irq,
1348        .dma_timer_expiry       = ide_dma_sff_timer_expiry,
1349        .dma_clear              = hpt370_irq_timeout,
1350        .dma_sff_read_status    = ide_dma_sff_read_status,
1351};
1352
1353static const struct ide_dma_ops hpt36x_dma_ops = {
1354        .dma_host_set           = ide_dma_host_set,
1355        .dma_setup              = ide_dma_setup,
1356        .dma_start              = ide_dma_start,
1357        .dma_end                = ide_dma_end,
1358        .dma_test_irq           = ide_dma_test_irq,
1359        .dma_lost_irq           = hpt366_dma_lost_irq,
1360        .dma_timer_expiry       = ide_dma_sff_timer_expiry,
1361        .dma_sff_read_status    = ide_dma_sff_read_status,
1362};
1363
1364static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1365        {       /* 0: HPT36x */
1366                .name           = DRV_NAME,
1367                .init_chipset   = init_chipset_hpt366,
1368                .init_hwif      = init_hwif_hpt366,
1369                .init_dma       = init_dma_hpt366,
1370                /*
1371                 * HPT36x chips have one channel per function and have
1372                 * both channel enable bits located differently and visible
1373                 * to both functions -- really stupid design decision... :-(
1374                 * Bit 4 is for the primary channel, bit 5 for the secondary.
1375                 */
1376                .enablebits     = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1377                .port_ops       = &hpt3xx_port_ops,
1378                .dma_ops        = &hpt36x_dma_ops,
1379                .host_flags     = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
1380                .pio_mask       = ATA_PIO4,
1381                .mwdma_mask     = ATA_MWDMA2,
1382        },
1383        {       /* 1: HPT3xx */
1384                .name           = DRV_NAME,
1385                .init_chipset   = init_chipset_hpt366,
1386                .init_hwif      = init_hwif_hpt366,
1387                .init_dma       = init_dma_hpt366,
1388                .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1389                .port_ops       = &hpt3xx_port_ops,
1390                .dma_ops        = &hpt37x_dma_ops,
1391                .host_flags     = IDE_HFLAGS_HPT3XX,
1392                .pio_mask       = ATA_PIO4,
1393                .mwdma_mask     = ATA_MWDMA2,
1394        }
1395};
1396
1397/**
1398 *      hpt366_init_one -       called when an HPT366 is found
1399 *      @dev: the hpt366 device
1400 *      @id: the matching pci id
1401 *
1402 *      Called when the PCI registration layer (or the IDE initialization)
1403 *      finds a device matching our IDE device tables.
1404 */
1405static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1406{
1407        const struct hpt_info *info = NULL;
1408        struct hpt_info *dyn_info;
1409        struct pci_dev *dev2 = NULL;
1410        struct ide_port_info d;
1411        u8 idx = id->driver_data;
1412        u8 rev = dev->revision;
1413        int ret;
1414
1415        if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1416                return -ENODEV;
1417
1418        switch (idx) {
1419        case 0:
1420                if (rev < 3)
1421                        info = &hpt36x;
1422                else {
1423                        switch (min_t(u8, rev, 6)) {
1424                        case 3: info = &hpt370;  break;
1425                        case 4: info = &hpt370a; break;
1426                        case 5: info = &hpt372;  break;
1427                        case 6: info = &hpt372n; break;
1428                        }
1429                        idx++;
1430                }
1431                break;
1432        case 1:
1433                info = (rev > 1) ? &hpt372n : &hpt372a;
1434                break;
1435        case 2:
1436                info = (rev > 1) ? &hpt302n : &hpt302;
1437                break;
1438        case 3:
1439                hpt371_init(dev);
1440                info = (rev > 1) ? &hpt371n : &hpt371;
1441                break;
1442        case 4:
1443                info = &hpt374;
1444                break;
1445        case 5:
1446                info = &hpt372n;
1447                break;
1448        }
1449
1450        printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
1451
1452        d = hpt366_chipsets[min_t(u8, idx, 1)];
1453
1454        d.udma_mask = info->udma_mask;
1455
1456        /* fixup ->dma_ops for HPT370/HPT370A */
1457        if (info == &hpt370 || info == &hpt370a)
1458                d.dma_ops = &hpt370_dma_ops;
1459
1460        if (info == &hpt36x || info == &hpt374)
1461                dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1462
1463        dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL);
1464        if (dyn_info == NULL) {
1465                printk(KERN_ERR "%s %s: out of memory!\n",
1466                        d.name, pci_name(dev));
1467                pci_dev_put(dev2);
1468                return -ENOMEM;
1469        }
1470
1471        /*
1472         * Copy everything from a static "template" structure
1473         * to just allocated per-chip hpt_info structure.
1474         */
1475        memcpy(dyn_info, info, sizeof(*dyn_info));
1476
1477        if (dev2) {
1478                memcpy(dyn_info + 1, info, sizeof(*dyn_info));
1479
1480                if (info == &hpt374)
1481                        hpt374_init(dev, dev2);
1482                else {
1483                        if (hpt36x_init(dev, dev2))
1484                                d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
1485                }
1486
1487                ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
1488                if (ret < 0) {
1489                        pci_dev_put(dev2);
1490                        kfree(dyn_info);
1491                }
1492                return ret;
1493        }
1494
1495        ret = ide_pci_init_one(dev, &d, dyn_info);
1496        if (ret < 0)
1497                kfree(dyn_info);
1498
1499        return ret;
1500}
1501
1502static void __devexit hpt366_remove(struct pci_dev *dev)
1503{
1504        struct ide_host *host = pci_get_drvdata(dev);
1505        struct ide_info *info = host->host_priv;
1506        struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
1507
1508        ide_pci_remove(dev);
1509        pci_dev_put(dev2);
1510        kfree(info);
1511}
1512
1513static const struct pci_device_id hpt366_pci_tbl[] __devinitconst = {
1514        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366),  0 },
1515        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372),  1 },
1516        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302),  2 },
1517        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371),  3 },
1518        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374),  4 },
1519        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
1520        { 0, },
1521};
1522MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1523
1524static struct pci_driver hpt366_pci_driver = {
1525        .name           = "HPT366_IDE",
1526        .id_table       = hpt366_pci_tbl,
1527        .probe          = hpt366_init_one,
1528        .remove         = __devexit_p(hpt366_remove),
1529        .suspend        = ide_pci_suspend,
1530        .resume         = ide_pci_resume,
1531};
1532
1533static int __init hpt366_ide_init(void)
1534{
1535        return ide_pci_register_driver(&hpt366_pci_driver);
1536}
1537
1538static void __exit hpt366_ide_exit(void)
1539{
1540        pci_unregister_driver(&hpt366_pci_driver);
1541}
1542
1543module_init(hpt366_ide_init);
1544module_exit(hpt366_ide_exit);
1545
1546MODULE_AUTHOR("Andre Hedrick");
1547MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1548MODULE_LICENSE("GPL");
1549
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