1config SYMBOL_PREFIX 2 string 3 default "_" 4 5config MMU 6 def_bool n 7 8config FPU 9 def_bool n 10 11config RWSEM_GENERIC_SPINLOCK 12 def_bool y 13 14config RWSEM_XCHGADD_ALGORITHM 15 def_bool n 16 17config BLACKFIN 18 def_bool y 19 select HAVE_ARCH_KGDB 20 select HAVE_ARCH_TRACEHOOK 21 select HAVE_DYNAMIC_FTRACE 22 select HAVE_FTRACE_MCOUNT_RECORD 23 select HAVE_FUNCTION_GRAPH_TRACER 24 select HAVE_FUNCTION_TRACER 25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST 26 select HAVE_IDE 27 select HAVE_IRQ_WORK 28 select HAVE_KERNEL_GZIP if RAMKERNEL 29 select HAVE_KERNEL_BZIP2 if RAMKERNEL 30 select HAVE_KERNEL_LZMA if RAMKERNEL 31 select HAVE_KERNEL_LZO if RAMKERNEL 32 select HAVE_OPROFILE 33 select HAVE_PERF_EVENTS 34 select ARCH_HAVE_CUSTOM_GPIO_H 35 select ARCH_WANT_OPTIONAL_GPIOLIB 36 select ARCH_WANT_IPC_PARSE_VERSION 37 select HAVE_GENERIC_HARDIRQS 38 select GENERIC_ATOMIC64 39 select GENERIC_IRQ_PROBE 40 select IRQ_PER_CPU if SMP 41 select USE_GENERIC_SMP_HELPERS if SMP 42 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG 43 select GENERIC_SMP_IDLE_THREAD 44 select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS 45 46config GENERIC_CSUM 47 def_bool y 48 49config GENERIC_BUG 50 def_bool y 51 depends on BUG 52 53config ZONE_DMA 54 def_bool y 55 56config GENERIC_GPIO 57 def_bool y 58 59config FORCE_MAX_ZONEORDER 60 int 61 default "14" 62 63config GENERIC_CALIBRATE_DELAY 64 def_bool y 65 66config LOCKDEP_SUPPORT 67 def_bool y 68 69config STACKTRACE_SUPPORT 70 def_bool y 71 72config TRACE_IRQFLAGS_SUPPORT 73 def_bool y 74 75source "init/Kconfig" 76 77source "kernel/Kconfig.preempt" 78 79source "kernel/Kconfig.freezer" 80 81menu "Blackfin Processor Options" 82 83comment "Processor and Board Settings" 84 85choice 86 prompt "CPU" 87 default BF533 88 89config BF512 90 bool "BF512" 91 help 92 BF512 Processor Support. 93 94config BF514 95 bool "BF514" 96 help 97 BF514 Processor Support. 98 99config BF516 100 bool "BF516" 101 help 102 BF516 Processor Support. 103 104config BF518 105 bool "BF518" 106 help 107 BF518 Processor Support. 108 109config BF522 110 bool "BF522" 111 help 112 BF522 Processor Support. 113 114config BF523 115 bool "BF523" 116 help 117 BF523 Processor Support. 118 119config BF524 120 bool "BF524" 121 help 122 BF524 Processor Support. 123 124config BF525 125 bool "BF525" 126 help 127 BF525 Processor Support. 128 129config BF526 130 bool "BF526" 131 help 132 BF526 Processor Support. 133 134config BF527 135 bool "BF527" 136 help 137 BF527 Processor Support. 138 139config BF531 140 bool "BF531" 141 help 142 BF531 Processor Support. 143 144config BF532 145 bool "BF532" 146 help 147 BF532 Processor Support. 148 149config BF533 150 bool "BF533" 151 help 152 BF533 Processor Support. 153 154config BF534 155 bool "BF534" 156 help 157 BF534 Processor Support. 158 159config BF536 160 bool "BF536" 161 help 162 BF536 Processor Support. 163 164config BF537 165 bool "BF537" 166 help 167 BF537 Processor Support. 168 169config BF538 170 bool "BF538" 171 help 172 BF538 Processor Support. 173 174config BF539 175 bool "BF539" 176 help 177 BF539 Processor Support. 178 179config BF542_std 180 bool "BF542" 181 help 182 BF542 Processor Support. 183 184config BF542M 185 bool "BF542m" 186 help 187 BF542 Processor Support. 188 189config BF544_std 190 bool "BF544" 191 help 192 BF544 Processor Support. 193 194config BF544M 195 bool "BF544m" 196 help 197 BF544 Processor Support. 198 199config BF547_std 200 bool "BF547" 201 help 202 BF547 Processor Support. 203 204config BF547M 205 bool "BF547m" 206 help 207 BF547 Processor Support. 208 209config BF548_std 210 bool "BF548" 211 help 212 BF548 Processor Support. 213 214config BF548M 215 bool "BF548m" 216 help 217 BF548 Processor Support. 218 219config BF549_std 220 bool "BF549" 221 help 222 BF549 Processor Support. 223 224config BF549M 225 bool "BF549m" 226 help 227 BF549 Processor Support. 228 229config BF561 230 bool "BF561" 231 help 232 BF561 Processor Support. 233 234config BF609 235 bool "BF609" 236 select CLKDEV_LOOKUP 237 help 238 BF609 Processor Support. 239 240endchoice 241 242config SMP 243 depends on BF561 244 select TICKSOURCE_CORETMR 245 bool "Symmetric multi-processing support" 246 ---help--- 247 This enables support for systems with more than one CPU, 248 like the dual core BF561. If you have a system with only one 249 CPU, say N. If you have a system with more than one CPU, say Y. 250 251 If you don't know what to do here, say N. 252 253config NR_CPUS 254 int 255 depends on SMP 256 default 2 if BF561 257 258config HOTPLUG_CPU 259 bool "Support for hot-pluggable CPUs" 260 depends on SMP && HOTPLUG 261 default y 262 263config BF_REV_MIN 264 int 265 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x 266 default 2 if (BF537 || BF536 || BF534) 267 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) 268 default 4 if (BF538 || BF539) 269 270config BF_REV_MAX 271 int 272 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x 273 default 3 if (BF537 || BF536 || BF534 || BF54xM) 274 default 5 if (BF561 || BF538 || BF539) 275 default 6 if (BF533 || BF532 || BF531) 276 277choice 278 prompt "Silicon Rev" 279 default BF_REV_0_0 if (BF51x || BF52x || BF60x) 280 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) 281 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) 282 283config BF_REV_0_0 284 bool "0.0" 285 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) 286 287config BF_REV_0_1 288 bool "0.1" 289 depends on (BF51x || BF52x || (BF54x && !BF54xM)) 290 291config BF_REV_0_2 292 bool "0.2" 293 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) 294 295config BF_REV_0_3 296 bool "0.3" 297 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) 298 299config BF_REV_0_4 300 bool "0.4" 301 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) 302 303config BF_REV_0_5 304 bool "0.5" 305 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) 306 307config BF_REV_0_6 308 bool "0.6" 309 depends on (BF533 || BF532 || BF531) 310 311config BF_REV_ANY 312 bool "any" 313 314config BF_REV_NONE 315 bool "none" 316 317endchoice 318 319config BF53x 320 bool 321 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) 322 default y 323 324config MEM_MT48LC64M4A2FB_7E 325 bool 326 depends on (BFIN533_STAMP) 327 default y 328 329config MEM_MT48LC16M16A2TG_75 330 bool 331 depends on (BFIN533_EZKIT || BFIN561_EZKIT \ 332 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ 333 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ 334 || BFIN527_BLUETECHNIX_CM) 335 default y 336 337config MEM_MT48LC32M8A2_75 338 bool 339 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) 340 default y 341 342config MEM_MT48LC8M32B2B5_7 343 bool 344 depends on (BFIN561_BLUETECHNIX_CM) 345 default y 346 347config MEM_MT48LC32M16A2TG_75 348 bool 349 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) 350 default y 351 352config MEM_MT48H32M16LFCJ_75 353 bool 354 depends on (BFIN526_EZBRD) 355 default y 356 357config MEM_MT47H64M16 358 bool 359 depends on (BFIN609_EZKIT) 360 default y 361 362source "arch/blackfin/mach-bf518/Kconfig" 363source "arch/blackfin/mach-bf527/Kconfig" 364source "arch/blackfin/mach-bf533/Kconfig" 365source "arch/blackfin/mach-bf561/Kconfig" 366source "arch/blackfin/mach-bf537/Kconfig" 367source "arch/blackfin/mach-bf538/Kconfig" 368source "arch/blackfin/mach-bf548/Kconfig" 369source "arch/blackfin/mach-bf609/Kconfig" 370 371menu "Board customizations" 372 373config CMDLINE_BOOL 374 bool "Default bootloader kernel arguments" 375 376config CMDLINE 377 string "Initial kernel command string" 378 depends on CMDLINE_BOOL 379 default "console=ttyBF0,57600" 380 help 381 If you don't have a boot loader capable of passing a command line string 382 to the kernel, you may specify one here. As a minimum, you should specify 383 the memory size and the root device (e.g., mem=8M, root=/dev/nfs). 384 385config BOOT_LOAD 386 hex "Kernel load address for booting" 387 default "0x1000" 388 range 0x1000 0x20000000 389 help 390 This option allows you to set the load address of the kernel. 391 This can be useful if you are on a board which has a small amount 392 of memory or you wish to reserve some memory at the beginning of 393 the address space. 394 395 Note that you need to keep this value above 4k (0x1000) as this 396 memory region is used to capture NULL pointer references as well 397 as some core kernel functions. 398 399config PHY_RAM_BASE_ADDRESS 400 hex "Physical RAM Base" 401 default 0x0 402 help 403 set BF609 FPGA physical SRAM base address 404 405config ROM_BASE 406 hex "Kernel ROM Base" 407 depends on ROMKERNEL 408 default "0x20040040" 409 range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x) 410 range 0x20000000 0x30000000 if (BF54x || BF561) 411 range 0xB0000000 0xC0000000 if (BF60x) 412 help 413 Make sure your ROM base does not include any file-header 414 information that is prepended to the kernel. 415 416 For example, the bootable U-Boot format (created with 417 mkimage) has a 64 byte header (0x40). So while the image 418 you write to flash might start at say 0x20080000, you have 419 to add 0x40 to get the kernel's ROM base as it will come 420 after the header. 421 422comment "Clock/PLL Setup" 423 424config CLKIN_HZ 425 int "Frequency of the crystal on the board in Hz" 426 default "10000000" if BFIN532_IP0X 427 default "11059200" if BFIN533_STAMP 428 default "24576000" if PNAV10 429 default "25000000" # most people use this 430 default "27000000" if BFIN533_EZKIT 431 default "30000000" if BFIN561_EZKIT 432 default "24000000" if BFIN527_AD7160EVAL 433 help 434 The frequency of CLKIN crystal oscillator on the board in Hz. 435 Warning: This value should match the crystal on the board. Otherwise, 436 peripherals won't work properly. 437 438config BFIN_KERNEL_CLOCK 439 bool "Re-program Clocks while Kernel boots?" 440 default n 441 help 442 This option decides if kernel clocks are re-programed from the 443 bootloader settings. If the clocks are not set, the SDRAM settings 444 are also not changed, and the Bootloader does 100% of the hardware 445 configuration. 446 447config PLL_BYPASS 448 bool "Bypass PLL" 449 depends on BFIN_KERNEL_CLOCK && (!BF60x) 450 default n 451 452config CLKIN_HALF 453 bool "Half Clock In" 454 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) 455 default n 456 help 457 If this is set the clock will be divided by 2, before it goes to the PLL. 458 459config VCO_MULT 460 int "VCO Multiplier" 461 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) 462 range 1 64 463 default "22" if BFIN533_EZKIT 464 default "45" if BFIN533_STAMP 465 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) 466 default "22" if BFIN533_BLUETECHNIX_CM 467 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) 468 default "20" if (BFIN561_EZKIT || BF609) 469 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) 470 default "25" if BFIN527_AD7160EVAL 471 help 472 This controls the frequency of the on-chip PLL. This can be between 1 and 64. 473 PLL Frequency = (Crystal Frequency) * (this setting) 474 475choice 476 prompt "Core Clock Divider" 477 depends on BFIN_KERNEL_CLOCK 478 default CCLK_DIV_1 479 help 480 This sets the frequency of the core. It can be 1, 2, 4 or 8 481 Core Frequency = (PLL frequency) / (this setting) 482 483config CCLK_DIV_1 484 bool "1" 485 486config CCLK_DIV_2 487 bool "2" 488 489config CCLK_DIV_4 490 bool "4" 491 492config CCLK_DIV_8 493 bool "8" 494endchoice 495 496config SCLK_DIV 497 int "System Clock Divider" 498 depends on BFIN_KERNEL_CLOCK 499 range 1 15 500 default 4 501 help 502 This sets the frequency of the system clock (including SDRAM or DDR) on 503 !BF60x else it set the clock for system buses and provides the 504 source from which SCLK0 and SCLK1 are derived. 505 This can be between 1 and 15 506 System Clock = (PLL frequency) / (this setting) 507 508config SCLK0_DIV 509 int "System Clock0 Divider" 510 depends on BFIN_KERNEL_CLOCK && BF60x 511 range 1 15 512 default 1 513 help 514 This sets the frequency of the system clock0 for PVP and all other 515 peripherals not clocked by SCLK1. 516 This can be between 1 and 15 517 System Clock0 = (System Clock) / (this setting) 518 519config SCLK1_DIV 520 int "System Clock1 Divider" 521 depends on BFIN_KERNEL_CLOCK && BF60x 522 range 1 15 523 default 1 524 help 525 This sets the frequency of the system clock1 (including SPORT, SPI and ACM). 526 This can be between 1 and 15 527 System Clock1 = (System Clock) / (this setting) 528 529config DCLK_DIV 530 int "DDR Clock Divider" 531 depends on BFIN_KERNEL_CLOCK && BF60x 532 range 1 15 533 default 2 534 help 535 This sets the frequency of the DDR memory. 536 This can be between 1 and 15 537 DDR Clock = (PLL frequency) / (this setting) 538 539choice 540 prompt "DDR SDRAM Chip Type" 541 depends on BFIN_KERNEL_CLOCK 542 depends on BF54x 543 default MEM_MT46V32M16_5B 544 545config MEM_MT46V32M16_6T 546 bool "MT46V32M16_6T" 547 548config MEM_MT46V32M16_5B 549 bool "MT46V32M16_5B" 550endchoice 551 552choice 553 prompt "DDR/SDRAM Timing" 554 depends on BFIN_KERNEL_CLOCK && !BF60x 555 default BFIN_KERNEL_CLOCK_MEMINIT_CALC 556 help 557 This option allows you to specify Blackfin SDRAM/DDR Timing parameters 558 The calculated SDRAM timing parameters may not be 100% 559 accurate - This option is therefore marked experimental. 560 561config BFIN_KERNEL_CLOCK_MEMINIT_CALC 562 bool "Calculate Timings (EXPERIMENTAL)" 563 depends on EXPERIMENTAL 564 565config BFIN_KERNEL_CLOCK_MEMINIT_SPEC 566 bool "Provide accurate Timings based on target SCLK" 567 help 568 Please consult the Blackfin Hardware Reference Manuals as well 569 as the memory device datasheet. 570 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram 571endchoice 572 573menu "Memory Init Control" 574 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC 575 576config MEM_DDRCTL0 577 depends on BF54x 578 hex "DDRCTL0" 579 default 0x0 580 581config MEM_DDRCTL1 582 depends on BF54x 583 hex "DDRCTL1" 584 default 0x0 585 586config MEM_DDRCTL2 587 depends on BF54x 588 hex "DDRCTL2" 589 default 0x0 590 591config MEM_EBIU_DDRQUE 592 depends on BF54x 593 hex "DDRQUE" 594 default 0x0 595 596config MEM_SDRRC 597 depends on !BF54x 598 hex "SDRRC" 599 default 0x0 600 601config MEM_SDGCTL 602 depends on !BF54x 603 hex "SDGCTL" 604 default 0x0 605endmenu 606 607# 608# Max & Min Speeds for various Chips 609# 610config MAX_VCO_HZ 611 int 612 default 400000000 if BF512 613 default 400000000 if BF514 614 default 400000000 if BF516 615 default 400000000 if BF518 616 default 400000000 if BF522 617 default 600000000 if BF523 618 default 400000000 if BF524 619 default 600000000 if BF525 620 default 400000000 if BF526 621 default 600000000 if BF527 622 default 400000000 if BF531 623 default 400000000 if BF532 624 default 750000000 if BF533 625 default 500000000 if BF534 626 default 400000000 if BF536 627 default 600000000 if BF537 628 default 533333333 if BF538 629 default 533333333 if BF539 630 default 600000000 if BF542 631 default 533333333 if BF544 632 default 600000000 if BF547 633 default 600000000 if BF548 634 default 533333333 if BF549 635 default 600000000 if BF561 636 default 800000000 if BF609 637 638config MIN_VCO_HZ 639 int 640 default 50000000 641 642config MAX_SCLK_HZ 643 int 644 default 200000000 if BF609 645 default 133333333 646 647config MIN_SCLK_HZ 648 int 649 default 27000000 650 651comment "Kernel Timer/Scheduler" 652 653source kernel/Kconfig.hz 654 655config SET_GENERIC_CLOCKEVENTS 656 bool "Generic clock events" 657 default y 658 select GENERIC_CLOCKEVENTS 659 660menu "Clock event device" 661 depends on GENERIC_CLOCKEVENTS 662config TICKSOURCE_GPTMR0 663 bool "GPTimer0" 664 depends on !SMP 665 select BFIN_GPTIMERS 666 667config TICKSOURCE_CORETMR 668 bool "Core timer" 669 default y 670endmenu 671 672menu "Clock souce" 673 depends on GENERIC_CLOCKEVENTS 674config CYCLES_CLOCKSOURCE 675 bool "CYCLES" 676 default y 677 depends on !BFIN_SCRATCH_REG_CYCLES 678 depends on !SMP 679 help 680 If you say Y here, you will enable support for using the 'cycles' 681 registers as a clock source. Doing so means you will be unable to 682 safely write to the 'cycles' register during runtime. You will 683 still be able to read it (such as for performance monitoring), but 684 writing the registers will most likely crash the kernel. 685 686config GPTMR0_CLOCKSOURCE 687 bool "GPTimer0" 688 select BFIN_GPTIMERS 689 depends on !TICKSOURCE_GPTMR0 690endmenu 691 692comment "Misc" 693 694choice 695 prompt "Blackfin Exception Scratch Register" 696 default BFIN_SCRATCH_REG_RETN 697 help 698 Select the resource to reserve for the Exception handler: 699 - RETN: Non-Maskable Interrupt (NMI) 700 - RETE: Exception Return (JTAG/ICE) 701 - CYCLES: Performance counter 702 703 If you are unsure, please select "RETN". 704 705config BFIN_SCRATCH_REG_RETN 706 bool "RETN" 707 help 708 Use the RETN register in the Blackfin exception handler 709 as a stack scratch register. This means you cannot 710 safely use NMI on the Blackfin while running Linux, but 711 you can debug the system with a JTAG ICE and use the 712 CYCLES performance registers. 713 714 If you are unsure, please select "RETN". 715 716config BFIN_SCRATCH_REG_RETE 717 bool "RETE" 718 help 719 Use the RETE register in the Blackfin exception handler 720 as a stack scratch register. This means you cannot 721 safely use a JTAG ICE while debugging a Blackfin board, 722 but you can safely use the CYCLES performance registers 723 and the NMI. 724 725 If you are unsure, please select "RETN". 726 727config BFIN_SCRATCH_REG_CYCLES 728 bool "CYCLES" 729 help 730 Use the CYCLES register in the Blackfin exception handler 731 as a stack scratch register. This means you cannot 732 safely use the CYCLES performance registers on a Blackfin 733 board at anytime, but you can debug the system with a JTAG 734 ICE and use the NMI. 735 736 If you are unsure, please select "RETN". 737 738endchoice 739 740endmenu 741 742 743menu "Blackfin Kernel Optimizations" 744 745comment "Memory Optimizations" 746 747config I_ENTRY_L1 748 bool "Locate interrupt entry code in L1 Memory" 749 default y 750 depends on !SMP 751 help 752 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked 753 into L1 instruction memory. (less latency) 754 755config EXCPT_IRQ_SYSC_L1 756 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" 757 default y 758 depends on !SMP 759 help 760 If enabled, the entire ASM lowlevel exception and interrupt entry code 761 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. 762 (less latency) 763 764config DO_IRQ_L1 765 bool "Locate frequently called do_irq dispatcher function in L1 Memory" 766 default y 767 depends on !SMP 768 help 769 If enabled, the frequently called do_irq dispatcher function is linked 770 into L1 instruction memory. (less latency) 771 772config CORE_TIMER_IRQ_L1 773 bool "Locate frequently called timer_interrupt() function in L1 Memory" 774 default y 775 depends on !SMP 776 help 777 If enabled, the frequently called timer_interrupt() function is linked 778 into L1 instruction memory. (less latency) 779 780config IDLE_L1 781 bool "Locate frequently idle function in L1 Memory" 782 default y 783 depends on !SMP 784 help 785 If enabled, the frequently called idle function is linked 786 into L1 instruction memory. (less latency) 787 788config SCHEDULE_L1 789 bool "Locate kernel schedule function in L1 Memory" 790 default y 791 depends on !SMP 792 help 793 If enabled, the frequently called kernel schedule is linked 794 into L1 instruction memory. (less latency) 795 796config ARITHMETIC_OPS_L1 797 bool "Locate kernel owned arithmetic functions in L1 Memory" 798 default y 799 depends on !SMP 800 help 801 If enabled, arithmetic functions are linked 802 into L1 instruction memory. (less latency) 803 804config ACCESS_OK_L1 805 bool "Locate access_ok function in L1 Memory" 806 default y 807 depends on !SMP 808 help 809 If enabled, the access_ok function is linked 810 into L1 instruction memory. (less latency) 811 812config MEMSET_L1 813 bool "Locate memset function in L1 Memory" 814 default y 815 depends on !SMP 816 help 817 If enabled, the memset function is linked 818 into L1 instruction memory. (less latency) 819 820config MEMCPY_L1 821 bool "Locate memcpy function in L1 Memory" 822 default y 823 depends on !SMP 824 help 825 If enabled, the memcpy function is linked 826 into L1 instruction memory. (less latency) 827 828config STRCMP_L1 829 bool "locate strcmp function in L1 Memory" 830 default y 831 depends on !SMP 832 help 833 If enabled, the strcmp function is linked 834 into L1 instruction memory (less latency). 835 836config STRNCMP_L1 837 bool "locate strncmp function in L1 Memory" 838 default y 839 depends on !SMP 840 help 841 If enabled, the strncmp function is linked 842 into L1 instruction memory (less latency). 843 844config STRCPY_L1 845 bool "locate strcpy function in L1 Memory" 846 default y 847 depends on !SMP 848 help 849 If enabled, the strcpy function is linked 850 into L1 instruction memory (less latency). 851 852config STRNCPY_L1 853 bool "locate strncpy function in L1 Memory" 854 default y 855 depends on !SMP 856 help 857 If enabled, the strncpy function is linked 858 into L1 instruction memory (less latency). 859 860config SYS_BFIN_SPINLOCK_L1 861 bool "Locate sys_bfin_spinlock function in L1 Memory" 862 default y 863 depends on !SMP 864 help 865 If enabled, sys_bfin_spinlock function is linked 866 into L1 instruction memory. (less latency) 867 868config IP_CHECKSUM_L1 869 bool "Locate IP Checksum function in L1 Memory" 870 default n 871 depends on !SMP 872 help 873 If enabled, the IP Checksum function is linked 874 into L1 instruction memory. (less latency) 875 876config CACHELINE_ALIGNED_L1 877 bool "Locate cacheline_aligned data to L1 Data Memory" 878 default y if !BF54x 879 default n if BF54x 880 depends on !SMP && !BF531 && !CRC32 881 help 882 If enabled, cacheline_aligned data is linked 883 into L1 data memory. (less latency) 884 885config SYSCALL_TAB_L1 886 bool "Locate Syscall Table L1 Data Memory" 887 default n 888 depends on !SMP && !BF531 889 help 890 If enabled, the Syscall LUT is linked 891 into L1 data memory. (less latency) 892 893config CPLB_SWITCH_TAB_L1 894 bool "Locate CPLB Switch Tables L1 Data Memory" 895 default n 896 depends on !SMP && !BF531 897 help 898 If enabled, the CPLB Switch Tables are linked 899 into L1 data memory. (less latency) 900 901config ICACHE_FLUSH_L1 902 bool "Locate icache flush funcs in L1 Inst Memory" 903 default y 904 help 905 If enabled, the Blackfin icache flushing functions are linked 906 into L1 instruction memory. 907 908 Note that this might be required to address anomalies, but 909 these functions are pretty small, so it shouldn't be too bad. 910 If you are using a processor affected by an anomaly, the build 911 system will double check for you and prevent it. 912 913config DCACHE_FLUSH_L1 914 bool "Locate dcache flush funcs in L1 Inst Memory" 915 default y 916 depends on !SMP 917 help 918 If enabled, the Blackfin dcache flushing functions are linked 919 into L1 instruction memory. 920 921config APP_STACK_L1 922 bool "Support locating application stack in L1 Scratch Memory" 923 default y 924 depends on !SMP 925 help 926 If enabled the application stack can be located in L1 927 scratch memory (less latency). 928 929 Currently only works with FLAT binaries. 930 931config EXCEPTION_L1_SCRATCH 932 bool "Locate exception stack in L1 Scratch Memory" 933 default n 934 depends on !SMP && !APP_STACK_L1 935 help 936 Whenever an exception occurs, use the L1 Scratch memory for 937 stack storage. You cannot place the stacks of FLAT binaries 938 in L1 when using this option. 939 940 If you don't use L1 Scratch, then you should say Y here. 941 942comment "Speed Optimizations" 943config BFIN_INS_LOWOVERHEAD 944 bool "ins[bwl] low overhead, higher interrupt latency" 945 default y 946 depends on !SMP 947 help 948 Reads on the Blackfin are speculative. In Blackfin terms, this means 949 they can be interrupted at any time (even after they have been issued 950 on to the external bus), and re-issued after the interrupt occurs. 951 For memory - this is not a big deal, since memory does not change if 952 it sees a read. 953 954 If a FIFO is sitting on the end of the read, it will see two reads, 955 when the core only sees one since the FIFO receives both the read 956 which is cancelled (and not delivered to the core) and the one which 957 is re-issued (which is delivered to the core). 958 959 To solve this, interrupts are turned off before reads occur to 960 I/O space. This option controls which the overhead/latency of 961 controlling interrupts during this time 962 "n" turns interrupts off every read 963 (higher overhead, but lower interrupt latency) 964 "y" turns interrupts off every loop 965 (low overhead, but longer interrupt latency) 966 967 default behavior is to leave this set to on (type "Y"). If you are experiencing 968 interrupt latency issues, it is safe and OK to turn this off. 969 970endmenu 971 972choice 973 prompt "Kernel executes from" 974 help 975 Choose the memory type that the kernel will be running in. 976 977config RAMKERNEL 978 bool "RAM" 979 help 980 The kernel will be resident in RAM when running. 981 982config ROMKERNEL 983 bool "ROM" 984 help 985 The kernel will be resident in FLASH/ROM when running. 986 987endchoice 988 989# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both 990config XIP_KERNEL 991 bool 992 default y 993 depends on ROMKERNEL 994 995source "mm/Kconfig" 996 997config BFIN_GPTIMERS 998 tristate "Enable Blackfin General Purpose Timers API" 999 default n 1000 help
1001 Enable support for the General Purpose Timers API. If you 1002 are unsure, say N. 1003 1004 To compile this driver as a module, choose M here: the module 1005 will be called gptimers. 1006 1007choice 1008 prompt "Uncached DMA region" 1009 default DMA_UNCACHED_1M 1010config DMA_UNCACHED_32M 1011 bool "Enable 32M DMA region" 1012config DMA_UNCACHED_16M 1013 bool "Enable 16M DMA region" 1014config DMA_UNCACHED_8M 1015 bool "Enable 8M DMA region" 1016config DMA_UNCACHED_4M 1017 bool "Enable 4M DMA region" 1018config DMA_UNCACHED_2M 1019 bool "Enable 2M DMA region" 1020config DMA_UNCACHED_1M 1021 bool "Enable 1M DMA region" 1022config DMA_UNCACHED_512K 1023 bool "Enable 512K DMA region" 1024config DMA_UNCACHED_256K 1025 bool "Enable 256K DMA region" 1026config DMA_UNCACHED_128K 1027 bool "Enable 128K DMA region" 1028config DMA_UNCACHED_NONE 1029 bool "Disable DMA region" 1030endchoice 1031 1032 1033comment "Cache Support" 1034 1035config BFIN_ICACHE 1036 bool "Enable ICACHE" 1037 default y 1038config BFIN_EXTMEM_ICACHEABLE 1039 bool "Enable ICACHE for external memory" 1040 depends on BFIN_ICACHE 1041 default y 1042config BFIN_L2_ICACHEABLE 1043 bool "Enable ICACHE for L2 SRAM" 1044 depends on BFIN_ICACHE 1045 depends on (BF54x || BF561 || BF60x) && !SMP 1046 default n 1047 1048config BFIN_DCACHE 1049 bool "Enable DCACHE" 1050 default y 1051config BFIN_DCACHE_BANKA 1052 bool "Enable only 16k BankA DCACHE - BankB is SRAM" 1053 depends on BFIN_DCACHE && !BF531 1054 default n 1055config BFIN_EXTMEM_DCACHEABLE 1056 bool "Enable DCACHE for external memory" 1057 depends on BFIN_DCACHE 1058 default y 1059choice 1060 prompt "External memory DCACHE policy" 1061 depends on BFIN_EXTMEM_DCACHEABLE 1062 default BFIN_EXTMEM_WRITEBACK if !SMP 1063 default BFIN_EXTMEM_WRITETHROUGH if SMP 1064config BFIN_EXTMEM_WRITEBACK 1065 bool "Write back" 1066 depends on !SMP 1067 help 1068 Write Back Policy: 1069 Cached data will be written back to SDRAM only when needed. 1070 This can give a nice increase in performance, but beware of 1071 broken drivers that do not properly invalidate/flush their 1072 cache. 1073 1074 Write Through Policy: 1075 Cached data will always be written back to SDRAM when the 1076 cache is updated. This is a completely safe setting, but 1077 performance is worse than Write Back. 1078 1079 If you are unsure of the options and you want to be safe, 1080 then go with Write Through. 1081 1082config BFIN_EXTMEM_WRITETHROUGH 1083 bool "Write through" 1084 help 1085 Write Back Policy: 1086 Cached data will be written back to SDRAM only when needed. 1087 This can give a nice increase in performance, but beware of 1088 broken drivers that do not properly invalidate/flush their 1089 cache. 1090 1091 Write Through Policy: 1092 Cached data will always be written back to SDRAM when the 1093 cache is updated. This is a completely safe setting, but 1094 performance is worse than Write Back. 1095 1096 If you are unsure of the options and you want to be safe, 1097 then go with Write Through. 1098 1099endchoice 1100 1101config BFIN_L2_DCACHEABLE 1102 bool "Enable DCACHE for L2 SRAM" 1103 depends on BFIN_DCACHE 1104 depends on (BF54x || BF561 || BF60x) && !SMP 1105 default n 1106choice 1107 prompt "L2 SRAM DCACHE policy" 1108 depends on BFIN_L2_DCACHEABLE 1109 default BFIN_L2_WRITEBACK 1110config BFIN_L2_WRITEBACK 1111 bool "Write back" 1112 1113config BFIN_L2_WRITETHROUGH 1114 bool "Write through" 1115endchoice 1116 1117 1118comment "Memory Protection Unit" 1119config MPU 1120 bool "Enable the memory protection unit (EXPERIMENTAL)" 1121 default n 1122 help 1123 Use the processor's MPU to protect applications from accessing 1124 memory they do not own. This comes at a performance penalty 1125 and is recommended only for debugging. 1126 1127comment "Asynchronous Memory Configuration" 1128 1129menu "EBIU_AMGCTL Global Control" 1130 depends on !BF60x 1131config C_AMCKEN 1132 bool "Enable CLKOUT" 1133 default y 1134 1135config C_CDPRIO 1136 bool "DMA has priority over core for ext. accesses" 1137 default n 1138 1139config C_B0PEN 1140 depends on BF561 1141 bool "Bank 0 16 bit packing enable" 1142 default y 1143 1144config C_B1PEN 1145 depends on BF561 1146 bool "Bank 1 16 bit packing enable" 1147 default y 1148 1149config C_B2PEN 1150 depends on BF561 1151 bool "Bank 2 16 bit packing enable" 1152 default y 1153 1154config C_B3PEN 1155 depends on BF561 1156 bool "Bank 3 16 bit packing enable" 1157 default n 1158 1159choice 1160 prompt "Enable Asynchronous Memory Banks" 1161 default C_AMBEN_ALL 1162 1163config C_AMBEN 1164 bool "Disable All Banks" 1165 1166config C_AMBEN_B0 1167 bool "Enable Bank 0" 1168 1169config C_AMBEN_B0_B1 1170 bool "Enable Bank 0 & 1" 1171 1172config C_AMBEN_B0_B1_B2 1173 bool "Enable Bank 0 & 1 & 2" 1174 1175config C_AMBEN_ALL 1176 bool "Enable All Banks" 1177endchoice 1178endmenu 1179 1180menu "EBIU_AMBCTL Control" 1181 depends on !BF60x 1182config BANK_0 1183 hex "Bank 0 (AMBCTL0.L)" 1184 default 0x7BB0 1185 help 1186 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are 1187 used to control the Asynchronous Memory Bank 0 settings. 1188 1189config BANK_1 1190 hex "Bank 1 (AMBCTL0.H)" 1191 default 0x7BB0 1192 default 0x5558 if BF54x 1193 help 1194 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are 1195 used to control the Asynchronous Memory Bank 1 settings. 1196 1197config BANK_2 1198 hex "Bank 2 (AMBCTL1.L)" 1199 default 0x7BB0 1200 help 1201 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are 1202 used to control the Asynchronous Memory Bank 2 settings. 1203 1204config BANK_3 1205 hex "Bank 3 (AMBCTL1.H)" 1206 default 0x99B3 1207 help 1208 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are 1209 used to control the Asynchronous Memory Bank 3 settings. 1210 1211endmenu 1212 1213config EBIU_MBSCTLVAL 1214 hex "EBIU Bank Select Control Register" 1215 depends on BF54x 1216 default 0 1217 1218config EBIU_MODEVAL 1219 hex "Flash Memory Mode Control Register" 1220 depends on BF54x 1221 default 1 1222 1223config EBIU_FCTLVAL 1224 hex "Flash Memory Bank Control Register" 1225 depends on BF54x 1226 default 6 1227endmenu 1228 1229############################################################################# 1230menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" 1231 1232config PCI 1233 bool "PCI support" 1234 depends on BROKEN 1235 help 1236 Support for PCI bus. 1237 1238source "drivers/pci/Kconfig" 1239 1240source "drivers/pcmcia/Kconfig" 1241 1242source "drivers/pci/hotplug/Kconfig" 1243 1244endmenu 1245 1246menu "Executable file formats" 1247 1248source "fs/Kconfig.binfmt" 1249 1250endmenu 1251 1252menu "Power management options" 1253 1254source "kernel/power/Kconfig" 1255 1256config ARCH_SUSPEND_POSSIBLE 1257 def_bool y 1258 1259choice 1260 prompt "Standby Power Saving Mode" 1261 depends on PM && !BF60x 1262 default PM_BFIN_SLEEP_DEEPER 1263config PM_BFIN_SLEEP_DEEPER 1264 bool "Sleep Deeper" 1265 help 1266 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic 1267 power dissipation by disabling the clock to the processor core (CCLK). 1268 Furthermore, Standby sets the internal power supply voltage (VDDINT) 1269 to 0.85 V to provide the greatest power savings, while preserving the 1270 processor state. 1271 The PLL and system clock (SCLK) continue to operate at a very low 1272 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, 1273 the SDRAM is put into Self Refresh Mode. Typically an external event 1274 such as GPIO interrupt or RTC activity wakes up the processor. 1275 Various Peripherals such as UART, SPORT, PPI may not function as 1276 normal during Sleep Deeper, due to the reduced SCLK frequency. 1277 When in the sleep mode, system DMA access to L1 memory is not supported. 1278 1279 If unsure, select "Sleep Deeper". 1280 1281config PM_BFIN_SLEEP 1282 bool "Sleep" 1283 help 1284 Sleep Mode (High Power Savings) - The sleep mode reduces power 1285 dissipation by disabling the clock to the processor core (CCLK). 1286 The PLL and system clock (SCLK), however, continue to operate in 1287 this mode. Typically an external event or RTC activity will wake 1288 up the processor. When in the sleep mode, system DMA access to L1 1289 memory is not supported. 1290 1291 If unsure, select "Sleep Deeper". 1292endchoice 1293 1294comment "Possible Suspend Mem / Hibernate Wake-Up Sources" 1295 depends on PM 1296 1297config PM_BFIN_WAKE_PH6 1298 bool "Allow Wake-Up from on-chip PHY or PH6 GP" 1299 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) 1300 default n 1301 help 1302 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) 1303 1304config PM_BFIN_WAKE_GP 1305 bool "Allow Wake-Up from GPIOs" 1306 depends on PM && BF54x 1307 default n 1308 help 1309 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) 1310 (all processors, except ADSP-BF549). This option sets 1311 the general-purpose wake-up enable (GPWE) control bit to enable 1312 wake-up upon detection of an active low signal on the /GPW (PH7) pin. 1313 On ADSP-BF549 this option enables the same functionality on the 1314 /MRXON pin also PH7. 1315 1316config PM_BFIN_WAKE_PA15 1317 bool "Allow Wake-Up from PA15" 1318 depends on PM && BF60x 1319 default n 1320 help 1321 Enable PA15 Wake-Up 1322 1323config PM_BFIN_WAKE_PA15_POL 1324 int "Wake-up priority" 1325 depends on PM_BFIN_WAKE_PA15 1326 default 0 1327 help 1328 Wake-Up priority 0(low) 1(high) 1329 1330config PM_BFIN_WAKE_PB15 1331 bool "Allow Wake-Up from PB15" 1332 depends on PM && BF60x 1333 default n 1334 help 1335 Enable PB15 Wake-Up 1336 1337config PM_BFIN_WAKE_PB15_POL 1338 int "Wake-up priority" 1339 depends on PM_BFIN_WAKE_PB15 1340 default 0 1341 help 1342 Wake-Up priority 0(low) 1(high) 1343 1344config PM_BFIN_WAKE_PC15 1345 bool "Allow Wake-Up from PC15" 1346 depends on PM && BF60x 1347 default n 1348 help 1349 Enable PC15 Wake-Up 1350 1351config PM_BFIN_WAKE_PC15_POL 1352 int "Wake-up priority" 1353 depends on PM_BFIN_WAKE_PC15 1354 default 0 1355 help 1356 Wake-Up priority 0(low) 1(high) 1357 1358config PM_BFIN_WAKE_PD06 1359 bool "Allow Wake-Up from PD06(ETH0_PHYINT)" 1360 depends on PM && BF60x 1361 default n 1362 help 1363 Enable PD06(ETH0_PHYINT) Wake-up 1364 1365config PM_BFIN_WAKE_PD06_POL 1366 int "Wake-up priority" 1367 depends on PM_BFIN_WAKE_PD06 1368 default 0 1369 help 1370 Wake-Up priority 0(low) 1(high) 1371 1372config PM_BFIN_WAKE_PE12 1373 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)" 1374 depends on PM && BF60x 1375 default n 1376 help 1377 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up 1378 1379config PM_BFIN_WAKE_PE12_POL 1380 int "Wake-up priority" 1381 depends on PM_BFIN_WAKE_PE12 1382 default 0 1383 help 1384 Wake-Up priority 0(low) 1(high) 1385 1386config PM_BFIN_WAKE_PG04 1387 bool "Allow Wake-Up from PG04(CAN0_RX)" 1388 depends on PM && BF60x 1389 default n 1390 help 1391 Enable PG04(CAN0_RX) Wake-up 1392 1393config PM_BFIN_WAKE_PG04_POL 1394 int "Wake-up priority" 1395 depends on PM_BFIN_WAKE_PG04 1396 default 0 1397 help 1398 Wake-Up priority 0(low) 1(high) 1399 1400config PM_BFIN_WAKE_PG13 1401 bool "Allow Wake-Up from PG13" 1402 depends on PM && BF60x 1403 default n 1404 help 1405 Enable PG13 Wake-Up 1406 1407config PM_BFIN_WAKE_PG13_POL 1408 int "Wake-up priority" 1409 depends on PM_BFIN_WAKE_PG13 1410 default 0 1411 help 1412 Wake-Up priority 0(low) 1(high) 1413 1414config PM_BFIN_WAKE_USB 1415 bool "Allow Wake-Up from (USB)" 1416 depends on PM && BF60x 1417 default n 1418 help 1419 Enable (USB) Wake-up 1420 1421config PM_BFIN_WAKE_USB_POL 1422 int "Wake-up priority" 1423 depends on PM_BFIN_WAKE_USB 1424 default 0 1425 help 1426 Wake-Up priority 0(low) 1(high) 1427 1428endmenu 1429 1430menu "CPU Frequency scaling" 1431 1432source "drivers/cpufreq/Kconfig" 1433 1434config BFIN_CPU_FREQ 1435 bool 1436 depends on CPU_FREQ 1437 select CPU_FREQ_TABLE 1438 default y 1439 1440config CPU_VOLTAGE 1441 bool "CPU Voltage scaling" 1442 depends on EXPERIMENTAL 1443 depends on CPU_FREQ 1444 default n 1445 help 1446 Say Y here if you want CPU voltage scaling according to the CPU frequency. 1447 This option violates the PLL BYPASS recommendation in the Blackfin Processor 1448 manuals. There is a theoretical risk that during VDDINT transitions 1449 the PLL may unlock. 1450 1451endmenu 1452 1453source "net/Kconfig" 1454 1455source "drivers/Kconfig" 1456 1457source "drivers/firmware/Kconfig" 1458 1459source "fs/Kconfig" 1460 1461source "arch/blackfin/Kconfig.debug" 1462 1463source "security/Kconfig" 1464 1465source "crypto/Kconfig" 1466 1467source "lib/Kconfig" 1468