linux/kernel/time/tick-broadcast.c
<<
v265-ion>tion1 v2.6.32.1 #L22 id="L22 class="line2 namf="L22>2.i2ona2 v class="comment"> * > n value="v2.6.32" ption> > v26< v1 #L32 id="L32 class="line2 namf="L32>2.i3ona2 v class="comment"> * > v26< v1 #L42 id="L42 class="line2 namf="L42>2.i4ona2 v class="comment"> * This file contains funcn>n s which emulate a local clo2" event > v26< v1 #L52 id="L52 class="line2 namf="L52>2.i5ona2 v class="comment"> * device via a ption> event source. > v26< v1 #L62 id="L62 class="line2 namf="L62>2.i6ona2 v class="comment"> * > v26< v1 #L72 id="L72 class="line2 namf="L72>2.i7ona2 v class="comment"> * Copyright(C) 2005-2006, Thomas Gleixner <tglx@> tronix.de> > v26< v1 #L82 id="L82 class="line2 namf="L82>2.i8ona2 v class="comment"> * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar > v26< v1 #L92 id="L92 class="line2 namf="L92>2.i9ona2 v class="comment"> * Copyright(C) 2006-2007, Tv2.sys Corp., Thomas Gleixner > v26< v1 #L102 id="L102 class="line2 namf="L102>2.tiona2 v class="comment"> * > v26< v1 #L112 id="L112 class="line2 namf="L112>2.11ona2 v class="comment"> * This code is l32enced under the GPL verspt 2. For details see > v26< v1 #L122 id="L122 class="line2 namf="L122>2.12ona2 v class="comment"> * value-base/COPYING. > v26< v1 #L132 id="L132 class="line2 namf="L132>2.13ona2 v class="comment"> */ > v26< v1 #L142 id="L142 class="line2 namf="L142>2.14ona2#include << v1 /cpu.h2 class="f> /cpu.hona2>6< v1 #L152 id="L152 class="line2 namf="L152>2.15ona2#include << v1 /err.h2 class="f> /err.hona2>6< v1 #L162 id="L162 class="line2 namf="L162>2.16ona2#include << v1 /hr"v2.r.h2 class="f> /hr"v2.r.hona2>6< v1 #L172 id="L172 class="line2 namf="L172>2.17ona2#include << v1 /interrupt.h2 class="f> /interrupt.hona2>6< v1 #L182 id="L182 class="line2 namf="L182>2.18ona2#include << v1 /percpu.h2 class="f> /percpu.hona2>6< v1 #L192 id="L192 class="line2 namf="L192>2.19ona2#include << v1 /profile.h2 class="f> /profile.hona2>6< v1 #L202 id="L202 class="line2 namf="L202>2.20ona2#include << v1 /sched.h2 class="f> /sched.hona2>6< v1 #L212 id="L212 class="line2 namf="L212>2.21ona26< v1 #L222 id="L222 class="line2 namf="L222>2.22ona2#include "< v1.32" internal.hona2"6< v1 #L232 id="L232 class="line2 namf="L232>2.23ona26< v1 #L242 id="L242 class="line2 namf="L242>2.24ona2 v class="comment">/* > v26< v1 #L252 id="L252 class="line2 namf="L252>2.25ona2 v class="comment"> * Btion> support >ti ptiken x86 hardware, whe v26< v1 #L262 id="L262 class="line2 namf="L262>2.26ona2 v class="comment"> * "v2.r stops in C3 sta.e. > v26< v1 #L272 id="L272 class="line2 namf="L272>2.27ona2 v class="comment"> */ > v26< v1 #L282 id="L282 class="line2 namf="L282>2.28ona26< v1 #L292 id="L292 class="line2 namf="L292>2.29ona2sta.32 struct v1.32"_deviceona2 v1 _device" class="s.32"_ption> _deviceona2;6< v1 #L302 id="L302 class="line2 namf="L302>2.3iona2 v class="comment">/* FIXME: Use cpumask_var_t. */ > v26< v1 #L312 id="L312 class="line2 namf="L312>2.31ona2sta.32 v1DECLARE_BITMAPona2( v1 _mask" class="s.32"_ption> _maskona2, v1NR_CPUSona2);6< v1 #L322 id="L322 class="line2 namf="L322>2.32ona2sta.32 v1DECLARE_BITMAPona2( v1.mpmaskona2, v1NR_CPUSona2);6< v1 #L332 id="L332 class="line2 namf="L332>2.33ona2sta.32 v1DEFINE_RAW_SPINLOCKona2( v1 _lo2"" class="s.32"_ption> _lo2"ona2);6< v1 #L342 id="L342 class="line2 namf="L342>2.34ona2sta.32 int v1 _>tice" class="s.32"_ption> _>ticeona2;6< v1 #L352 id="L352 class="line2 namf="L352>2.35ona26< v1 #L362 id="L362 class="line2 namf="L362>2.36ona2#ifdef v1CONFIG_TICK_ONESHOTona26< v1 #L372 id="L372 class="line2 namf="L372>2.37ona2sta.32 void v1 _clear_oneshot" class="s.32"_ption> _clear_oneshotona2(int v1cpuona2);6< v1 #L382 id="L382 class="line2 namf="L382>2.38ona2#else6< v1 #L392 id="L392 class="line2 namf="L392>2.39ona2sta.32 v1inlineona2 void v1 _clear_oneshot" class="s.32"_ption> _clear_oneshotona2(int v1cpuona2) { }6< v1 #L402 id="L402 class="line2 namf="L402>2.40ona2#endif6< v1 #L412 id="L412 class="line2 namf="L412>2.41ona26< v1 #L422 id="L422 class="line2 namf="L422>2.42ona2 v class="comment">/* > v26< v1 #L432 id="L432 class="line2 namf="L432>2.43ona2 v class="comment"> * Debugging: see "v2.r_li > v26< v1 #L442 id="L442 class="line2 namf="L442>2.44ona2 v class="comment"> */ > v26< v1 #L452 id="L452 class="line2 namf="L452>2.45ona2struct v1.32"_deviceona2 * v1 _device" class="s.32"_get_ption> _deviceona2(void)6< v1 #L462 id="L462 class="line2 namf="L462>2.46ona2{6< v1 #L472 id="L472 class="line2 namf="L472>2.47ona2 return & v1 _device" class="s.32"_ption> _deviceona2;6< v1 #L482 id="L482 class="line2 namf="L482>2.48ona2}6< v1 #L492 id="L492 class="line2 namf="L492>2.49ona26< v1 #L502 id="L502 class="line2 namf="L502>2.50ona2struct v1cpumaskona2 * v1 _mask" class="s.32"_get_ption> _maskona2(void)6< v1 #L512 id="L512 class="line2 namf="L512>2.51ona2{6< v1 #L522 id="L522 class="line2 namf="L522>2.52ona2 return v1.o_cpumaskona2( v1 _mask" class="s.32"_ption> _maskona2);6< v1 #L532 id="L532 class="line2 namf="L532>2.53ona2}6< v1 #L542 id="L542 class="line2 namf="L542>2.54ona26< v1 #L552 id="L552 class="line2 namf="L552>2.55ona2 v class="comment">/* > v26< v1 #L562 id="L562 class="line2 namf="L562>2.56ona2 v class="comment"> * Start the device in period32 mode > v26< v1 #L572 id="L572 class="line2 namf="L572>2.57ona2 v class="comment"> */ > v26< v1 #L582 id="L582 class="line2 namf="L582>2.58ona2sta.32 void v1 _start_period32" class="s.32"_ption> _start_period32ona2(struct v1clo2"_event_deviceona2 * v1b2ona2)6< v1 #L592 id="L592 class="line2 namf="L592>2.59ona2{6< v1 #L602 id="L602 class="line2 namf="L602>2.60ona2 if ( v1b2ona2)6< v1 #L612 id="L612 class="line2 namf="L612>2.61ona2 v1.32"_setup_period32ona2( v1b2ona2, 1);6< v1 #L622 id="L622 class="line2 namf="L622>2.62ona2}6< v1 #L632 id="L632 class="line2 namf="L632>2.63ona26< v1 #L642 id="L642 class="line2 namf="L642>2.64ona2 v class="comment">/* > v26< v1 #L652 id="L652 class="line2 namf="L652>2.65ona2 v class="comment"> * Check, if the device c v be utilized as ption> device: > v26< v1 #L662 id="L662 class="line2 namf="L662>2.66ona2 v class="comment"> */ > v26< v1 #L672 id="L672 class="line2 namf="L672>2.67ona2int v1 _device" class="s.32"_check_ption> _deviceona2(struct v1clo2"_event_deviceona2 * v1devona2)6< v1 #L682 id="L682 class="line2 namf="L682>2.68ona2{6< v1 #L692 id="L692 class="line2 namf="L692>2.69ona2 if (( v1 _device" class="s.32"_ption> _deviceona2. v1evtdevona2 &&6< v1 #L702 id="L702 class="line2 namf="L702>2.70ona2 v1 _device" class="s.32"_ption> _deviceona2. v1evtdevona2-> v1ra.3ngona2 >= v1devona2-> v1ra.3ngona2) ||6< v1 #L712 id="L712 class="line2 namf="L712>2.71ona2 ( v1devona2-> v1featuresona2 & v1CLOCK_EVT_FEAT_C3STOPona2))6< v1 #L722 id="L722 class="line2 namf="L722>2.72ona2 return 0;6< v1 #L732 id="L732 class="line2 namf="L732>2.73ona26< v1 #L742 id="L742 class="line2 namf="L742>2.74ona2 v1clo2"events_exchange_deviceona2( v1 _device" class="s.32"_ption> _deviceona2. v1evtdevona2, v1devona2);6< v1 #L752 id="L752 class="line2 namf="L752>2.75ona2 v1 _device" class="s.32"_ption> _deviceona2. v1evtdevona2 = v1devona2;6< v1 #L762 id="L762 class="line2 namf="L762>2.76ona2 if (! v1cpumask_emptyona2( v1 _mask" class="s.32"_get_ption> _maskona2()))6< v1 #L772 id="L772 class="line2 namf="L772>2.77ona2 v1 _start_period32" class="s.32"_ption> _start_period32ona2( v1devona2);6< v1 #L782 id="L782 class="line2 namf="L782>2.78ona2 return 1;6< v1 #L792 id="L792 class="line2 namf="L792>2.79ona2}6< v1 #L802 id="L802 class="line2 namf="L802>2.80ona26< v1 #L812 id="L812 class="line2 namf="L812>2.81ona2 v class="comment">/* > v26< v1 #L822 id="L822 class="line2 namf="L822>2.82ona2 v class="comment"> * Check, if the device is the ption> device > v26< v1 #L832 id="L832 class="line2 namf="L832>2.83ona2 v class="comment"> */ > v26< v1 #L842 id="L842 class="line2 namf="L842>2.84ona2int v1 _device" class="s.32"_is_ption> _deviceona2(struct v1clo2"_event_deviceona2 * v1devona2)6< v1 #L852 id="L852 class="line2 namf="L852>2.85ona2{6< v1 #L862 id="L862 class="line2 namf="L862>2.86ona2 return ( v1devona2 && v1 _device" class="s.32"_ption> _deviceona2. v1evtdevona2 == v1devona2);6< v1 #L872 id="L872 class="line2 namf="L872>2.87ona2}6< v1 #L882 id="L882 class="line2 namf="L882>2.88ona26< v1 #L892 id="L892 class="line2 namf="L892>2.89ona2 v class="comment">/* > v26< v1 #L902 id="L902 class="line2 namf="L902>2.9iona2 v class="comment"> * Check, if the device is disfuncn>n al and a place holder, which > v26< v1 #L912 id="L912 class="line2 namf="L912>2.91ona2 v class="comment"> * needs to be handled by the ption> device. > v26< v1 #L922 id="L922 class="line2 namf="L922>2.92ona2 v class="comment"> */ > v26< v1 #L932 id="L932 class="line2 namf="L932>2.93ona2int v1 " class="s.32"_device_uses_ption> ona2(struct v1clo2"_event_deviceona2 * v1devona2, int v1cpuona2)6< v1 #L942 id="L942 class="line2 namf="L942>2.94ona2{6< v1 #L952 id="L952 class="line2 namf="L952>2.95ona2 unsigned long v1flagsona2;6< v1 #L962 id="L962 class="line2 namf="L962>2.96ona2 int v1re ona2 = 0;6< v1 #L972 id="L972 class="line2 namf="L972>2.97ona26< v1 #L982 id="L982 class="line2 namf="L982>2.98ona2 v1raw_spin_lo2"_irqsaveona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona2);6< v1 #L992 id="L992 class="line2 namf="L992>2.99ona26< v1 #L1002 id="L1002 class="line2 namf="L1002>2100ona2 v class="comment">/* > v26< v1 #L1012 id="L1012 class="line2 namf="L1012>2101ona2 v class="comment"> * Devices might be registered with both period32 and oneshoton v26< v1 #L1022 id="L1022 class="line2 namf="L1022>2102ona2 v class="comment"> * mode disabled. This signals, that the device needs to beon v26< v1 #L1032 id="L1032 class="line2 namf="L1032>2103ona2 v class="comment"> * operated from the ption> device and is a placeholder >tion v26< v1 #L1042 id="L1042 class="line2 namf="L1042>2104ona2 v class="comment"> * the cpu local device. > v26< v1 #L1052 id="L1052 class="line2 namf="L1052>2105ona2 v class="comment"> */ > v26< v1 #L1062 id="L1062 class="line2 namf="L1062>2106ona2 if (! v1n al" class="s.32"_device_is_funcn>n alona2( v1devona2)) {6< v1 #L1072 id="L1072 class="line2 namf="L1072>2107ona2 v1devona2-> v1event_handlerona2 = v1.32"_handle_period32ona2;6< v1 #L1082 id="L1082 class="line2 namf="L1082>2108ona2 v1cpumask_set_cpuona2( v1cpuona2, v1 _mask" class="s.32"_get_ption> _maskona2());6< v1 #L1092 id="L1092 class="line2 namf="L1092>2109ona2 v1 _start_period32" class="s.32"_ption> _start_period32ona2( v1 _device" class="s.32"_ption> _deviceona2. v1evtdevona2);6< v1 #L1102 id="L1102 class="line2 namf="L1102>2110ona2 v1re ona2 = 1;6< v1 #L1112 id="L1112 class="line2 namf="L1112>2111ona2 } else {6< v1 #L1122 id="L1122 class="line2 namf="L1122>2112ona2 v class="comment">/* > v26< v1 #L1132 id="L1132 class="line2 namf="L1132>2113ona2 v class="comment"> * When the new device is not affected by the stop > v26< v1 #L1142 id="L1142 class="line2 namf="L1142>2114ona2 v class="comment"> * feature and the cpu is marked in the ption> maskon v26< v1 #L1152 id="L1152 class="line2 namf="L1152>2115ona2 v class="comment"> * then clear the ption> bit. > v26< v1 #L1162 id="L1162 class="line2 namf="L1162>2116ona2 v class="comment"> */ > v26< v1 #L1172 id="L1172 class="line2 namf="L1172>2117ona2 if (!( v1devona2-> v1featuresona2 & v1CLOCK_EVT_FEAT_C3STOPona2)) {6< v1 #L1182 id="L1182 class="line2 namf="L1182>2118ona2 int v1cpuona2 = v1smp_processor_idona2();6< v1 #L1192 id="L1192 class="line2 namf="L1192>2119ona26< v1 #L1202 id="L1202 class="line2 namf="L1202>2120ona2 v1cpumask_clear_cpuona2( v1cpuona2, v1 _mask" class="s.32"_get_ption> _maskona2());6< v1 #L1212 id="L1212 class="line2 namf="L1212>2121ona2 v1 _clear_oneshot" class="s.32"_ption> _clear_oneshotona2( v1cpuona2);6< v1 #L1222 id="L1222 class="line2 namf="L1222>2122ona2 }6< v1 #L1232 id="L1232 class="line2 namf="L1232>2123ona2 }6< v1 #L1242 id="L1242 class="line2 namf="L1242>2124ona2 v1raw_spin_unlo2"_irqrestoreona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona2);6< v1 #L1252 id="L1252 class="line2 namf="L1252>2125ona2 return v1re ona2;6< v1 #L1262 id="L1262 class="line2 namf="L1262>2126ona2}6< v1 #L1272 id="L1272 class="line2 namf="L1272>2127ona26< v1 #L1282 id="L1282 class="line2 namf="L1282>2128ona2 v class="comment">/* > v26< v1 #L1292 id="L1292 class="line2 namf="L1292>2129ona2 v class="comment"> * Btion> the event to the cpus, which are set in the mask (mangled). > v26< v1 #L1302 id="L1302 class="line2 namf="L1302>213iona2 v class="comment"> */ > v26< v1 #L1312 id="L1312 class="line2 namf="L1312>2131ona2sta.32 void v1 " class="s.32"_do_ption> ona2(struct v1cpumaskona2 * v1maskona2)6< v1 #L1322 id="L1322 class="line2 namf="L1322>2132ona2{6< v1 #L1332 id="L1332 class="line2 namf="L1332>2133ona2 int v1cpuona2 = v1smp_processor_idona2();6< v1 #L1342 id="L1342 class="line2 namf="L1342>2134ona2 struct v1.32"_deviceona2 * v1tdona2;6< v1 #L1352 id="L1352 class="line2 namf="L1352>2135ona26< v1 #L1362 id="L1362 class="line2 namf="L1362>2136ona2 v class="comment">/* > v26< v1 #L1372 id="L1372 class="line2 namf="L1372>2137ona2 v class="comment"> * Check, if the current cpu is in the mask > v26< v1 #L1382 id="L1382 class="line2 namf="L1382>2138ona2 v class="comment"> */ > v26< v1 #L1392 id="L1392 class="line2 namf="L1392>2139ona2 if ( v1cpumask_test_cpuona2( v1cpuona2, v1maskona2)) {6< v1 #L1402 id="L1402 class="line2 namf="L1402>2140ona2 v1cpumask_clear_cpuona2( v1cpuona2, v1maskona2);6< v1 #L1412 id="L1412 class="line2 namf="L1412>2141ona2 v1tdona2 = & v1per_cpuona2( v1.32"_cpu_deviceona2, v1cpuona2);6< v1 #L1422 id="L1422 class="line2 namf="L1422>2142ona2 v1tdona2-> v1evtdevona2-> v1event_handlerona2( v1tdona2-> v1evtdevona2);6< v1 #L1432 id="L1432 class="line2 namf="L1432>2143ona2 }6< v1 #L1442 id="L1442 class="line2 namf="L1442>2144ona26< v1 #L1452 id="L1452 class="line2 namf="L1452>2145ona2 if (! v1cpumask_emptyona2( v1maskona2)) {6< v1 #L1462 id="L1462 class="line2 namf="L1462>2146ona2 v class="comment">/* > v26< v1 #L1472 id="L1472 class="line2 namf="L1472>2147ona2 v class="comment"> * It might be necessary to actually check whether the devices > v26< v1 #L1482 id="L1482 class="line2 namf="L1482>2148ona2 v class="comment"> * have different ption> funcn>n s. For now, ju us/ the > v26< v1 #L1492 id="L1492 class="line2 namf="L1492>2149ona2 v class="comment"> * one of the fir device. This works as long as we have this > v26< v1 #L1502 id="L1502 class="line2 namf="L1502>215iona2 v class="comment"> * misfeature only on x86 (lapi ) > v26< v1 #L1512 id="L1512 class="line2 namf="L1512>2151ona2 v class="comment"> */ > v26< v1 #L1522 id="L1522 class="line2 namf="L1522>2152ona2 v1tdona2 = & v1per_cpuona2( v1.32"_cpu_deviceona2, v1cpumask_fir ona2( v1maskona2));6< v1 #L1532 id="L1532 class="line2 namf="L1532>2153ona2 v1tdona2-> v1evtdevona2-> v1 " class="sption> ona2( v1maskona2);6< v1 #L1542 id="L1542 class="line2 namf="L1542>2154ona2 }6< v1 #L1552 id="L1552 class="line2 namf="L1552>2155ona2}6< v1 #L1562 id="L1562 class="line2 namf="L1562>2156ona26< v1 #L1572 id="L1572 class="line2 namf="L1572>2157ona2 v class="comment">/* > v26< v1 #L1582 id="L1582 class="line2 namf="L1582>2158ona2 v class="comment"> * Period32 ption> : > v26< v1 #L1592 id="L1592 class="line2 namf="L1592>2159ona2 v class="comment"> * - invoke the ption> handlers > v26< v1 #L1602 id="L1602 class="line2 namf="L1602>216iona2 v class="comment"> */ > v26< v1 #L1612 id="L1612 class="line2 namf="L1612>2161ona2sta.32 void v1 " class="s.32"_do_period32_ption> ona2(void)6< v1 #L1622 id="L1622 class="line2 namf="L1622>2162ona2{6< v1 #L1632 id="L1632 class="line2 namf="L1632>2163ona2 v1raw_spin_lo2"ona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2);6< v1 #L1642 id="L1642 class="line2 namf="L1642>2164ona26< v1 #L1652 id="L1652 class="line2 namf="L1652>2165ona2 v1cpumask_andona2( v1.o_cpumaskona2( v1.mpmaskona2),6< v1 #L1662 id="L1662 class="line2 namf="L1662>2166ona2 v1cpu_online_maskona2, v1 _mask" class="s.32"_get_ption> _maskona2());6< v1 #L1672 id="L1672 class="line2 namf="L1672>2167ona2 v1 " class="s.32"_do_ption> ona2( v1.o_cpumaskona2( v1.mpmaskona2));6< v1 #L1682 id="L1682 class="line2 namf="L1682>2168ona26< v1 #L1692 id="L1692 class="line2 namf="L1692>2169ona2 v1raw_spin_unlo2"ona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2);6< v1 #L1702 id="L1702 class="line2 namf="L1702>2170ona2}6< v1 #L1712 id="L1712 class="line2 namf="L1712>2171ona26< v1 #L1722 id="L1722 class="line2 namf="L1722>2172ona2 v class="comment">/* > v26< v1 #L1732 id="L1732 class="line2 namf="L1732>2173ona2 v class="comment"> * Event handler >ti period32 ption> .32"s > v26< v1 #L1742 id="L1742 class="line2 namf="L1742>2174ona2 v class="comment"> */ > v26< v1 #L1752 id="L1752 class="line2 namf="L1752>2175ona2sta.32 void v1 " class="s.32"_handle_period32_ption> ona2(struct v1clo2"_event_deviceona2 * v1devona2)6< v1 #L1762 id="L1762 class="line2 namf="L1762>2176ona2{6< v1 #L1772 id="L1772 class="line2 namf="L1772>2177ona2 v1k"v2._ ona2 v1nextona2;6< v1 #L1782 id="L1782 class="line2 namf="L1782>2178ona26< v1 #L1792 id="L1792 class="line2 namf="L1792>2179ona2 v1 " class="s.32"_do_period32_ption> ona2();6< v1 #L1802 id="L1802 class="line2 namf="L1802>2180ona26< v1 #L1812 id="L1812 class="line2 namf="L1812>2181ona2 v class="comment">/* > v26< v1 #L1822 id="L1822 class="line2 namf="L1822>2182ona2 v class="comment"> * The device is in period32 mode. No reprogramming necessary: > v26< v1 #L1832 id="L1832 class="line2 namf="L1832>2183ona2 v class="comment"> */ > v26< v1 #L1842 id="L1842 class="line2 namf="L1842>2184ona2 if ( v1devona2-> v1modeona2 == v1CLOCK_EVT_MODE_PERIODICona2)6< v1 #L1852 id="L1852 class="line2 namf="L1852>2185ona2 return;6< v1 #L1862 id="L1862 class="line2 namf="L1862>2186ona26< v1 #L1872 id="L1872 class="line2 namf="L1872>2187ona2 v class="comment">/* > v26< v1 #L1882 id="L1882 class="line2 namf="L1882>2188ona2 v class="comment"> * Setup the next period >ti devices, which do not haveon v26< v1 #L1892 id="L1892 class="line2 namf="L1892>2189ona2 v class="comment"> * period32 mode. We read dev->next_event fir and add to iton v26< v1 #L1902 id="L1902 class="line2 namf="L1902>219iona2 v class="comment"> * when the event already expired. clo2"events_program_event() > v26< v1 #L1912 id="L1912 class="line2 namf="L1912>2191ona2 v class="comment"> * sets dev->next_event only when the event is really > v26< v1 #L1922 id="L1922 class="line2 namf="L1922>2192ona2 v class="comment"> * programmed to the device. > v26< v1 #L1932 id="L1932 class="line2 namf="L1932>2193ona2 v class="comment"> */ > v26< v1 #L1942 id="L1942 class="line2 namf="L1942>2194ona2 >ti ( v1nextona2 = v1devona2-> v1next_event >a2; ;) {6< v1 #L1952 id="L1952 class="line2 namf="L1952>2195ona2 v1nextona2 = v1k"v2._addona2( v1nextona2, v1.32"_periodona2);6< v1 #L1962 id="L1962 class="line2 namf="L1962>2196ona26< v1 #L1972 id="L1972 class="line2 namf="L1972>2197ona2 if (! v1clo2"events_program_eventona2( v1devona2, v1nextona2, v1falseona2))6< v1 #L1982 id="L1982 class="line2 namf="L1982>2198ona2 return;6< v1 #L1992 id="L1992 class="line2 namf="L1992>2199ona2 v1 " class="s.32"_do_period32_ption> ona2();6< v1 #L2002 id="L2002 class="line2 namf="L2002>2200ona2 }6< v1 #L2012 id="L2012 class="line2 namf="L2012>2201ona2}6< v1 #L2022 id="L2022 class="line2 namf="L2022>2202ona26< v1 #L2032 id="L2032 class="line2 namf="L2032>2203ona2 v class="comment">/* > v26< v1 #L2042 id="L2042 class="line2 namf="L2042>2204ona2 v class="comment"> * Powersta.e in>timan>n : The system enters/leaves a sta.e, whe v26< v1 #L2052 id="L2052 class="line2 namf="L2052>2205ona2 v class="comment"> * affected devices might stop > v26< v1 #L2062 id="L2062 class="line2 namf="L2062>2206ona2 v class="comment"> */ > v26< v1 #L2072 id="L2072 class="line2 namf="L2072>2207ona2sta.32 void v1 _on_off" class="s.32"_do_ption> _on_offona2(unsigned long * v1reasonona2)6< v1 #L2082 id="L2082 class="line2 namf="L2082>2208ona2{6< v1 #L2092 id="L2092 class="line2 namf="L2092>2209ona2 struct v1clo2"_event_deviceona2 * v1b2ona2, * v1devona2;6< v1 #L2102 id="L2102 class="line2 namf="L2102>2210ona2 struct v1.32"_deviceona2 * v1tdona2;6< v1 #L2112 id="L2112 class="line2 namf="L2112>2211ona2 unsigned long v1flagsona2;6< v1 #L2122 id="L2122 class="line2 namf="L2122>2212ona2 int v1cpuona2, v1bc_stoppedona2;6< v1 #L2132 id="L2132 class="line2 namf="L2132>2213ona26< v1 #L2142 id="L2142 class="line2 namf="L2142>2214ona2 v1raw_spin_lo2"_irqsaveona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona2);6< v1 #L2152 id="L2152 class="line2 namf="L2152>2215ona26< v1 #L2162 id="L2162 class="line2 namf="L2162>2216ona2 v1cpuona2 = v1smp_processor_idona2();6< v1 #L2172 id="L2172 class="line2 namf="L2172>2217ona2 v1tdona2 = & v1per_cpuona2( v1.32"_cpu_deviceona2, v1cpuona2);6< v1 #L2182 id="L2182 class="line2 namf="L2182>2218ona2 v1devona2 = v1tdona2-> v1evtdevona2;6< v1 #L2192 id="L2192 class="line2 namf="L2192>2219ona2 v1b2ona2 = v1 _device" class="s.32"_ption> _deviceona2. v1evtdevona2;6< v1 #L2202 id="L2202 class="line2 namf="L2202>2220ona26< v1 #L2212 id="L2212 class="line2 namf="L2212>2221ona2 v class="comment">/* > v26< v1 #L2222 id="L2222 class="line2 namf="L2222>2222ona2 v class="comment"> * Is the device not affected by the powersta.e ? > v26< v1 #L2232 id="L2232 class="line2 namf="L2232>2223ona2 v class="comment"> */ > v26< v1 #L2242 id="L2242 class="line2 namf="L2242>2224ona2 if (! v1devona2 || !( v1devona2-> v1featuresona2 & v1CLOCK_EVT_FEAT_C3STOPona2))6< v1 #L2252 id="L2252 class="line2 namf="L2252>2225ona2 goto v1ou ona2;6< v1 #L2262 id="L2262 class="line2 namf="L2262>2226ona26< v1 #L2272 id="L2272 class="line2 namf="L2272>2227ona2 if (! v1n al" class="s.32"_device_is_funcn>n alona2( v1devona2))6< v1 #L2282 id="L2282 class="line2 namf="L2282>2228ona2 goto v1ou ona2;6< v1 #L2292 id="L2292 class="line2 namf="L2292>2229ona26< v1 #L2302 id="L2302 class="line2 namf="L2302>2230ona2 v1bc_stoppedona2 = v1cpumask_emptyona2( v1 _mask" class="s.32"_get_ption> _maskona2());6< v1 #L2312 id="L2312 class="line2 namf="L2312>2231ona26< v1 #L2322 id="L2322 class="line2 namf="L2322>2232ona2 switch (* v1reasonona2) {6< v1 #L2332 id="L2332 class="line2 namf="L2332>2233ona2 > e v1CLOCK_EVT_NOTIFY_BROADCAST_ONona2:6< v1 #L2342 id="L2342 class="line2 namf="L2342>2234ona2 > e v1CLOCK_EVT_NOTIFY_BROADCAST_FORCEona2:6< v1 #L2352 id="L2352 class="line2 namf="L2352>2235ona2 if (! v1cpumask_test_cpuona2( v1cpuona2, v1 _mask" class="s.32"_get_ption> _maskona2())) {6< v1 #L2362 id="L2362 class="line2 namf="L2362>2236ona2 v1cpumask_set_cpuona2( v1cpuona2, v1 _mask" class="s.32"_get_ption> _maskona2());6< v1 #L2372 id="L2372 class="line2 namf="L2372>2237ona2 if ( v1 _device" class="s.32"_ption> _deviceona2. v1modeona2 ==6< v1 #L2382 id="L2382 class="line2 namf="L2382>2238ona2 v1TICKDEV_MODE_PERIODICona2)6< v1 #L2392 id="L2392 class="line2 namf="L2392>2239ona2 v1clo2"events_shutdownona2( v1devona2);6< v1 #L2402 id="L2402 class="line2 namf="L2402>2240ona2 }6< v1 #L2412 id="L2412 class="line2 namf="L2412>2241ona2 if (* v1reasonona2 == v1CLOCK_EVT_NOTIFY_BROADCAST_FORCEona2)6< v1 #L2422 id="L2422 class="line2 namf="L2422>2242ona2 v1 _force" class="s.32"_ption> _forceona2 = 1;6< v1 #L2432 id="L2432 class="line2 namf="L2432>2243ona2 break;6< v1 #L2442 id="L2442 class="line2 namf="L2442>2244ona2 > e v1CLOCK_EVT_NOTIFY_BROADCAST_OFFona2:6< v1 #L2452 id="L2452 class="line2 namf="L2452>2245ona2 if (! v1 _force" class="s.32"_ption> _forceona2 &&6< v1 #L2462 id="L2462 class="line2 namf="L2462>2246ona2 v1cpumask_test_cpuona2( v1cpuona2, v1 _mask" class="s.32"_get_ption> _maskona2())) {6< v1 #L2472 id="L2472 class="line2 namf="L2472>2247ona2 v1cpumask_clear_cpuona2( v1cpuona2, v1 _mask" class="s.32"_get_ption> _maskona2());6< v1 #L2482 id="L2482 class="line2 namf="L2482>2248ona2 if ( v1 _device" class="s.32"_ption> _deviceona2. v1modeona2 ==6< v1 #L2492 id="L2492 class="line2 namf="L2492>2249ona2 v1TICKDEV_MODE_PERIODICona2)6< v1 #L2502 id="L2502 class="line2 namf="L2502>2250ona2 v1.32"_setup_period32ona2( v1devona2, 0);6< v1 #L2512 id="L2512 class="line2 namf="L2512>2251ona2 }6< v1 #L2522 id="L2522 class="line2 namf="L2522>2252ona2 break;6< v1 #L2532 id="L2532 class="line2 namf="L2532>2253ona2 }6< v1 #L2542 id="L2542 class="line2 namf="L2542>2254ona26< v1 #L2552 id="L2552 class="line2 namf="L2552>2255ona2 if ( v1cpumask_emptyona2( v1 _mask" class="s.32"_get_ption> _maskona2())) {6< v1 #L2562 id="L2562 class="line2 namf="L2562>2256ona2 if (! v1bc_stoppedona2)6< v1 #L2572 id="L2572 class="line2 namf="L2572>2257ona2 v1clo2"events_shutdownona2( v1b2ona2);6< v1 #L2582 id="L2582 class="line2 namf="L2582>2258ona2 } else if ( v1bc_stoppedona2) {6< v1 #L2592 id="L2592 class="line2 namf="L2592>2259ona2 if ( v1 _device" class="s.32"_ption> _deviceona2. v1modeona2 == v1TICKDEV_MODE_PERIODICona2)6< v1 #L2602 id="L2602 class="line2 namf="L2602>2260ona2 v1 _start_period32" class="s.32"_ption> _start_period32ona2( v1b2ona2);6< v1 #L2612 id="L2612 class="line2 namf="L2612>2261ona2 else6< v1 #L2622 id="L2622 class="line2 namf="L2622>2262ona2 v1 _setup_oneshot" class="s.32"_ption> _setup_oneshotona2( v1b2ona2);6< v1 #L2632 id="L2632 class="line2 namf="L2632>2263ona2 }6< v1 #L2642 id="L2642 class="line2 namf="L2642>2264ona2 v1ou ona2:6< v1 #L2652 id="L2652 class="line2 namf="L2652>2265ona2 v1raw_spin_unlo2"_irqrestoreona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona2);6< v1 #L2662 id="L2662 class="line2 namf="L2662>2266ona2}6< v1 #L2672 id="L2672 class="line2 namf="L2672>2267ona26< v1 #L2682 id="L2682 class="line2 namf="L2682>2268ona2 v class="comment">/* > v26< v1 #L2692 id="L2692 class="line2 namf="L2692>2269ona2 v class="comment"> * Powersta.e in>timan>n : The system enters/leaves a sta.e, whe v26< v1 #L2702 id="L2702 class="line2 namf="L2702>227iona2 v class="comment"> * affected devices might stop. > v26< v1 #L2712 id="L2712 class="line2 namf="L2712>2271ona2 v class="comment"> */ > v26< v1 #L2722 id="L2722 class="line2 namf="L2722>2272ona2void v1 _on_off" class="s.32"_ption> _on_offona2(unsigned long v1reasonona2, int * v1oncpuona2)6< v1 #L2732 id="L2732 class="line2 namf="L2732>2273ona2{6< v1 #L2742 id="L2742 class="line2 namf="L2742>2274ona2 if (! v1cpumask_test_cpuona2(* v1oncpuona2, v1cpu_online_maskona2))6< v1 #L2752 id="L2752 class="line2 namf="L2752>2275ona2 v1printkona2( v1KERN_ERRona2 v class="string">".32" ption> : ignoring ption> for " > v26< v1 #L2762 id="L2762 class="line2 namf="L2762>2276ona2 v class="string">"offline CPU #%d\n" > v2, * v1oncpuona2);6< v1 #L2772 id="L2772 class="line2 namf="L2772>2277ona2 else6< v1 #L2782 id="L2782 class="line2 namf="L2782>2278ona2 v1 _on_off" class="s.32"_do_ption> _on_offona2(& v1reasonona2);6< v1 #L2792 id="L2792 class="line2 namf="L2792>2279ona2}6< v1 #L2802 id="L2802 class="line2 namf="L2802>2280ona26< v1 #L2812 id="L2812 class="line2 namf="L2812>2281ona2 v class="comment">/* > v26< v1 #L2822 id="L2822 class="line2 namf="L2822>2282ona2 v class="comment"> * Set the period32 handler depending on ption> on/offon v26< v1 #L2832 id="L2832 class="line2 namf="L2832>2283ona2 v class="comment"> */ > v26< v1 #L2842 id="L2842 class="line2 namf="L2842>2284ona2void v1.32"_set_period32_handlerona2(struct v1clo2"_event_deviceona2 * v1devona2, int v1 " class="sbtion> ona2)6< v1 #L2852 id="L2852 class="line2 namf="L2852>2285ona2{6< v1 #L2862 id="L2862 class="line2 namf="L2862>2286ona2 if (! v1 " class="sbtion> ona2)6< v1 #L2872 id="L2872 class="line2 namf="L2872>2287ona2 v1devona2-> v1event_handlerona2 = v1.32"_handle_period32ona2;6< v1 #L2882 id="L2882 class="line2 namf="L2882>2288ona2 else6< v1 #L2892 id="L2892 class="line2 namf="L2892>2289ona2 v1devona2-> v1event_handlerona2 = v1 " class="s.32"_handle_period32_ption> ona2;6< v1 #L2902 id="L2902 class="line2 namf="L2902>2290ona2}6< v1 #L2912 id="L2912 class="line2 namf="L2912>2291ona26< v1 #L2922 id="L2922 class="line2 namf="L2922>2292ona2 v class="comment">/* > v26< v1 #L2932 id="L2932 class="line2 namf="L2932>2293ona2 v class="comment"> * Remove a CPU from ption> ing > v26< v1 #L2942 id="L2942 class="line2 namf="L2942>2294ona2 v class="comment"> */ > v26< v1 #L2952 id="L2952 class="line2 namf="L2952>2295ona2void v1 " class="s.32"_shutdown_ption> ona2(unsigned int * v1cpupona2)6< v1 #L2962 id="L2962 class="line2 namf="L2962>2296ona2{6< v1 #L2972 id="L2972 class="line2 namf="L2972>2297ona2 struct v1clo2"_event_deviceona2 * v1b2ona2;6< v1 #L2982 id="L2982 class="line2 namf="L2982>2298ona2 unsigned long v1flagsona2;6< v1 #L2992 id="L2992 class="line2 namf="L2992>2299ona2 unsigned int v1cpuona2 = * v1cpupona2;6< v1 #L3002 id="L3002 class="line2 namf="L3002>2300ona26< v1 #L3012 id="L3012 class="line2 namf="L3012>2301ona2 v1raw_spin_lo2"_irqsaveona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona2);6< v1 #L3022 id="L3022 class="line2 namf="L3022>2302ona26< v1 #L3032 id="L3032 class="line2 namf="L3032>2303ona2 v1b2ona2 = v1 _device" class="s.32"_ption> _deviceona2. v1evtdevona2;6< v1 #L3042 id="L3042 class="line2 namf="L3042>2304ona2 v1cpumask_clear_cpuona2( v1cpuona2, v1 _mask" class="s.32"_get_ption> _maskona2());6< v1 #L3052 id="L3052 class="line2 namf="L3052>2305ona26< v1 #L3062 id="L3062 class="line2 namf="L3062>2306ona2 if ( v1 _device" class="s.32"_ption> _deviceona2. v1modeona2 == v1TICKDEV_MODE_PERIODICona2) {6< v1 #L3072 id="L3072 class="line2 namf="L3072>2307ona2 if ( v1b2ona2 && v1cpumask_emptyona2( v1 _mask" class="s.32"_get_ption> _maskona2()))6< v1 #L3082 id="L3082 class="line2 namf="L3082>2308ona2 v1clo2"events_shutdownona2( v1b2ona2);6< v1 #L3092 id="L3092 class="line2 namf="L3092>2309ona2 }6< v1 #L3102 id="L3102 class="line2 namf="L3102>2310ona26< v1 #L3112 id="L3112 class="line2 namf="L3112>2311ona2 v1raw_spin_unlo2"_irqrestoreona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona2);6< v1 #L3122 id="L3122 class="line2 namf="L3122>2312ona2}6< v1 #L3132 id="L3132 class="line2 namf="L3132>2313ona26< v1 #L3142 id="L3142 class="line2 namf="L3142>2314ona2void v1 " class="s.32"_suspend_ption> ona2(void)6< v1 #L3152 id="L3152 class="line2 namf="L3152>2315ona2{6< v1 #L3162 id="L3162 class="line2 namf="L3162>2316ona2 struct v1clo2"_event_deviceona2 * v1b2ona2;6< v1 #L3172 id="L3172 class="line2 namf="L3172>2317ona2 unsigned long v1flagsona2;6< v1 #L3182 id="L3182 class="line2 namf="L3182>2318ona26< v1 #L3192 id="L3192 class="line2 namf="L3192>2319ona2 v1raw_spin_lo2"_irqsaveona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona2);6< v1 #L3202 id="L3202 class="line2 namf="L3202>2320ona26< v1 #L3212 id="L3212 class="line2 namf="L3212>2321ona2 v1b2ona2 = v1 _device" class="s.32"_ption> _deviceona2. v1evtdevona2;6< v1 #L3222 id="L3222 class="line2 namf="L3222>2322ona2 if ( v1b2ona2)6< v1 #L3232 id="L3232 class="line2 namf="L3232>2323ona2 v1clo2"events_shutdownona2( v1b2ona2);6< v1 #L3242 id="L3242 class="line2 namf="L3242>2324ona26< v1 #L3252 id="L3252 class="line2 namf="L3252>2325ona2 v1raw_spin_unlo2"_irqrestoreona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona2);6< v1 #L3262 id="L3262 class="line2 namf="L3262>2326ona2}6< v1 #L3272 id="L3272 class="line2 namf="L3272>2327ona26< v1 #L3282 id="L3282 class="line2 namf="L3282>2328ona2int v1 " class="s.32"_resume_ption> ona2(void)6< v1 #L3292 id="L3292 class="line2 namf="L3292>2329ona2{6< v1 #L3302 id="L3302 class="line2 namf="L3302>2330ona2 struct v1clo2"_event_deviceona2 * v1b2ona2;6< v1 #L3312 id="L3312 class="line2 namf="L3312>2331ona2 unsigned long v1flagsona2;6< v1 #L3322 id="L3322 class="line2 namf="L3322>2332ona2 int v1 " class="sbtion> ona2 = 0;6< v1 #L3332 id="L3332 class="line2 namf="L3332>2333ona26< v1 #L3342 id="L3342 class="line2 namf="L3342>2334ona2 v1raw_spin_lo2"_irqsaveona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona2);6< v1 #L3352 id="L3352 class="line2 namf="L3352>2335ona26< v1 #L3362 id="L3362 class="line2 namf="L3362>2336ona2 v1b2ona2 = v1 _device" class="s.32"_ption> _deviceona2. v1evtdevona2;6< v1 #L3372 id="L3372 class="line2 namf="L3372>2337ona26< v1 #L3382 id="L3382 class="line2 namf="L3382>2338ona2 if ( v1b2ona2) {6< v1 #L3392 id="L3392 class="line2 namf="L3392>2339ona2 v1clo2"events_set_modeona2( v1b2ona2, v1CLOCK_EVT_MODE_RESUMEona2);6< v1 #L3402 id="L3402 class="line2 namf="L3402>2340ona26< v1 #L3412 id="L3412 class="line2 namf="L3412>2341ona2 switch ( v1 _device" class="s.32"_ption> _deviceona2. v1modeona2) {6< v1 #L3422 id="L3422 class="line2 namf="L3422>2342ona2 c e v1TICKDEV_MODE_PERIODICona2:6< v1 #L3432 id="L3432 class="line2 namf="L3432>2343ona2 if (! v1cpumask_emptyona2( v1 _mask" class="s.32"_get_ption> _maskona2()))6< v1 #L3442 id="L3442 class="line2 namf="L3442>2344ona2 v1 _start_period32" class="s.32"_ption> _start_period32ona2( v1b2ona2);6< v1 #L3452 id="L3452 class="line2 namf="L3452>2345ona2 v1 " class="sbtion> ona2 = v1cpumask_test_cpuona2( v1smp_processor_idona2(),6< v1 #L3462 id="L3462 class="line2 namf="L3462>2346ona2 v1 _mask" class="s.32"_get_ption> _maskona2());6< v1 #L3472 id="L3472 class="line2 namf="L3472>2347ona2 break;6< v1 #L3482 id="L3482 class="line2 namf="L3482>2348ona2 c e v1TICKDEV_MODE_ONESHOTona2:6< v1 #L3492 id="L3492 class="line2 namf="L3492>2349ona2 if (! v1cpumask_emptyona2( v1 _mask" class="s.32"_get_ption> _maskona2()))6< v1 #L3502 id="L3502 class="line2 namf="L3502>2350ona2 v1 " class="sbtion> ona2 = v1 _oneshot" class="s.32"_resume_ption> _oneshotona2( v1b2ona2);6< v1 #L3512 id="L3512 class="line2 namf="L3512>2351ona2 break;6< v1 #L3522 id="L3522 class="line2 namf="L3522>2352ona2 }6< v1 #L3532 id="L3532 class="line2 namf="L3532>2353ona2 }6< v1 #L3542 id="L3542 class="line2 namf="L3542>2354ona2 v1raw_spin_unlo2"_irqrestoreona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona2);6< v1 #L3552 id="L3552 class="line2 namf="L3552>2355ona26< v1 #L3562 id="L3562 class="line2 namf="L3562>2356ona2 return v1 " class="sbtion> ona2;6< v1 #L3572 id="L3572 class="line2 namf="L3572>2357ona2}6< v1 #L3582 id="L3582 class="line2 namf="L3582>2358ona26< v1 #L3592 id="L3592 class="line2 namf="L3592>2359ona26< v1 #L3602 id="L3602 class="line2 namf="L3602>2360ona2#ifdef v1CONFIG_TICK_ONESHOTona26< v1 #L3612 id="L3612 class="line2 namf="L3612>2361ona26< v1 #L3622 id="L3622 class="line2 namf="L3622>2362ona2 v class="comment">/* FIXME: u e cpumask_var_t. */ > v26< v1 #L3632 id="L3632 class="line2 namf="L3632>2363ona2sta.32 v1DECLARE_BITMAPona2( v1 _oneshot_mask" class="s.32"_ption> _oneshot_maskona2, v1NR_CPUSona2);6< v1 #L3642 id="L3642 class="line2 namf="L3642>2364ona26< v1 #L3652 id="L3652 class="line2 namf="L3652>2365ona2 v class="comment">/* > v26< v1 #L3662 id="L3662 class="line2 namf="L3662>2366ona2 v class="comment"> * Exposed >ti debugging: see "v2.r_li > v26< v1 #L3672 id="L3672 class="line2 namf="L3672>2367ona2 v class="comment"> */ > v26< v1 #L3682 id="L3682 class="line2 namf="L3682>2368ona2struct v1cpumaskona2 * v1 _oneshot_mask" class="s.32"_get_ption> _oneshot_maskona2(void)6< v1 #L3692 id="L3692 class="line2 namf="L3692>2369ona2{6< v1 #L3702 id="L3702 class="line2 namf="L3702>2370ona2 return v1to_cpumaskona2( v1 _oneshot_mask" class="s.32"_ption> _oneshot_maskona2);6< v1 #L3712 id="L3712 class="line2 namf="L3712>2371ona2}6< v1 #L3722 id="L3722 class="line2 namf="L3722>2372ona26< v1 #L3732 id="L3732 class="line2 namf="L3732>2373ona2sta.32 int v1 _set_event" class="s.32"_ption> _set_eventona2( v1k"v2._tona2 v1expiresona2, int v1forceona2)6< v1 #L3742 id="L3742 class="line2 namf="L3742>2374ona2{6< v1 #L3752 id="L3752 class="line2 namf="L3752>2375ona2 struct v1clo2"_event_deviceona2 * v1b2ona2 = v1 _device" class="s.32"_ption> _deviceona2. v1evtdevona2;6< v1 #L3762 id="L3762 class="line2 namf="L3762>2376ona26< v1 #L3772 id="L3772 class="line2 namf="L3772>2377ona2 if ( v1b2ona2-> v1modeona2 != v1CLOCK_EVT_MODE_ONESHOTona2)6< v1 #L3782 id="L3782 class="line2 namf="L3782>2378ona2 v1clo2"events_set_modeona2( v1b2ona2, v1CLOCK_EVT_MODE_ONESHOTona2);6< v1 #L3792 id="L3792 class="line2 namf="L3792>2379ona26< v1 #L3802 id="L3802 class="line2 namf="L3802>2380ona2 return v1clo2"events_program_eventona2( v1b2ona2, v1expiresona2, v1forceona2);6< v1 #L3812 id="L3812 class="line2 namf="L3812>2381ona2}6< v1 #L3822 id="L3822 class="line2 namf="L3822>2382ona26< v1 #L3832 id="L3832 class="line2 namf="L3832>2383ona2int v1 _oneshot" class="s.32"_resume_ption> _oneshotona2(struct v1clo2"_event_deviceona2 * v1b2ona2)6< v1 #L3842 id="L3842 class="line2 namf="L3842>2384ona2{6< v1 #L3852 id="L3852 class="line2 namf="L3852>2385ona2 v1clo2"events_set_modeona2( v1b2ona2, v1CLOCK_EVT_MODE_ONESHOTona2);6< v1 #L3862 id="L3862 class="line2 namf="L3862>2386ona2 return 0;6< v1 #L3872 id="L3872 class="line2 namf="L3872>2387ona2}6< v1 #L3882 id="L3882 class="line2 namf="L3882>2388ona26< v1 #L3892 id="L3892 class="line2 namf="L3892>2389ona2 v class="comment">/* > v26< v1 #L3902 id="L3902 class="line2 namf="L3902>239iona2 v class="comment"> * Called >rom irq_enter() when idle was interrupted to reenable th/ > v26< v1 #L3912 id="L3912 class="line2 namf="L3912>2391ona2 v class="comment"> * per cpu device. > v26< v1 #L3922 id="L3922 class="line2 namf="L3922>2392ona2 v class="comment"> */ > v26< v1 #L3932 id="L3932 class="line2 namf="L3932>2393ona2void v1 " class="s.32"_che2"_oneshot_ption> ona2(int v1cpuona2)6< v1 #L3942 id="L3942 class="line2 namf="L3942>2394ona2{6< v1 #L3952 id="L3952 class="line2 namf="L3952>2395ona2 if ( v1cpumask_test_cpuona2( v1cpuona2, v1to_cpumaskona2( v1 _oneshot_mask" class="s.32"_ption> _oneshot_maskona2))) {6< v1 #L3962 id="L3962 class="line2 namf="L3962>2396ona2 struct v1.32"_deviceona2 * v1tdona2 = & v1per_cpuona2( v1.32"_cpu_deviceona2, v1cpuona2);6< v1 #L3972 id="L3972 class="line2 namf="L3972>2397ona26< v1 #L3982 id="L3982 class="line2 namf="L3982>2398ona2 v1clo2"events_set_modeona2( v1tdona2-> v1evtdevona2, v1CLOCK_EVT_MODE_ONESHOTona2);6< v1 #L3992 id="L3992 class="line2 namf="L3992>2399ona2 }6< v1 #L4002 id="L4002 class="line2 namf="L4002>2400ona2}6< v1 #L4012 id="L4012 class="line2 namf="L4012>2401ona26< v1 #L4022 id="L4022 class="line2 namf="L4022>2402ona2 v class="comment">/* > v26< v1 #L4032 id="L4032 class="line2 namf="L4032>2403ona2 v class="comment"> * Handle oneshot mode ption> ing > v26< v1 #L4042 id="L4042 class="line2 namf="L4042>2404ona2 v class="comment"> */ > v26< v1 #L4052 id="L4052 class="line2 namf="L4052>2405ona2sta.32 void v1 " class="s.32"_handle_oneshot_ption> ona2(struct v1clo2"_event_deviceona2 * v1devona2)6< v1 #L4062 id="L4062 class="line2 namf="L4062>2406ona2{6< v1 #L4072 id="L4072 class="line2 namf="L4072>2407ona2 struct v1.32"_deviceona2 * v1tdona2;6< v1 #L4082 id="L4082 class="line2 namf="L4082>2408ona2 v1k"v2._tona2 v1nowona2, v1next_eventona2;6< v1 #L4092 id="L4092 class="line2 namf="L4092>2409ona2 int v1cpuona2;6< v1 #L4102 id="L4102 class="line2 namf="L4102>2410ona26< v1 #L4112 id="L4112 class="line2 namf="L4112>2411ona2 v1raw_spin_lo2"ona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2);6< v1 #L4122 id="L4122 class="line2 namf="L4122>2412ona2 v1againona2:6< v1 #L4132 id="L4132 class="line2 namf="L4132>2413ona2 v1devona2-> v1next_eventona2. v1.v64ona2 = v1KTIME_MAXona2;6< v1 #L4142 id="L4142 class="line2 namf="L4142>2414ona2 v1next_eventona2. v1.v64ona2 = v1KTIME_MAXona2;6< v1 #L4152 id="L4152 class="line2 namf="L4152>2415ona2 v1cpumask_clearona2( v1to_cpumaskona2( v1tmpmaskona2));6< v1 #L4162 id="L4162 class="line2 namf="L4162>2416ona2 v1nowona2 = v1k"v2._getona2();6< v1 #L4172 id="L4172 class="line2 namf="L4172>2417ona2 v class="comment">/* Find all expired events */ > v26< v1 #L4182 id="L4182 class="line2 namf="L4182>2418ona2 v1for_each_cpuona2( v1cpuona2, v1 _oneshot_mask" class="s.32"_get_ption> _oneshot_maskona2()) {6< v1 #L4192 id="L4192 class="line2 namf="L4192>2419ona2 v1tdona2 = & v1per_cpuona2( v1.32"_cpu_deviceona2, v1cpuona2);6< v1 #L4202 id="L4202 class="line2 namf="L4202>2420ona2 if ( v1tdona2-> v1evtdevona2-> v1next_eventona2. v1.v64ona2 <= v1nowona2. v1.v64ona2)6< v1 #L4212 id="L4212 class="line2 namf="L4212>2421ona2 v1cpumask_set_cpuona2( v1cpuona2, v1to_cpumaskona2( v1tmpmaskona2));6< v1 #L4222 id="L4222 class="line2 namf="L4222>2422ona2 else if ( v1tdona2-> v1evtdevona2-> v1next_eventona2. v1.v64ona2 < v1next_eventona2. v1.v64ona2)6< v1 #L4232 id="L4232 class="line2 namf="L4232>2423ona2 v1next_eventona2. v1.v64ona2 = v1tdona2-> v1evtdevona2-> v1next_eventona2. v1.v64ona2;6< v1 #L4242 id="L4242 class="line2 namf="L4242>2424ona2 }6< v1 #L4252 id="L4252 class="line2 namf="L4252>2425ona26< v1 #L4262 id="L4262 class="line2 namf="L4262>2426ona2 v class="comment">/* > v26< v1 #L4272 id="L4272 class="line2 namf="L4272>2427ona2 v class="comment"> * Wakeup the cpus which have an expired event. > v26< v1 #L4282 id="L4282 class="line2 namf="L4282>2428ona2 v class="comment"> */ > v26< v1 #L4292 id="L4292 class="line2 namf="L4292>2429ona2 v1 " class="s.32"_do_ption> ona2( v1to_cpumaskona2( v1tmpmaskona2));6< v1 #L4302 id="L4302 class="line2 namf="L4302>2430ona26< v1 #L4312 id="L4312 class="line2 namf="L4312>2431ona2 v class="comment">/* > v26< v1 #L4322 id="L4322 class="line2 namf="L4322>2432ona2 v class="comment"> * Two reasons >ti reprogram: > v26< v1 #L4332 id="L4332 class="line2 namf="L4332>2433ona2 v class="comment"> * > v26< v1 #L4342 id="L4342 class="line2 namf="L4342>2434ona2 v class="comment"> * - The global event did not expire any CPU local > v26< v1 #L4352 id="L4352 class="line2 namf="L4352>2435ona2 v class="comment"> * events. This happens in dyn.32" mode, as the maximum PIT > v26< v1 #L4362 id="L4362 class="line2 namf="L4362>2436ona2 v class="comment"> * delta is quite small. > v26< v1 #L4372 id="L4372 class="line2 namf="L4372>2437ona2 v class="comment"> * > v26< v1 #L4382 id="L4382 class="line2 namf="L4382>2438ona2 v class="comment"> * - There are pending events on sleeping CPUs which were noton v26< v1 #L4392 id="L4392 class="line2 namf="L4392>2439ona2 v class="comment"> * in the event maskon v26< v1 #L4402 id="L4402 class="line2 namf="L4402>244iona2 v class="comment"> */ > v26< v1 #L4412 id="L4412 class="line2 namf="L4412>2441ona2 if ( v1next_eventona2. v1.v64ona2 != v1KTIME_MAXona2) {6< v1 #L4422 id="L4422 class="line2 namf="L4422>2442ona2 v class="comment">/* > v26< v1 #L4432 id="L4432 class="line2 namf="L4432>2443ona2 v class="comment"> * Rearm the ption> device. If event expired, > v26< v1 #L4442 id="L4442 class="line2 namf="L4442>2444ona2 v class="comment"> * repeat the abov/ > v26< v1 #L4452 id="L4452 class="line2 namf="L4452>2445ona2 v class="comment"> */ > v26< v1 #L4462 id="L4462 class="line2 namf="L4462>2446ona2 if ( v1 _set_event" class="s.32"_ption> _set_eventona2( v1next_eventona2, 0))6< v1 #L4472 id="L4472 class="line2 namf="L4472>2447ona2 goto v1againona2;6< v1 #L4482 id="L4482 class="line2 namf="L4482>2448ona2 }6< v1 #L4492 id="L4492 class="line2 namf="L4492>2449ona2 v1raw_spin_unlo2"ona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2);6< v1 #L4502 id="L4502 class="line2 namf="L4502>2450ona2}6< v1 #L4512 id="L4512 class="line2 namf="L4512>2451ona26< v1 #L4522 id="L4522 class="line2 namf="L4522>2452ona2 v class="comment">/* > v26< v1 #L4532 id="L4532 class="line2 namf="L4532>2453ona2 v class="comment"> * Powersta.e in>timation: The system enters/leaves a sta.e, wher/ > v26< v1 #L4542 id="L4542 class="line2 namf="L4542>2454ona2 v class="comment"> * affected devices might stop > v26< v1 #L4552 id="L4552 class="line2 namf="L4552>2455ona2 v class="comment"> */ > v26< v1 #L4562 id="L4562 class="line2 namf="L4562>2456ona2void v1 _oneshot_control" class="s.32"_ption> _oneshot_controlona2(unsigned long v1reasonona2)6< v1 #L4572 id="L4572 class="line2 namf="L4572>2457ona2{6< v1 #L4582 id="L4582 class="line2 namf="L4582>2458ona2 struct v1clo2"_event_deviceona2 * v1b2ona2, * v1devona2;6< v1 #L4592 id="L4592 class="line2 namf="L4592>2459ona2 struct v1.32"_deviceona2 * v1tdona2;6< v1 #L4602 id="L4602 class="line2 namf="L4602>2460ona2 unsigned long v1flagsona2;6< v1 #L4612 id="L4612 class="line2 namf="L4612>2461ona2 int v1cpuona2;6< v1 #L4622 id="L4622 class="line2 namf="L4622>2462ona26< v1 #L4632 id="L4632 class="line2 namf="L4632>2463ona2 v class="comment">/* > v26< v1 #L4642 id="L4642 class="line2 namf="L4642>2464ona2 v class="comment"> * Period32 mode does not care about the enter/exit of power > v26< v1 #L4652 id="L4652 class="line2 namf="L4652>2465ona2 v class="comment"> * sta.es > v26< v1 #L4662 id="L4662 class="line2 namf="L4662>2466ona2 v class="comment"> */ > v26< v1 #L4672 id="L4672 class="line2 namf="L4672>2467ona2 if ( v1 _device" class="s.32"_ption> _deviceona2. v1modeona2 == v1TICKDEV_MODE_PERIODICona2)6< v1 #L4682 id="L4682 class="line2 namf="L4682>2468ona2 return;6< v1 #L4692 id="L4692 class="line2 namf="L4692>2469ona26< v1 #L4702 id="L4702 class="line2 namf="L4702>2470ona2 v class="comment">/* > v26< v1 #L4712 id="L4712 class="line2 namf="L4712>2471ona2 v class="comment"> * We are called with preemtion disabled >rom the depth of th/ > v26< v1 #L4722 id="L4722 class="line2 namf="L4722>2472ona2 v class="comment"> * idle code, so we can't be moved away. > v26< v1 #L4732 id="L4732 class="line2 namf="L4732>2473ona2 v class="comment"> */ > v26< v1 #L4742 id="L4742 class="line2 namf="L4742>2474ona2 v1cpuona2 = v1smp_processor_idona2();6< v1 #L4752 id="L4752 class="line2 namf="L4752>2475ona2 v1tdona2 = & v1per_cpuona2( v1.32"_cpu_deviceona2, v1cpuona2);6< v1 #L4762 id="L4762 class="line2 namf="L4762>2476ona2 v1devona2 = v1tdona2-> v1evtdevona2;6< v1 #L4772 id="L4772 class="line2 namf="L4772>2477ona26< v1 #L4782 id="L4782 class="line2 namf="L4782>2478ona2 if (!( v1devona2-> v1featuresona2 & v1CLOCK_EVT_FEAT_C3STOPona2))6< v1 #L4792 id="L4792 class="line2 namf="L4792>2479ona2 return;6< v1 #L4802 id="L4802 class="line2 namf="L4802>2480ona26< v1 #L4812 id="L4812 class="line2 namf="L4812>2481ona2 v1b2ona2 = v1 _device" class="s.32"_ption> _deviceona2. v1evtdevona2;6< v1 #L4822 id="L4822 class="line2 namf="L4822>2482ona26< v1 #L4832 id="L4832 class="line2 namf="L4832>2483ona2 v1raw_spin_lo2"_irqsaveona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona2);6< v1 #L4842 id="L4842 class="line2 namf="L4842>2484ona2 if ( v1reasonona2 == v1CLOCK_EVT_NOTIFY_BROADCAST_ENTERona2) {6< v1 #L4852 id="L4852 class="line2 namf="L4852>2485ona2 if (! v1cpumask_test_cpuona2( v1cpuona2, v1 _oneshot_mask" class="s.32"_get_ption> _oneshot_maskona2())) {6< v1 #L4862 id="L4862 class="line2 namf="L4862>2486ona2 v1cpumask_set_cpuona2( v1cpuona2, v1 _oneshot_mask" class="s.32"_get_ption> _oneshot_maskona2());6< v1 #L4872 id="L4872 class="line2 namf="L4872>2487ona2 v1clo2"events_set_modeona2( v1devona2, v1CLOCK_EVT_MODE_SHUTDOWNona2);6< v1 #L4882 id="L4882 class="line2 namf="L4882>2488ona2 if ( v1devona2-> v1next_eventona2. v1.v64ona2 < v1b2ona2-> v1next_eventona2. v1.v64ona2)6< v1 #L4892 id="L4892 class="line2 namf="L4892>2489ona2 v1 _set_event" class="s.32"_ption> _set_eventona2( v1devona2-> v1next_eventona2, 1);6< v1 #L4902 id="L4902 class="line2 namf="L4902>2490ona2 }6< v1 #L4912 id="L4912 class="line2 namf="L4912>2491ona2 } else {6< v1 #L4922 id="L4922 class="line2 namf="L4922>2492ona2 if ( v1cpumask_test_cpuona2( v1cpuona2, v1 _oneshot_mask" class="s.32"_get_ption> _oneshot_maskona2())) {6< v1 #L4932 id="L4932 class="line2 namf="L4932>2493ona2 v1cpumask_clear_cpuona2( v1cpuona2,6< v1 #L4942 id="L4942 class="line2 namf="L4942>2494ona2 v1 _oneshot_mask" class="s.32"_get_ption> _oneshot_maskona2());6< v1 #L4952 id="L4952 class="line2 namf="L4952>2495ona2 v1clo2"events_set_modeona2( v1devona2, v1CLOCK_EVT_MODE_ONESHOTona2);6< v1 #L4962 id="L4962 class="line2 namf="L4962>2496ona2 if ( v1devona2-> v1next_eventona2. v1.v64ona2 != v1KTIME_MAXona2)6< v1 #L4972 id="L4972 class="line2 namf="L4972>2497ona2 v1.32"_program_eventona2( v1devona2-> v1next_eventona2, 1);6< v1 #L4982 id="L4982 class="line2 namf="L4982>2498ona2 }6< v1 #L4992 id="L4992 class="line2 namf="L4992>2499ona2 }6< v1 #L5002 id="L5002 class="line2 namf="L5002>2500ona2 v1raw_spin_unlo2"_irqrestoreona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona2);6< v1 #L5012 id="L5012 class="line2 namf="L5012>2501ona2}6< v1 #L5022 id="L5022 class="line2 namf="L5022>2502ona26< v1 #L5032 id="L5032 class="line2 namf="L5032>2503ona2 v class="comment">/* > v26< v1 #L5042 id="L5042 class="line2 namf="L5042>2504ona2 v class="comment"> * Reset the one shot ption> >ti a cpuon v26< v1 #L5052 id="L5052 class="line2 namf="L5052>2505ona2 v class="comment"> *on v26< v1 #L5062 id="L5062 class="line2 namf="L5062>2506ona2 v class="comment"> * Called with .32"_ption> _lo2" heldon v26< v1 #L5072 id="L5072 class="line2 namf="L5072>2507ona2 v class="comment"> */ > v26< v1 #L5082 id="L5082 class="line2 namf="L5082>2508ona2sta.32 void v1 _clear_oneshot" class="s.32"_ption> _clear_oneshotona2(int v1cpuona2)6< v1 #L5092 id="L5092 class="line2 namf="L5092>2509ona2{6< v1 #L5102 id="L5102 class="line2 namf="L5102>2510ona2 v1cpumask_clear_cpuona2( v1cpuona2, v1 _oneshot_mask" class="s.32"_get_ption> _oneshot_maskona2());6< v1 #L5112 id="L5112 class="line2 namf="L5112>2511ona2}6< v1 #L5122 id="L5122 class="line2 namf="L5122>2512ona26< v1 #L5132 id="L5132 class="line2 namf="L5132>2513ona2sta.32 void v1 _init_next_event" class="s.32"_ption> _init_next_eventona2(struct v1cpumaskona2 * v1maskona2,6< v1 #L5142 id="L5142 class="line2 namf="L5142>2514ona2 v1k"v2._tona2 v1expiresona2)6< v1 #L5152 id="L5152 class="line2 namf="L5152>2515ona2{6< v1 #L5162 id="L5162 class="line2 namf="L5162>2516ona2 struct v1.32"_deviceona2 * v1tdona2;6< v1 #L5172 id="L5172 class="line2 namf="L5172>2517ona2 int v1cpuona2;6< v1 #L5182 id="L5182 class="line2 namf="L5182>2518ona26< v1 #L5192 id="L5192 class="line2 namf="L5192>2519ona2 v1for_each_cpuona2( v1cpuona2, v1maskona2) {6< v1 #L5202 id="L5202 class="line2 namf="L5202>2520ona2 v1tdona2 = & v1per_cpuona2( v1.32"_cpu_deviceona2, v1cpuona2);6< v1 #L5212 id="L5212 class="line2 namf="L5212>2521ona2 if ( v1tdona2-> v1evtdevona2)6< v1 #L5222 id="L5222 class="line2 namf="L5222>2522ona2 v1tdona2-> v1evtdevona2-> v1next_eventona2 = v1expiresona2;6< v1 #L5232 id="L5232 class="line2 namf="L5232>2523ona2 }6< v1 #L5242 id="L5242 class="line2 namf="L5242>2524ona2}6< v1 #L5252 id="L5252 class="line2 namf="L5252>2525ona26< v1 #L5262 id="L5262 class="line2 namf="L5262>2526ona2 v class="comment">/**on v26< v1 #L5272 id="L5272 class="line2 namf="L5272>2527ona2 v class="comment"> * .32"_ption> _setup_oneshot - setup the ption> deviceon v26< v1 #L5282 id="L5282 class="line2 namf="L5282>2528ona2 v class="comment"> */ > v26< v1 #L5292 id="L5292 class="line2 namf="L5292>2529ona2void v1 _setup_oneshot" class="s.32"_ption> _setup_oneshotona2(struct v1clo2"_event_deviceona2 * v1b2ona2)6< v1 #L5302 id="L5302 class="line2 namf="L5302>2530ona2{6< v1 #L5312 id="L5312 class="line2 namf="L5312>2531ona2 int v1cpuona2 = v1smp_processor_idona2();6< v1 #L5322 id="L5322 class="line2 namf="L5322>2532ona26< v1 #L5332 id="L5332 class="line2 namf="L5332>2533ona2 v class="comment">/* Set it up only once ! */ > v26< v1 #L5342 id="L5342 class="line2 namf="L5342>2534ona2 if ( v1b2ona2-> v1event_handlerona2 != v1 " class="s.32"_handle_oneshot_ption> ona2) {6< v1 #L5352 id="L5352 class="line2 namf="L5352>2535ona2 int v1was_period32ona2 = v1b2ona2-> v1modeona2 == v1CLOCK_EVT_MODE_PERIODICona2;6< v1 #L5362 id="L5362 class="line2 namf="L5362>2536ona26< v1 #L5372 id="L5372 class="line2 namf="L5372>2537ona2 v1b2ona2-> v1event_handlerona2 = v1 " class="s.32"_handle_oneshot_ption> ona2;6< v1 #L5382 id="L5382 class="line2 namf="L5382>2538ona26< v1 #L5392 id="L5392 class="line2 namf="L5392>253 devent5_id" class="ssmp_processor_idona2();6< v1 #L5322 id="L5322 class="line2 namf="L5322>2532ona26< v1 #L5332 id="L5332 class="line2 namf="L5332>2533ona2 v class="comment">/* Set it u1de=.mpmask" clas12" ptionX2 namf="L5352>2535ona2 6cla2" class="sntona2. 1cpuo #L41=cpumne2 namf="L4252>2425ona26< v1 2 v1for_each_cpuona2IME_MAXon52) {6< v12453ona2 v class="comment"> * Powersta.5t"> 5 * Rearm the pt5on> 5 device. If event expired, > v26< v1 #L4442 id="L4442 class5"line2 na5f="L4442>2444ona2 v c5="L445omment"> * repeat the abov/ > F14o0s="line * repeat the abov/ "L5342>253h .32"_ption> _lo2" hel4Ot+cod32">cpuo 2 * T12" ptionX2 namf="L5352>2535ona2 6cl5wersta.e in>timation: The system enters/leaves a sta.e, wion: T> i * events. This happens in dyn.32" mode, ass="comment"> * 84ine2 namf="L4262>paiona2ptiond="L5372shotona2(s.mf="neL3932 < v1 .32" ptiot_eventona2, 0))6< v1 #L4472 id="L4472 class= ion> _init bit> v2thos d }6<1 _handle_o1smp_processor_idona2();6< v154 v class="comment"> * in t72 class= #L41=cpumne2 namf="L4252>2425ona26< v1 #L4322 id="L4322 class="line2 namf="L4322>2432ona2 v class="c5132 id="L5132 class="line2 namf="L5ona2sta.32 void v1.32"_ption> _init_nexn> #L5512 id="L4512 class="lin52 nam54 if ( v1 #L5132 id="L5132 claue="v2.6.32" ption> #L4322 id="L4322 class="line2 namf="L4322>2432ona2 v class="comment"> * Two reasons >ti reprogr5ne2 namf=5L4532>2453ona2 v clas5="com55v1 ss="line2 namf="L5132>2513ona2sta.32 void v1 _init_next_6< v1 #L51s/leaves 5 sta.e, wher/ > v26< v52422ona2 elach_cpu" class="s< ss="line2 namf="L5132>2513ona2sta.32 void v1 _init_next_6< v1 #L51sid="L4442namf="L4542>2454ona2 5 clas55 }6< v1 #L4322 id="L4322 class="line2 namf="L4322>2432ona2 v class="comment"> * Two reasons >ti reprogr5neat the a4552 id="L4552 class="li5e2 na5f="L45ment"> * Two reasons >ti reprogr5ni * evencode=.32"_ption> _ones5ot_co55ona2 struct /opt+code=was_perioe="v2.6.32" ption> #L5372 id="L5372 clasopt+c #L48 v1 #L4322 id="L4322 class="line2 namf="L4322>2432ona2 v class="c v1devona2-> v1next_evento.6.32" ption> #L3882 id="L3882 class="line2 namf="L3882>2388ona26< v1 #L3892 id="L3892 class="line2 namf="L385.32" ptio5> #L4582 id="L4582 c5ass="557ona2 v1k"v2._tona2 v1exlue="v2.6.32" ptue="v2.6.32" ption> #L4322 id="L4322 class="line2 namf="L4322>2432ona2 v class="c5 #L3892 id="L3892 class="line2 namf="L385.opt+code52" ption> #L4592 id=5L459255 v1 # v1 #L5312 id="L5312="line2 namf="L4912>2491ona2 } else {6< v1raw_s5 #54612 55 if ( v1raw_s5ne2 namf=5L4622>2462ona26< v1 eventona2( v1devona2-> v1next_eventona2, 1);6< v1 #L4162 id="L4162 class="line2 namf="L4162>2416ona2 51 5L464256neshot_maskona2())) {6< v1 #L5are about5the enter/exit of power 5 v256a2 v c5="L445omment"> * repeat the abov/ > F14o0s="line * re"L4652 cl5ss="line2 namf="L4652>2455ona256lo2" hel4Ot+cod32">cpuo 2 * T12" ptionX2 nam/optf (st3222" ptioswitches932 dle_oneshot_p} e The system enters/leaves a sta.e, wion: T> 662 id="L5662 class="line2 namf="L5662>2566ona2 v class="comment"> tionX2 namoneshi ption>ll>timatiption> on2 de=tv64gener is quite small. > v26< v1 _de5ice" 5lass="s.32"_ption> _deviceona2tionX2 nam(d="L5372) hotona2(st cla. Somoneshi pis < v1anint v1cpuona2)6< v+code=TIC5DEV_MODE_PERIODIC" class5"sTICKDEV_MODE_PERIODICona2)6< v1 af thi The system enters/leaves a sta.e, wion: T> 6opt+code5mf="L4682>2468ona2 5 56 v class="comment"> * in t72 class=932 }6<1 62 class=" id="L4712 class="line2 5amf="56f="L4402>244iona2 v class="commen72 class= #L41=cpumne2 namf="L4252>2425ona26< v1rom the depth of th5 > 56 if ( v1cpumask_clear_cpuona2( v12522ona2 v1tdona2-> v15472on52 v class=" * .32"_ption> _setup_oneshot - setup th1 5L473257 class="scpumaskona2 * v12474ona2 5v1event_handlerona2 != 2" ption>5 #L4752 id="L4752 cla5s="li5e2 namf="L4752>2475ona2 repeat the abov/ > F14o0s="line * recode=per_5pu" class="sper_cpu5na2( 57.32"_ption> _lo2" heldon vSelect dle_onesod="aona2phot_p v2theshotona2(struct v1c"line2 na5f="L4762>2476ona2 5 v1<57 #L4572 id="L4572 class="line2 namf="L4572>2457ona2{6< v124757ne2 namf="L4582>2458ona2 struct switch_#L4ass="line2 namf="L5312>2531ona2 witch_#L4ass="licpu" amf="v2.6.32" ption> #L5322 id="L5322 clasSTOPona2)56< v12459ona2 struct52>2479ona5 return;65 v1tdona2;6< v1 #L4602 id="L4602 class="line2 namf="Lt+code=.d" class="stdona2-> v1.32"_pt5on> 5_deviceona2. n> #L4632 id="L4632 class="line2 namf="L4632>2463ona2 v class="comment">/* > v26< 5value="v256.32" ption> #L4822 5582 i522 class="line2 namf="L4822>2482ona26< v12e26< v12482ona26< v12e26< vmf="L5832>2483ona2 v1CLOCK_EVT_NOTIFY_BROADCAST_ENTERona2) {6< v1 #L4852 id="L4852 class="line2 namf="L4852>2485ona2 if (! v1reasonona2 == v1 line2 namf="L4692>2469ona26< v1 #L4702 id="L4702 class="lin2 namf="L4702>2470ona2 value="v2.6.32" ption>70ona2 value="comment">/* > v26< 5value="v256.32" ption> ">per_cpulass="scpumask_test5cpuon52( v1save" class="sraw_spin_lo2"_irqsaveona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona5ne2 namf=5L4862>2486ona2 5 5 v1was_period32ona2 = v12487ona2 5 5 v12531ona2 int v1cpus="swas_period32ona2 = v1flagsona5ne="v2.6.38ona2 5 i58lass="line2 namf="L4792>2479ona2 5lass="s.v64ona2)6< v1tdona2 = & v1 #L5032 id="L5032 class="line2 namf="L5032>2503ona2 v class="comment">/* > v26< v1 #L5042 id="L5042 class="line2 namf="L5042>2504ona202>2490on52 }6< v1<5opt v5lue="vv12474ona v1c5uona25922>2482ona26< v12e26< v1 _oneshot_maskona2(5)) {659.32" ption> #L4442 id="L4442 class5"line2 e2 namf="54932>2493ona2 5 59vices might stop > v26< v1 #L4552 id="L4555 _oneshot5mask" class="s.32"_5et_pt59ass="comment"> */ > v26< v1 v2.6.4552 id="(st/opt value="v2.6.32" ption> #L4552 id="L4555 ">per_cpuo2"events_set_modeona2( 5v124965na2 5 if 5 v12497ona2 5 5 na2 struct52>2479ona5 5 }6< v1 #class="line2 namf="L4632>2463ona2 v class="comment">/* > v26< 5value="v256.32" ption> (& v5 5_lo2"5 class="sclass="li.6.3 v1/* > v26< 5value="v256.32" ption> (2>2490on5flagsona2);6< v1 #L4722 id="L4722 class="line2 n6012>2501o6a2}6< v1 #L5022 id="L5022 class="lineCLOCK_EVT_NOTIFY_BROADCAST_ENTER" class="sCLOCK_EVT_NOTIFY_BROADCAST_ENTERona2) {6< v1 #L4852 id="L4852 class="line2 namf="L4852>2485ona2 if (! v1 * Reset the6one s60.32" ption> #L4442 id="L4442 class5"line262.6.32" p6ion> #L5052 id="L5056 clas60 might stop > v26< v1 #L4552 id="L4556t"> *on 6v26< v1 #L5062 id="L5062 clo bcv26< v1Ca2 * Cal6ed with .32"_ption> _l62" he6don v26< v1 #L5082 id="L5082 clasamf="L4252>2425ona26< v1rom the 6t+code=.36"_ption> _clear_onesho6" cla60pt+code=dev" class="sdess="line2 namf="L5122>2512ona26< v1 #L5132 id="L5132 class="line2 namf="L5132>2513ona2sta.32 void v1 _init_next_event" class="s.32"_ption> _init_next_eventona2(struct v16tion> 6#L5092 id="L5092 class="6ine2 60lass="line2 namf="L4792>2479ona2 6s="line2 6amf="L5102>2510ona2 6 v60="stdona2 = & v1 #L5032 id="L5032 class="line2 namf="L5032>2503ona2 v class="comment">/* > v26< v1 #L5042 id="L5042 class="line2 namf="L5042> 6s9"line2 6alagsona2);6< v12474on612>2511on62}6< v12482ona26< v12e26< v1cp6masko61mf="L4732>2473ona2 v cla1 #L4552 id="L4556< v1 6 #L561cpuona2 = v1 #L50class=pt value="v2.6.32" ption> #L4552 id="L4556<"> *on 6 6 61ass="comment"> */ > v26< v12>2425ona26< v1rom the 62 namf="L6162>2516ona2 stru6t v6 class="actiNOTIFY_BROADCAST_lass="comment"> class="actiNO> #L5322 id="L5322 clasSTOPona2)56< v1cp6ona2;6< v1 #L5162 id="L5162 class="line2 namf="L5162>2516ona26< v1evtdonona2 == v1 line2 namf="L4692>2469ona26< v1 #L4702 id="L4702 class="linn2 namf="L4702>2470ona2 value="v2.6.32" ption>70ona2 value="comment">/* > v26< 5value="v256.32" ption> 6 v1c6uona26 v12474on61="line2 6ne2 namf="L5202>2520ona26 6 v1tdona6 = & 6v1 #L4552 id="L455612>2521on62 if ( v6 lass=s a sta.e, wion: T> 62 class=" id="L4712 cl6evtd6vona2-> v12473ona2 v clas12>2425ona26< v1rom the 6="L5232>2623ona2 }6< v1was_peross="sclo2"_erosss="li v1 class="availalueTIFY_BROADCAST_lass="comment"> class="availalue> #L5322 id="L5322 clasSTOPona2)56< v1 < v1 #L5162 v cl6ss="comment"> * .32"_pti6n> 62( v1tdona2;6< v1 #L4602 id="L4602 class="line2 namf="Lt+code=.d" class="ssave" class="sraw_spin_lo2"_irqsaveona2(& v1 _lo2"" class="s.32"_ption> _lo2"ona2, v1flagsona626< v16 #65282 id="L5282 class="line2 namf="L5282>2528on62 v cl6ss="comment"> */ > v266 v1evtdonona2 == v1s?2( v1devona2-> v1 #L4812 id="L4812 class="line2 namf="L4812>2481ona2 value="v2.6.32" ption> #L389 value="class:6< v1flagsona62 v1 6_setu62 v12474on6 v1b2o6a2)6<62 v1tdona630ona2{6<6v16 #L#endif v1tdona62ona26< v6 6 #L53
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