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10#ifndef VIDEO_SH_MIPI_DSI_H
11#define VIDEO_SH_MIPI_DSI_H
12
13enum sh_mipi_dsi_data_fmt {
14 MIPI_RGB888,
15 MIPI_RGB565,
16 MIPI_RGB666_LP,
17 MIPI_RGB666,
18 MIPI_BGR888,
19 MIPI_BGR565,
20 MIPI_BGR666_LP,
21 MIPI_BGR666,
22 MIPI_YUYV,
23 MIPI_UYVY,
24 MIPI_YUV420_L,
25 MIPI_YUV420,
26};
27
28struct sh_mobile_lcdc_chan_cfg;
29
30#define SH_MIPI_DSI_HSABM (1 << 0)
31#define SH_MIPI_DSI_HBPBM (1 << 1)
32#define SH_MIPI_DSI_HFPBM (1 << 2)
33#define SH_MIPI_DSI_BL2E (1 << 3)
34#define SH_MIPI_DSI_VSEE (1 << 4)
35#define SH_MIPI_DSI_HSEE (1 << 5)
36#define SH_MIPI_DSI_HSAE (1 << 6)
37
38#define SH_MIPI_DSI_HSbyteCLK (1 << 24)
39#define SH_MIPI_DSI_HS6divCLK (1 << 25)
40#define SH_MIPI_DSI_HS4divCLK (1 << 26)
41
42#define SH_MIPI_DSI_SYNC_PULSES_MODE (SH_MIPI_DSI_VSEE | \
43 SH_MIPI_DSI_HSEE | \
44 SH_MIPI_DSI_HSAE)
45#define SH_MIPI_DSI_SYNC_EVENTS_MODE (0)
46#define SH_MIPI_DSI_SYNC_BURST_MODE (SH_MIPI_DSI_BL2E)
47
48struct sh_mipi_dsi_info {
49 enum sh_mipi_dsi_data_fmt data_format;
50 struct sh_mobile_lcdc_chan_cfg *lcd_chan;
51 int lane;
52 unsigned long flags;
53 u32 clksrc;
54 u32 phyctrl;
55 unsigned int vsynw_offset;
56 int (*set_dot_clock)(struct platform_device *pdev,
57 void __iomem *base,
58 int enable);
59};
60
61#endif
62