linux/include/linux/sh_pfc.h
<<
on> 4.1/spa="v 4.1/form"v 4.1a on> 4. href="../linux+v3oti10/include/linux/sh_pfc.h">on> 4.1img src="../.static/gfx/right.png" alt=">>">on1/spa="von1spa= class="lxr_search">on> on> 4.1input typ3.1hidden" nam3.1navtarget" v3.1">on> 4.1input typ3.1text" nam3.1search" id.1search">on> 4.1butt >typ3.1submit">Search 4. onclick="return ajax_prefs();">on> 4.Prefsv 4.1/a>on1/spa="v> 4. .1/div"v> 4. .1form aclue=="ajax+*" method="post" onsubmit="return false;">on1input typ3.1hidden" nam3.1ajax_lookup" id.1ajax_lookup" v3.1">o> 4. .1/form"vo> 4. .1div class="headingbott m"> 4. 4. 4. .1div id.1search_results" class="search_results"v 4"v> 4. .1/div"v 1div id.1content">v 1div id.1file_contents""
. .11/a>1spa= class="comment">/*1/spa="v. .21/a>1spa= class="comment"> * SuperH Pin Funclue= Controller Support1/spa="v. .31/a>1spa= class="comment"> *1/spa="v. .41/a>1spa= class="comment"> * Copyright (c) 2008 Magnus Damm1/spa="v. .51/a>1spa= class="comment"> *1/spa="v. .61/a>1spa= class="comment"> * This file is subject to the terms and condilue=s of the GNU General Public1/spa="v. .71/a>1spa= class="comment"> * License.  See the file "COPYING" in the main directory of this archive1/spa="v. .81/a>1spa= class="comment"> * for more details.1/spa="v. .91/a>1spa= class="comment"> */1/spa="v. ion a"v. 111/a>#ifndef.1a href="+code=__SH_PFC_H" class="sref">__SH_PFC_Hn a"v. 121/a>#define.1a href="+code=__SH_PFC_H" class="sref">__SH_PFC_Hn a"v. 13n a"v. 141/a>#include <linux/stringify.h1/a>>v. 151/a>#include <asm-generic/gpio.h1/a>>v. 16n a"v. 171/a>typ3def.unsigned short.1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a>;v. 181/a>typ3def.unsigned short.1a href="+code=pinmux_flag_t" class="sref">pinmux_flag_t1/a>;v. 19n a"v. 2on a"enum {v. 211/a>        1a href="+code=PINMUX_TYPE_NONE" class="sref">PINMUX_TYPE_NONE1/a>,v. 22n a"v. 231/a>        1a href="+code=PINMUX_TYPE_FUNCTION" class="sref">PINMUX_TYPE_FUNCTION1/a>,v. 241/a>        1a href="+code=PINMUX_TYPE_GPIO" class="sref">PINMUX_TYPE_GPIO1/a>,v. 251/a>        1a href="+code=PINMUX_TYPE_OUTPUT" class="sref">PINMUX_TYPE_OUTPUT1/a>,v. 261/a>        1a href="+code=PINMUX_TYPE_INPUT" class="sref">PINMUX_TYPE_INPUT1/a>,v. 271/a>        1a href="+code=PINMUX_TYPE_INPUT_PULLUP" class="sref">PINMUX_TYPE_INPUT_PULLUP1/a>,v. 281/a>        1a href="+code=PINMUX_TYPE_INPUT_PULLDOWN" class="sref">PINMUX_TYPE_INPUT_PULLDOWN1/a>,v. 29n a"v. 301/a>        1a href="+code=PINMUX_FLAG_TYPE" class="sref">PINMUX_FLAG_TYPE1/a>,       1spa= class="comment">/* must be last */1/spa="v. 311/a>};v. 32n a"v. 331/a>#define.1a href="+code=PINMUX_FLAG_DBIT_SHIFT" class="sref">PINMUX_FLAG_DBIT_SHIFT1/a>      5v. 341/a>#define.1a href="+code=PINMUX_FLAG_DBIT" class="sref">PINMUX_FLAG_DBIT1/a>            (0x1f <<.1a href="+code=PINMUX_FLAG_DBIT_SHIFT" class="sref">PINMUX_FLAG_DBIT_SHIFT1/a>)v. 351/a>#define.1a href="+code=PINMUX_FLAG_DREG_SHIFT" class="sref">PINMUX_FLAG_DREG_SHIFT1/a>      10v. 361/a>#define.1a href="+code=PINMUX_FLAG_DREG" class="sref">PINMUX_FLAG_DREG1/a>            (0x3f <<.1a href="+code=PINMUX_FLAG_DREG_SHIFT" class="sref">PINMUX_FLAG_DREG_SHIFT1/a>)v. 37n a"v. 381/a>struct.1a href="+code=pinmux_gpio" class="sref">pinmux_gpio1/a> {v. 391/a>        1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> 1a href="+code=enum_id" class="sref">enum_id1/a>;v. 401/a>        1a href="+code=pinmux_flag_t" class="sref">pinmux_flag_t1/a> 1a href="+code=flags" class="sref">flags1/a>;v. 411/a>        const char *1a href="+code=nam3" class="sref">nam31/a>;v. 421/a>};v. 43n a"v. 441/a>#define.1a href="+code=PINMUX_GPIO" class="sref">PINMUX_GPIO1/a>(1a href="+code=gpio" class="sref">gpio1/a>,.1a href="+code=data_or_mark" class="sref">data_or_mark1/a>) \v. 451/a>        [1a href="+code=gpio" class="sref">gpio1/a>] = { .1a href="+code=nam3" class="sref">nam31/a> = 1a href="+code=__stringify" class="sref">__stringify1/a>(1a href="+code=gpio" class="sref">gpio1/a>), .1a href="+code=enum_id" class="sref">enum_id1/a> = 1a href="+code=data_or_mark" class="sref">data_or_mark1/a>, .1a href="+code=flags" class="sref">flags1/a> = 1a href="+code=PINMUX_TYPE_NONE" class="sref">PINMUX_TYPE_NONE1/a> }v. 46n a"v. 471/a>#define.1a href="+code=PINMUX_DATA" class="sref">PINMUX_DATA1/a>(1a href="+code=data_or_mark" class="sref">data_or_mark1/a>, 1a href="+code=ids" class="sref">ids1/a>...) 1a href="+code=data_or_mark" class="sref">data_or_mark1/a>, 1a href="+code=ids" class="sref">ids1/a>, 0v. 48n a"v. 491/a>struct.1a href="+code=pinmux_cfg_reg" class="sref">pinmux_cfg_reg1/a> {v. 501/a>        unsigned long.1a href="+code=reg" class="sref">reg1/a>, 1a href="+code=reg_width" class="sref">reg_width1/a>, 1a href="+code=field_width" class="sref">field_width1/a>;v. 511/a>        unsigned long.*1a href="+code=cnt" class="sref">cnt1/a>;v. 521/a>        1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> *1a href="+code=enum_ids" class="sref">enum_ids1/a>;v. 531/a>        unsigned long.*1a href="+code=var_field_width" class="sref">var_field_width1/a>;v. 541/a>};v. 55n a"v. 561/a>#define.1a href="+code=PINMUX_CFG_REG" class="sref">PINMUX_CFG_REG1/a>(1a href="+code=nam3" class="sref">nam31/a>, 1a href="+code=r" class="sref">r1/a>, 1a href="+code=r_width" class="sref">r_width1/a>, 1a href="+code=f_width" class="sref">f_width1/a>) \v. 571/a>        .1a href="+code=reg" class="sref">reg1/a> = 1a href="+code=r" class="sref">r1/a>, .1a href="+code=reg_width" class="sref">reg_width1/a> = 1a href="+code=r_width" class="sref">r_width1/a>, .1a href="+code=field_width" class="sref">field_width1/a> = 1a href="+code=f_width" class="sref">f_width1/a>,         \v. 581/a>        .1a href="+code=cnt" class="sref">cnt1/a> = (unsigned long.[1a href="+code=r_width" class="sref">r_width1/a> / 1a href="+code=f_width" class="sref">f_width1/a>]) {}, \v. 591/a>        .1a href="+code=enum_ids" class="sref">enum_ids1/a> = (1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> [(1a href="+code=r_width" class="sref">r_width1/a> / 1a href="+code=f_width" class="sref">f_width1/a>) * (1 <<.1a href="+code=f_width" class="sref">f_width1/a>)])v. 6on a"v. 611/a>#define.1a href="+code=PINMUX_CFG_REG_VAR" class="sref">PINMUX_CFG_REG_VAR1/a>(1a href="+code=nam3" class="sref">nam31/a>, 1a href="+code=r" class="sref">r1/a>, 1a href="+code=r_width" class="sref">r_width1/a>, 1a href="+code=var_fw0" class="sref">var_fw01/a>, 1a href="+code=var_fwn" class="sref">var_fwn1/a>...) \v. 621/a>        .1a href="+code=reg" class="sref">reg1/a> = 1a href="+code=r" class="sref">r1/a>, .1a href="+code=reg_width" class="sref">reg_width1/a> = 1a href="+code=r_width" class="sref">r_width1/a>, \v. 631/a>        .1a href="+code=cnt" class="sref">cnt1/a> = (unsigned long.[1a href="+code=r_width" class="sref">r_width1/a>]) {}, \v. 641/a>        .1a href="+code=var_field_width" class="sref">var_field_width1/a> = (unsigned long.[1a href="+code=r_width" class="sref">r_width1/a>]) { 1a href="+code=var_fw0" class="sref">var_fw01/a>, 1a href="+code=var_fwn" class="sref">var_fwn1/a>, 0 }, \v. 651/a>        .1a href="+code=enum_ids" class="sref">enum_ids1/a> = (1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> [])v. 66n a"v. 671/a>struct.1a href="+code=pinmux_data_reg" class="sref">pinmux_data_reg1/a> {v. 681/a>        unsigned long.1a href="+code=reg" class="sref">reg1/a>, 1a href="+code=reg_width" class="sref">reg_width1/a>, 1a href="+code=reg_shadow" class="sref">reg_shadow1/a>;v. 691/a>        1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> *1a href="+code=enum_ids" class="sref">enum_ids1/a>;v. 701/a>        void 1a href="+code=__iomem" class="sref">__iomem1/a> *1a href="+code=mapped_reg" class="sref">mapped_reg1/a>;v. 711/a>};v. 72n a"v. 731/a>#define.1a href="+code=PINMUX_DATA_REG" class="sref">PINMUX_DATA_REG1/a>(1a href="+code=nam3" class="sref">nam31/a>, 1a href="+code=r" class="sref">r1/a>, 1a href="+code=r_width" class="sref">r_width1/a>) \v. 741/a>        .1a href="+code=reg" class="sref">reg1/a> = 1a href="+code=r" class="sref">r1/a>, .1a href="+code=reg_width" class="sref">reg_width1/a> = 1a href="+code=r_width" class="sref">r_width1/a>, \v. 751/a>        .1a href="+code=enum_ids" class="sref">enum_ids1/a> = (1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> [1a href="+code=r_width" class="sref">r_width1/a>]) \v. 76n a"v. 771/a>struct.1a href="+code=pinmux_irq" class="sref">pinmux_irq1/a> {v. 781/a>        int.1a href="+code=irq" class="sref">irq1/a>;v. 791/a>        1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> *1a href="+code=enum_ids" class="sref">enum_ids1/a>;v. 801/a>};v. 81n a"v. 821/a>#define.1a href="+code=PINMUX_IRQ" class="sref">PINMUX_IRQ1/a>(1a href="+code=irq_nr" class="sref">irq_nr1/a>, 1a href="+code=ids" class="sref">ids1/a>...)                         \v. 831/a>        { .1a href="+code=irq" class="sref">irq1/a> = 1a href="+code=irq_nr" class="sref">irq_nr1/a>, .1a href="+code=enum_ids" class="sref">enum_ids1/a> = (1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> []) { 1a href="+code=ids" class="sref">ids1/a>, 0 } }    \v. 84n a"v. 851/a>struct.1a href="+code=pinmux_rang3" class="sref">pinmux_rang31/a> {v. 861/a>        1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> 1a href="+code=begin" class="sref">begin1/a>;v. 871/a>        1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> 1a href="+code=end" class="sref">end1/a>;v. 881/a>        1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> 1a href="+code=forc3" class="sref">forc31/a>;v. 891/a>};v. 9on a"v. 911/a>struct.1a href="+code=pfc_window" class="sref">pfc_window1/a> {v. 921/a>        1a href="+code=phys_addr_t" class="sref">phys_addr_t1/a> 1a href="+code=phys" class="sref">phys1/a>;v. 931/a>        void 1a href="+code=__iomem" class="sref">__iomem1/a> *1a href="+code=virt" class="sref">virt1/a>;v. 941/a>        unsigned long.1a href="+code=siz3" class="sref">siz31/a>;v. 951/a>};v. 96n a"v. 971/a>struct.1a href="+code=sh_pfc" class="sref">sh_pfc1/a> {v. 981/a>        char *1a href="+code=nam3" class="sref">nam31/a>;v. 991/a>        1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> 1a href="+code=reserved_id" class="sref">reserved_id1/a>;v.1001/a>        struct.1a href="+code=pinmux_rang3" class="sref">pinmux_rang31/a> 1a href="+code=data" class="sref">data1/a>;v.1011/a>        struct.1a href="+code=pinmux_rang3" class="sref">pinmux_rang31/a> 1a href="+code=input" class="sref">input1/a>;v.1021/a>        struct.1a href="+code=pinmux_rang3" class="sref">pinmux_rang31/a> 1a href="+code=input_pd" class="sref">input_pd1/a>;v.1031/a>        struct.1a href="+code=pinmux_rang3" class="sref">pinmux_rang31/a> 1a href="+code=input_pu" class="sref">input_pu1/a>;v.1041/a>        struct.1a href="+code=pinmux_rang3" class="sref">pinmux_rang31/a> 1a href="+code=output" class="sref">output1/a>;v.1051/a>        struct.1a href="+code=pinmux_rang3" class="sref">pinmux_rang31/a> 1a href="+code=mark" class="sref">mark1/a>;v.1061/a>        struct.1a href="+code=pinmux_rang3" class="sref">pinmux_rang31/a> 1a href="+code=funclue=" class="sref">funclue=1/a>;v.107n a"v.1081/a>        unsigned 1a href="+code=first_gpio" class="sref">first_gpio1/a>, 1a href="+code=last_gpio" class="sref">last_gpio1/a>;v.109n a"v.1101/a>        struct.1a href="+code=pinmux_gpio" class="sref">pinmux_gpio1/a> *1a href="+code=gpios" class="sref">gpios1/a>;v.1111/a>        struct.1a href="+code=pinmux_cfg_reg" class="sref">pinmux_cfg_reg1/a> *1a href="+code=cfg_regs" class="sref">cfg_regs1/a>;v.1121/a>        struct.1a href="+code=pinmux_data_reg" class="sref">pinmux_data_reg1/a> *1a href="+code=data_regs" class="sref">data_regs1/a>;v.113n a"v.1141/a>        1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> *1a href="+code=gpio_data" class="sref">gpio_data1/a>;v.1151/a>        unsigned int.1a href="+code=gpio_data_siz3" class="sref">gpio_data_siz31/a>;v.116n a"v.1171/a>        struct.1a href="+code=pinmux_irq" class="sref">pinmux_irq1/a> *1a href="+code=gpio_irq" class="sref">gpio_irq1/a>;v.1181/a>        unsigned int.1a href="+code=gpio_irq_siz3" class="sref">gpio_irq_siz31/a>;v.119n a"v.1201/a>        1a href="+code=spinlock_t" class="sref">spinlock_t1/a> 1a href="+code=lock" class="sref">lock1/a>;v.121n a"v.1221/a>        struct.1a href="+code=resourc3" class="sref">resourc31/a> *1a href="+code=resourc3" class="sref">resourc31/a>;v.1231/a>        unsigned int.1a href="+code=num_resourc3s" class="sref">num_resourc3s1/a>;v.1241/a>        struct.1a href="+code=pfc_window" class="sref">pfc_window1/a> *1a href="+code=window" class="sref">window1/a>;v.125n a"v.1261/a>        unsigned long.1a href="+code=unlock_reg" class="sref">unlock_reg1/a>;v.1271/a>};v.128n a"v.1291/a>1spa= class="comment">/* XXX compat for now */1/spa="v.1301/a>#define.1a href="+code=pinmux_info" class="sref">pinmux_info1/a> 1a href="+code=sh_pfc" class="sref">sh_pfc1/a>v.131n a"v.1321/a>1spa= class="comment">/* drivers/sh/pfc/gpio.c */1/spa="v.1331/a>int.1a href="+code=sh_pfc_register_gpiochip" class="sref">sh_pfc_register_gpiochip1/a>(struct.1a href="+code=sh_pfc" class="sref">sh_pfc1/a> *1a href="+code=pfc" class="sref">pfc1/a>);v.134n a"v.1351/a>1spa= class="comment">/* drivers/sh/pfc/pinctrl.c */1/spa="v.1361/a>int.1a href="+code=sh_pfc_register_pinctrl" class="sref">sh_pfc_register_pinctrl1/a>(struct.1a href="+code=sh_pfc" class="sref">sh_pfc1/a> *1a href="+code=pfc" class="sref">pfc1/a>);v.137n a"v.1381/a>1spa= class="comment">/* drivers/sh/pfc/core.c */1/spa="v.1391/a>int.1a href="+code=register_sh_pfc" class="sref">register_sh_pfc1/a>(struct.1a href="+code=sh_pfc" class="sref">sh_pfc1/a> *1a href="+code=pfc" class="sref">pfc1/a>);v.14on a"v.1411/a>int.1a href="+code=sh_pfc_read_bit" class="sref">sh_pfc_read_bit1/a>(struct.1a href="+code=pinmux_data_reg" class="sref">pinmux_data_reg1/a> *1a href="+code=dr" class="sref">dr1/a>, unsigned long.1a href="+code=in_pos" class="sref">in_pos1/a>);v.1421/a>void 1a href="+code=sh_pfc_write_bit" class="sref">sh_pfc_write_bit1/a>(struct.1a href="+code=pinmux_data_reg" class="sref">pinmux_data_reg1/a> *1a href="+code=dr" class="sref">dr1/a>, unsigned long.1a href="+code=in_pos" class="sref">in_pos1/a>,v.1431/a>                      unsigned long.1a href="+code=
  v3" class="sref">v  v31/a>);v.1441/a>int.1a href="+code=sh_pfc_get_data_reg" class="sref">sh_pfc_get_data_reg1/a>(struct.1a href="+code=sh_pfc" class="sref">sh_pfc1/a> *1a href="+code=pfc" class="sref">pfc1/a>, unsigned 1a href="+code=gpio" class="sref">gpio1/a>,v.1451/a>                        struct.1a href="+code=pinmux_data_reg" class="sref">pinmux_data_reg1/a> **1a href="+code=drp" class="sref">drp1/a>, int.*1a href="+code=bitp" class="sref">bitp1/a>);v.1461/a>int.1a href="+code=sh_pfc_gpio_to_enum" class="sref">sh_pfc_gpio_to_enum1/a>(struct.1a href="+code=sh_pfc" class="sref">sh_pfc1/a> *1a href="+code=pfc" class="sref">pfc1/a>, unsigned 1a href="+code=gpio" class="sref">gpio1/a>, int.1a href="+code=pos" class="sref">pos1/a>,v.1471/a>                        1a href="+code=pinmux_enum_t" class="sref">pinmux_enum_t1/a> *1a href="+code=enum_idp" class="sref">enum_idp1/a>);v.148n a"int.1a href="+code=sh_pfc_config_gpio" class="sref">sh_pfc_config_gpio1/a>(struct.1a href="+code=sh_pfc" class="sref">sh_pfc1/a> *1a href="+code=pfc" class="sref">pfc1/a>, unsigned 1a href="+code=gpio" class="sref">gpio1/a>, int.1a href="+code=pinmux_typ3" class="sref">pinmux_typ31/a>,v.1491/a>                       int.1a href="+code=cfg_mode" class="sref">cfg_mode1/a>);v.15on a"v.1511/a>1spa= class="comment">/* xxx */1/spa="v.1521/a>static.1a href="+code=inline" class="sref">inline1/a> int.1a href="+code=register_pinmux" class="sref">register_pinmux1/a>(struct.1a href="+code=pinmux_info" class="sref">pinmux_info1/a> *1a href="+code=pip" class="sref">pip1/a>)v.1531/a>{v.1541/a>        struct.1a href="+code=sh_pfc" class="sref">sh_pfc1/a> *1a href="+code=pfc" class="sref">pfc1/a> = 1a href="+code=pip" class="sref">pip1/a>;v.1551/a>        return 1a href="+code=register_sh_pfc" class="sref">register_sh_pfc1/a>(1a href="+code=pfc" class="sref">pfc1/a>);v.1561/a>}v.157n a"v.1581/a>enum { 1a href="+code=GPIO_CFG_DRYRUN" class="sref">GPIO_CFG_DRYRUN1/a>, 1a href="+code=GPIO_CFG_REQ" class="sref">GPIO_CFG_REQ1/a>, 1a href="+code=GPIO_CFG_FREE" class="sref">GPIO_CFG_FREE1/a> };v.159n a"v.16on a"1spa= class="comment">/* helper macro for port */1/spa="v.1611/a>#define.1a href="+code=PORT_1" class="sref">PORT_11/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>, 1a href="+code=sfx" class="sref">sfx1/a>) 1a href="+code=f=" class="sref">fn1/a>(1a href="+code=pfx" class="sref">pfx1/a>, 1a href="+code=sfx" class="sref">sfx1/a>)v.162n a"v.1631/a>#define.1a href="+code=PORT_10" class="sref">PORT_101/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>, 1a href="+code=sfx" class="sref">sfx1/a>) \v.1641/a>        1a href="+code=PORT_1" class="sref">PORT_11/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##0, 1a href="+code=sfx" class="sref">sfx1/a>), 1a href="+code=PORT_1" class="sref">PORT_11/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##1, 1a href="+code=sfx" class="sref">sfx1/a>),       \v.1651/a>        1a href="+code=PORT_1" class="sref">PORT_11/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##2, 1a href="+code=sfx" class="sref">sfx1/a>), 1a href="+code=PORT_1" class="sref">PORT_11/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##3, 1a href="+code=sfx" class="sref">sfx1/a>),       \v.1661/a>        1a href="+code=PORT_1" class="sref">PORT_11/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##4, 1a href="+code=sfx" class="sref">sfx1/a>), 1a href="+code=PORT_1" class="sref">PORT_11/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##5, 1a href="+code=sfx" class="sref">sfx1/a>),       \v.1671/a>        1a href="+code=PORT_1" class="sref">PORT_11/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##6, 1a href="+code=sfx" class="sref">sfx1/a>), 1a href="+code=PORT_1" class="sref">PORT_11/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##7, 1a href="+code=sfx" class="sref">sfx1/a>),       \v.1681/a>        1a href="+code=PORT_1" class="sref">PORT_11/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##8, 1a href="+code=sfx" class="sref">sfx1/a>), 1a href="+code=PORT_1" class="sref">PORT_11/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##9, 1a href="+code=sfx" class="sref">sfx1/a>)v.169n a"v.1701/a>#define.1a href="+code=PORT_90" class="sref">PORT_901/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>, 1a href="+code=sfx" class="sref">sfx1/a>) \v.1711/a>        1a href="+code=PORT_10" class="sref">PORT_101/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##1, 1a href="+code=sfx" class="sref">sfx1/a>), 1a href="+code=PORT_10" class="sref">PORT_101/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##2, 1a href="+code=sfx" class="sref">sfx1/a>),     \v.1721/a>        1a href="+code=PORT_10" class="sref">PORT_101/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##3, 1a href="+code=sfx" class="sref">sfx1/a>), 1a href="+code=PORT_10" class="sref">PORT_101/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##4, 1a href="+code=sfx" class="sref">sfx1/a>),     \v.1731/a>        1a href="+code=PORT_10" class="sref">PORT_101/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##5, 1a href="+code=sfx" class="sref">sfx1/a>), 1a href="+code=PORT_10" class="sref">PORT_101/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##6, 1a href="+code=sfx" class="sref">sfx1/a>),     \v.1741/a>        1a href="+code=PORT_10" class="sref">PORT_101/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##7, 1a href="+code=sfx" class="sref">sfx1/a>), 1a href="+code=PORT_10" class="sref">PORT_101/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##8, 1a href="+code=sfx" class="sref">sfx1/a>),     \v.1751/a>        1a href="+code=PORT_10" class="sref">PORT_101/a>(1a href="+code=f=" class="sref">fn1/a>, 1a href="+code=pfx" class="sref">pfx1/a>##9, 1a href="+code=sfx" class="sref">sfx1/a>)v.176n a"v.1771/a>#define.1a href="+code=_PORT_ALL" class="sref">_PORT_ALL1/a>(1a href="+code=pfx" class="sref">pfx1/a>, 1a href="+code=sfx" class="sref">sfx1/a>) 1a href="+code=pfx" class="sref">pfx1/a>##_##sfxv.1781/a>#define.1a href="+code=_GPIO_PORT" class="sref">_GPIO_PORT1/a>(1a href="+code=pfx" class="sref">pfx1/a>, 1a href="+code=sfx" class="sref">sfx1/a>) 1a href="+code=PINMUX_GPIO" class="sref">PINMUX_GPIO1/a>(1a href="+code=GPIO_PORT" class="sref">GPIO_PORT1/a>##pfx, 1a href="+code=PORT" class="sref">PORT1/a>##pfx##_DATA)v.1791/a>#define.1a href="+code=PORT_ALL" class="sref">PORT_ALL1/a>(1a href="+code=str" class="sref">str1/a>)   1a href="+code=CPU_ALL_PORT" class="sref">CPU_ALL_PORT1/a>(1a href="+code=_PORT_ALL" class="sref">_PORT_ALL1/a>, 1a href="+code=PORT" class="sref">PORT1/a>, 1a href="+code=str" class="sref">str1/a>)v.1801/a>#define.1a href="+code=GPIO_PORT_ALL" class="sref">GPIO_PORT_ALL1/a>() 1a href="+code=CPU_ALL_PORT" class="sref">CPU_ALL_PORT1/a>(1a href="+code=_GPIO_PORT" class="sref">_GPIO_PORT1/a>, , 1a href="+code=unused" class="sref">unused1/a>)v.1811/a>#define.1a href="+code=GPIO_FN" class="sref">GPIO_FN1/a>(1a href="+code=str" class="sref">str1/a>) 1a href="+code=PINMUX_GPIO" class="sref">PINMUX_GPIO1/a>(1a href="+code=GPIO_FN_" class="sref">GPIO_FN_1/a>##str, 1a href="+code=str" class="sref">str1/a>##_MARK)v.182n a"v.1831/a>1spa= class="comment">/* helper macro for pinmux_enum_t */1/spa="v.1841/a>#define.1a href="+code=PORT_DATA_I" class="sref">PORT_DATA_I1/a>(1a href="+code=nr" class="sref">nr1/a>) \v.1851/a>        1a href="+code=PINMUX_DATA" class="sref">PINMUX_DATA1/a>(1a href="+code=PORT" class="sref">PORT1/a>##nr##_DATA, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN0, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN)v.186n a"v.1871/a>#define.1a href="+code=PORT_DATA_I_PD" class="sref">PORT_DATA_I_PD1/a>(1a href="+code=nr" class="sref">nr1/a>)      \v.1881/a>        1a href="+code=PINMUX_DATA" class="sref">PINMUX_DATA1/a>(1a href="+code=PORT" class="sref">PORT1/a>##nr##_DATA, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN0,    \v.1891/a>                    1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN_PD)v.19on a"v.1911/a>#define.1a href="+code=PORT_DATA_I_PU" class="sref">PORT_DATA_I_PU1/a>(1a href="+code=nr" class="sref">nr1/a>)      \v.1921/a>        1a href="+code=PINMUX_DATA" class="sref">PINMUX_DATA1/a>(1a href="+code=PORT" class="sref">PORT1/a>##nr##_DATA, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN0,    \v.1931/a>                    1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN_PU)v.194n a"v.1951/a>#define.1a href="+code=PORT_DATA_I_PU_PD" class="sref">PORT_DATA_I_PU_PD1/a>(1a href="+code=nr" class="sref">nr1/a>)   \v.1961/a>        1a href="+code=PINMUX_DATA" class="sref">PINMUX_DATA1/a>(1a href="+code=PORT" class="sref">PORT1/a>##nr##_DATA, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN0,                    \v.1971/a>                    1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN_PD, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN_PU)v.198n a"v.1991/a>#define.1a href="+code=PORT_DATA_O" class="sref">PORT_DATA_O1/a>(1a href="+code=nr" class="sref">nr1/a>)         \v.2001/a>        1a href="+code=PINMUX_DATA" class="sref">PINMUX_DATA1/a>(1a href="+code=PORT" class="sref">PORT1/a>##nr##_DATA, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN0, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_OUT)v.201n a"v.2021/a>#define.1a href="+code=PORT_DATA_IO" class="sref">PORT_DATA_IO1/a>(1a href="+code=nr" class="sref">nr1/a>)        \v.2031/a>        1a href="+code=PINMUX_DATA" class="sref">PINMUX_DATA1/a>(1a href="+code=PORT" class="sref">PORT1/a>##nr##_DATA, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN0, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_OUT,    \v.2041/a>                    1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN)v.205n a"v.2061/a>#define.1a href="+code=PORT_DATA_IO_PD" class="sref">PORT_DATA_IO_PD1/a>(1a href="+code=nr" class="sref">nr1/a>)     \v.2071/a>        1a href="+code=PINMUX_DATA" class="sref">PINMUX_DATA1/a>(1a href="+code=PORT" class="sref">PORT1/a>##nr##_DATA, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN0, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_OUT,    \v.2081/a>                    1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN_PD)v.209n a"v.2101/a>#define.1a href="+code=PORT_DATA_IO_PU" class="sref">PORT_DATA_IO_PU1/a>(1a href="+code=nr" class="sref">nr1/a>)     \v.2111/a>        1a href="+code=PINMUX_DATA" class="sref">PINMUX_DATA1/a>(1a href="+code=PORT" class="sref">PORT1/a>##nr##_DATA, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN0, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_OUT,    \v.2121/a>                    1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN_PU)v.213n a"v.2141/a>#define.1a href="+code=PORT_DATA_IO_PU_PD" class="sref">PORT_DATA_IO_PU_PD1/a>(1a href="+code=nr" class="sref">nr1/a>)  \v.2151/a>        1a href="+code=PINMUX_DATA" class="sref">PINMUX_DATA1/a>(1a href="+code=PORT" class="sref">PORT1/a>##nr##_DATA, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN0, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_OUT,    \v.2161/a>                    1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN_PD, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN_PU)v.217n a"v.2181/a>1spa= class="comment">/* helper macro for top 4 bits in PORTnCR */1/spa="v.2191/a>#define.1a href="+code=_PCRH" class="sref">_PCRH1/a>(1a href="+code=in" class="sref">in1/a>, 1a href="+code=in_pd" class="sref">in_pd1/a>, 1a href="+code=in_pu" class="sref">in_pu1/a>, 1a href="+code=out" class="sref">out1/a>)    \v.2201/a>        0, (1a href="+code=out" class="sref">out1/a>), (1a href="+code=in" class="sref">in1/a>), 0,              \v.2211/a>        0, 0, 0, 0,                     \v.2221/a>        0, 0, (1a href="+code=in_pd" class="sref">in_pd1/a>), 0,               \v.2231/a>        0, 0, (1a href="+code=in_pu" class="sref">in_pu1/a>), 0v.224n a"v.2251/a>#define.1a href="+code=PORTCR" class="sref">PORTCR1/a>(1a href="+code=nr" class="sref">nr1/a>, 1a href="+code=reg" class="sref">reg1/a>)                                                 \v.2261/a>        {                                                               \v.2271/a>                1a href="+code=PINMUX_CFG_REG" class="sref">PINMUX_CFG_REG1/a>(1spa= class="string">"PORT"1/spa=" 1a href="+code=nr" class="sref">nr1/a> 1spa= class="string">"CR"1/spa=", 1a href="+code=reg" class="sref">reg1/a>, 8, 4) {             \v.2281/a>                        1a href="+code=_PCRH" class="sref">_PCRH1/a>(1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN_PD,          \v.2291/a>                              1a href="+code=PORT" class="sref">PORT1/a>##nr##_IN_PU, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_OUT),        \v.2301/a>                                1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN0, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN1,         \v.2311/a>                                1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN2, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN3,         \v.2321/a>                                1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN4, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN5,         \v.2331/a>                                1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN6, 1a href="+code=PORT" class="sref">PORT1/a>##nr##_FN7 }        \v.2341/a>        }v.235n a"v.2361/a>#endif 1spa= class="comment">/* __SH_PFC_H */1/spa="v.237n a"


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