linux/include/linux/sh_clk.h
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   1#ifndef __SH_CLOCK_H
   2#define __SH_CLOCK_H
   3
   4#include <linux/list.h>
   5#include <linux/seq_file.h>
   6#include <linux/cpufreq.h>
   7#include <linux/types.h>
   8#include <linux/kref.h>
   9#include <linux/clk.h>
  10#include <linux/err.h>
  11
  12struct clk;
  13
  14struct clk_mapping {
  15        phys_addr_t             phys;
  16        void __iomem            *base;
  17        unsigned long           len;
  18        struct kref             ref;
  19};
  20
  21struct sh_clk_ops {
  22#ifdef CONFIG_SH_CLK_CPG_LEGACY
  23        void (*init)(struct clk *clk);
  24#endif
  25        int (*enable)(struct clk *clk);
  26        void (*disable)(struct clk *clk);
  27        unsigned long (*recalc)(struct clk *clk);
  28        int (*set_rate)(struct clk *clk, unsigned long rate);
  29        int (*set_parent)(struct clk *clk, struct clk *parent);
  30        long (*round_rate)(struct clk *clk, unsigned long rate);
  31};
  32
  33#define SH_CLK_DIV_MSK(div)     ((1 << (div)) - 1)
  34#define SH_CLK_DIV4_MSK         SH_CLK_DIV_MSK(4)
  35#define SH_CLK_DIV6_MSK         SH_CLK_DIV_MSK(6)
  36
  37struct clk {
  38        struct list_head        node;
  39        struct clk              *parent;
  40        struct clk              **parent_table; /* list of parents to */
  41        unsigned short          parent_num;     /* choose between */
  42        unsigned char           src_shift;      /* source clock field in the */
  43        unsigned char           src_width;      /* configuration register */
  44        struct sh_clk_ops       *ops;
  45
  46        struct list_head        children;
  47        struct list_head        sibling;        /* node for children */
  48
  49        int                     usecount;
  50
  51        unsigned long           rate;
  52        unsigned long           flags;
  53
  54        void __iomem            *enable_reg;
  55        unsigned int            enable_bit;
  56        void __iomem            *mapped_reg;
  57
  58        unsigned int            div_mask;
  59        unsigned long           arch_flags;
  60        void                    *priv;
  61        struct clk_mapping      *mapping;
  62        struct cpufreq_frequency_table *freq_table;
  63        unsigned int            nr_freqs;
  64};
  65
  66#define CLK_ENABLE_ON_INIT      BIT(0)
  67
  68#define CLK_ENABLE_REG_32BIT    BIT(1)  /* default access size */
  69#define CLK_ENABLE_REG_16BIT    BIT(2)
  70#define CLK_ENABLE_REG_8BIT     BIT(3)
  71
  72#define CLK_MASK_DIV_ON_DISABLE BIT(4)
  73
  74#define CLK_ENABLE_REG_MASK     (CLK_ENABLE_REG_32BIT | \
  75                                 CLK_ENABLE_REG_16BIT | \
  76                                 CLK_ENABLE_REG_8BIT)
  77
  78/* drivers/sh/clk.c */
  79unsigned long followparent_recalc(struct clk *);
  80void recalculate_root_clocks(void);
  81void propagate_rate(struct clk *);
  82int clk_reparent(struct clk *child, struct clk *parent);
  83int clk_register(struct clk *);
  84void clk_unregister(struct clk *);
  85void clk_enable_init_clocks(void);
  86
  87struct clk_div_mult_table {
  88        unsigned int *divisors;
  89        unsigned int nr_divisors;
  90        unsigned int *multipliers;
  91        unsigned int nr_multipliers;
  92};
  93
  94struct cpufreq_frequency_table;
  95void clk_rate_table_build(struct clk *clk,
  96                          struct cpufreq_frequency_table *freq_table,
  97                          int nr_freqs,
  98                          struct clk_div_mult_table *src_table,
  99                          unsigned long *bitmap);
 100
 101long clk_rate_table_round(struct clk *clk,
 102                          struct cpufreq_frequency_table *freq_table,
 103                          unsigned long rate);
 104
 105int clk_rate_table_find(struct clk *clk,
 106                        struct cpufreq_frequency_table *freq_table,
 107                        unsigned long rate);
 108
 109long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
 110                              unsigned int div_max, unsigned long rate);
 111
 112long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
 113                               unsigned int mult_max, unsigned long rate);
 114
 115long clk_round_parent(struct clk *clk, unsigned long target,
 116                      unsigned long *best_freq, unsigned long *parent_freq,
 117                      unsigned int div_min, unsigned int div_max);
 118
 119#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags)          \
 120{                                                                       \
 121        .parent         = _parent,                                      \
 122        .enable_reg     = (void __iomem *)_enable_reg,                  \
 123        .enable_bit     = _enable_bit,                                  \
 124        .flags          = _flags,                                       \
 125}
 126
 127#define SH_CLK_MSTP32(_p, _r, _b, _f)                                   \
 128        SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT)
 129
 130#define SH_CLK_MSTP16(_p, _r, _b, _f)                                   \
 131        SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT)
 132
 133#define SH_CLK_MSTP8(_p, _r, _b, _f)                                    \
 134        SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT)
 135
 136int sh_clk_mstp_register(struct clk *clks, int nr);
 137
 138/*
 139 * MSTP registration never really cared about access size, despite the
 140 * original enable/disable pairs assuming a 32-bit access. Clocks are
 141 * responsible for defining their access sizes either directly or via the
 142 * clock definition wrappers.
 143 */
 144static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
 145{
 146        return sh_clk_mstp_register(clks, nr);
 147}
 148
 149#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
 150{                                                               \
 151        .parent = _parent,                                      \
 152        .enable_reg = (void __iomem *)_reg,                     \
 153        .enable_bit = _shift,                                   \
 154        .arch_flags = _div_bitmap,                              \
 155        .div_mask = SH_CLK_DIV4_MSK,                            \
 156        .flags = _flags,                                        \
 157}
 158
 159struct clk_div_table {
 160        struct clk_div_mult_table *div_mult_table;
 161        void (*kick)(struct clk *clk);
 162};
 163
 164#define clk_div4_table clk_div_table
 165
 166int sh_clk_div4_register(struct clk *clks, int nr,
 167                         struct clk_div4_table *table);
 168int sh_clk_div4_enable_register(struct clk *clks, int nr,
 169                         struct clk_div4_table *table);
 170int sh_clk_div4_reparent_register(struct clk *clks, int nr,
 171                         struct clk_div4_table *table);
 172
 173#define SH_CLK_DIV6_EXT(_reg, _flags, _parents,                 \
 174                        _num_parents, _src_shift, _src_width)   \
 175{                                                               \
 176        .enable_reg = (void __iomem *)_reg,                     \
 177        .enable_bit = 0, /* unused */                           \
 178        .flags = _flags | CLK_MASK_DIV_ON_DISABLE,              \
 179        .div_mask = SH_CLK_DIV6_MSK,                            \
 180        .parent_table = _parents,                               \
 181        .parent_num = _num_parents,                             \
 182        .src_shift = _src_shift,                                \
 183        .src_width = _src_width,                                \
 184}
 185
 186#define SH_CLK_DIV6(_parent, _reg, _flags)                      \
 187{                                                               \
 188        .parent         = _parent,                              \
 189        .enable_reg     = (void __iomem *)_reg,                 \
 190        .enable_bit     = 0,    /* unused */                    \
 191        .div_mask       = SH_CLK_DIV6_MSK,                      \
 192        .flags          = _flags | CLK_MASK_DIV_ON_DISABLE,     \
 193}
 194
 195int sh_clk_div6_register(struct clk *clks, int nr);
 196int sh_clk_div6_reparent_register(struct clk *clks, int nr);
 197
 198#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 199#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
 200#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
 201
 202#endif /* __SH_CLOCK_H */
 203
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