linux/include/linux/mdio.h
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   1/*
   2 * linux/mdio.h: definitions for MDIO (clause 45) transceivers
   3 * Copyright 2006-2009 Solarflare Communications Inc.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License version 2 as published
   7 * by the Free Software Foundation, incorporated herein by reference.
   8 */
   9
  10#ifndef __LINUX_MDIO_H__
  11#define __LINUX_MDIO_H__
  12
  13#include <linux/types.h>
  14#include <linux/mii.h>
  15
  16/* MDIO Manageable Devices (MMDs). */
  17#define MDIO_MMD_PMAPMD         1       /* Physical Medium Attachment/
  18                                         * Physical Medium Dependent */
  19#define MDIO_MMD_WIS            2       /* WAN Interface Sublayer */
  20#define MDIO_MMD_PCS            3       /* Physical Coding Sublayer */
  21#define MDIO_MMD_PHYXS          4       /* PHY Extender Sublayer */
  22#define MDIO_MMD_DTEXS          5       /* DTE Extender Sublayer */
  23#define MDIO_MMD_TC             6       /* Transmission Convergence */
  24#define MDIO_MMD_AN             7       /* Auto-Negotiation */
  25#define MDIO_MMD_C22EXT         29      /* Clause 22 extension */
  26#define MDIO_MMD_VEND1          30      /* Vendor specific 1 */
  27#define MDIO_MMD_VEND2          31      /* Vendor specific 2 */
  28
  29/* Generic MDIO registers. */
  30#define MDIO_CTRL1              MII_BMCR
  31#define MDIO_STAT1              MII_BMSR
  32#define MDIO_DEVID1             MII_PHYSID1
  33#define MDIO_DEVID2             MII_PHYSID2
  34#define MDIO_SPEED              4       /* Speed ability */
  35#define MDIO_DEVS1              5       /* Devices in package */
  36#define MDIO_DEVS2              6
  37#define MDIO_CTRL2              7       /* 10G control 2 */
  38#define MDIO_STAT2              8       /* 10G status 2 */
  39#define MDIO_PMA_TXDIS          9       /* 10G PMA/PMD transmit disable */
  40#define MDIO_PMA_RXDET          10      /* 10G PMA/PMD receive signal detect */
  41#define MDIO_PMA_EXTABLE        11      /* 10G PMA/PMD extended ability */
  42#define MDIO_PKGID1             14      /* Package identifier */
  43#define MDIO_PKGID2             15
  44#define MDIO_AN_ADVERTISE       16      /* AN advertising (base page) */
  45#define MDIO_AN_LPA             19      /* AN LP abilities (base page) */
  46#define MDIO_PCS_EEE_ABLE       20      /* EEE Capability register */
  47#define MDIO_PCS_EEE_WK_ERR     22      /* EEE wake error counter */
  48#define MDIO_PHYXS_LNSTAT       24      /* PHY XGXS lane state */
  49#define MDIO_AN_EEE_ADV         60      /* EEE advertisement */
  50#define MDIO_AN_EEE_LPABLE      61      /* EEE link partner ability */
  51
  52/* Media-dependent registers. */
  53#define MDIO_PMA_10GBT_SWAPPOL  130     /* 10GBASE-T pair swap & polarity */
  54#define MDIO_PMA_10GBT_TXPWR    131     /* 10GBASE-T TX power control */
  55#define MDIO_PMA_10GBT_SNR      133     /* 10GBASE-T SNR margin, lane A.
  56                                         * Lanes B-D are numbered 134-136. */
  57#define MDIO_PMA_10GBR_FECABLE  170     /* 10GBASE-R FEC ability */
  58#define MDIO_PCS_10GBX_STAT1    24      /* 10GBASE-X PCS status 1 */
  59#define MDIO_PCS_10GBRT_STAT1   32      /* 10GBASE-R/-T PCS status 1 */
  60#define MDIO_PCS_10GBRT_STAT2   33      /* 10GBASE-R/-T PCS status 2 */
  61#define MDIO_AN_10GBT_CTRL      32      /* 10GBASE-T auto-negotiation control */
  62#define MDIO_AN_10GBT_STAT      33      /* 10GBASE-T auto-negotiation status */
  63
  64/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
  65#define MDIO_PMA_LASI_RXCTRL    0x9000  /* RX_ALARM control */
  66#define MDIO_PMA_LASI_TXCTRL    0x9001  /* TX_ALARM control */
  67#define MDIO_PMA_LASI_CTRL      0x9002  /* LASI control */
  68#define MDIO_PMA_LASI_RXSTAT    0x9003  /* RX_ALARM status */
  69#define MDIO_PMA_LASI_TXSTAT    0x9004  /* TX_ALARM status */
  70#define MDIO_PMA_LASI_STAT      0x9005  /* LASI status */
  71
  72/* Control register 1. */
  73/* Enable extended speed selection */
  74#define MDIO_CTRL1_SPEEDSELEXT          (BMCR_SPEED1000 | BMCR_SPEED100)
  75/* All speed selection bits */
  76#define MDIO_CTRL1_SPEEDSEL             (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
  77#define MDIO_CTRL1_FULLDPLX             BMCR_FULLDPLX
  78#define MDIO_CTRL1_LPOWER               BMCR_PDOWN
  79#define MDIO_CTRL1_RESET                BMCR_RESET
  80#define MDIO_PMA_CTRL1_LOOPBACK         0x0001
  81#define MDIO_PMA_CTRL1_SPEED1000        BMCR_SPEED1000
  82#define MDIO_PMA_CTRL1_SPEED100         BMCR_SPEED100
  83#define MDIO_PCS_CTRL1_LOOPBACK         BMCR_LOOPBACK
  84#define MDIO_PHYXS_CTRL1_LOOPBACK       BMCR_LOOPBACK
  85#define MDIO_AN_CTRL1_RESTART           BMCR_ANRESTART
  86#define MDIO_AN_CTRL1_ENABLE            BMCR_ANENABLE
  87#define MDIO_AN_CTRL1_XNP               0x2000  /* Enable extended next page */
  88#define MDIO_PCS_CTRL1_CLKSTOP_EN       0x400   /* Stop the clock during LPI */
  89
  90/* 10 Gb/s */
  91#define MDIO_CTRL1_SPEED10G             (MDIO_CTRL1_SPEEDSELEXT | 0x00)
  92/* 10PASS-TS/2BASE-TL */
  93#define MDIO_CTRL1_SPEED10P2B           (MDIO_CTRL1_SPEEDSELEXT | 0x04)
  94
  95/* Status register 1. */
  96#define MDIO_STAT1_LPOWERABLE           0x0002  /* Low-power ability */
  97#define MDIO_STAT1_LSTATUS              BMSR_LSTATUS
  98#define MDIO_STAT1_FAULT                0x0080  /* Fault */
  99#define MDIO_AN_STAT1_LPABLE            0x0001  /* Link partner AN ability */
 100#define MDIO_AN_STAT1_ABLE              BMSR_ANEGCAPABLE
 101#define MDIO_AN_STAT1_RFAULT            BMSR_RFAULT
 102#define MDIO_AN_STAT1_COMPLETE          BMSR_ANEGCOMPLETE
 103#define MDIO_AN_STAT1_PAGE              0x0040  /* Page received */
 104#define MDIO_AN_STAT1_XNP               0x0080  /* Extended next page status */
 105
 106/* Speed register. */
 107#define MDIO_SPEED_10G                  0x0001  /* 10G capable */
 108#define MDIO_PMA_SPEED_2B               0x0002  /* 2BASE-TL capable */
 109#define MDIO_PMA_SPEED_10P              0x0004  /* 10PASS-TS capable */
 110#define MDIO_PMA_SPEED_1000             0x0010  /* 1000M capable */
 111#define MDIO_PMA_SPEED_100              0x0020  /* 100M capable */
 112#define MDIO_PMA_SPEED_10               0x0040  /* 10M capable */
 113#define MDIO_PCS_SPEED_10P2B            0x0002  /* 10PASS-TS/2BASE-TL capable */
 114
 115/* Device present registers. */
 116#define MDIO_DEVS_PRESENT(devad)        (1 << (devad))
 117#define MDIO_DEVS_PMAPMD                MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
 118#define MDIO_DEVS_WIS                   MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
 119#define MDIO_DEVS_PCS                   MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
 120#define MDIO_DEVS_PHYXS                 MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
 121#define MDIO_DEVS_DTEXS                 MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
 122#define MDIO_DEVS_TC                    MDIO_DEVS_PRESENT(MDIO_MMD_TC)
 123#define MDIO_DEVS_AN                    MDIO_DEVS_PRESENT(MDIO_MMD_AN)
 124#define MDIO_DEVS_C22EXT                MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
 125
 126/* Control register 2. */
 127#define MDIO_PMA_CTRL2_TYPE             0x000f  /* PMA/PMD type selection */
 128#define MDIO_PMA_CTRL2_10GBCX4          0x0000  /* 10GBASE-CX4 type */
 129#define MDIO_PMA_CTRL2_10GBEW           0x0001  /* 10GBASE-EW type */
 130#define MDIO_PMA_CTRL2_10GBLW           0x0002  /* 10GBASE-LW type */
 131#define MDIO_PMA_CTRL2_10GBSW           0x0003  /* 10GBASE-SW type */
 132#define MDIO_PMA_CTRL2_10GBLX4          0x0004  /* 10GBASE-LX4 type */
 133#define MDIO_PMA_CTRL2_10GBER           0x0005  /* 10GBASE-ER type */
 134#define MDIO_PMA_CTRL2_10GBLR           0x0006  /* 10GBASE-LR type */
 135#define MDIO_PMA_CTRL2_10GBSR           0x0007  /* 10GBASE-SR type */
 136#define MDIO_PMA_CTRL2_10GBLRM          0x0008  /* 10GBASE-LRM type */
 137#define MDIO_PMA_CTRL2_10GBT            0x0009  /* 10GBASE-T type */
 138#define MDIO_PMA_CTRL2_10GBKX4          0x000a  /* 10GBASE-KX4 type */
 139#define MDIO_PMA_CTRL2_10GBKR           0x000b  /* 10GBASE-KR type */
 140#define MDIO_PMA_CTRL2_1000BT           0x000c  /* 1000BASE-T type */
 141#define MDIO_PMA_CTRL2_1000BKX          0x000d  /* 1000BASE-KX type */
 142#define MDIO_PMA_CTRL2_100BTX           0x000e  /* 100BASE-TX type */
 143#define MDIO_PMA_CTRL2_10BT             0x000f  /* 10BASE-T type */
 144#define MDIO_PCS_CTRL2_TYPE             0x0003  /* PCS type selection */
 145#define MDIO_PCS_CTRL2_10GBR            0x0000  /* 10GBASE-R type */
 146#define MDIO_PCS_CTRL2_10GBX            0x0001  /* 10GBASE-X type */
 147#define MDIO_PCS_CTRL2_10GBW            0x0002  /* 10GBASE-W type */
 148#define MDIO_PCS_CTRL2_10GBT            0x0003  /* 10GBASE-T type */
 149
 150/* Status register 2. */
 151#define MDIO_STAT2_RXFAULT              0x0400  /* Receive fault */
 152#define MDIO_STAT2_TXFAULT              0x0800  /* Transmit fault */
 153#define MDIO_STAT2_DEVPRST              0xc000  /* Device present */
 154#define MDIO_STAT2_DEVPRST_VAL          0x8000  /* Device present value */
 155#define MDIO_PMA_STAT2_LBABLE           0x0001  /* PMA loopback ability */
 156#define MDIO_PMA_STAT2_10GBEW           0x0002  /* 10GBASE-EW ability */
 157#define MDIO_PMA_STAT2_10GBLW           0x0004  /* 10GBASE-LW ability */
 158#define MDIO_PMA_STAT2_10GBSW           0x0008  /* 10GBASE-SW ability */
 159#define MDIO_PMA_STAT2_10GBLX4          0x0010  /* 10GBASE-LX4 ability */
 160#define MDIO_PMA_STAT2_10GBER           0x0020  /* 10GBASE-ER ability */
 161#define MDIO_PMA_STAT2_10GBLR           0x0040  /* 10GBASE-LR ability */
 162#define MDIO_PMA_STAT2_10GBSR           0x0080  /* 10GBASE-SR ability */
 163#define MDIO_PMD_STAT2_TXDISAB          0x0100  /* PMD TX disable ability */
 164#define MDIO_PMA_STAT2_EXTABLE          0x0200  /* Extended abilities */
 165#define MDIO_PMA_STAT2_RXFLTABLE        0x1000  /* Receive fault ability */
 166#define MDIO_PMA_STAT2_TXFLTABLE        0x2000  /* Transmit fault ability */
 167#define MDIO_PCS_STAT2_10GBR            0x0001  /* 10GBASE-R capable */
 168#define MDIO_PCS_STAT2_10GBX            0x0002  /* 10GBASE-X capable */
 169#define MDIO_PCS_STAT2_10GBW            0x0004  /* 10GBASE-W capable */
 170#define MDIO_PCS_STAT2_RXFLTABLE        0x1000  /* Receive fault ability */
 171#define MDIO_PCS_STAT2_TXFLTABLE        0x2000  /* Transmit fault ability */
 172
 173/* Transmit disable register. */
 174#define MDIO_PMD_TXDIS_GLOBAL           0x0001  /* Global PMD TX disable */
 175#define MDIO_PMD_TXDIS_0                0x0002  /* PMD TX disable 0 */
 176#define MDIO_PMD_TXDIS_1                0x0004  /* PMD TX disable 1 */
 177#define MDIO_PMD_TXDIS_2                0x0008  /* PMD TX disable 2 */
 178#define MDIO_PMD_TXDIS_3                0x0010  /* PMD TX disable 3 */
 179
 180/* Receive signal detect register. */
 181#define MDIO_PMD_RXDET_GLOBAL           0x0001  /* Global PMD RX signal detect */
 182#define MDIO_PMD_RXDET_0                0x0002  /* PMD RX signal detect 0 */
 183#define MDIO_PMD_RXDET_1                0x0004  /* PMD RX signal detect 1 */
 184#define MDIO_PMD_RXDET_2                0x0008  /* PMD RX signal detect 2 */
 185#define MDIO_PMD_RXDET_3                0x0010  /* PMD RX signal detect 3 */
 186
 187/* Extended abilities register. */
 188#define MDIO_PMA_EXTABLE_10GCX4         0x0001  /* 10GBASE-CX4 ability */
 189#define MDIO_PMA_EXTABLE_10GBLRM        0x0002  /* 10GBASE-LRM ability */
 190#define MDIO_PMA_EXTABLE_10GBT          0x0004  /* 10GBASE-T ability */
 191#define MDIO_PMA_EXTABLE_10GBKX4        0x0008  /* 10GBASE-KX4 ability */
 192#define MDIO_PMA_EXTABLE_10GBKR         0x0010  /* 10GBASE-KR ability */
 193#define MDIO_PMA_EXTABLE_1000BT         0x0020  /* 1000BASE-T ability */
 194#define MDIO_PMA_EXTABLE_1000BKX        0x0040  /* 1000BASE-KX ability */
 195#define MDIO_PMA_EXTABLE_100BTX         0x0080  /* 100BASE-TX ability */
 196#define MDIO_PMA_EXTABLE_10BT           0x0100  /* 10BASE-T ability */
 197
 198/* PHY XGXS lane state register. */
 199#define MDIO_PHYXS_LNSTAT_SYNC0         0x0001
 200#define MDIO_PHYXS_LNSTAT_SYNC1         0x0002
 201#define MDIO_PHYXS_LNSTAT_SYNC2         0x0004
 202#define MDIO_PHYXS_LNSTAT_SYNC3         0x0008
 203#define MDIO_PHYXS_LNSTAT_ALIGN         0x1000
 204
 205/* PMA 10GBASE-T pair swap & polarity */
 206#define MDIO_PMA_10GBT_SWAPPOL_ABNX     0x0001  /* Pair A/B uncrossed */
 207#define MDIO_PMA_10GBT_SWAPPOL_CDNX     0x0002  /* Pair C/D uncrossed */
 208#define MDIO_PMA_10GBT_SWAPPOL_AREV     0x0100  /* Pair A polarity reversed */
 209#define MDIO_PMA_10GBT_SWAPPOL_BREV     0x0200  /* Pair B polarity reversed */
 210#define MDIO_PMA_10GBT_SWAPPOL_CREV     0x0400  /* Pair C polarity reversed */
 211#define MDIO_PMA_10GBT_SWAPPOL_DREV     0x0800  /* Pair D polarity reversed */
 212
 213/* PMA 10GBASE-T TX power register. */
 214#define MDIO_PMA_10GBT_TXPWR_SHORT      0x0001  /* Short-reach mode */
 215
 216/* PMA 10GBASE-T SNR registers. */
 217/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
 218#define MDIO_PMA_10GBT_SNR_BIAS         0x8000
 219#define MDIO_PMA_10GBT_SNR_MAX          127
 220
 221/* PMA 10GBASE-R FEC ability register. */
 222#define MDIO_PMA_10GBR_FECABLE_ABLE     0x0001  /* FEC ability */
 223#define MDIO_PMA_10GBR_FECABLE_ERRABLE  0x0002  /* FEC error indic. ability */
 224
 225/* PCS 10GBASE-R/-T status register 1. */
 226#define MDIO_PCS_10GBRT_STAT1_BLKLK     0x0001  /* Block lock attained */
 227
 228/* PCS 10GBASE-R/-T status register 2. */
 229#define MDIO_PCS_10GBRT_STAT2_ERR       0x00ff
 230#define MDIO_PCS_10GBRT_STAT2_BER       0x3f00
 231
 232/* AN 10GBASE-T control register. */
 233#define MDIO_AN_10GBT_CTRL_ADV10G       0x1000  /* Advertise 10GBASE-T */
 234
 235/* AN 10GBASE-T status register. */
 236#define MDIO_AN_10GBT_STAT_LPTRR        0x0200  /* LP training reset req. */
 237#define MDIO_AN_10GBT_STAT_LPLTABLE     0x0400  /* LP loop timing ability */
 238#define MDIO_AN_10GBT_STAT_LP10G        0x0800  /* LP is 10GBT capable */
 239#define MDIO_AN_10GBT_STAT_REMOK        0x1000  /* Remote OK */
 240#define MDIO_AN_10GBT_STAT_LOCOK        0x2000  /* Local OK */
 241#define MDIO_AN_10GBT_STAT_MS           0x4000  /* Master/slave config */
 242#define MDIO_AN_10GBT_STAT_MSFLT        0x8000  /* Master/slave config fault */
 243
 244/* EEE Supported/Advertisement/LP Advertisement registers.
 245 *
 246 * EEE capability Register (3.20), Advertisement (7.60) and
 247 * Link partner ability (7.61) registers have and can use the same identical
 248 * bit masks.
 249 */
 250#define MDIO_AN_EEE_ADV_100TX   0x0002  /* Advertise 100TX EEE cap */
 251#define MDIO_AN_EEE_ADV_1000T   0x0004  /* Advertise 1000T EEE cap */
 252/* Note: the two defines above can be potentially used by the user-land
 253 * and cannot remove them now.
 254 * So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros
 255 * using the previous ones (that can be considered obsolete).
 256 */
 257#define MDIO_EEE_100TX          MDIO_AN_EEE_ADV_100TX   /* 100TX EEE cap */
 258#define MDIO_EEE_1000T          MDIO_AN_EEE_ADV_1000T   /* 1000T EEE cap */
 259#define MDIO_EEE_10GT           0x0008  /* 10GT EEE cap */
 260#define MDIO_EEE_1000KX         0x0010  /* 1000KX EEE cap */
 261#define MDIO_EEE_10GKX4         0x0020  /* 10G KX4 EEE cap */
 262#define MDIO_EEE_10GKR          0x0040  /* 10G KR EEE cap */
 263
 264/* LASI RX_ALARM control/status registers. */
 265#define MDIO_PMA_LASI_RX_PHYXSLFLT      0x0001  /* PHY XS RX local fault */
 266#define MDIO_PMA_LASI_RX_PCSLFLT        0x0008  /* PCS RX local fault */
 267#define MDIO_PMA_LASI_RX_PMALFLT        0x0010  /* PMA/PMD RX local fault */
 268#define MDIO_PMA_LASI_RX_OPTICPOWERFLT  0x0020  /* RX optical power fault */
 269#define MDIO_PMA_LASI_RX_WISLFLT        0x0200  /* WIS local fault */
 270
 271/* LASI TX_ALARM control/status registers. */
 272#define MDIO_PMA_LASI_TX_PHYXSLFLT      0x0001  /* PHY XS TX local fault */
 273#define MDIO_PMA_LASI_TX_PCSLFLT        0x0008  /* PCS TX local fault */
 274#define MDIO_PMA_LASI_TX_PMALFLT        0x0010  /* PMA/PMD TX local fault */
 275#define MDIO_PMA_LASI_TX_LASERPOWERFLT  0x0080  /* Laser output power fault */
 276#define MDIO_PMA_LASI_TX_LASERTEMPFLT   0x0100  /* Laser temperature fault */
 277#define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200  /* Laser bias current fault */
 278
 279/* LASI control/status registers. */
 280#define MDIO_PMA_LASI_LSALARM           0x0001  /* LS_ALARM enable/status */
 281#define MDIO_PMA_LASI_TXALARM           0x0002  /* TX_ALARM enable/status */
 282#define MDIO_PMA_LASI_RXALARM           0x0004  /* RX_ALARM enable/status */
 283
 284/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */
 285
 286#define MDIO_PHY_ID_C45                 0x8000
 287#define MDIO_PHY_ID_PRTAD               0x03e0
 288#define MDIO_PHY_ID_DEVAD               0x001f
 289#define MDIO_PHY_ID_C45_MASK                                            \
 290        (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
 291
 292static inline __u16 mdio_phy_id_c45(int prtad, int devad)
 293{
 294        return MDIO_PHY_ID_C45 | (prtad << 5) | devad;
 295}
 296
 297#ifdef __KERNEL__
 298
 299static inline bool mdio_phy_id_is_c45(int phy_id)
 300{
 301        return (phy_id & MDIO_PHY_ID_C45) && !(phy_id & ~MDIO_PHY_ID_C45_MASK);
 302}
 303
 304static inline __u16 mdio_phy_id_prtad(int phy_id)
 305{
 306        return (phy_id & MDIO_PHY_ID_PRTAD) >> 5;
 307}
 308
 309static inline __u16 mdio_phy_id_devad(int phy_id)
 310{
 311        return phy_id & MDIO_PHY_ID_DEVAD;
 312}
 313
 314/**
 315 * struct mdio_if_info - Ethernet controller MDIO interface
 316 * @prtad: PRTAD of the PHY (%MDIO_PRTAD_NONE if not present/unknown)
 317 * @mmds: Mask of MMDs expected to be present in the PHY.  This must be
 318 *      non-zero unless @prtad = %MDIO_PRTAD_NONE.
 319 * @mode_support: MDIO modes supported.  If %MDIO_SUPPORTS_C22 is set then
 320 *      MII register access will be passed through with @devad =
 321 *      %MDIO_DEVAD_NONE.  If %MDIO_EMULATE_C22 is set then access to
 322 *      commonly used clause 22 registers will be translated into
 323 *      clause 45 registers.
 324 * @dev: Net device structure
 325 * @mdio_read: Register read function; returns value or negative error code
 326 * @mdio_write: Register write function; returns 0 or negative error code
 327 */
 328struct mdio_if_info {
 329        int prtad;
 330        u32 mmds;
 331        unsigned mode_support;
 332
 333        struct net_device *dev;
 334        int (*mdio_read)(struct net_device *dev, int prtad, int devad,
 335                         u16 addr);
 336        int (*mdio_write)(struct net_device *dev, int prtad, int devad,
 337                          u16 addr, u16 val);
 338};
 339
 340#define MDIO_PRTAD_NONE                 (-1)
 341#define MDIO_DEVAD_NONE                 (-1)
 342#define MDIO_SUPPORTS_C22               1
 343#define MDIO_SUPPORTS_C45               2
 344#define MDIO_EMULATE_C22                4
 345
 346struct ethtool_cmd;
 347struct ethtool_pauseparam;
 348extern int mdio45_probe(struct mdio_if_info *mdio, int prtad);
 349extern int mdio_set_flag(const struct mdio_if_info *mdio,
 350                         int prtad, int devad, u16 addr, int mask,
 351                         bool sense);
 352extern int mdio45_links_ok(const struct mdio_if_info *mdio, u32 mmds);
 353extern int mdio45_nway_restart(const struct mdio_if_info *mdio);
 354extern void mdio45_ethtool_gset_npage(const struct mdio_if_info *mdio,
 355                                      struct ethtool_cmd *ecmd,
 356                                      u32 npage_adv, u32 npage_lpa);
 357extern void
 358mdio45_ethtool_spauseparam_an(const struct mdio_if_info *mdio,
 359                              const struct ethtool_pauseparam *ecmd);
 360
 361/**
 362 * mdio45_ethtool_gset - get settings for ETHTOOL_GSET
 363 * @mdio: MDIO interface
 364 * @ecmd: Ethtool request structure
 365 *
 366 * Since the CSRs for auto-negotiation using next pages are not fully
 367 * standardised, this function does not attempt to decode them.  Use
 368 * mdio45_ethtool_gset_npage() to specify advertisement bits from next
 369 * pages.
 370 */
 371static inline void mdio45_ethtool_gset(const struct mdio_if_info *mdio,
 372                                       struct ethtool_cmd *ecmd)
 373{
 374        mdio45_ethtool_gset_npage(mdio, ecmd, 0, 0);
 375}
 376
 377extern int mdio_mii_ioctl(const struct mdio_if_info *mdio,
 378                          struct mii_ioctl_data *mii_data, int cmd);
 379
 380#endif /* __KERNEL__ */
 381#endif /* __LINUX_MDIO_H__ */
 382
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