linux/include/linux/dmaengine.h
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   1/*
   2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms of the GNU General Public License as published by the Free
   6 * Software Foundation; either version 2 of the License, or (at your option)
   7 * any later version.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program; if not, write to the Free Software Foundation, Inc., 59
  16 * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17 *
  18 * The full GNU General Public License is included in this distribution in the
  19 * file called COPYING.
  20 */
  21#ifndef LINUX_DMAENGINE_H
  22#define LINUX_DMAENGINE_H
  23
  24#include <linux/device.h>
  25#include <linux/uio.h>
  26#include <linux/bug.h>
  27#include <linux/scatterlist.h>
  28#include <linux/bitmap.h>
  29#include <linux/types.h>
  30#include <asm/page.h>
  31
  32/**
  33 * typedef dma_cookie_t - an opaque DMA cookie
  34 *
  35 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
  36 */
  37typedef s32 dma_cookie_t;
  38#define DMA_MIN_COOKIE  1
  39#define DMA_MAX_COOKIE  INT_MAX
  40
  41#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
  42
  43/**
  44 * enum dma_status - DMA transaction status
  45 * @DMA_SUCCESS: transaction completed successfully
  46 * @DMA_IN_PROGRESS: transaction not yet processed
  47 * @DMA_PAUSED: transaction is paused
  48 * @DMA_ERROR: transaction failed
  49 */
  50enum dma_status {
  51        DMA_SUCCESS,
  52        DMA_IN_PROGRESS,
  53        DMA_PAUSED,
  54        DMA_ERROR,
  55};
  56
  57/**
  58 * enum dma_transaction_type - DMA transaction types/indexes
  59 *
  60 * Note: The DMA_ASYNC_TX capability is not to be set by drivers.  It is
  61 * automatically set as dma devices are registered.
  62 */
  63enum dma_transaction_type {
  64        DMA_MEMCPY,
  65        DMA_XOR,
  66        DMA_PQ,
  67        DMA_XOR_VAL,
  68        DMA_PQ_VAL,
  69        DMA_MEMSET,
  70        DMA_INTERRUPT,
  71        DMA_SG,
  72        DMA_PRIVATE,
  73        DMA_ASYNC_TX,
  74        DMA_SLAVE,
  75        DMA_CYCLIC,
  76        DMA_INTERLEAVE,
  77/* last transaction type for creation of the capabilities mask */
  78        DMA_TX_TYPE_END,
  79};
  80
  81/**
  82 * enum dma_transfer_direction - dma transfer mode and direction indicator
  83 * @DMA_MEM_TO_MEM: Async/Memcpy mode
  84 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
  85 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
  86 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
  87 */
  88enum dma_transfer_direction {
  89        DMA_MEM_TO_MEM,
  90        DMA_MEM_TO_DEV,
  91        DMA_DEV_TO_MEM,
  92        DMA_DEV_TO_DEV,
  93        DMA_TRANS_NONE,
  94};
  95
  96/**
  97 * Interleaved Transfer Request
  98 * ----------------------------
  99 * A chunk is collection of contiguous bytes to be transfered.
 100 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
 101 * ICGs may or maynot change between chunks.
 102 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
 103 *  that when repeated an integral number of times, specifies the transfer.
 104 * A transfer template is specification of a Frame, the number of times
 105 *  it is to be repeated and other per-transfer attributes.
 106 *
 107 * Practically, a client driver would have ready a template for each
 108 *  type of transfer it is going to need during its lifetime and
 109 *  set only 'src_start' and 'dst_start' before submitting the requests.
 110 *
 111 *
 112 *  |      Frame-1        |       Frame-2       | ~ |       Frame-'numf'  |
 113 *  |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
 114 *
 115 *    ==  Chunk size
 116 *    ... ICG
 117 */
 118
 119/**
 120 * struct data_chunk - Element of scatter-gather list that makes a frame.
 121 * @size: Number of bytes to read from source.
 122 *        size_dst := fn(op, size_src), so doesn't mean much for destination.
 123 * @icg: Number of bytes to jump after last src/dst address of this
 124 *       chunk and before first src/dst address for next chunk.
 125 *       Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
 126 *       Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
 127 */
 128struct data_chunk {
 129        size_t size;
 130        size_t icg;
 131};
 132
 133/**
 134 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
 135 *       and attributes.
 136 * @src_start: Bus address of source for the first chunk.
 137 * @dst_start: Bus address of destination for the first chunk.
 138 * @dir: Specifies the type of Source and Destination.
 139 * @src_inc: If the source address increments after reading from it.
 140 * @dst_inc: If the destination address increments after writing to it.
 141 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
 142 *              Otherwise, source is read contiguously (icg ignored).
 143 *              Ignored if src_inc is false.
 144 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
 145 *              Otherwise, destination is filled contiguously (icg ignored).
 146 *              Ignored if dst_inc is false.
 147 * @numf: Number of frames in this template.
 148 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
 149 * @sgl: Array of {chunk,icg} pairs that make up a frame.
 150 */
 151struct dma_interleaved_template {
 152        dma_addr_t src_start;
 153        dma_addr_t dst_start;
 154        enum dma_transfer_direction dir;
 155        bool src_inc;
 156        bool dst_inc;
 157        bool src_sgl;
 158        bool dst_sgl;
 159        size_t numf;
 160        size_t frame_size;
 161        struct data_chunk sgl[0];
 162};
 163
 164/**
 165 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
 166 *  control completion, and communicate status.
 167 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
 168 *  this transaction
 169 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
 170 *  acknowledges receipt, i.e. has has a chance to establish any dependency
 171 *  chains
 172 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
 173 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
 174 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
 175 *      (if not set, do the source dma-unmapping as page)
 176 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
 177 *      (if not set, do the destination dma-unmapping as page)
 178 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
 179 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
 180 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
 181 *  sources that were the result of a previous operation, in the case of a PQ
 182 *  operation it continues the calculation with new sources
 183 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
 184 *  on the result of this operation
 185 */
 186enum dma_ctrl_flags {
 187        DMA_PREP_INTERRUPT = (1 << 0),
 188        DMA_CTRL_ACK = (1 << 1),
 189        DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
 190        DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
 191        DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
 192        DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
 193        DMA_PREP_PQ_DISABLE_P = (1 << 6),
 194        DMA_PREP_PQ_DISABLE_Q = (1 << 7),
 195        DMA_PREP_CONTINUE = (1 << 8),
 196        DMA_PREP_FENCE = (1 << 9),
 197};
 198
 199/**
 200 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
 201 * on a running channel.
 202 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
 203 * @DMA_PAUSE: pause ongoing transfers
 204 * @DMA_RESUME: resume paused transfer
 205 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
 206 * that need to runtime reconfigure the slave channels (as opposed to passing
 207 * configuration data in statically from the platform). An additional
 208 * argument of struct dma_slave_config must be passed in with this
 209 * command.
 210 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
 211 * into external start mode.
 212 */
 213enum dma_ctrl_cmd {
 214        DMA_TERMINATE_ALL,
 215        DMA_PAUSE,
 216        DMA_RESUME,
 217        DMA_SLAVE_CONFIG,
 218        FSLDMA_EXTERNAL_START,
 219};
 220
 221/**
 222 * enum sum_check_bits - bit position of pq_check_flags
 223 */
 224enum sum_check_bits {
 225        SUM_CHECK_P = 0,
 226        SUM_CHECK_Q = 1,
 227};
 228
 229/**
 230 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
 231 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
 232 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
 233 */
 234enum sum_check_flags {
 235        SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
 236        SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
 237};
 238
 239
 240/**
 241 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
 242 * See linux/cpumask.h
 243 */
 244typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
 245
 246/**
 247 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
 248 * @memcpy_count: transaction counter
 249 * @bytes_transferred: byte counter
 250 */
 251
 252struct dma_chan_percpu {
 253        /* stats */
 254        unsigned long memcpy_count;
 255        unsigned long bytes_transferred;
 256};
 257
 258/**
 259 * struct dma_chan - devices supply DMA channels, clients use them
 260 * @device: ptr to the dma device who supplies this channel, always !%NULL
 261 * @cookie: last cookie value returned to client
 262 * @completed_cookie: last completed cookie for this channel
 263 * @chan_id: channel ID for sysfs
 264 * @dev: class device for sysfs
 265 * @device_node: used to add this to the device chan list
 266 * @local: per-cpu pointer to a struct dma_chan_percpu
 267 * @client-count: how many clients are using this channel
 268 * @table_count: number of appearances in the mem-to-mem allocation table
 269 * @private: private data for certain client-channel associations
 270 */
 271struct dma_chan {
 272        struct dma_device *device;
 273        dma_cookie_t cookie;
 274        dma_cookie_t completed_cookie;
 275
 276        /* sysfs */
 277        int chan_id;
 278        struct dma_chan_dev *dev;
 279
 280        struct list_head device_node;
 281        struct dma_chan_percpu __percpu *local;
 282        int client_count;
 283        int table_count;
 284        void *private;
 285};
 286
 287/**
 288 * struct dma_chan_dev - relate sysfs device node to backing channel device
 289 * @chan - driver channel device
 290 * @device - sysfs device
 291 * @dev_id - parent dma_device dev_id
 292 * @idr_ref - reference count to gate release of dma_device dev_id
 293 */
 294struct dma_chan_dev {
 295        struct dma_chan *chan;
 296        struct device device;
 297        int dev_id;
 298        atomic_t *idr_ref;
 299};
 300
 301/**
 302 * enum dma_slave_buswidth - defines bus with of the DMA slave
 303 * device, source or target buses
 304 */
 305enum dma_slave_buswidth {
 306        DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
 307        DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
 308        DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
 309        DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
 310        DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
 311};
 312
 313/**
 314 * struct dma_slave_config - dma slave channel runtime config
 315 * @direction: whether the data shall go in or out on this slave
 316 * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
 317 * legal values, DMA_BIDIRECTIONAL is not acceptable since we
 318 * need to differentiate source and target addresses.
 319 * @src_addr: this is the physical address where DMA slave data
 320 * should be read (RX), if the source is memory this argument is
 321 * ignored.
 322 * @dst_addr: this is the physical address where DMA slave data
 323 * should be written (TX), if the source is memory this argument
 324 * is ignored.
 325 * @src_addr_width: this is the width in bytes of the source (RX)
 326 * register where DMA data shall be read. If the source
 327 * is memory this may be ignored depending on architecture.
 328 * Legal values: 1, 2, 4, 8.
 329 * @dst_addr_width: same as src_addr_width but for destination
 330 * target (TX) mutatis mutandis.
 331 * @src_maxburst: the maximum number of words (note: words, as in
 332 * units of the src_addr_width member, not bytes) that can be sent
 333 * in one burst to the device. Typically something like half the
 334 * FIFO depth on I/O peripherals so you don't overflow it. This
 335 * may or may not be applicable on memory sources.
 336 * @dst_maxburst: same as src_maxburst but for destination target
 337 * mutatis mutandis.
 338 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
 339 * with 'true' if peripheral should be flow controller. Direction will be
 340 * selected at Runtime.
 341 * @slave_id: Slave requester id. Only valid for slave channels. The dma
 342 * slave peripheral will have unique id as dma requester which need to be
 343 * pass as slave config.
 344 *
 345 * This struct is passed in as configuration data to a DMA engine
 346 * in order to set up a certain channel for DMA transport at runtime.
 347 * The DMA device/engine has to provide support for an additional
 348 * command in the channel config interface, DMA_SLAVE_CONFIG
 349 * and this struct will then be passed in as an argument to the
 350 * DMA engine device_control() function.
 351 *
 352 * The rationale for adding configuration information to this struct
 353 * is as follows: if it is likely that most DMA slave controllers in
 354 * the world will support the configuration option, then make it
 355 * generic. If not: if it is fixed so that it be sent in static from
 356 * the platform data, then prefer to do that. Else, if it is neither
 357 * fixed at runtime, nor generic enough (such as bus mastership on
 358 * some CPU family and whatnot) then create a custom slave config
 359 * struct and pass that, then make this config a member of that
 360 * struct, if applicable.
 361 */
 362struct dma_slave_config {
 363        enum dma_transfer_direction direction;
 364        dma_addr_t src_addr;
 365        dma_addr_t dst_addr;
 366        enum dma_slave_buswidth src_addr_width;
 367        enum dma_slave_buswidth dst_addr_width;
 368        u32 src_maxburst;
 369        u32 dst_maxburst;
 370        bool device_fc;
 371        unsigned int slave_id;
 372};
 373
 374static inline const char *dma_chan_name(struct dma_chan *chan)
 375{
 376        return dev_name(&chan->dev->device);
 377}
 378
 379void dma_chan_cleanup(struct kref *kref);
 380
 381/**
 382 * typedef dma_filter_fn - callback filter for dma_request_channel
 383 * @chan: channel to be reviewed
 384 * @filter_param: opaque parameter passed through dma_request_channel
 385 *
 386 * When this optional parameter is specified in a call to dma_request_channel a
 387 * suitable channel is passed to this routine for further dispositioning before
 388 * being returned.  Where 'suitable' indicates a non-busy channel that
 389 * satisfies the given capability mask.  It returns 'true' to indicate that the
 390 * channel is suitable.
 391 */
 392typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
 393
 394typedef void (*dma_async_tx_callback)(void *dma_async_param);
 395/**
 396 * struct dma_async_tx_descriptor - async transaction descriptor
 397 * ---dma generic offload fields---
 398 * @cookie: tracking cookie for this transaction, set to -EBUSY if
 399 *      this tx is sitting on a dependency list
 400 * @flags: flags to augment operation preparation, control completion, and
 401 *      communicate status
 402 * @phys: physical address of the descriptor
 403 * @chan: target channel for this operation
 404 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
 405 * @callback: routine to call after this operation is complete
 406 * @callback_param: general parameter to pass to the callback routine
 407 * ---async_tx api specific fields---
 408 * @next: at completion submit this descriptor
 409 * @parent: pointer to the next level up in the dependency chain
 410 * @lock: protect the parent and next pointers
 411 */
 412struct dma_async_tx_descriptor {
 413        dma_cookie_t cookie;
 414        enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
 415        dma_addr_t phys;
 416        struct dma_chan *chan;
 417        dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
 418        dma_async_tx_callback callback;
 419        void *callback_param;
 420#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
 421        struct dma_async_tx_descriptor *next;
 422        struct dma_async_tx_descriptor *parent;
 423        spinlock_t lock;
 424#endif
 425};
 426
 427#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
 428static inline void txd_lock(struct dma_async_tx_descriptor *txd)
 429{
 430}
 431static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
 432{
 433}
 434static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
 435{
 436        BUG();
 437}
 438static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
 439{
 440}
 441static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
 442{
 443}
 444static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
 445{
 446        return NULL;
 447}
 448static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
 449{
 450        return NULL;
 451}
 452
 453#else
 454static inline void txd_lock(struct dma_async_tx_descriptor *txd)
 455{
 456        spin_lock_bh(&txd->lock);
 457}
 458static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
 459{
 460        spin_unlock_bh(&txd->lock);
 461}
 462static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
 463{
 464        txd->next = next;
 465        next->parent = txd;
 466}
 467static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
 468{
 469        txd->parent = NULL;
 470}
 471static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
 472{
 473        txd->next = NULL;
 474}
 475static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
 476{
 477        return txd->parent;
 478}
 479static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
 480{
 481        return txd->next;
 482}
 483#endif
 484
 485/**
 486 * struct dma_tx_state - filled in to report the status of
 487 * a transfer.
 488 * @last: last completed DMA cookie
 489 * @used: last issued DMA cookie (i.e. the one in progress)
 490 * @residue: the remaining number of bytes left to transmit
 491 *      on the selected transfer for states DMA_IN_PROGRESS and
 492 *      DMA_PAUSED if this is implemented in the driver, else 0
 493 */
 494struct dma_tx_state {
 495        dma_cookie_t last;
 496        dma_cookie_t used;
 497        u32 residue;
 498};
 499
 500/**
 501 * struct dma_device - info on the entity supplying DMA services
 502 * @chancnt: how many DMA channels are supported
 503 * @privatecnt: how many DMA channels are requested by dma_request_channel
 504 * @channels: the list of struct dma_chan
 505 * @global_node: list_head for global dma_device_list
 506 * @cap_mask: one or more dma_capability flags
 507 * @max_xor: maximum number of xor sources, 0 if no capability
 508 * @max_pq: maximum number of PQ sources and PQ-continue capability
 509 * @copy_align: alignment shift for memcpy operations
 510 * @xor_align: alignment shift for xor operations
 511 * @pq_align: alignment shift for pq operations
 512 * @fill_align: alignment shift for memset operations
 513 * @dev_id: unique device ID
 514 * @dev: struct device reference for dma mapping api
 515 * @device_alloc_chan_resources: allocate resources and return the
 516 *      number of allocated descriptors
 517 * @device_free_chan_resources: release DMA channel's resources
 518 * @device_prep_dma_memcpy: prepares a memcpy operation
 519 * @device_prep_dma_xor: prepares a xor operation
 520 * @device_prep_dma_xor_val: prepares a xor validation operation
 521 * @device_prep_dma_pq: prepares a pq operation
 522 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
 523 * @device_prep_dma_memset: prepares a memset operation
 524 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
 525 * @device_prep_slave_sg: prepares a slave dma operation
 526 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
 527 *      The function takes a buffer of size buf_len. The callback function will
 528 *      be called after period_len bytes have been transferred.
 529 * @device_prep_interleaved_dma: Transfer expression in a generic way.
 530 * @device_control: manipulate all pending operations on a channel, returns
 531 *      zero or error code
 532 * @device_tx_status: poll for transaction completion, the optional
 533 *      txstate parameter can be supplied with a pointer to get a
 534 *      struct with auxiliary transfer status information, otherwise the call
 535 *      will just return a simple status code
 536 * @device_issue_pending: push pending transactions to hardware
 537 */
 538struct dma_device {
 539
 540        unsigned int chancnt;
 541        unsigned int privatecnt;
 542        struct list_head channels;
 543        struct list_head global_node;
 544        dma_cap_mask_t  cap_mask;
 545        unsigned short max_xor;
 546        unsigned short max_pq;
 547        u8 copy_align;
 548        u8 xor_align;
 549        u8 pq_align;
 550        u8 fill_align;
 551        #define DMA_HAS_PQ_CONTINUE (1 << 15)
 552
 553        int dev_id;
 554        struct device *dev;
 555
 556        int (*device_alloc_chan_resources)(struct dma_chan *chan);
 557        void (*device_free_chan_resources)(struct dma_chan *chan);
 558
 559        struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
 560                struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 561                size_t len, unsigned long flags);
 562        struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
 563                struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
 564                unsigned int src_cnt, size_t len, unsigned long flags);
 565        struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
 566                struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
 567                size_t len, enum sum_check_flags *result, unsigned long flags);
 568        struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
 569                struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
 570                unsigned int src_cnt, const unsigned char *scf,
 571                size_t len, unsigned long flags);
 572        struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
 573                struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
 574                unsigned int src_cnt, const unsigned char *scf, size_t len,
 575                enum sum_check_flags *pqres, unsigned long flags);
 576        struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
 577                struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
 578                unsigned long flags);
 579        struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
 580                struct dma_chan *chan, unsigned long flags);
 581        struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
 582                struct dma_chan *chan,
 583                struct scatterlist *dst_sg, unsigned int dst_nents,
 584                struct scatterlist *src_sg, unsigned int src_nents,
 585                unsigned long flags);
 586
 587        struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
 588                struct dma_chan *chan, struct scatterlist *sgl,
 589                unsigned int sg_len, enum dma_transfer_direction direction,
 590                unsigned long flags, void *context);
 591        struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
 592                struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 593                size_t period_len, enum dma_transfer_direction direction,
 594                void *context);
 595        struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
 596                struct dma_chan *chan, struct dma_interleaved_template *xt,
 597                unsigned long flags);
 598        int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 599                unsigned long arg);
 600
 601        enum dma_status (*device_tx_status)(struct dma_chan *chan,
 602                                            dma_cookie_t cookie,
 603                                            struct dma_tx_state *txstate);
 604        void (*device_issue_pending)(struct dma_chan *chan);
 605};
 606
 607static inline int dmaengine_device_control(struct dma_chan *chan,
 608                                           enum dma_ctrl_cmd cmd,
 609                                           unsigned long arg)
 610{
 611        return chan->device->device_control(chan, cmd, arg);
 612}
 613
 614static inline int dmaengine_slave_config(struct dma_chan *chan,
 615                                          struct dma_slave_config *config)
 616{
 617        return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
 618                        (unsigned long)config);
 619}
 620
 621static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
 622        struct dma_chan *chan, dma_addr_t buf, size_t len,
 623        enum dma_transfer_direction dir, unsigned long flags)
 624{
 625        struct scatterlist sg;
 626        sg_init_table(&sg, 1);
 627        sg_dma_address(&sg) = buf;
 628        sg_dma_len(&sg) = len;
 629
 630        return chan->device->device_prep_slave_sg(chan, &sg, 1,
 631                                                  dir, flags, NULL);
 632}
 633
 634static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
 635        struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
 636        enum dma_transfer_direction dir, unsigned long flags)
 637{
 638        return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
 639                                                  dir, flags, NULL);
 640}
 641
 642#ifdef CONFIG_RAPIDIO_DMA_ENGINE
 643struct rio_dma_ext;
 644static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
 645        struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
 646        enum dma_transfer_direction dir, unsigned long flags,
 647        struct rio_dma_ext *rio_ext)
 648{
 649        return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
 650                                                  dir, flags, rio_ext);
 651}
 652#endif
 653
 654static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
 655                struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 656                size_t period_len, enum dma_transfer_direction dir)
 657{
 658        return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
 659                                                period_len, dir, NULL);
 660}
 661
 662static inline int dmaengine_terminate_all(struct dma_chan *chan)
 663{
 664        return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
 665}
 666
 667static inline int dmaengine_pause(struct dma_chan *chan)
 668{
 669        return dmaengine_device_control(chan, DMA_PAUSE, 0);
 670}
 671
 672static inline int dmaengine_resume(struct dma_chan *chan)
 673{
 674        return dmaengine_device_control(chan, DMA_RESUME, 0);
 675}
 676
 677static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
 678        dma_cookie_t cookie, struct dma_tx_state *state)
 679{
 680        return chan->device->device_tx_status(chan, cookie, state);
 681}
 682
 683static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
 684{
 685        return desc->tx_submit(desc);
 686}
 687
 688static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
 689{
 690        size_t mask;
 691
 692        if (!align)
 693                return true;
 694        mask = (1 << align) - 1;
 695        if (mask & (off1 | off2 | len))
 696                return false;
 697        return true;
 698}
 699
 700static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
 701                                       size_t off2, size_t len)
 702{
 703        return dmaengine_check_align(dev->copy_align, off1, off2, len);
 704}
 705
 706static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
 707                                      size_t off2, size_t len)
 708{
 709        return dmaengine_check_align(dev->xor_align, off1, off2, len);
 710}
 711
 712static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
 713                                     size_t off2, size_t len)
 714{
 715        return dmaengine_check_align(dev->pq_align, off1, off2, len);
 716}
 717
 718static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
 719                                       size_t off2, size_t len)
 720{
 721        return dmaengine_check_align(dev->fill_align, off1, off2, len);
 722}
 723
 724static inline void
 725dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
 726{
 727        dma->max_pq = maxpq;
 728        if (has_pq_continue)
 729                dma->max_pq |= DMA_HAS_PQ_CONTINUE;
 730}
 731
 732static inline bool dmaf_continue(enum dma_ctrl_flags flags)
 733{
 734        return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
 735}
 736
 737static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
 738{
 739        enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
 740
 741        return (flags & mask) == mask;
 742}
 743
 744static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
 745{
 746        return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
 747}
 748
 749static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
 750{
 751        return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
 752}
 753
 754/* dma_maxpq - reduce maxpq in the face of continued operations
 755 * @dma - dma device with PQ capability
 756 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
 757 *
 758 * When an engine does not support native continuation we need 3 extra
 759 * source slots to reuse P and Q with the following coefficients:
 760 * 1/ {00} * P : remove P from Q', but use it as a source for P'
 761 * 2/ {01} * Q : use Q to continue Q' calculation
 762 * 3/ {00} * Q : subtract Q from P' to cancel (2)
 763 *
 764 * In the case where P is disabled we only need 1 extra source:
 765 * 1/ {01} * Q : use Q to continue Q' calculation
 766 */
 767static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
 768{
 769        if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
 770                return dma_dev_to_maxpq(dma);
 771        else if (dmaf_p_disabled_continue(flags))
 772                return dma_dev_to_maxpq(dma) - 1;
 773        else if (dmaf_continue(flags))
 774                return dma_dev_to_maxpq(dma) - 3;
 775        BUG();
 776}
 777
 778/* --- public DMA engine API --- */
 779
 780#ifdef CONFIG_DMA_ENGINE
 781void dmaengine_get(void);
 782void dmaengine_put(void);
 783#else
 784static inline void dmaengine_get(void)
 785{
 786}
 787static inline void dmaengine_put(void)
 788{
 789}
 790#endif
 791
 792#ifdef CONFIG_NET_DMA
 793#define net_dmaengine_get()     dmaengine_get()
 794#define net_dmaengine_put()     dmaengine_put()
 795#else
 796static inline void net_dmaengine_get(void)
 797{
 798}
 799static inline void net_dmaengine_put(void)
 800{
 801}
 802#endif
 803
 804#ifdef CONFIG_ASYNC_TX_DMA
 805#define async_dmaengine_get()   dmaengine_get()
 806#define async_dmaengine_put()   dmaengine_put()
 807#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
 808#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
 809#else
 810#define async_dma_find_channel(type) dma_find_channel(type)
 811#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
 812#else
 813static inline void async_dmaengine_get(void)
 814{
 815}
 816static inline void async_dmaengine_put(void)
 817{
 818}
 819static inline struct dma_chan *
 820async_dma_find_channel(enum dma_transaction_type type)
 821{
 822        return NULL;
 823}
 824#endif /* CONFIG_ASYNC_TX_DMA */
 825
 826dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
 827        void *dest, void *src, size_t len);
 828dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
 829        struct page *page, unsigned int offset, void *kdata, size_t len);
 830dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
 831        struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
 832        unsigned int src_off, size_t len);
 833void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
 834        struct dma_chan *chan);
 835
 836static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
 837{
 838        tx->flags |= DMA_CTRL_ACK;
 839}
 840
 841static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
 842{
 843        tx->flags &= ~DMA_CTRL_ACK;
 844}
 845
 846static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
 847{
 848        return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
 849}
 850
 851#define first_dma_cap(mask) __first_dma_cap(&(mask))
 852static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
 853{
 854        return min_t(int, DMA_TX_TYPE_END,
 855                find_first_bit(srcp->bits, DMA_TX_TYPE_END));
 856}
 857
 858#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
 859static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
 860{
 861        return min_t(int, DMA_TX_TYPE_END,
 862                find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
 863}
 864
 865#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
 866static inline void
 867__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
 868{
 869        set_bit(tx_type, dstp->bits);
 870}
 871
 872#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
 873static inline void
 874__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
 875{
 876        clear_bit(tx_type, dstp->bits);
 877}
 878
 879#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
 880static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
 881{
 882        bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
 883}
 884
 885#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
 886static inline int
 887__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
 888{
 889        return test_bit(tx_type, srcp->bits);
 890}
 891
 892#define for_each_dma_cap_mask(cap, mask) \
 893        for ((cap) = first_dma_cap(mask);       \
 894                (cap) < DMA_TX_TYPE_END;        \
 895                (cap) = next_dma_cap((cap), (mask)))
 896
 897/**
 898 * dma_async_issue_pending - flush pending transactions to HW
 899 * @chan: target DMA channel
 900 *
 901 * This allows drivers to push copies to HW in batches,
 902 * reducing MMIO writes where possible.
 903 */
 904static inline void dma_async_issue_pending(struct dma_chan *chan)
 905{
 906        chan->device->device_issue_pending(chan);
 907}
 908
 909#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
 910
 911/**
 912 * dma_async_is_tx_complete - poll for transaction completion
 913 * @chan: DMA channel
 914 * @cookie: transaction identifier to check status of
 915 * @last: returns last completed cookie, can be NULL
 916 * @used: returns last issued cookie, can be NULL
 917 *
 918 * If @last and @used are passed in, upon return they reflect the driver
 919 * internal state and can be used with dma_async_is_complete() to check
 920 * the status of multiple cookies without re-checking hardware state.
 921 */
 922static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
 923        dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
 924{
 925        struct dma_tx_state state;
 926        enum dma_status status;
 927
 928        status = chan->device->device_tx_status(chan, cookie, &state);
 929        if (last)
 930                *last = state.last;
 931        if (used)
 932                *used = state.used;
 933        return status;
 934}
 935
 936#define dma_async_memcpy_complete(chan, cookie, last, used)\
 937        dma_async_is_tx_complete(chan, cookie, last, used)
 938
 939/**
 940 * dma_async_is_complete - test a cookie against chan state
 941 * @cookie: transaction identifier to test status of
 942 * @last_complete: last know completed transaction
 943 * @last_used: last cookie value handed out
 944 *
 945 * dma_async_is_complete() is used in dma_async_memcpy_complete()
 946 * the test logic is separated for lightweight testing of multiple cookies
 947 */
 948static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
 949                        dma_cookie_t last_complete, dma_cookie_t last_used)
 950{
 951        if (last_complete <= last_used) {
 952                if ((cookie <= last_complete) || (cookie > last_used))
 953                        return DMA_SUCCESS;
 954        } else {
 955                if ((cookie <= last_complete) && (cookie > last_used))
 956                        return DMA_SUCCESS;
 957        }
 958        return DMA_IN_PROGRESS;
 959}
 960
 961static inline void
 962dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
 963{
 964        if (st) {
 965                st->last = last;
 966                st->used = used;
 967                st->residue = residue;
 968        }
 969}
 970
 971enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
 972#ifdef CONFIG_DMA_ENGINE
 973enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
 974void dma_issue_pending_all(void);
 975struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
 976void dma_release_channel(struct dma_chan *chan);
 977#else
 978static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
 979{
 980        return DMA_SUCCESS;
 981}
 982static inline void dma_issue_pending_all(void)
 983{
 984}
 985static inline struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask,
 986                                              dma_filter_fn fn, void *fn_param)
 987{
 988        return NULL;
 989}
 990static inline void dma_release_channel(struct dma_chan *chan)
 991{
 992}
 993#endif
 994
 995/* --- DMA device --- */
 996
 997int dma_async_device_register(struct dma_device *device);
 998void dma_async_device_unregister(struct dma_device *device);
 999void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1000struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1001struct dma_chan *net_dma_find_channel(void);
1002#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1003
1004/* --- Helper iov-locking functions --- */
1005
1006struct dma_page_list {
1007        char __user *base_address;
1008        int nr_pages;
1009        struct page **pages;
1010};
1011
1012struct dma_pinned_list {
1013        int nr_iovecs;
1014        struct dma_page_list page_list[0];
1015};
1016
1017struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
1018void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
1019
1020dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
1021        struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
1022dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
1023        struct dma_pinned_list *pinned_list, struct page *page,
1024        unsigned int offset, size_t len);
1025
1026#endif /* DMAENGINE_H */
1027
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