linux/drivers/scsi/gdth.h
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   1#ifndef _GDTH_H
   2#define _GDTH_H
   3
   4/*
   5 * Header file for the GDT Disk Array/Storage RAID controllers driver for Linux
   6 * 
   7 * gdth.h Copyright (C) 1995-06 ICP vortex, Achim Leubner
   8 * See gdth.c for further informations and 
   9 * below for supported controller types
  10 *
  11 * <achim_leubner@adaptec.com>
  12 *
  13 * $Id: gdth.h,v 1.58 2006/01/11 16:14:09 achim Exp $
  14 */
  15
  16#include <linux/types.h>
  17
  18#ifndef TRUE
  19#define TRUE 1
  20#endif
  21#ifndef FALSE
  22#define FALSE 0
  23#endif
  24
  25/* defines, macros */
  26
  27/* driver version */
  28#define GDTH_VERSION_STR        "3.05"
  29#define GDTH_VERSION            3
  30#define GDTH_SUBVERSION         5
  31
  32/* protocol version */
  33#define PROTOCOL_VERSION        1
  34
  35/* OEM IDs */
  36#define OEM_ID_ICP      0x941c
  37#define OEM_ID_INTEL    0x8000
  38
  39/* controller classes */
  40#define GDT_ISA         0x01                    /* ISA controller */
  41#define GDT_EISA        0x02                    /* EISA controller */
  42#define GDT_PCI         0x03                    /* PCI controller */
  43#define GDT_PCINEW      0x04                    /* new PCI controller */
  44#define GDT_PCIMPR      0x05                    /* PCI MPR controller */
  45/* GDT_EISA, controller subtypes EISA */
  46#define GDT3_ID         0x0130941c              /* GDT3000/3020 */
  47#define GDT3A_ID        0x0230941c              /* GDT3000A/3020A/3050A */
  48#define GDT3B_ID        0x0330941c              /* GDT3000B/3010A */
  49/* GDT_ISA */
  50#define GDT2_ID         0x0120941c              /* GDT2000/2020 */
  51
  52/* vendor ID, device IDs (PCI) */
  53/* these defines should already exist in <linux/pci.h> */
  54#ifndef PCI_VENDOR_ID_VORTEX
  55#define PCI_VENDOR_ID_VORTEX            0x1119  /* PCI controller vendor ID */
  56#endif
  57#ifndef PCI_VENDOR_ID_INTEL
  58#define PCI_VENDOR_ID_INTEL             0x8086  
  59#endif
  60
  61#ifndef PCI_DEVICE_ID_VORTEX_GDT60x0
  62/* GDT_PCI */
  63#define PCI_DEVICE_ID_VORTEX_GDT60x0    0       /* GDT6000/6020/6050 */
  64#define PCI_DEVICE_ID_VORTEX_GDT6000B   1       /* GDT6000B/6010 */
  65/* GDT_PCINEW */
  66#define PCI_DEVICE_ID_VORTEX_GDT6x10    2       /* GDT6110/6510 */
  67#define PCI_DEVICE_ID_VORTEX_GDT6x20    3       /* GDT6120/6520 */
  68#define PCI_DEVICE_ID_VORTEX_GDT6530    4       /* GDT6530 */
  69#define PCI_DEVICE_ID_VORTEX_GDT6550    5       /* GDT6550 */
  70/* GDT_PCINEW, wide/ultra SCSI controllers */
  71#define PCI_DEVICE_ID_VORTEX_GDT6x17    6       /* GDT6117/6517 */
  72#define PCI_DEVICE_ID_VORTEX_GDT6x27    7       /* GDT6127/6527 */
  73#define PCI_DEVICE_ID_VORTEX_GDT6537    8       /* GDT6537 */
  74#define PCI_DEVICE_ID_VORTEX_GDT6557    9       /* GDT6557/6557-ECC */
  75/* GDT_PCINEW, wide SCSI controllers */
  76#define PCI_DEVICE_ID_VORTEX_GDT6x15    10      /* GDT6115/6515 */
  77#define PCI_DEVICE_ID_VORTEX_GDT6x25    11      /* GDT6125/6525 */
  78#define PCI_DEVICE_ID_VORTEX_GDT6535    12      /* GDT6535 */
  79#define PCI_DEVICE_ID_VORTEX_GDT6555    13      /* GDT6555/6555-ECC */
  80#endif
  81
  82#ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RP
  83/* GDT_MPR, RP series, wide/ultra SCSI */
  84#define PCI_DEVICE_ID_VORTEX_GDT6x17RP  0x100   /* GDT6117RP/GDT6517RP */
  85#define PCI_DEVICE_ID_VORTEX_GDT6x27RP  0x101   /* GDT6127RP/GDT6527RP */
  86#define PCI_DEVICE_ID_VORTEX_GDT6537RP  0x102   /* GDT6537RP */
  87#define PCI_DEVICE_ID_VORTEX_GDT6557RP  0x103   /* GDT6557RP */
  88/* GDT_MPR, RP series, narrow/ultra SCSI */
  89#define PCI_DEVICE_ID_VORTEX_GDT6x11RP  0x104   /* GDT6111RP/GDT6511RP */
  90#define PCI_DEVICE_ID_VORTEX_GDT6x21RP  0x105   /* GDT6121RP/GDT6521RP */
  91#endif
  92#ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RD
  93/* GDT_MPR, RD series, wide/ultra SCSI */
  94#define PCI_DEVICE_ID_VORTEX_GDT6x17RD  0x110   /* GDT6117RD/GDT6517RD */
  95#define PCI_DEVICE_ID_VORTEX_GDT6x27RD  0x111   /* GDT6127RD/GDT6527RD */
  96#define PCI_DEVICE_ID_VORTEX_GDT6537RD  0x112   /* GDT6537RD */
  97#define PCI_DEVICE_ID_VORTEX_GDT6557RD  0x113   /* GDT6557RD */
  98/* GDT_MPR, RD series, narrow/ultra SCSI */
  99#define PCI_DEVICE_ID_VORTEX_GDT6x11RD  0x114   /* GDT6111RD/GDT6511RD */
 100#define PCI_DEVICE_ID_VORTEX_GDT6x21RD  0x115   /* GDT6121RD/GDT6521RD */
 101/* GDT_MPR, RD series, wide/ultra2 SCSI */
 102#define PCI_DEVICE_ID_VORTEX_GDT6x18RD  0x118   /* GDT6118RD/GDT6518RD/
 103                                                   GDT6618RD */
 104#define PCI_DEVICE_ID_VORTEX_GDT6x28RD  0x119   /* GDT6128RD/GDT6528RD/
 105                                                   GDT6628RD */
 106#define PCI_DEVICE_ID_VORTEX_GDT6x38RD  0x11A   /* GDT6538RD/GDT6638RD */
 107#define PCI_DEVICE_ID_VORTEX_GDT6x58RD  0x11B   /* GDT6558RD/GDT6658RD */
 108/* GDT_MPR, RN series (64-bit PCI), wide/ultra2 SCSI */
 109#define PCI_DEVICE_ID_VORTEX_GDT7x18RN  0x168   /* GDT7118RN/GDT7518RN/
 110                                                   GDT7618RN */
 111#define PCI_DEVICE_ID_VORTEX_GDT7x28RN  0x169   /* GDT7128RN/GDT7528RN/
 112                                                   GDT7628RN */
 113#define PCI_DEVICE_ID_VORTEX_GDT7x38RN  0x16A   /* GDT7538RN/GDT7638RN */
 114#define PCI_DEVICE_ID_VORTEX_GDT7x58RN  0x16B   /* GDT7558RN/GDT7658RN */
 115#endif
 116
 117#ifndef PCI_DEVICE_ID_VORTEX_GDT6x19RD
 118/* GDT_MPR, RD series, Fibre Channel */
 119#define PCI_DEVICE_ID_VORTEX_GDT6x19RD  0x210   /* GDT6519RD/GDT6619RD */
 120#define PCI_DEVICE_ID_VORTEX_GDT6x29RD  0x211   /* GDT6529RD/GDT6629RD */
 121/* GDT_MPR, RN series (64-bit PCI), Fibre Channel */
 122#define PCI_DEVICE_ID_VORTEX_GDT7x19RN  0x260   /* GDT7519RN/GDT7619RN */
 123#define PCI_DEVICE_ID_VORTEX_GDT7x29RN  0x261   /* GDT7529RN/GDT7629RN */
 124#endif
 125
 126#ifndef PCI_DEVICE_ID_VORTEX_GDTMAXRP
 127/* GDT_MPR, last device ID */
 128#define PCI_DEVICE_ID_VORTEX_GDTMAXRP   0x2ff   
 129#endif
 130
 131#ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX
 132/* new GDT Rx Controller */
 133#define PCI_DEVICE_ID_VORTEX_GDTNEWRX   0x300
 134#endif
 135
 136#ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX2
 137/* new(2) GDT Rx Controller */
 138#define PCI_DEVICE_ID_VORTEX_GDTNEWRX2  0x301
 139#endif        
 140
 141#ifndef PCI_DEVICE_ID_INTEL_SRC
 142/* Intel Storage RAID Controller */
 143#define PCI_DEVICE_ID_INTEL_SRC         0x600
 144#endif
 145
 146#ifndef PCI_DEVICE_ID_INTEL_SRC_XSCALE
 147/* Intel Storage RAID Controller */
 148#define PCI_DEVICE_ID_INTEL_SRC_XSCALE  0x601
 149#endif
 150
 151/* limits */
 152#define GDTH_SCRATCH    PAGE_SIZE               /* 4KB scratch buffer */
 153#define GDTH_MAXCMDS    120
 154#define GDTH_MAXC_P_L   16                      /* max. cmds per lun */
 155#define GDTH_MAX_RAW    2                       /* max. cmds per raw device */
 156#define MAXOFFSETS      128
 157#define MAXHA           16
 158#define MAXID           127
 159#define MAXLUN          8
 160#define MAXBUS          6
 161#define MAX_EVENTS      100                     /* event buffer count */
 162#define MAX_RES_ARGS    40                      /* device reservation, 
 163                                                   must be a multiple of 4 */
 164#define MAXCYLS         1024
 165#define HEADS           64
 166#define SECS            32                      /* mapping 64*32 */
 167#define MEDHEADS        127
 168#define MEDSECS         63                      /* mapping 127*63 */
 169#define BIGHEADS        255
 170#define BIGSECS         63                      /* mapping 255*63 */
 171
 172/* special command ptr. */
 173#define UNUSED_CMND     ((Scsi_Cmnd *)-1)
 174#define INTERNAL_CMND   ((Scsi_Cmnd *)-2)
 175#define SCREEN_CMND     ((Scsi_Cmnd *)-3)
 176#define SPECIAL_SCP(p)  (p==UNUSED_CMND || p==INTERNAL_CMND || p==SCREEN_CMND)
 177
 178/* controller services */
 179#define SCSIRAWSERVICE  3
 180#define CACHESERVICE    9
 181#define SCREENSERVICE   11
 182
 183/* screenservice defines */
 184#define MSG_INV_HANDLE  -1                      /* special message handle */
 185#define MSGLEN          16                      /* size of message text */
 186#define MSG_SIZE        34                      /* size of message structure */
 187#define MSG_REQUEST     0                       /* async. event: message */
 188
 189/* cacheservice defines */
 190#define SECTOR_SIZE     0x200                   /* always 512 bytes per sec. */
 191
 192/* DPMEM constants */
 193#define DPMEM_MAGIC     0xC0FFEE11
 194#define IC_HEADER_BYTES 48
 195#define IC_QUEUE_BYTES  4
 196#define DPMEM_COMMAND_OFFSET    IC_HEADER_BYTES+IC_QUEUE_BYTES*MAXOFFSETS
 197
 198/* cluster_type constants */
 199#define CLUSTER_DRIVE         1
 200#define CLUSTER_MOUNTED       2
 201#define CLUSTER_RESERVED      4
 202#define CLUSTER_RESERVE_STATE (CLUSTER_DRIVE|CLUSTER_MOUNTED|CLUSTER_RESERVED)
 203
 204/* commands for all services, cache service */
 205#define GDT_INIT        0                       /* service initialization */
 206#define GDT_READ        1                       /* read command */
 207#define GDT_WRITE       2                       /* write command */
 208#define GDT_INFO        3                       /* information about devices */
 209#define GDT_FLUSH       4                       /* flush dirty cache buffers */
 210#define GDT_IOCTL       5                       /* ioctl command */
 211#define GDT_DEVTYPE     9                       /* additional information */
 212#define GDT_MOUNT       10                      /* mount cache device */
 213#define GDT_UNMOUNT     11                      /* unmount cache device */
 214#define GDT_SET_FEAT    12                      /* set feat. (scatter/gather) */
 215#define GDT_GET_FEAT    13                      /* get features */
 216#define GDT_WRITE_THR   16                      /* write through */
 217#define GDT_READ_THR    17                      /* read through */
 218#define GDT_EXT_INFO    18                      /* extended info */
 219#define GDT_RESET       19                      /* controller reset */
 220#define GDT_RESERVE_DRV 20                      /* reserve host drive */
 221#define GDT_RELEASE_DRV 21                      /* release host drive */
 222#define GDT_CLUST_INFO  22                      /* cluster info */
 223#define GDT_RW_ATTRIBS  23                      /* R/W attribs (write thru,..)*/
 224#define GDT_CLUST_RESET 24                      /* releases the cluster drives*/
 225#define GDT_FREEZE_IO   25                      /* freezes all IOs */
 226#define GDT_UNFREEZE_IO 26                      /* unfreezes all IOs */
 227#define GDT_X_INIT_HOST 29                      /* ext. init: 64 bit support */
 228#define GDT_X_INFO      30                      /* ext. info for drives>2TB */
 229
 230/* raw service commands */
 231#define GDT_RESERVE     14                      /* reserve dev. to raw serv. */
 232#define GDT_RELEASE     15                      /* release device */
 233#define GDT_RESERVE_ALL 16                      /* reserve all devices */
 234#define GDT_RELEASE_ALL 17                      /* release all devices */
 235#define GDT_RESET_BUS   18                      /* reset bus */
 236#define GDT_SCAN_START  19                      /* start device scan */
 237#define GDT_SCAN_END    20                      /* stop device scan */  
 238#define GDT_X_INIT_RAW  21                      /* ext. init: 64 bit support */
 239
 240/* screen service commands */
 241#define GDT_REALTIME    3                       /* realtime clock to screens. */
 242#define GDT_X_INIT_SCR  4                       /* ext. init: 64 bit support */
 243
 244/* IOCTL command defines */
 245#define SCSI_DR_INFO    0x00                    /* SCSI drive info */                   
 246#define SCSI_CHAN_CNT   0x05                    /* SCSI channel count */   
 247#define SCSI_DR_LIST    0x06                    /* SCSI drive list */
 248#define SCSI_DEF_CNT    0x15                    /* grown/primary defects */
 249#define DSK_STATISTICS  0x4b                    /* SCSI disk statistics */
 250#define IOCHAN_DESC     0x5d                    /* description of IO channel */
 251#define IOCHAN_RAW_DESC 0x5e                    /* description of raw IO chn. */
 252#define L_CTRL_PATTERN  0x20000000L             /* SCSI IOCTL mask */
 253#define ARRAY_INFO      0x12                    /* array drive info */
 254#define ARRAY_DRV_LIST  0x0f                    /* array drive list */
 255#define ARRAY_DRV_LIST2 0x34                    /* array drive list (new) */
 256#define LA_CTRL_PATTERN 0x10000000L             /* array IOCTL mask */
 257#define CACHE_DRV_CNT   0x01                    /* cache drive count */
 258#define CACHE_DRV_LIST  0x02                    /* cache drive list */
 259#define CACHE_INFO      0x04                    /* cache info */
 260#define CACHE_CONFIG    0x05                    /* cache configuration */
 261#define CACHE_DRV_INFO  0x07                    /* cache drive info */
 262#define BOARD_FEATURES  0x15                    /* controller features */
 263#define BOARD_INFO      0x28                    /* controller info */
 264#define SET_PERF_MODES  0x82                    /* set mode (coalescing,..) */
 265#define GET_PERF_MODES  0x83                    /* get mode */
 266#define CACHE_READ_OEM_STRING_RECORD 0x84       /* read OEM string record */ 
 267#define HOST_GET        0x10001L                /* get host drive list */
 268#define IO_CHANNEL      0x00020000L             /* default IO channel */
 269#define INVALID_CHANNEL 0x0000ffffL             /* invalid channel */
 270
 271/* service errors */
 272#define S_OK            1                       /* no error */
 273#define S_GENERR        6                       /* general error */
 274#define S_BSY           7                       /* controller busy */
 275#define S_CACHE_UNKNOWN 12                      /* cache serv.: drive unknown */
 276#define S_RAW_SCSI      12                      /* raw serv.: target error */
 277#define S_RAW_ILL       0xff                    /* raw serv.: illegal */
 278#define S_NOFUNC        -2                      /* unknown function */
 279#define S_CACHE_RESERV  -24                     /* cache: reserv. conflict */   
 280
 281/* timeout values */
 282#define INIT_RETRIES    100000                  /* 100000 * 1ms = 100s */
 283#define INIT_TIMEOUT    100000                  /* 100000 * 1ms = 100s */
 284#define POLL_TIMEOUT    10000                   /* 10000 * 1ms = 10s */
 285
 286/* priorities */
 287#define DEFAULT_PRI     0x20
 288#define IOCTL_PRI       0x10
 289#define HIGH_PRI        0x08
 290
 291/* data directions */
 292#define GDTH_DATA_IN    0x01000000L             /* data from target */
 293#define GDTH_DATA_OUT   0x00000000L             /* data to target */
 294
 295/* BMIC registers (EISA controllers) */
 296#define ID0REG          0x0c80                  /* board ID */
 297#define EINTENABREG     0x0c89                  /* interrupt enable */
 298#define SEMA0REG        0x0c8a                  /* command semaphore */
 299#define SEMA1REG        0x0c8b                  /* status semaphore */
 300#define LDOORREG        0x0c8d                  /* local doorbell */
 301#define EDENABREG       0x0c8e                  /* EISA system doorbell enab. */
 302#define EDOORREG        0x0c8f                  /* EISA system doorbell */
 303#define MAILBOXREG      0x0c90                  /* mailbox reg. (16 bytes) */
 304#define EISAREG         0x0cc0                  /* EISA configuration */
 305
 306/* other defines */
 307#define LINUX_OS        8                       /* used for cache optim. */
 308#define SECS32          0x1f                    /* round capacity */
 309#define BIOS_ID_OFFS    0x10                    /* offset contr-ID in ISABIOS */
 310#define LOCALBOARD      0                       /* board node always 0 */
 311#define ASYNCINDEX      0                       /* cmd index async. event */
 312#define SPEZINDEX       1                       /* cmd index unknown service */
 313#define COALINDEX       (GDTH_MAXCMDS + 2)
 314
 315/* features */
 316#define SCATTER_GATHER  1                       /* s/g feature */
 317#define GDT_WR_THROUGH  0x100                   /* WRITE_THROUGH supported */
 318#define GDT_64BIT       0x200                   /* 64bit / drv>2TB support */
 319
 320#include "gdth_ioctl.h"
 321
 322/* screenservice message */
 323typedef struct {                               
 324    u32     msg_handle;                     /* message handle */
 325    u32     msg_len;                        /* size of message */
 326    u32     msg_alen;                       /* answer length */
 327    u8      msg_answer;                     /* answer flag */
 328    u8      msg_ext;                        /* more messages */
 329    u8      msg_reserved[2];
 330    char        msg_text[MSGLEN+2];             /* the message text */
 331} __attribute__((packed)) gdth_msg_str;
 332
 333
 334/* IOCTL data structures */
 335
 336/* Status coalescing buffer for returning multiple requests per interrupt */
 337typedef struct {
 338    u32     status;
 339    u32     ext_status;
 340    u32     info0;
 341    u32     info1;
 342} __attribute__((packed)) gdth_coal_status;
 343
 344/* performance mode data structure */
 345typedef struct {
 346    u32     version;            /* The version of this IOCTL structure. */
 347    u32     st_mode;            /* 0=dis., 1=st_buf_addr1 valid, 2=both  */
 348    u32     st_buff_addr1;      /* physical address of status buffer 1 */
 349    u32     st_buff_u_addr1;    /* reserved for 64 bit addressing */
 350    u32     st_buff_indx1;      /* reserved command idx. for this buffer */
 351    u32     st_buff_addr2;      /* physical address of status buffer 1 */
 352    u32     st_buff_u_addr2;    /* reserved for 64 bit addressing */
 353    u32     st_buff_indx2;      /* reserved command idx. for this buffer */
 354    u32     st_buff_size;       /* size of each buffer in bytes */
 355    u32     cmd_mode;           /* 0 = mode disabled, 1 = cmd_buff_addr1 */ 
 356    u32     cmd_buff_addr1;     /* physical address of cmd buffer 1 */   
 357    u32     cmd_buff_u_addr1;   /* reserved for 64 bit addressing */
 358    u32     cmd_buff_indx1;     /* cmd buf addr1 unique identifier */
 359    u32     cmd_buff_addr2;     /* physical address of cmd buffer 1 */   
 360    u32     cmd_buff_u_addr2;   /* reserved for 64 bit addressing */
 361    u32     cmd_buff_indx2;     /* cmd buf addr1 unique identifier */
 362    u32     cmd_buff_size;      /* size of each cmd buffer in bytes */
 363    u32     reserved1;
 364    u32     reserved2;
 365} __attribute__((packed)) gdth_perf_modes;
 366
 367/* SCSI drive info */
 368typedef struct {
 369    u8      vendor[8];                      /* vendor string */
 370    u8      product[16];                    /* product string */
 371    u8      revision[4];                    /* revision */
 372    u32     sy_rate;                        /* current rate for sync. tr. */
 373    u32     sy_max_rate;                    /* max. rate for sync. tr. */
 374    u32     no_ldrive;                      /* belongs to this log. drv.*/
 375    u32     blkcnt;                         /* number of blocks */
 376    u16      blksize;                        /* size of block in bytes */
 377    u8      available;                      /* flag: access is available */
 378    u8      init;                           /* medium is initialized */
 379    u8      devtype;                        /* SCSI devicetype */
 380    u8      rm_medium;                      /* medium is removable */
 381    u8      wp_medium;                      /* medium is write protected */
 382    u8      ansi;                           /* SCSI I/II or III? */
 383    u8      protocol;                       /* same as ansi */
 384    u8      sync;                           /* flag: sync. transfer enab. */
 385    u8      disc;                           /* flag: disconnect enabled */
 386    u8      queueing;                       /* flag: command queing enab. */
 387    u8      cached;                         /* flag: caching enabled */
 388    u8      target_id;                      /* target ID of device */
 389    u8      lun;                            /* LUN id of device */
 390    u8      orphan;                         /* flag: drive fragment */
 391    u32     last_error;                     /* sense key or drive state */
 392    u32     last_result;                    /* result of last command */
 393    u32     check_errors;                   /* err. in last surface check */
 394    u8      percent;                        /* progress for surface check */
 395    u8      last_check;                     /* IOCTRL operation */
 396    u8      res[2];
 397    u32     flags;                          /* from 1.19/2.19: raw reserv.*/
 398    u8      multi_bus;                      /* multi bus dev? (fibre ch.) */
 399    u8      mb_status;                      /* status: available? */
 400    u8      res2[2];
 401    u8      mb_alt_status;                  /* status on second bus */
 402    u8      mb_alt_bid;                     /* number of second bus */
 403    u8      mb_alt_tid;                     /* target id on second bus */
 404    u8      res3;
 405    u8      fc_flag;                        /* from 1.22/2.22: info valid?*/
 406    u8      res4;
 407    u16      fc_frame_size;                  /* frame size (bytes) */
 408    char        wwn[8];                         /* world wide name */
 409} __attribute__((packed)) gdth_diskinfo_str;
 410
 411/* get SCSI channel count  */
 412typedef struct {
 413    u32     channel_no;                     /* number of channel */
 414    u32     drive_cnt;                      /* drive count */
 415    u8      siop_id;                        /* SCSI processor ID */
 416    u8      siop_state;                     /* SCSI processor state */ 
 417} __attribute__((packed)) gdth_getch_str;
 418
 419/* get SCSI drive numbers */
 420typedef struct {
 421    u32     sc_no;                          /* SCSI channel */
 422    u32     sc_cnt;                         /* sc_list[] elements */
 423    u32     sc_list[MAXID];                 /* minor device numbers */
 424} __attribute__((packed)) gdth_drlist_str;
 425
 426/* get grown/primary defect count */
 427typedef struct {
 428    u8      sddc_type;                      /* 0x08: grown, 0x10: prim. */
 429    u8      sddc_format;                    /* list entry format */
 430    u8      sddc_len;                       /* list entry length */
 431    u8      sddc_res;
 432    u32     sddc_cnt;                       /* entry count */
 433} __attribute__((packed)) gdth_defcnt_str;
 434
 435/* disk statistics */
 436typedef struct {
 437    u32     bid;                            /* SCSI channel */
 438    u32     first;                          /* first SCSI disk */
 439    u32     entries;                        /* number of elements */
 440    u32     count;                          /* (R) number of init. el. */
 441    u32     mon_time;                       /* time stamp */
 442    struct {
 443        u8  tid;                            /* target ID */
 444        u8  lun;                            /* LUN */
 445        u8  res[2];
 446        u32 blk_size;                       /* block size in bytes */
 447        u32 rd_count;                       /* bytes read */
 448        u32 wr_count;                       /* bytes written */
 449        u32 rd_blk_count;                   /* blocks read */
 450        u32 wr_blk_count;                   /* blocks written */
 451        u32 retries;                        /* retries */
 452        u32 reassigns;                      /* reassigns */
 453    } __attribute__((packed)) list[1];
 454} __attribute__((packed)) gdth_dskstat_str;
 455
 456/* IO channel header */
 457typedef struct {
 458    u32     version;                        /* version (-1UL: newest) */
 459    u8      list_entries;                   /* list entry count */
 460    u8      first_chan;                     /* first channel number */
 461    u8      last_chan;                      /* last channel number */
 462    u8      chan_count;                     /* (R) channel count */
 463    u32     list_offset;                    /* offset of list[0] */
 464} __attribute__((packed)) gdth_iochan_header;
 465
 466/* get IO channel description */
 467typedef struct {
 468    gdth_iochan_header  hdr;
 469    struct {
 470        u32         address;                /* channel address */
 471        u8          type;                   /* type (SCSI, FCAL) */
 472        u8          local_no;               /* local number */
 473        u16          features;               /* channel features */
 474    } __attribute__((packed)) list[MAXBUS];
 475} __attribute__((packed)) gdth_iochan_str;
 476
 477/* get raw IO channel description */
 478typedef struct {
 479    gdth_iochan_header  hdr;
 480    struct {
 481        u8      proc_id;                    /* processor id */
 482        u8      proc_defect;                /* defect ? */
 483        u8      reserved[2];
 484    } __attribute__((packed)) list[MAXBUS];
 485} __attribute__((packed)) gdth_raw_iochan_str;
 486
 487/* array drive component */
 488typedef struct {
 489    u32     al_controller;                  /* controller ID */
 490    u8      al_cache_drive;                 /* cache drive number */
 491    u8      al_status;                      /* cache drive state */
 492    u8      al_res[2];     
 493} __attribute__((packed)) gdth_arraycomp_str;
 494
 495/* array drive information */
 496typedef struct {
 497    u8      ai_type;                        /* array type (RAID0,4,5) */
 498    u8      ai_cache_drive_cnt;             /* active cachedrives */
 499    u8      ai_state;                       /* array drive state */
 500    u8      ai_master_cd;                   /* master cachedrive */
 501    u32     ai_master_controller;           /* ID of master controller */
 502    u32     ai_size;                        /* user capacity [sectors] */
 503    u32     ai_striping_size;               /* striping size [sectors] */
 504    u32     ai_secsize;                     /* sector size [bytes] */
 505    u32     ai_err_info;                    /* failed cache drive */
 506    u8      ai_name[8];                     /* name of the array drive */
 507    u8      ai_controller_cnt;              /* number of controllers */
 508    u8      ai_removable;                   /* flag: removable */
 509    u8      ai_write_protected;             /* flag: write protected */
 510    u8      ai_devtype;                     /* type: always direct access */
 511    gdth_arraycomp_str  ai_drives[35];          /* drive components: */
 512    u8      ai_drive_entries;               /* number of drive components */
 513    u8      ai_protected;                   /* protection flag */
 514    u8      ai_verify_state;                /* state of a parity verify */
 515    u8      ai_ext_state;                   /* extended array drive state */
 516    u8      ai_expand_state;                /* array expand state (>=2.18)*/
 517    u8      ai_reserved[3];
 518} __attribute__((packed)) gdth_arrayinf_str;
 519
 520/* get array drive list */
 521typedef struct {
 522    u32     controller_no;                  /* controller no. */
 523    u8      cd_handle;                      /* master cachedrive */
 524    u8      is_arrayd;                      /* Flag: is array drive? */
 525    u8      is_master;                      /* Flag: is array master? */
 526    u8      is_parity;                      /* Flag: is parity drive? */
 527    u8      is_hotfix;                      /* Flag: is hotfix drive? */
 528    u8      res[3];
 529} __attribute__((packed)) gdth_alist_str;
 530
 531typedef struct {
 532    u32     entries_avail;                  /* allocated entries */
 533    u32     entries_init;                   /* returned entries */
 534    u32     first_entry;                    /* first entry number */
 535    u32     list_offset;                    /* offset of following list */
 536    gdth_alist_str list[1];                     /* list */
 537} __attribute__((packed)) gdth_arcdl_str;
 538
 539/* cache info/config IOCTL */
 540typedef struct {
 541    u32     version;                        /* firmware version */
 542    u16      state;                          /* cache state (on/off) */
 543    u16      strategy;                       /* cache strategy */
 544    u16      write_back;                     /* write back state (on/off) */
 545    u16      block_size;                     /* cache block size */
 546} __attribute__((packed)) gdth_cpar_str;
 547
 548typedef struct {
 549    u32     csize;                          /* cache size */
 550    u32     read_cnt;                       /* read/write counter */
 551    u32     write_cnt;
 552    u32     tr_hits;                        /* hits */
 553    u32     sec_hits;
 554    u32     sec_miss;                       /* misses */
 555} __attribute__((packed)) gdth_cstat_str;
 556
 557typedef struct {
 558    gdth_cpar_str   cpar;
 559    gdth_cstat_str  cstat;
 560} __attribute__((packed)) gdth_cinfo_str;
 561
 562/* cache drive info */
 563typedef struct {
 564    u8      cd_name[8];                     /* cache drive name */
 565    u32     cd_devtype;                     /* SCSI devicetype */
 566    u32     cd_ldcnt;                       /* number of log. drives */
 567    u32     cd_last_error;                  /* last error */
 568    u8      cd_initialized;                 /* drive is initialized */
 569    u8      cd_removable;                   /* media is removable */
 570    u8      cd_write_protected;             /* write protected */
 571    u8      cd_flags;                       /* Pool Hot Fix? */
 572    u32     ld_blkcnt;                      /* number of blocks */
 573    u32     ld_blksize;                     /* blocksize */
 574    u32     ld_dcnt;                        /* number of disks */
 575    u32     ld_slave;                       /* log. drive index */
 576    u32     ld_dtype;                       /* type of logical drive */
 577    u32     ld_last_error;                  /* last error */
 578    u8      ld_name[8];                     /* log. drive name */
 579    u8      ld_error;                       /* error */
 580} __attribute__((packed)) gdth_cdrinfo_str;
 581
 582/* OEM string */
 583typedef struct {
 584    u32     ctl_version;
 585    u32     file_major_version;
 586    u32     file_minor_version;
 587    u32     buffer_size;
 588    u32     cpy_count;
 589    u32     ext_error;
 590    u32     oem_id;
 591    u32     board_id;
 592} __attribute__((packed)) gdth_oem_str_params;
 593
 594typedef struct {
 595    u8      product_0_1_name[16];
 596    u8      product_4_5_name[16];
 597    u8      product_cluster_name[16];
 598    u8      product_reserved[16];
 599    u8      scsi_cluster_target_vendor_id[16];
 600    u8      cluster_raid_fw_name[16];
 601    u8      oem_brand_name[16];
 602    u8      oem_raid_type[16];
 603    u8      bios_type[13];
 604    u8      bios_title[50];
 605    u8      oem_company_name[37];
 606    u32     pci_id_1;
 607    u32     pci_id_2;
 608    u8      validation_status[80];
 609    u8      reserved_1[4];
 610    u8      scsi_host_drive_inquiry_vendor_id[16];
 611    u8      library_file_template[16];
 612    u8      reserved_2[16];
 613    u8      tool_name_1[32];
 614    u8      tool_name_2[32];
 615    u8      tool_name_3[32];
 616    u8      oem_contact_1[84];
 617    u8      oem_contact_2[84];
 618    u8      oem_contact_3[84];
 619} __attribute__((packed)) gdth_oem_str;
 620
 621typedef struct {
 622    gdth_oem_str_params params;
 623    gdth_oem_str        text;
 624} __attribute__((packed)) gdth_oem_str_ioctl;
 625
 626/* board features */
 627typedef struct {
 628    u8      chaining;                       /* Chaining supported */
 629    u8      striping;                       /* Striping (RAID-0) supp. */
 630    u8      mirroring;                      /* Mirroring (RAID-1) supp. */
 631    u8      raid;                           /* RAID-4/5/10 supported */
 632} __attribute__((packed)) gdth_bfeat_str;
 633
 634/* board info IOCTL */
 635typedef struct {
 636    u32     ser_no;                         /* serial no. */
 637    u8      oem_id[2];                      /* OEM ID */
 638    u16      ep_flags;                       /* eprom flags */
 639    u32     proc_id;                        /* processor ID */
 640    u32     memsize;                        /* memory size (bytes) */
 641    u8      mem_banks;                      /* memory banks */
 642    u8      chan_type;                      /* channel type */
 643    u8      chan_count;                     /* channel count */
 644    u8      rdongle_pres;                   /* dongle present? */
 645    u32     epr_fw_ver;                     /* (eprom) firmware version */
 646    u32     upd_fw_ver;                     /* (update) firmware version */
 647    u32     upd_revision;                   /* update revision */
 648    char        type_string[16];                /* controller name */
 649    char        raid_string[16];                /* RAID firmware name */
 650    u8      update_pres;                    /* update present? */
 651    u8      xor_pres;                       /* XOR engine present? */
 652    u8      prom_type;                      /* ROM type (eprom/flash) */
 653    u8      prom_count;                     /* number of ROM devices */
 654    u32     dup_pres;                       /* duplexing module present? */
 655    u32     chan_pres;                      /* number of expansion chn. */
 656    u32     mem_pres;                       /* memory expansion inst. ? */
 657    u8      ft_bus_system;                  /* fault bus supported? */
 658    u8      subtype_valid;                  /* board_subtype valid? */
 659    u8      board_subtype;                  /* subtype/hardware level */
 660    u8      ramparity_pres;                 /* RAM parity check hardware? */
 661} __attribute__((packed)) gdth_binfo_str; 
 662
 663/* get host drive info */
 664typedef struct {
 665    char        name[8];                        /* host drive name */
 666    u32     size;                           /* size (sectors) */
 667    u8      host_drive;                     /* host drive number */
 668    u8      log_drive;                      /* log. drive (master) */
 669    u8      reserved;
 670    u8      rw_attribs;                     /* r/w attribs */
 671    u32     start_sec;                      /* start sector */
 672} __attribute__((packed)) gdth_hentry_str;
 673
 674typedef struct {
 675    u32     entries;                        /* entry count */
 676    u32     offset;                         /* offset of entries */
 677    u8      secs_p_head;                    /* sectors/head */
 678    u8      heads_p_cyl;                    /* heads/cylinder */
 679    u8      reserved;
 680    u8      clust_drvtype;                  /* cluster drive type */
 681    u32     location;                       /* controller number */
 682    gdth_hentry_str entry[MAX_HDRIVES];         /* entries */
 683} __attribute__((packed)) gdth_hget_str;    
 684
 685
 686/* DPRAM structures */
 687
 688/* interface area ISA/PCI */
 689typedef struct {
 690    u8              S_Cmd_Indx;             /* special command */
 691    u8 volatile     S_Status;               /* status special command */
 692    u16              reserved1;
 693    u32             S_Info[4];              /* add. info special command */
 694    u8 volatile     Sema0;                  /* command semaphore */
 695    u8              reserved2[3];
 696    u8              Cmd_Index;              /* command number */
 697    u8              reserved3[3];
 698    u16 volatile     Status;                 /* command status */
 699    u16              Service;                /* service(for async.events) */
 700    u32             Info[2];                /* additional info */
 701    struct {
 702        u16          offset;                 /* command offs. in the DPRAM*/
 703        u16          serv_id;                /* service */
 704    } __attribute__((packed)) comm_queue[MAXOFFSETS];            /* command queue */
 705    u32             bios_reserved[2];
 706    u8              gdt_dpr_cmd[1];         /* commands */
 707} __attribute__((packed)) gdt_dpr_if;
 708
 709/* SRAM structure PCI controllers */
 710typedef struct {
 711    u32     magic;                          /* controller ID from BIOS */
 712    u16      need_deinit;                    /* switch betw. BIOS/driver */
 713    u8      switch_support;                 /* see need_deinit */
 714    u8      padding[9];
 715    u8      os_used[16];                    /* OS code per service */
 716    u8      unused[28];
 717    u8      fw_magic;                       /* contr. ID from firmware */
 718} __attribute__((packed)) gdt_pci_sram;
 719
 720/* SRAM structure EISA controllers (but NOT GDT3000/3020) */
 721typedef struct {
 722    u8      os_used[16];                    /* OS code per service */
 723    u16      need_deinit;                    /* switch betw. BIOS/driver */
 724    u8      switch_support;                 /* see need_deinit */
 725    u8      padding;
 726} __attribute__((packed)) gdt_eisa_sram;
 727
 728
 729/* DPRAM ISA controllers */
 730typedef struct {
 731    union {
 732        struct {
 733            u8      bios_used[0x3c00-32];   /* 15KB - 32Bytes BIOS */
 734            u32     magic;                  /* controller (EISA) ID */
 735            u16      need_deinit;            /* switch betw. BIOS/driver */
 736            u8      switch_support;         /* see need_deinit */
 737            u8      padding[9];
 738            u8      os_used[16];            /* OS code per service */
 739        } __attribute__((packed)) dp_sram;
 740        u8          bios_area[0x4000];      /* 16KB reserved for BIOS */
 741    } bu;
 742    union {
 743        gdt_dpr_if      ic;                     /* interface area */
 744        u8          if_area[0x3000];        /* 12KB for interface */
 745    } u;
 746    struct {
 747        u8          memlock;                /* write protection DPRAM */
 748        u8          event;                  /* release event */
 749        u8          irqen;                  /* board interrupts enable */
 750        u8          irqdel;                 /* acknowledge board int. */
 751        u8 volatile Sema1;                  /* status semaphore */
 752        u8          rq;                     /* IRQ/DRQ configuration */
 753    } __attribute__((packed)) io;
 754} __attribute__((packed)) gdt2_dpram_str;
 755
 756/* DPRAM PCI controllers */
 757typedef struct {
 758    union {
 759        gdt_dpr_if      ic;                     /* interface area */
 760        u8          if_area[0xff0-sizeof(gdt_pci_sram)];
 761    } u;
 762    gdt_pci_sram        gdt6sr;                 /* SRAM structure */
 763    struct {
 764        u8          unused0[1];
 765        u8 volatile Sema1;                  /* command semaphore */
 766        u8          unused1[3];
 767        u8          irqen;                  /* board interrupts enable */
 768        u8          unused2[2];
 769        u8          event;                  /* release event */
 770        u8          unused3[3];
 771        u8          irqdel;                 /* acknowledge board int. */
 772        u8          unused4[3];
 773    } __attribute__((packed)) io;
 774} __attribute__((packed)) gdt6_dpram_str;
 775
 776/* PLX register structure (new PCI controllers) */
 777typedef struct {
 778    u8              cfg_reg;        /* DPRAM cfg.(2:below 1MB,0:anywhere)*/
 779    u8              unused1[0x3f];
 780    u8 volatile     sema0_reg;              /* command semaphore */
 781    u8 volatile     sema1_reg;              /* status semaphore */
 782    u8              unused2[2];
 783    u16 volatile     status;                 /* command status */
 784    u16              service;                /* service */
 785    u32             info[2];                /* additional info */
 786    u8              unused3[0x10];
 787    u8              ldoor_reg;              /* PCI to local doorbell */
 788    u8              unused4[3];
 789    u8 volatile     edoor_reg;              /* local to PCI doorbell */
 790    u8              unused5[3];
 791    u8              control0;               /* control0 register(unused) */
 792    u8              control1;               /* board interrupts enable */
 793    u8              unused6[0x16];
 794} __attribute__((packed)) gdt6c_plx_regs;
 795
 796/* DPRAM new PCI controllers */
 797typedef struct {
 798    union {
 799        gdt_dpr_if      ic;                     /* interface area */
 800        u8          if_area[0x4000-sizeof(gdt_pci_sram)];
 801    } u;
 802    gdt_pci_sram        gdt6sr;                 /* SRAM structure */
 803} __attribute__((packed)) gdt6c_dpram_str;
 804
 805/* i960 register structure (PCI MPR controllers) */
 806typedef struct {
 807    u8              unused1[16];
 808    u8 volatile     sema0_reg;              /* command semaphore */
 809    u8              unused2;
 810    u8 volatile     sema1_reg;              /* status semaphore */
 811    u8              unused3;
 812    u16 volatile     status;                 /* command status */
 813    u16              service;                /* service */
 814    u32             info[2];                /* additional info */
 815    u8              ldoor_reg;              /* PCI to local doorbell */
 816    u8              unused4[11];
 817    u8 volatile     edoor_reg;              /* local to PCI doorbell */
 818    u8              unused5[7];
 819    u8              edoor_en_reg;           /* board interrupts enable */
 820    u8              unused6[27];
 821    u32             unused7[939];         
 822    u32             severity;       
 823    char                evt_str[256];           /* event string */
 824} __attribute__((packed)) gdt6m_i960_regs;
 825
 826/* DPRAM PCI MPR controllers */
 827typedef struct {
 828    gdt6m_i960_regs     i960r;                  /* 4KB i960 registers */
 829    union {
 830        gdt_dpr_if      ic;                     /* interface area */
 831        u8          if_area[0x3000-sizeof(gdt_pci_sram)];
 832    } u;
 833    gdt_pci_sram        gdt6sr;                 /* SRAM structure */
 834} __attribute__((packed)) gdt6m_dpram_str;
 835
 836
 837/* PCI resources */
 838typedef struct {
 839    struct pci_dev      *pdev;
 840    unsigned long               dpmem;                  /* DPRAM address */
 841    unsigned long               io;                     /* IO address */
 842} gdth_pci_str;
 843
 844
 845/* controller information structure */
 846typedef struct {
 847    struct Scsi_Host    *shost;
 848    struct list_head    list;
 849    u16         hanum;
 850    u16              oem_id;                 /* OEM */
 851    u16              type;                   /* controller class */
 852    u32             stype;                  /* subtype (PCI: device ID) */
 853    u16              fw_vers;                /* firmware version */
 854    u16              cache_feat;             /* feat. cache serv. (s/g,..)*/
 855    u16              raw_feat;               /* feat. raw service (s/g,..)*/
 856    u16              screen_feat;            /* feat. raw service (s/g,..)*/
 857    u16              bmic;                   /* BMIC address (EISA) */
 858    void __iomem        *brd;                   /* DPRAM address */
 859    u32             brd_phys;               /* slot number/BIOS address */
 860    gdt6c_plx_regs      *plx;                   /* PLX regs (new PCI contr.) */
 861    gdth_cmd_str        cmdext;
 862    gdth_cmd_str        *pccb;                  /* address command structure */
 863    u32             ccb_phys;               /* phys. address */
 864#ifdef INT_COAL
 865    gdth_coal_status    *coal_stat;             /* buffer for coalescing int.*/
 866    u64             coal_stat_phys;         /* phys. address */
 867#endif
 868    char                *pscratch;              /* scratch (DMA) buffer */
 869    u64             scratch_phys;           /* phys. address */
 870    u8              scratch_busy;           /* in use? */
 871    u8              dma64_support;          /* 64-bit DMA supported? */
 872    gdth_msg_str        *pmsg;                  /* message buffer */
 873    u64             msg_phys;               /* phys. address */
 874    u8              scan_mode;              /* current scan mode */
 875    u8              irq;                    /* IRQ */
 876    u8              drq;                    /* DRQ (ISA controllers) */
 877    u16              status;                 /* command status */
 878    u16              service;                /* service/firmware ver./.. */
 879    u32             info;
 880    u32             info2;                  /* additional info */
 881    Scsi_Cmnd           *req_first;             /* top of request queue */
 882    struct {
 883        u8          present;                /* Flag: host drive present? */
 884        u8          is_logdrv;              /* Flag: log. drive (master)? */
 885        u8          is_arraydrv;            /* Flag: array drive? */
 886        u8          is_master;              /* Flag: array drive master? */
 887        u8          is_parity;              /* Flag: parity drive? */
 888        u8          is_hotfix;              /* Flag: hotfix drive? */
 889        u8          master_no;              /* number of master drive */
 890        u8          lock;                   /* drive locked? (hot plug) */
 891        u8          heads;                  /* mapping */
 892        u8          secs;
 893        u16          devtype;                /* further information */
 894        u64         size;                   /* capacity */
 895        u8          ldr_no;                 /* log. drive no. */
 896        u8          rw_attribs;             /* r/w attributes */
 897        u8          cluster_type;           /* cluster properties */
 898        u8          media_changed;          /* Flag:MOUNT/UNMOUNT occurred */
 899        u32         start_sec;              /* start sector */
 900    } hdr[MAX_LDRIVES];                         /* host drives */
 901    struct {
 902        u8          lock;                   /* channel locked? (hot plug) */
 903        u8          pdev_cnt;               /* physical device count */
 904        u8          local_no;               /* local channel number */
 905        u8          io_cnt[MAXID];          /* current IO count */
 906        u32         address;                /* channel address */
 907        u32         id_list[MAXID];         /* IDs of the phys. devices */
 908    } raw[MAXBUS];                              /* SCSI channels */
 909    struct {
 910        Scsi_Cmnd       *cmnd;                  /* pending request */
 911        u16          service;                /* service */
 912    } cmd_tab[GDTH_MAXCMDS];                    /* table of pend. requests */
 913    struct gdth_cmndinfo {                      /* per-command private info */
 914        int index;
 915        int internal_command;                   /* don't call scsi_done */
 916        gdth_cmd_str *internal_cmd_str;         /* crier for internal messages*/
 917        dma_addr_t sense_paddr;                 /* sense dma-addr */
 918        u8 priority;
 919        int timeout_count;                      /* # of timeout calls */
 920        volatile int wait_for_completion;
 921        u16 status;
 922        u32 info;
 923        enum dma_data_direction dma_dir;
 924        int phase;                              /* ???? */
 925        int OpCode;
 926    } cmndinfo[GDTH_MAXCMDS];                   /* index==0 is free */
 927    u8              bus_cnt;                /* SCSI bus count */
 928    u8              tid_cnt;                /* Target ID count */
 929    u8              bus_id[MAXBUS];         /* IOP IDs */
 930    u8              virt_bus;               /* number of virtual bus */
 931    u8              more_proc;              /* more /proc info supported */
 932    u16              cmd_cnt;                /* command count in DPRAM */
 933    u16              cmd_len;                /* length of actual command */
 934    u16              cmd_offs_dpmem;         /* actual offset in DPRAM */
 935    u16              ic_all_size;            /* sizeof DPRAM interf. area */
 936    gdth_cpar_str       cpar;                   /* controller cache par. */
 937    gdth_bfeat_str      bfeat;                  /* controller features */
 938    gdth_binfo_str      binfo;                  /* controller info */
 939    gdth_evt_data       dvr;                    /* event structure */
 940    spinlock_t          smp_lock;
 941    struct pci_dev      *pdev;
 942    char                oem_name[8];
 943#ifdef GDTH_DMA_STATISTICS
 944    unsigned long               dma32_cnt, dma64_cnt;   /* statistics: DMA buffer */
 945#endif
 946    struct scsi_device         *sdev;
 947} gdth_ha_str;
 948
 949static inline struct gdth_cmndinfo *gdth_cmnd_priv(struct scsi_cmnd* cmd)
 950{
 951        return (struct gdth_cmndinfo *)cmd->host_scribble;
 952}
 953
 954/* INQUIRY data format */
 955typedef struct {
 956    u8      type_qual;
 957    u8      modif_rmb;
 958    u8      version;
 959    u8      resp_aenc;
 960    u8      add_length;
 961    u8      reserved1;
 962    u8      reserved2;
 963    u8      misc;
 964    u8      vendor[8];
 965    u8      product[16];
 966    u8      revision[4];
 967} __attribute__((packed)) gdth_inq_data;
 968
 969/* READ_CAPACITY data format */
 970typedef struct {
 971    u32     last_block_no;
 972    u32     block_length;
 973} __attribute__((packed)) gdth_rdcap_data;
 974
 975/* READ_CAPACITY (16) data format */
 976typedef struct {
 977    u64     last_block_no;
 978    u32     block_length;
 979} __attribute__((packed)) gdth_rdcap16_data;
 980
 981/* REQUEST_SENSE data format */
 982typedef struct {
 983    u8      errorcode;
 984    u8      segno;
 985    u8      key;
 986    u32     info;
 987    u8      add_length;
 988    u32     cmd_info;
 989    u8      adsc;
 990    u8      adsq;
 991    u8      fruc;
 992    u8      key_spec[3];
 993} __attribute__((packed)) gdth_sense_data;
 994
 995/* MODE_SENSE data format */
 996typedef struct {
 997    struct {
 998        u8  data_length;
 999        u8  med_type;
1000        u8  dev_par;
1001        u8  bd_length;
1002    } __attribute__((packed)) hd;
1003    struct {
1004        u8  dens_code;
1005        u8  block_count[3];
1006        u8  reserved;
1007        u8  block_length[3];
1008    } __attribute__((packed)) bd;
1009} __attribute__((packed)) gdth_modep_data;
1010
1011/* stack frame */
1012typedef struct {
1013    unsigned long       b[10];                          /* 32/64 bit compiler ! */
1014} __attribute__((packed)) gdth_stackframe;
1015
1016
1017/* function prototyping */
1018
1019int gdth_proc_info(struct Scsi_Host *, char *,char **,off_t,int,int);
1020
1021#endif
1022
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