linux/drivers/pinctrl/pinctrl-tegra.h
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   1/*
   2 * Driver for the NVIDIA Tegra pinmux
   3 *
   4 * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 */
  15
  16#ifndef __PINMUX_TEGRA_H__
  17#define __PINMUX_TEGRA_H__
  18
  19/**
  20 * struct tegra_function - Tegra pinctrl mux function
  21 * @name: The name of the function, exported to pinctrl core.
  22 * @groups: An array of pin groups that may select this function.
  23 * @ngroups: The number of entries in @groups.
  24 */
  25struct tegra_function {
  26        const char *name;
  27        const char * const *groups;
  28        unsigned ngroups;
  29};
  30
  31/**
  32 * struct tegra_pingroup - Tegra pin group
  33 * @mux_reg:            Mux register offset. -1 if unsupported.
  34 * @mux_bank:           Mux register bank. 0 if unsupported.
  35 * @mux_bit:            Mux register bit. 0 if unsupported.
  36 * @pupd_reg:           Pull-up/down register offset. -1 if unsupported.
  37 * @pupd_bank:          Pull-up/down register bank. 0 if unsupported.
  38 * @pupd_bit:           Pull-up/down register bit. 0 if unsupported.
  39 * @tri_reg:            Tri-state register offset. -1 if unsupported.
  40 * @tri_bank:           Tri-state register bank. 0 if unsupported.
  41 * @tri_bit:            Tri-state register bit. 0 if unsupported.
  42 * @einput_reg:         Enable-input register offset. -1 if unsupported.
  43 * @einput_bank:        Enable-input register bank. 0 if unsupported.
  44 * @einput_bit:         Enable-input register bit. 0 if unsupported.
  45 * @odrain_reg:         Open-drain register offset. -1 if unsupported.
  46 * @odrain_bank:        Open-drain register bank. 0 if unsupported.
  47 * @odrain_bit:         Open-drain register bit. 0 if unsupported.
  48 * @lock_reg:           Lock register offset. -1 if unsupported.
  49 * @lock_bank:          Lock register bank. 0 if unsupported.
  50 * @lock_bit:           Lock register bit. 0 if unsupported.
  51 * @ioreset_reg:        IO reset register offset. -1 if unsupported.
  52 * @ioreset_bank:       IO reset register bank. 0 if unsupported.
  53 * @ioreset_bit:        IO reset register bit. 0 if unsupported.
  54 * @drv_reg:            Drive fields register offset. -1 if unsupported.
  55 *                      This register contains the hsm, schmitt, lpmd, drvdn,
  56 *                      drvup, slwr, and slwf parameters.
  57 * @drv_bank:           Drive fields register bank. 0 if unsupported.
  58 * @hsm_bit:            High Speed Mode register bit. 0 if unsupported.
  59 * @schmitt_bit:        Scmitt register bit. 0 if unsupported.
  60 * @lpmd_bit:           Low Power Mode register bit. 0 if unsupported.
  61 * @drvdn_bit:          Drive Down register bit. 0 if unsupported.
  62 * @drvdn_width:        Drive Down field width. 0 if unsupported.
  63 * @drvup_bit:          Drive Up register bit. 0 if unsupported.
  64 * @drvup_width:        Drive Up field width. 0 if unsupported.
  65 * @slwr_bit:           Slew Rising register bit. 0 if unsupported.
  66 * @slwr_width:         Slew Rising field width. 0 if unsupported.
  67 * @slwf_bit:           Slew Falling register bit. 0 if unsupported.
  68 * @slwf_width:         Slew Falling field width. 0 if unsupported.
  69 *
  70 * A representation of a group of pins (possibly just one pin) in the Tegra
  71 * pin controller. Each group allows some parameter or parameters to be
  72 * configured. The most common is mux function selection. Many others exist
  73 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
  74 * certain groups may only support configuring certain parameters, hence
  75 * each parameter is optional, represented by a -1 "reg" value.
  76 */
  77struct tegra_pingroup {
  78        const char *name;
  79        const unsigned *pins;
  80        unsigned npins;
  81        unsigned funcs[4];
  82        unsigned func_safe;
  83        s16 mux_reg;
  84        s16 pupd_reg;
  85        s16 tri_reg;
  86        s16 einput_reg;
  87        s16 odrain_reg;
  88        s16 lock_reg;
  89        s16 ioreset_reg;
  90        s16 drv_reg;
  91        u32 mux_bank:2;
  92        u32 pupd_bank:2;
  93        u32 tri_bank:2;
  94        u32 einput_bank:2;
  95        u32 odrain_bank:2;
  96        u32 ioreset_bank:2;
  97        u32 lock_bank:2;
  98        u32 drv_bank:2;
  99        u32 mux_bit:5;
 100        u32 pupd_bit:5;
 101        u32 tri_bit:5;
 102        u32 einput_bit:5;
 103        u32 odrain_bit:5;
 104        u32 lock_bit:5;
 105        u32 ioreset_bit:5;
 106        u32 hsm_bit:5;
 107        u32 schmitt_bit:5;
 108        u32 lpmd_bit:5;
 109        u32 drvdn_bit:5;
 110        u32 drvup_bit:5;
 111        u32 slwr_bit:5;
 112        u32 slwf_bit:5;
 113        u32 drvdn_width:6;
 114        u32 drvup_width:6;
 115        u32 slwr_width:6;
 116        u32 slwf_width:6;
 117};
 118
 119/**
 120 * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
 121 * @ngpios:     The number of GPIO pins the pin controller HW affects.
 122 * @pins:       An array describing all pins the pin controller affects.
 123 *              All pins which are also GPIOs must be listed first within the
 124 *              array, and be numbered identically to the GPIO controller's
 125 *              numbering.
 126 * @npins:      The numbmer of entries in @pins.
 127 * @functions:  An array describing all mux functions the SoC supports.
 128 * @nfunctions: The numbmer of entries in @functions.
 129 * @groups:     An array describing all pin groups the pin SoC supports.
 130 * @ngroups:    The numbmer of entries in @groups.
 131 */
 132struct tegra_pinctrl_soc_data {
 133        unsigned ngpios;
 134        const struct pinctrl_pin_desc *pins;
 135        unsigned npins;
 136        const struct tegra_function *functions;
 137        unsigned nfunctions;
 138        const struct tegra_pingroup *groups;
 139        unsigned ngroups;
 140};
 141
 142int tegra_pinctrl_probe(struct platform_device *pdev,
 143                        const struct tegra_pinctrl_soc_data *soc_data);
 144int tegra_pinctrl_remove(struct platform_device *pdev);
 145
 146#endif
 147
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