linux/drivers/pinctrl/pinctrl-imx51.c
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   1/*
   2 * imx51 pinctrl driver based on imx pinmux core
   3 *
   4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
   5 * Copyright (C) 2012 Linaro, Inc.
   6 *
   7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; either version 2 of the License, or
  12 * (at your option) any later version.
  13 */
  14
  15#include <linux/err.h>
  16#include <linux/init.h>
  17#include <linux/io.h>
  18#include <linux/module.h>
  19#include <linux/of.h>
  20#include <linux/of_device.h>
  21#include <linux/pinctrl/pinctrl.h>
  22
  23#include "pinctrl-imx.h"
  24
  25enum imx51_pads {
  26        MX51_PAD_EIM_D16 = 1,
  27        MX51_PAD_EIM_D17 = 2,
  28        MX51_PAD_EIM_D18 = 3,
  29        MX51_PAD_EIM_D19 = 4,
  30        MX51_PAD_EIM_D20 = 5,
  31        MX51_PAD_EIM_D21 = 6,
  32        MX51_PAD_EIM_D22 = 7,
  33        MX51_PAD_EIM_D23 = 8,
  34        MX51_PAD_EIM_D24 = 9,
  35        MX51_PAD_EIM_D25 = 10,
  36        MX51_PAD_EIM_D26 = 11,
  37        MX51_PAD_EIM_D27 = 12,
  38        MX51_PAD_EIM_D28 = 13,
  39        MX51_PAD_EIM_D29 = 14,
  40        MX51_PAD_EIM_D30 = 15,
  41        MX51_PAD_EIM_D31 = 16,
  42        MX51_PAD_EIM_A16 = 17,
  43        MX51_PAD_EIM_A17 = 18,
  44        MX51_PAD_EIM_A18 = 19,
  45        MX51_PAD_EIM_A19 = 20,
  46        MX51_PAD_EIM_A20 = 21,
  47        MX51_PAD_EIM_A21 = 22,
  48        MX51_PAD_EIM_A22 = 23,
  49        MX51_PAD_EIM_A23 = 24,
  50        MX51_PAD_EIM_A24 = 25,
  51        MX51_PAD_EIM_A25 = 26,
  52        MX51_PAD_EIM_A26 = 27,
  53        MX51_PAD_EIM_A27 = 28,
  54        MX51_PAD_EIM_EB0 = 29,
  55        MX51_PAD_EIM_EB1 = 30,
  56        MX51_PAD_EIM_EB2 = 31,
  57        MX51_PAD_EIM_EB3 = 32,
  58        MX51_PAD_EIM_OE = 33,
  59        MX51_PAD_EIM_CS0 = 34,
  60        MX51_PAD_EIM_CS1 = 35,
  61        MX51_PAD_EIM_CS2 = 36,
  62        MX51_PAD_EIM_CS3 = 37,
  63        MX51_PAD_EIM_CS4 = 38,
  64        MX51_PAD_EIM_CS5 = 39,
  65        MX51_PAD_EIM_DTACK = 40,
  66        MX51_PAD_EIM_LBA = 41,
  67        MX51_PAD_EIM_CRE = 42,
  68        MX51_PAD_DRAM_CS1 = 43,
  69        MX51_PAD_NANDF_WE_B = 44,
  70        MX51_PAD_NANDF_RE_B = 45,
  71        MX51_PAD_NANDF_ALE = 46,
  72        MX51_PAD_NANDF_CLE = 47,
  73        MX51_PAD_NANDF_WP_B = 48,
  74        MX51_PAD_NANDF_RB0 = 49,
  75        MX51_PAD_NANDF_RB1 = 50,
  76        MX51_PAD_NANDF_RB2 = 51,
  77        MX51_PAD_NANDF_RB3 = 52,
  78        MX51_PAD_GPIO_NAND = 53,
  79        MX51_PAD_NANDF_CS0 = 54,
  80        MX51_PAD_NANDF_CS1 = 55,
  81        MX51_PAD_NANDF_CS2 = 56,
  82        MX51_PAD_NANDF_CS3 = 57,
  83        MX51_PAD_NANDF_CS4 = 58,
  84        MX51_PAD_NANDF_CS5 = 59,
  85        MX51_PAD_NANDF_CS6 = 60,
  86        MX51_PAD_NANDF_CS7 = 61,
  87        MX51_PAD_NANDF_RDY_INT = 62,
  88        MX51_PAD_NANDF_D15 = 63,
  89        MX51_PAD_NANDF_D14 = 64,
  90        MX51_PAD_NANDF_D13 = 65,
  91        MX51_PAD_NANDF_D12 = 66,
  92        MX51_PAD_NANDF_D11 = 67,
  9inctrl/pinctrl-imx51.c#L83" id="L83" class=D10" class="sref">MX51_PAD_NANDF_76lass=D10" class="sref">MX5_3.4"
	  >
 9nctrl-im951.c#L84" id="L84" clas9="lin9" name="L84">  84          85          86         = 61,
  87         = 62,
  88        X51_PAD_7ANDF_D15 = 63,
  89        X51_PAD_7ANDF_D14 = 64,
  89        X51_PAD_7ANDF_D13 = 65,
  91        >MX51_PADANDF_D12 = 66,
  92        MMX51_PADANDF_D11 = 67,
  9inctrl/pinctrl-imx51.c#L83" d="L83" class=D10" class="sref">X51_PAD_7ANDF_76lass=D10" class="sref">MX5_3.4"
	  >
 10nctrl-imx051.c#L14" id="L14" class04"lis=" name="L84">  84         = 59,
  85         = 60,
  86         = 61,
  87         = 62,
  88         = 63,
  89         = 64,
  89         = 65,
  91         = 66,
  92         = 67,
  9inctrl/pinctrl-imx51.CSI1eDiX51_PAD_NANDF_CS7" class=CSI1eDiX51_PAD_8ANDF_76lass=D10" class="sref">MX5_3.4"
	  >
 1inctrl-imxx51.c#L14" id="L14" classs="li11" name="L84">  84         = 59,
  85         = 60,
  86         = 61,
  87         = 62,
  88         = 63,
  89         = 64,
  89         = 65,
  91         = 66,
  92         = 67,
  9inctrl/pinctrl-imx51.CSI2eDiX51_PAD_NANDF_D15" class=CSI2eDiX51_PAD_9ANDF_76lass=D10" class="sref">MX5_3.4"
	  >
 1inctrl-im1x51.c#L24" id="L24" clas1s="li12" name="L84">  84         = 59,
  85         = 60,
  26         = 61,
  27         = 62,
  28         = 63,
  29         = 64,
  30         = 65,
  31         = 66,
  32         = 67,
  33        MX5_3.4"
	  >
 1inctrl-im1x51.c#L34" id="L34" clas1s="li1e" name="L34">  34         = 59,
  35         = 10,
  36         = 61,
  37         = 62,
  38         = 63,
  39         = 64,
  40         = 65,
  41         = 66,
  42         = 67,
  43        MX5_3.4"
	  >
 1inctrl-im1x51.c#L44" id="L44" clas1s="li1e" name="L44">  44         = 59,
  45         = 20,
  46         = 61,
  47         = 22,
  48         = 23,
  49         = 64,
  50         = 65,
  51         = 66,
  52         = 67,
  53        MX5_3.4"
	  >
 1inctrl-im1x51.c#L54" id="L54" clas1s="li1e" name="L54">  54         = 59,
  55         = 30,
  56         = 61,
  57         = 22,
  58         = 23,
  59         = 64,
  60         = 65,
  61         = 66,
  62         = 67,
  63        MX5_3.4"
	  >
 1inctrl-im1x51.c#L64" id="L64" clas1s="li1e" name="L64">  64         = 59,
  65         = 40,
  66         = 61,
  67         = 22,
  68         = 23,
  69         = 64,
  70         = 65,
  71         = 66,
  72         = 67,
  73        MX5_3.4"
	  >
 1inctrl-im1x51.c#L74" id="L74" clas1s="li1e" name="L74">  74         = 59,
  75         = 50,
  76         = 61,
  77         = 22,
  78         = 23,
  79         = 64,
  80         = 65,
  81         = 66,
  82         = 67,
  83        MX5_3.4"
	  >
 1inctrl-im1x51.c#L84" id="L84" clas1s="li1e" name="L84">  84         = 59,
  85         = 60,
  86         = 61,
  87         = 22,
  88         = 23,
  89         = 64,
  90         = 65,
  91         = 66,
  92         = 67,
  9inctrl/pinctrl-imx51.DISP1_DATMX51_PAD_NANDF_CS0" class=DISP1_DATid51_PAD_1NANDF_76lass=D10" class="sref">MX5_3.4"
	  >
 19nctrl-im1951.c#L84" id="L84" clas19="li19" name="L84">  84        MX51_PAD_ANDF_CS5 = 59,
  85         = 60,
  86         = 61,
  87         = 62,
  88         = 63,
  89        MX51_PAD_ANDF_D14 = 64,
  89         = 65,
  91         = 66,
  92         = 67,
  9inctrl/pinctrl-imx51.DISP1_DATXX51_PAD_NANDF_CS0" class=DISP1_DAT">MX51_PA17ANDF_76lass=D10" class="sref">MX5_3.4"
	  >
 20nctrl-im2051.c#L14" id="L14" clas204"li2=" name="L84">  84        MX51_PA17ANDF_CS5 = 59,
  85         = 60,
  86        MX51_PA18ANDF_CS7 = 61,
  87        MX51_PA18D_EIM_D17 = 2,
  88         = 3,
  89         = 64,
  89         = 65,
  91         = 66,
  92         = 67,
  9inctrl/pinctrl-imx51.DI2ePINX51_PAD_NANDF_D13" class=DI2ePIN>MX51_PA18ANDF_76lass=D10" class="sref">MX5_3.4"
	  >
 2inctrl-im2x51.c#L14" id="L14" clas2s="li21" name="L84">  84         = 59,
  85         = 60,
  86         = 61,
  87         = 62,
  88         = 63,
  89         = 64,
  89         = 65,
  91         = 66,
  92         = 67,
  9inctrl/pinctrl-imx51.DISP2_DATX51_PAD_NANDF_CS7" class=DISP2_DATX51_PAD_19ANDF_76lass=D10" class="sref">MX5_3.4"
	  >
 2inctrl-im2x51.c#L24" id="L24" clas2s="li22" name="L84">  84         = 59,
  85         = 60,
  26         = 61,
  27        MX51_PAD0_RDY_INT = 62,
  28         = 63,
  29         = 64,
  30         = 65,
  31         = 66,
  32         = 67,
  33        MX5_3.4"
	  >
 2inctrl-im2x51.c#L34" id="L34" clas2s="li2e" name="L34">  34         = 59,
  35          36          37          38          39         = 64,
  40          41          42          43        MX5_3.4"
	  >
 2inctrl-im2x51.c#L44" id="L44" clas2s="li2e" name="L44">  44         = 59,
  45          46          47          48          49         = 64,
  50          51          52          53        MX5_3.4"
	  >
 2inctrl-im2x51.c#L54" id="L54" clas2s="li2e" name="L54">  54          55          56         = 61,
  57         = 22,
  58         = 23,
  59         = 64,
  60         = 65,
  61         = 66,
  62          63        MX5_3.4"
	  >
 2inctrl-im2x51.c#L64" id="L64" clas2s="li2e" name="L64">  64         = 59,
  65          66          67          68          69          70         = 65,
 = 65,
/* pinct register maps */ = 65,
  70       pin_dri_regMX51_PAD_EIM_A1pin_dri_reg51_PA  70       pin cldri_regsMX51_PAD_EIM_A1pin cldri_regs51_P[]AD_{DF_D13 = 65,
  75       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDiX_=AUD4_RXFS */ = 65,
  76       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDiX_=AUD5_TXX */ = 65,
  77       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDiX_="sreDiX */ = 65,
  78       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDiX_="sre2_0 */ = 65,
  79       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDiX_=I2C1_SDA */ = 65,
  80       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDiX_=UART2_CTS */ = 65,
  81       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDiX_=USBH2_DATAX */ = 65,
  82       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi7_=AUD5_RXX */ = 65,
  83       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi7_="sreDi7 */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi7_="sre2_1 */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi7_=UART2_RXX */ = 65,
  86       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi7_=UART3_CTS */ = 65,
  87       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi7_=USBH2_DATA1 */ = 65,
  88       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi8_=AUD5_TXC */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi8_="sreDi8 */ = 65,
  90       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi8_="sre2_2 */ = 65,
  91       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi8_=UART2_TXX */ = 65,
  92       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi8_=UART3_RTS */ = 65,
  9inctrl/pinctIMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi8_=USBH2_DATA2 */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi9_=AUD4_RXC */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi9_=AUD5_TXFS */ = 65,
  86       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi9_="sreDi9 */ = 65,
  87       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi9_="sre2_3 */ = 65,
  88       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi9_=I2C1_SCL */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi9_=UART2_RTS */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDi9_=USBH2_DATA3 */ = 65,
  91       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD20_=AUD4_TXX */ = 65,
  92       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD20_="sreD20 */ = 65,
  9inctrl/pinctIMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD20_="sre2_4 */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD20_=SRTC_ALARreDEB */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD20_=USBH2_DATA4 */ = 65,
  86       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD21_=AUD4_RXX */ = 65,
  87       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD21_="sreD21 */ = 65,
  88       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD21_="sre2_5 */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD21_=SRTC_ALARreDEB */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD21_=USBH2_DATA5 */ = 65,
  91       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD22_=AUD4_TXC */ = 65,
  92       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD22_="sreD22 */ = 65,
  9inctrl/pinctIMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD22_="sre2_X */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD22_=USBH2_DATAX */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD23_=AUD4_TXFS */ = 65,
  86       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD23_="sreD23 */ = 65,
  87       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD23_="sre2_7 */ = 65,
  88       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD23_=SPDIF_OUT1 */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD23_=USBH2_DATA7 */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD24_=AUD6_RXFS */ = 65,
  91       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD24_="sreD24 */ = 65,
  92       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD24_="sre2_8 */ = 65,
  9inctrl/pinctIMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD24_=I2C2_SDA */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD24_=UART3_CTS */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD24_=USBOTG_DATAX */ = 65,
  26       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD25_="sreD25 */ = 65,
  27       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD25_=KEY_COLX */ = 65,
  28       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD25_=UART2_CTS */ = 65,
  29       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD25_=UART3_RXX */ = 65,
  30       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD25_=USBOTG_DATA1 */ = 65,
  31       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD2X_="sreD2X */ = 65,
  32       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD26_=KEY_COL7 */ = 65,
  33       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD26_=UART2_RTS */ = 65,
  34       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD26_=UART3_TXX */ = 65,
  35       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD26_=USBOTG_DATA2 */ = 65,
  36       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD27_=AUD6_RXC */ = 65,
  37       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD27_="sreD27 */ = 65,
  38       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD27_="sre2_9 */ = 65,
  39       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD27_=I2C2_SCL */ = 65,
  40       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD27_=UART3_RTS */ = 65,
  41       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD27_=USBOTG_DATA3 */ = 65,
  42       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD28_=AUD6_TXX */ = 65,
  43       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD28_="sreD28 */ = 65,
  44       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD28_=KEY_ROW4 */ = 65,
  45       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD28_=USBOTG_DATA4 */ = 65,
  46       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD29_=AUD6_RXX */ = 65,
  47       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD29_="sreD29 */ = 65,
  48       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD29_=KEY_ROW5 */ = 65,
  49       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD29_=USBOTG_DATA5 */ = 65,
  50       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD30_=AUD6_TXC */ = 65,
  51       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD30_="sreD3X */ = 65,
  52       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD30_=KEY_ROWX */ = 65,
  53       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD30_=USBOTG_DATAX */ = 65,
  54       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD31_=AUD6_TXFS */ = 65,
  55       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD31_="sreD31 */ = 65,
  56       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD31_=KEY_ROW7 */ = 65,
  57       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreD31_=USBOTG_DATA7 */ = 65,
  58       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreAiX_="sreAiX */ = 65,
  59       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreAiX_="sre2_1X */ = 65,
  60       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreAiX_=OSC_FREQ_SELX */ = 65,
  61       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreAi7_="sreAi7 */ = 65,
  62       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreAi7_="sre2_11 */ = 65,
  63       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreAi7_=OSC_FREQ_SEL1 */ = 65,
  64       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreAi8__BOOT_LPBX */ = 65,
  65       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreAi8_="sreAi8 */ = 65,
  66       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreAi8_="sre2_12 */ = 65,
  67       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreAi9__BOOT_LPB1 */ = 65,
  68       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreAi9_="sreAi9 */ = 65,
  69       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreAi9_="sre2_13 */ = 65,
  70       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA20_=BOOT_UART_SRCX */ = 65,
  61       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA20_="sreA20 */ = 65,
  62       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA20_="sre2_14 */ = 65,
  63       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA21_=BOOT_UART_SRC1 */ = 65,
  64       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA21_="sreA21 */ = 65,
  75       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA21_="sre2_15 */ = 65,
  76       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA22_="sreA22 */ = 65,
  77       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA22_="sre2_iX */ = 65,
  78       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA23_=BOOT_HPN_EN */ = 65,
  79       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA23_="sreA23 */ = 65,
  80       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA23_="sre2_i7 */ = 65,
  81       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA24_="sreA24 */ = 65,
  82       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA24_="sre2_i8 */ = 65,
  83       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA24_=USBH2_CLK */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA25__DISP1ePIN4 */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA25_="sreA25 */ = 65,
  86       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA25_="sre2_i9 */ = 65,
  87       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA25_=USBH2_DIR */ = 65,
  88       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA26__CSI1_DATA_EN */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA26__DISP2_EXT_CLK */ = 65,
  90       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA2X_="sreA2X */ = 65,
  91       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA2X_="sre2_20 */ = 65,
  92       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA26_=USBH2_STP */ = 65,
  9inctrl/pinctIMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA27_=CSI2_DATA_EN */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA27_=DISP1ePIN1 */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA27_="sreA27 */ = 65,
  86       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA27_="sre2_21 */ = 65,
  87       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreA27_=USBH2_NXT */ = 65,
  88       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEBX_="sreEBX */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEB=_="sreEB1 */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEB2_=AUD5_RXFS */ = 65,
  91       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEB2__CSI1_D2 */ = 65,
  92       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEB2_="sreEB2 */ = 65,
  9inctrl/pinctIMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEB2_=FEC_MDIO */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEB2_="sre2_22 */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEB2_="sT_CMPOUT1 */ = 65,
  86       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEB=_=AUD5_RXC */ = 65,
  87       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEB3__CSI1_D3 */ = 65,
  88       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEB3_="sreEB3 */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEB=_=FEC_RDATA1 */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEB3_="sre2_23 */ = 65,
  91       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreEB3_="sT_CMPOUT2 */ = 65,
  92       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreOE_="sreOE */ = 65,
  9inctrl/pinctIMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreOE_="sre2_24 */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCSX_="sreCSX */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCSX_="sre2_25 */ = 65,
  86       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS=_="sreCS1 */ = 65,
  87       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS1_="sre2_2X */ = 65,
  88       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS2_=AUD5_TXX */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS2_=CSI1_D4 */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS2_="sreCS2 */ = 65,
  91       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS2_=FEC_RDATA2 */ = 65,
  92       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS2_="sre2_27 */ = 65,
  9inctrl/pinctIMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS2_=USBOTG_STP */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS=_=AUD5_RXX */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS3__CSI1_D5 */ = 65,
  26       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS3_="sreCS3 */ = 65,
  27       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS3_=FEC_RDATA3 */ = 65,
  28       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS3_="sre2_28 */ = 65,
  29       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS3_=USBOTG_NXT */ = 65,
  30       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS4_=AUD5_TXC */ = 65,
  31       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS4__CSI1_DX */ = 65,
  32       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS4_="sreCS4 */ = 65,
  33       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS4_=FEC_RX_ER */ = 65,
  34       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS4_="sre2_29 */ = 65,
  35       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS4_=USBOTG_CLK */ = 65,
  36       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS5_=AUD5_TXFS */ = 65,
  37       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS5__CSI1_D7 */ = 65,
  38       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS5__DISP1eEXT_CLK */ = 65,
  39       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS5_="sreCS5 */ = 65,
  40       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS5_=FEC_CRS */ = 65,
  41       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS5_="sre2_3X */ = 65,
  42       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCS5_=USBOTG_DIR */ = 65,
  43       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDTACK_="sreDTACK */ = 65,
  44       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreDTACK_="sre2_31 */ = 65,
  45       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreLBA_="sreLBA */ = 65,
  46       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreLBA_="sre3_1 */ = 65,
  47       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCRE_="sreCRE */ = 65,
  48       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sreCRE_="sre3_2 */ = 65,
  49       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=DRAreCS=_=DRAreCS= */ = 65,
  50       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_WE_B_="sre3_3 */ = 65,
  51       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_WE_B_=NANDF_WE_B */ = 65,
  52       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_WE_B_=PATA_DIOW */ = 65,
  53       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_WE_B_=SD3_DATAX */ = 65,
  54       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RE_B_="sre3_4 */ = 65,
  55       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RE_B_=NANDF_RE_B */ = 65,
  56       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RE_B_=PATA_DIOR */ = 65,
  57       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RE_B_=SD3_DATA= */ = 65,
  58       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_ALE_="sre3_5 */ = 65,
  59       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_ALE_=NANDF_ALE */ = 65,
  60       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_ALE_=PATA_BUFFER_EN */ = 65,
  61       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CLE_="sre3_X */ = 65,
  62       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CLE_=NANDF_CLE */ = 65,
  63       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CLE_=PATA_RESET_B */ = 65,
  64       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_WP_B_="sre3_7 */ = 65,
  65       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_WP_B_=NANDF_WP_B */ = 65,
  66       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_WP_B_=PATA_DMACK */ = 65,
  67       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_WP_B_=SD3_DATA2 */ = 65,
  68       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RBX_="CSPI2_SS= */ = 65,
  69       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB0_="sre3_8 */ = 65,
  70       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB0_=NANDF_RB0 */ = 65,
  61       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB0_=PATA_DMARQ */ = 65,
  62       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB0_=SD3_DATA3 */ = 65,
  63       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB=_=CSPI_MOSI */ = 65,
  64       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB=_="CSPI2_RDY */ = 65,
  75       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB=_="sre3_9 */ = 65,
  76       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB1_=NANDF_RB= */ = 65,
  77       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB1_=PATA_IORDY */ = 65,
  78       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB1_=SD4_CMX */ = 65,
  79       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB2__DISP2_WAIT */ = 65,
  80       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB2_="CSPI2_SCLK */ = 65,
  81       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB2_=FEC_COL */ = 65,
  82       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB2_="sre3_10 */ = 65,
  83       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB2_=NANDF_RB2 */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB2_=USBH3_H3_DP */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB2_=USBH3_NXT */ = 65,
  86       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB=__DISP1eWAIT */ = 65,
  87       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB3_="CSPI2_MISO */ = 65,
  88       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB3_=FEC_RX_CLK */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB3_="sre3_1= */ = 65,
  90       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB3_=NANDF_RB3 */ = 65,
  91       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB3_=USBH3_CLK */ = 65,
  92       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RB3_=USBH3_H3_DM */ = 65,
  9inctrl/pinctIMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sre=NAND_="sre=NAND */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class="sre=NAND_=PATA_INTRQ */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CSX_="sre3_1X */ = 65,
  86       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS0_=NANDF_CSX */ = 65,
  87       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS1_="sre3_17 */ = 65,
  88       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS1_=NANDF_CS= */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS2_=CSPI_SCLK */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS2_=FEC_TX_ER */ = 65,
  91       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS2_="sre3_18 */ = 65,
  92       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS2_=NANDF_CS2 */ = 65,
  9inctrl/pinctIMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS2_=PATA_CS_X */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS2_=SD4_CLK */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS2_=USBH3_H1_DP */ = 65,
  86       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS=_=FEC_MDC */ = 65,
  87       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS3_="sre3_19 */ = 65,
  88       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS3_=NANDF_CS3 */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS3_=PATA_CS_= */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS3_=SD4_DATX */ = 65,
  91       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS3_=USBH3_H1_DM */ = 65,
  92       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS4_=FEC_TDATA= */ = 65,
  9inctrl/pinctIMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS4_="sre3_2X */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS4_=NANDF_CS4 */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS4_=PATA_DA_X */ = 65,
  86       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS4_=SD4_DAT= */ = 65,
  87       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS4_=USBH3_STP */ = 65,
  88       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS5_=FEC_TDATA2 */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS5_="sre3_2= */ = 65,
  89       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS5_=NANDF_CS5 */ = 65,
  91       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS5_=PATA_DA_= */ = 65,
  92       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS5_=SD4_DAT2 */ = 65,
  9inctrl/pinctIMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS5_=USBH3_DIR */ = 65,
  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS6_=CSPI_SS3 */ = 65,
  85       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS6_=FEC_TDATA3 */ = 65,
  26       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS6_="sre3_22 */ = 65,
  27       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS6_=NANDF_CSX */ = 65,
  28       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS6_=PATA_DA_2 */ = 65,
  29       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS6_=SD4_DAT3 */ = 65,
  30       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS7_=FEC_TX_EN */ = 65,
  31       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS7_="sre3_23 */ = 65,
  32       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS7_=NANDF_CS7 */ = 65,
  33       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS7_=SD3_CLK */ = 65,
  34       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RDY_INT_="CSPI2_SSX */ = 65,
  35       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RDY_INT_=FEC_TX_CLK */ = 65,
  36       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RDY_INT_="sre3_24 */ = 65,
  37       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RDY_INT_=NANDF_RDY_INT */ = 65,
  38       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_RDY_INT_=SD3_CMX */ = 65,
  39       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D1X_="CSPI2_MOSI */ = 65,
  40       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D1X_="sre3_25 */ = 65,
  41       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D1X_=NANDF_D1X */ = 65,
  42       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D1X_=PATA_DATA1X */ = 65,
  43       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D1X_=SD3_DAT7 */ = 65,
  44       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D1=_="CSPI2_SS3 */ = 65,
  45       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D14_="sre3_2X */ = 65,
  46       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D14_=NANDF_D14 */ = 65,
  47       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D14_=PATA_DATA14 */ = 65,
  48       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D14_=SD3_DATX */ = 65,
  49       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D1=_="CSPI2_SS2 */ = 65,
  50       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D13_="sre3_27 */ = 65,
  51       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D13_=NANDF_D13 */ = 65,
  52       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D13_=PATA_DATA13 */ = 65,
  53       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D13_=SD3_DATX */ = 65,
  54       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D12_="CSPI2_SS= */ = 65,
  55       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D12_="sre3_28 */ = 65,
  56       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D12_=NANDF_D12 */ = 65,
  57       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D12_=PATA_DATA12 */ = 65,
  58       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D12_=SD3_DAT4 */ = 65,
  59       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D1=_=FEC_RX_DV */ = 65,
  60       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D11_="sre3_29 */ = 65,
  61       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_D11_=NANDF_D1= */ = 65,
/*=NANDF_D1X nam, 0x53c, 0x1s5s="li52" name="L84">  84       IMXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 5" class=NANDF_CLE_=NANDF_CLE */ = 65,
/*=NANDF_D1X naIN_REGMXePIx1s5s="li52" name="L84">  84       IMXePIN_Rf=NANDF_RBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c5 0x000, 05, 5* 6" 5lass=NANDF_CLE_=PATA_RESET_B */ = 65,
/*56" class=NANDF_WP_B_="sre3_7 */ = 65,
 = 65,
  84       IMXePI0_REGMX51_PADAD_EIM_CS3" class=NANDF_RDY_INT nam, 0x538, 0x150, 2, 0,0, 0x000,),  = 65,
  84       IMXePI0=NANDF_WP_BMX51_PAD_EIM_CS1" class=NANDF_WP_B nam, 0x4f4, 0x118,52, 0x944,50), /* 65 class=NANDF_WP_B_=SD3_DATA2 */ = 65,
/* 65 class=NANDF_RBX_="CSPI2_SS= */ = 65,
/5 6" class=NANDF_RB0_="sre3_8 */ = 65,
/* 5" class=NANDF_RB0_=NANDF_RB0 */ = 65,
  84       IMXeP9_REGMX51_PA_D1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x164 0, 0x000,0), /* 65 class=NANDF_RB0_=PATA_DMARQ */ = 65,
/* 5" class=NANDF_RB0_=SD3_DATA3 */ = 65,
/* 5" class=NANDF_RB=_=CSPI_MOSI */ = 65,
/* 65 class=NANDF_RB=_="CSPI2_RDY */ = 65,
/5 6" class=NANDF_RB=_="sre3_9 */ = 65,
  84       IMXeP8_REGMX51_PA_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16000, 0x000, 0), /* 5" class=NANDF_RB1_=NANDF_RB= */ = 65,
  84       IMXeP8_RANDF_WP_CS=MX51_PAD_EIM_CS4" class=NANDF_CS= nam, 0x528, 0x140,2, 0x944,50), /* 65 class=NANDF_RB1_=PATA_IORDY */ = 65,
/5 6" class=NANDF_RB1_=SD4_CMX */ = 65,
/* 65 class=NANDF_RB2__DISP2_WAIT */ = 65,
  84       IMXeP7_REGMX51_PA_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15c50, 0x0005),  = 65,
/5 6" class=NANDF_RB2_=FEC_COL */ = 65,
/*56" class=NANDF_RB2_="sre3_10 */ = 65,
/* 5" class=NANDF_RB2_=NANDF_RB2 */ = 65,
  84       IMXeP6_REGMX51_PA_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x158 , 0x000,5),  = 65,
/* 5" class=NANDF_RB2_=USBH3_NXT */ = 65,
/* 65 class=NANDF_RB=__DISP1eWAIT */ = 65,
 = 65,
/* 65 class=NANDF_RB3_=FEC_RX_CLK */ = 65,
  84       IMXePhref=NANDF_D_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15c, 3, 0x005, 0), /*56" class=NANDF_RB3_="sre3_1= */ = 65,
/* 5" class=NANDF_RB3_=NANDF_RB3 */ = 65,
/* 5" class=NANDF_RB3_=USBH3_CLK */ = 65,
 = 65,
/* 5" class="sre=NAND_="sre=NAND */ = 65,
  84       IMXePhref=NANDF_D_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x160,, 0x000,50), /* 65 class="sre=NAND_=PATA_INTRQ */ = 65,
/*56" class=NANDF_CSX_="sre3_1X */ = 65,
/* 5" class=NANDF_CS0_=NANDF_CSX */ = 65,
/*56" class=NANDF_CS1_="sre3_17 */ = 65,
/* 5" class=NANDF_CS1_=NANDF_CS= */ = 65,
  84       IMXePhref=NANDF_DRBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c6 6, 0x9146 0), /* 6" class=NANDF_CS2_=CSPI_SCLK */ = 65,
/* 6" class=NANDF_CS2_=FEC_TX_ER */ = 65,
/*66" class=NANDF_CS2_="sre3_18 */ = 65,
/* 6" class=NANDF_CS2_=NANDF_CS2 */ = 65,
/* 6" class=NANDF_CS2_=PATA_CS_X */ = 65,
  84       IMXePhref=NANDF_DBMX51_PAD_EIM_CS1" class=NANDF_WP_B nam, 0x4f4, 0x118,6 5, 0x0006 ), /6 6" class=NANDF_CS2_=SD4_CLK */ = 65,
 = 65,
/6 6" class=NANDF_CS=_=FEC_MDC */ = 65,
 7     I8XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /*66" class=NANDF_CS3_="sre3_19 */ = 65,
 7     I8XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /* 6" class=NANDF_CS3_=NANDF_CS3 */ = 65,
 7     I8XePm, 0x53c, 0x1s5s="li52" name="L84">  84       IMXePI_REGMX51_PADD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156 1, 0x0006 0), /* 6" class=NANDF_CS3_=PATA_CS_= */ = 65,
 7     I8XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55        /*66" class=NANDF_CS3_=SD4_DATX */ = 65,
 7     I8XePIN_REa1X51_PAD_EIM_A1IMXePIN_REG nam(  55         = 65,
/* 66 class=NANDF_CS4_=FEC_TDATA= */ = 65,
/*66" class=NANDF_CS4_="sre3_2X */ = 65,
  84       IMXeP0_REGMX51_PACS=MX51_PAD_EIM_CS4" class=NANDF_CS= nam, 0x528, 0x1406,5, 0x0006 0), /* 6" class=NANDF_CS4_=NANDF_CS4 */ = 65,
/* 6" class=NANDF_CS4_=PATA_DA_X */ = 65,
/*66" class=NANDF_CS4_=SD4_DAT= */ = 65,
 7NDF_D19XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17D8_ CSI17D8D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156  3, 0x006 0), /* 6" class=NANDF_CS4_=USBH3_STP */ = 65,
 7NDF_D19XePIN_RE99XePIx1s5s="li52" name="L84">  84     CSI17D8_ f=NAND1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x160, 62, 0x000,60), /* 66 class=NANDF_CS5_=FEC_TDATA2 */ = 65,
 8     I9XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17D9_ CSI17D_D1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x166, 3, 0x006, 0), /*66" class=NANDF_CS5_="sre3_2= */ = 65,
 8     I9XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17D9_ f=NAND1RBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c6 0, 0x0006 0), /* 6" class=NANDF_CS5_=NANDF_CS5 */ = 65,
 8     I9XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17D1i_ CSI17D1iBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c6 2, 0x0006 0), /* 6" class=NANDF_CS5_=PATA_DA_= */ = 65,
/*66" class=NANDF_CS5_=SD4_DAT2 */ = 65,
 8NDF_D1aXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17D hreCSI17D hD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156, 3, 0x006 0), /* 6" class=NANDF_CS5_=USBH3_DIR */ = 65,
 9     IaXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17D hreCSI17D hD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156,5, 0x0006, 0), /*66" class=NANDF_CS6_=CSPI_SS3 */ = 65,
 9     IaXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17D14reCSI17D _D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x1662, 0x000,60), /* 66 class=NANDF_CS6_=FEC_TDATA3 */ = 65,
 9     IbGMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17D15reCSI17D _D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156, 3, 0x006, 0), /*66" class=NANDF_CS6_="sre3_22 */ = 65,
 9NDF_D1bXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17D 6reCSI17D _D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x156 0, 0x0006 0), /* 6" class=NANDF_CS6_=NANDF_CSX */ = 65,
 a     IbXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17D 7reCSI17D _D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156 1, 0x0006 0), /* 6" class=NANDF_CS6_=PATA_DA_2 */ = 65,
 a     IbXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17D18_ CSI17D18D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156, 5, 0x006, 0), /*66" class=NANDF_CS6_=SD4_DAT3 */ = 65,
 a     IcGMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17D19_ CSI17D1_D1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x166 1, 0x0006 0), /* 6" class=NANDF_CS7_=FEC_TX_EN */ = 65,
 aNDF_D1cXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17VSYNC_ CSI17VSYNCD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x166 2, 0x0006, 0), /*66" class=NANDF_CS7_="sre3_23 */ = 65,
 aNDF_D1cXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17VSYNC_ f=NAND1_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x166 0, 0x0006 0), /* 6" class=NANDF_CS7_=NANDF_CS7 */ = 65,
 b     IcXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17HSYNC_ CSI17HSYNCD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x166  3, 0x0060, 0), /6 6" class=NANDF_CS7_=SD3_CLK */ = 65,
 b     IcXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI17HSYNC_ f=NAND1_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156x000, 0),6/*66" cl6ss=NANDF_RDY_INT_="CSPI2_SSX */ = 65,
 bXeP/pinctrl/p5inctNO_MUXd="L86" clas49=NO_MUX  86   CSI17PIXCLK_ CSI17PIXCLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156x, 0x000,6/*66" cl6ss=NANDF_RDY_INT_=FEC_TX_CLK */ = 65,
 b8eP/pinctrl/p5inctNO_MUXd="L86" clas49=NO_MUX  86   CSI17MCLK_ CSI17MCLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156x 3, 0x006, 6* 6" 6lass=NANDF_RDY_INT_="sre3_24 */ = 65,
 bNDF_D1cXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI27D hreCSI27D hD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1568, 0), /* 6"6class6NANDF_RDY_INT_=NANDF_RDY_INT */ = 65,
 bNDF_D1cXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI2 = 65,
 c     IdGMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI27D hreCSI27D hD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156, 0x000, 6),  = 65,
 c     IdGMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI2/*66" class=NANDF_D1X_="sre3_25 */ = 65,
 c     IdXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI27D14reCSI27D _D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x166 0, 0x0006 0), /* 6" class=NANDF_D1X_=NANDF_D1X */ = 65,
 c     IdXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI27D15reCSI27D _D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156, 0x000, 6),  = 65,
 cNDF_D1dXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI27D 6reCSI27D _D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x156, 5, 0x006, 0), /*66" class=NANDF_D1X_=SD3_DAT7 */ = 65,
 d     IeGMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI27D 7reCSI27D _D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1562, 0x934,60), /* 66 class=NANDF_D1=_="CSPI2_SS3 */ = 65,
 d     IeXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI27D18reCSI27D 8D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156, 3, 0x006, 0), /*66" class=NANDF_D14_="sre3_2X */ = 65,
 d     IeXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI2/* 6" class=NANDF_D14_=NANDF_D14 */ = 65,
 d     IeXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI27D19reCSI27D _D1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x166, 0x000, 6),  = 65,
 d     IeXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI2/*66" class=NANDF_D14_=SD3_DATX */ = 65,
 dNDF_D1eXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI27VSYNC_ CSI27VSYNCD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x1662, 0x000,60), /* 66 class=NANDF_D1=_="CSPI2_SS2 */ = 65,
 dNDF_D1eXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI2/*66" class=NANDF_D13_="sre3_27 */ = 65,
 e     IfGMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI27HSYNC_ CSI27HSYNCD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x166 0, 0x0006 0), /* 6" class=NANDF_D13_=NANDF_D13 */ = 65,
 e     IfGMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI2 = 65,
 e     IfXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI27PIXCLK_ CSI27PIXCLKD1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x166, 5, 0x006, 0), /*66" class=NANDF_D13_=SD3_DATX */ = 65,
 e     IfXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSI2/* 66 class=NANDF_D12_="CSPI2_SS= */ = 65,
 e     IfXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   I2C1_CLK_ f=NA4D1_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x156, 3, 0x006, 0), /*66" class=NANDF_D12_="sre3_28 */ = 65,
 e     IfXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   I2C1_CLK_ I2C1_CLKD1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x156,0, 0x0006 0), /* 6" class=NANDF_D12_=NANDF_D12 */ = 65,
 eNDF_D1fXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   I2C1_DAT_ f=NA4D1_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156, 0x000, 6),  = 65,
 eNDF_D1fXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   I2C1_DAT_ I2C1_DATD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156, 5, 0x006, 0), /*66" class=NANDF_D12_=SD3_DAT4 */ = 65,
 fGMXIx20GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   AUD3_BB_TXD_ AUD3_TXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156 2, 0x96c6 0), /* 6" class=NANDF_D1=_=FEC_RX_DV */ = 65,
 fGMXIx20GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   AUD3_BB_TXD_ f=NA4D18D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156, 3, 0x006, 0), /*66" class=NANDF_D11_="sre3_29 */ = 65,
 f4MXIx20XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   AUD3_BB_RXD_ AUD3_RXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156 0, 0x0006 0), /* 6" class=NANDF_D11_=NANDF_D1= */ = 65,
 f4MXIx20XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   AUD3_BB_RXD_ f=NA4D1_D1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x166651_PAD/*6NANDF_D25anmDF_D13commen6">/* 6" class=NANDF_CLE_=NANDF_CLE */ = 65,
 f4MXIx20XePm, 0x9f4MX2PAD_EIM_A1IMXePIN_REG nam(  55   AUD3_BB_RXD_ UART3_RXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156  5, 0x006, 6* 6" 6lass=NANDF_CLE_=PATA_RESET_B */ = 65,
 f8MXIx20XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   AUD3_BB_CK_ AUD3_TXCD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x166, 3, 0x996, 0), /*66" class=NANDF_WP_B_="sre3_7 */ = 65,
 f8MXIx20XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   AUD3_BB_CK_ f=NA4D2iBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c6, 3, 0x006),  = 65,
 fcMXIx20XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   AUD3_BB_FS_ AUD3_TXFSBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c6,0, 0x0006),  = 65,
 fcMXIx20XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   AUD3_BB_FS_ f=NA4D2DD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1562, 0x944,60), /* 66 class=NANDF_WP_B_=SD3_DATA2 */ = 65,
 fcMXIx20XePm, 0x53c, 0x1s5s="li52" name="L84">  84     AUD3_BB_FS_ UART3_TXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156  5, 0x0060), /* 66 class=NANDF_RBX_="CSPI2_SS= */ = 65,
60GMXIx21GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSPI17MOSI__ECSPI17MOSID1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156c, 3, 0x964, 0), /6 6" class=NANDF_RB0_="sre3_8 */ = 65,
60GMXIx21GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSPI17MOSI__f=NA4D2hD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156 0, 0x0006 0), /* 6" class=NANDF_RB0_=NANDF_RB0 */ = 65,
60GMXIx21GMXm, 0x9bXePIx1s5s="li52" name="L84">  84     CSPI17MOSI__I2C1_SDAD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156 0, 0x00060), /* 66 class=NANDF_RB0_=PATA_DMARQ */ = 65,
604MXIx21XePm, 0x8cXePIx1s5s="li52" name="L84">  84     CSPI17MISO_ AUD4_RXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156c51_PAD/*6 0), /* 6" class=NANDF_RB0_=SD3_DATA3 */ = 65,
604MXIx21XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSPI17MISO_ ECSPI17MISOD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156c 5, 0x006 0), /* 6" class=NANDF_RB=_=CSPI_MOSI */ = 65,
604MXIx21XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSPI17MISO_ f=NA4D2RBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c62, 0x000,60), /* 66 class=NANDF_RB=_="CSPI2_RDY */ = 65,
608MXIx218ePm, 0x8cXePIx1s5s="li52" name="L84">  84     CSPI17SSi_ AUD4_TXCD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x1660, 3, 0x060, 0), /6 6" class=NANDF_RB=_="sre3_9 */ = 65,
608MXIx218ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSPI17SSi_ ECSPI17SSiD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x16600, 0x0006 0), /* 6" class=NANDF_RB1_=NANDF_RB= */ = 65,
608MXIx218ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSPI17SSi_ f=NA4D2_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x1662, 0x944,60), /* 66 class=NANDF_RB1_=PATA_IORDY */ = 65,
  84     CSPI17SSi_ AUD4_TXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156c 5, 0x0060, 0), /6 6" class=NANDF_RB1_=SD4_CMX */ = 65,
/* 66 class=NANDF_RB2__DISP2_WAIT */ = 65,
 = 65,
  84     CSPI17RDY_ AUD4_TXFSBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c64, 1, 0x96c, 0), /6 6" class=NANDF_RB2_=FEC_COL */ = 65,
/*66" class=NANDF_RB2_="sre3_10 */ = 65,
/* 6" class=NANDF_RB2_=NANDF_RB2 */ = 65,
614MXIx22XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSPI17SCLK_ ECSPI17SCLKD1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x156 , 0x000,6),  = 65,
614MXIx22XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   CSPI17SCLK_ f=NA4D2_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156 , 3, 0x06 0), /* 6" class=NANDF_RB2_=USBH3_NXT */ = 65,
614MXIx22XePm, 0x9b   Ix1s5s="li52" name="L84">  84     CSPI17SCLK_ I2C1_SCLD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156 0, 0x00060), /* 66 class=NANDF_RB=__DISP1eWAIT */ = 65,
618MXIx228ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART1_RXD_ f=NA4D28D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156, 0x000, 6),  = 65,
618MXIx228ePIN_RE9eX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART1_RXD_ UART1_RXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156, 5, 0x0060), /* 66 class=NANDF_RB3_=FEC_RX_CLK */ = 65,
61cMXIx22cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART1_TXD_ f=NA4D2_D1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x166, 3, 0x006, 0), /*66" class=NANDF_RB3_="sre3_1= */ = 65,
61cMXIx22cePm, 0x53c, 0x1s5s="li52" name="L84">  84     UART1_TXD_ PWM2 PWMOD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156 0, 0x0006 0), /* 6" class=NANDF_RB3_=NANDF_RB3 */ = 65,
61cMXIx22cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART1_TXD_ UART1_TXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156 , 1, 0x96 0), /* 6" class=NANDF_RB3_=USBH3_CLK */ = 65,
62GMXIx23GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART1_RTS_ f=NA4D3iD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x166, 0x000, 6),  = 65,
62GMXIx23GMXIN_RE9eX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART1_RTS_ UART1_RTSD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x166,0, 0x0006 0), /* 6" class="sre=NAND_="sre=NAND */ = 65,
624MXIx23XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART1_CTS_ f=NA4D3DD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156,, 0x000,60), /* 66 class="sre=NAND_=PATA_INTRQ */ = 65,
624MXIx23XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART1_CTS_ UART1_CTSD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x166,, 3, 0x06, 0), /*66" class=NANDF_CSX_="sre3_1X */ = 65,
628MXIx23XePm, 0x53c, 0x1s5s="li52" name="L84">  84     UART2_RXD__FIRI_TXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x156 0, 0x0006 0), /* 6" class=NANDF_CS0_=NANDF_CSX */ = 65,
628MXIx23XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART2_RXD_ f=NA1D2iBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c6, 0x000, 6, 0), /*66" class=NANDF_CS1_="sre3_17 */ = 65,
628MXIx23XePIN_RE9ecMX2PAD_EIM_A1IMXePIN_REG nam(  55   UART2_RXD_ UART2_RXDBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c6, 5, 0x006 0), /* 6" class=NANDF_CS1_=NANDF_CS= */ = 65,
62cMXIx23cePm, 0x53c, 0x1s5s="li52" name="L84">  84     UART2_TXD_ FIRI_RXDBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7 6, 0x9147 0), /* 7" class=NANDF_CS2_=CSPI_SCLK */ = 65,
62cMXIx23cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART2_TXD_ f=NA1D2DD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 2, 0x0007 0), /* 7" class=NANDF_CS2_=FEC_TX_ER */ = 65,
62cMXIx23cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART2_TXD_ UART2_TXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 2, 0x0007 0), /*76" class=NANDF_CS2_="sre3_18 */ = 65,
63GMXIx240MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART3_RXD_ CSI17DiBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7 0, 0x0007 0), /* 7" class=NANDF_CS2_=NANDF_CS2 */ = 65,
63GMXIx240MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART3_RXD_ f=NA1D2hD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 1, 0x0007 0), /* 7" class=NANDF_CS2_=PATA_CS_X */ = 65,
63GMXIx240MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART3_RXD_ UART1_DTRD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 5, 0x0007 ), /7 6" class=NANDF_CS2_=SD4_CLK */ = 65,
63GMXIx240MXm, 0x9f4MX4PAD_EIM_A1IMXePIN_REG nam(  55   UART3_RXD_ UART3_RXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157, 0x000, 7),  = 65,
634MXIx244MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART3_TXD_ CSI17DDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 70x000, 7)0), /7 6" class=NANDF_CS=_=FEC_MDC */ = 65,
634MXIx244MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART3_TXD_ f=NA1D2RBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7, 3, 0x007, 0), /*76" class=NANDF_CS3_="sre3_19 */ = 65,
634MXIx244MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   UART3_TXD_ UART1_DSRD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 93, 0x007,0), /* 7" class=NANDF_CS3_=NANDF_CS3 */ = 65,
634MXIx244MXm, 0x53c, 0x1s5s="li52" name="L84">  84     UART3_TXD_ UART3_TXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 1, 0x0007 0), /* 7" class=NANDF_CS3_=PATA_CS_= */ = 65,
638MXIx24XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   OWIRE_LINE_ f=NA1D2_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x167, 5, 0x007, 0), /*76" class=NANDF_CS3_=SD4_DATX */ = 65,
638MXIx24XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   OWIRE_LINE_ OWIRE_LINED1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x167,2, 0x0007),  = 65,
638MXIx24XeP6N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   OWIRE_LINE_ SPDIF_OUTD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1572, 0x000,70), /* 67 class=NANDF_CS4_=FEC_TDATA= */ = 65,
63cMXIx24cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   KEY_ROWi_ KEY_ROWiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15721, 0x0007, 0), /*76" class=NANDF_CS4_="sre3_2X */ = 65,
/* 7" class=NANDF_CS4_=NANDF_CS4 */ = 65,
644MXIx254MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   KEY_ROWi_ KEY_ROWhD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 1, 0x0007 0), /* 7" class=NANDF_CS4_=PATA_DA_X */ = 65,
648MXIx25XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   KEY_ROWi_ KEY_ROWRBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7 70x000, 7, 0), /*76" class=NANDF_CS4_=SD4_DAT= */ = 65,
64cMXIx25cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   KEY_COLi_ KEY_COLiBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7  3, 0x007 0), /* 7" class=NANDF_CS4_=USBH3_STP */ = 65,
64cMXIx25ceP7, 0x90cMXIPAD_EIM_A1IMXePIN_REG nam(  55   KEY_COLi_ PLL1_BYPBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7 93, 0x0070), /* 67 class=NANDF_CS5_=FEC_TDATA2 */ = 65,
/*76" class=NANDF_CS5_="sre3_2= */ = 65,
/* 7" class=NANDF_CS5_=NANDF_CS5 */ = 65,
654MXIx264MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   KEY_COLi_ KEY_COLhD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 2, 0x0007 0), /* 7" class=NANDF_CS5_=PATA_DA_= */ = 65,
654MXIx264MX7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   KEY_COLi_ PLL3_BYPBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7 , 0x000,7, 0), /*76" class=NANDF_CS5_=SD4_DAT2 */ = 65,
658MXIx26XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   KEY_COLi_ KEY_COLRBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7, 3, 0x007 0), /* 7" class=NANDF_CS5_=USBH3_DIR */ = 65,
65cMXIx26cePIN_RE9bXePIx1s5s="li52" name="L84">  84     KEY_COLi_ I2C2_SCLD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157,5, 0x0007, 0), /*76" class=NANDF_CS6_=CSPI_SS3 */ = 65,
65cMXIx26cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   KEY_COL4_ KEY_COL_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x1672, 0x000,70), /* 67 class=NANDF_CS6_=FEC_TDATA3 */ = 65,
65cMXIx26ceP6N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   KEY_COL4_ SPDIF_OUTDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157,70x000, 7, 0), /*76" class=NANDF_CS6_="sre3_22 */ = 65,
65cMXIx26cePm, 0x53c, 0x1s5s="li52" name="L84">  84     KEY_COL4_ UART1_RID1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 0, 0x0007 0), /* 7" class=NANDF_CS6_=NANDF_CSX */ = 65,
65cMXIx26ceP2, 0x9f0MX4PAD_EIM_A1IMXePIN_REG nam(  55   KEY_COL4_ UART3_RTSD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x167 1, 0x0007 0), /* 7" class=NANDF_CS6_=PATA_DA_2 */ = 65,
66GMXIx270ePIN_RE9bXePIx1s5s="li52" name="L84">  84     KEY_COLi_ I2C2_SDAD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157, 5, 0x007, 0), /*76" class=NANDF_CS6_=SD4_DAT3 */ = 65,
66GMXIx270ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   KEY_COL5_ KEY_COL_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 1, 0x0007 0), /* 7" class=NANDF_CS7_=FEC_TX_EN */ = 65,
66GMXIx270ePm, 0x53c, 0x1s5s="li52" name="L84">  84     KEY_COL5_ UART1_DCDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 2, 0x0007, 0), /*76" class=NANDF_CS7_="sre3_23 */ = 65,
66GMXIx270ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   KEY_COL5_ UART3_CTSD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x167 0, 0x0007 0), /* 7" class=NANDF_CS7_=NANDF_CS7 */ = 65,
678MXIx27XePm, 0x91XePIx1s5s="li52" name="L84">  84     USBH1_CLK_ CSPI7SCLKD1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x157  3, 0x0070, 0), /7 6" class=NANDF_CS7_=SD3_CLK */ = 65,
678MXIx27XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_CLK_ f=NA1D2_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 5, 0x0007/*76" cl7ss=NANDF_RDY_INT_="CSPI2_SSX */ = 65,
678MXIx27XeP5N_RE9bXeP2PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_CLK_ I2C2_SCLD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157x, 0x000,7/*76" cl7ss=NANDF_RDY_INT_=FEC_TX_CLK */ = 65,
678MXIx27XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_CLK_ USBH1_CLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157x70x000, 7, 7* 6" 7lass=NANDF_RDY_INT_="sre3_24 */ = 65,
67cMXIx27cePm, 0x91XePIx1s5s="li52" name="L84">  84     USBH1_DIR_ CSPI7MOSID1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1578, 0), /* 6"7class7NANDF_RDY_INT_=NANDF_RDY_INT */ = 65,
67cMXIx27cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DIR_ f=NA1D2_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x157 1, 0x0007),  = 65,
67cMXIx27ceP5N_RE9bXeP2PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DIR_ I2C2_SDAD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157, 0x000, 7),  = 65,
67cMXIx27cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DIR_ USBH1_DIRD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157,1, 0x0007, 0), /*76" class=NANDF_D1X_="sre3_25 */ = 65,
68GMXIx280ePm, 0x53c, 0x1s5s="li52" name="L84">  84     USBH1_STP_ CSPI7RDYBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7 0, 0x0007 0), /* 7" class=NANDF_D1X_=NANDF_D1X */ = 65,
68GMXIx280ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_STP_ f=NA1D2_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157, 0x000, 7),  = 65,
68GMXIx280eP5N_RE9f4MX6PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_STP_ UART3_RXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157, 5, 0x007, 0), /*76" class=NANDF_D1X_=SD3_DAT7 */ = 65,
68GMXIx280ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_STP_ USBH1_STPD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157,5, 0x00070), /* 67 class=NANDF_D1=_="CSPI2_SS3 */ = 65,
684MXIx28XePm, 0x918MXIPAD_EIM_A1IMXePIN_REG nam(  55   USBH1_NXT_ CSPI7MISOD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157, 3, 0x007, 0), /*76" class=NANDF_D14_="sre3_2X */ = 65,
684MXIx28XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_NXT_ f=NA1D28D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 0, 0x0007 0), /* 7" class=NANDF_D14_=NANDF_D14 */ = 65,
684MXIx28XeP5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_NXT_ UART3_TXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157, 0x000, 7),  = 65,
684MXIx28XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_NXT_ USBH1_NXTD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157,1, 0x0007, 0), /*76" class=NANDF_D14_=SD3_DATX */ = 65,
688MXIx28XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATAi_ f=NA1D1DD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1572, 0x000,70), /* 67 class=NANDF_D1=_="CSPI2_SS2 */ = 65,
688MXIx28XePm, 0x53c, 0x1s5s="li52" name="L84">  84     USBH1_DATAi_ UART2_CTSD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x167, 3, 0x007, 0), /*76" class=NANDF_D13_="sre3_27 */ = 65,
688MXIx28XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATAi_ USBH1_DATAiD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x167,0, 0x0007 0), /* 7" class=NANDF_D13_=NANDF_D13 */ = 65,
 = 65,
/*76" class=NANDF_D13_=SD3_DATX */ = 65,
/* 67 class=NANDF_D12_="CSPI2_SS= */ = 65,
69GMXIx290ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATAi_ f=NA1D1RBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7, 3, 0x007, 0), /*76" class=NANDF_D12_="sre3_28 */ = 65,
69GMXIx290ePm, 0x53c, 0x1s5s="li52" name="L84">  84     USBH1_DATA2_ UART2_TXDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157,0, 0x0007 0), /* 7" class=NANDF_D12_=NANDF_D12 */ = 65,
69GMXIx290ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATA2_ USBH1_DATAhD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157, 0x000, 7),  = 65,
694MXIx29XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATAi_ f=NA1D1_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x167, 5, 0x007, 0), /*76" class=NANDF_D12_=SD3_DAT4 */ = 65,
694MXIx29XePm, 0x9eXeP5PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATAi_ UART2_RTSD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x167 2, 0x96c7 0), /* 7" class=NANDF_D1=_=FEC_RX_DV */ = 65,
694MXIx29XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATA3_ USBH1_DATARBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7, 3, 0x007, 0), /*76" class=NANDF_D11_="sre3_29 */ = 65,
698MXIx29XePm, 0x53c, 0x1s5s="li52" name="L84">  84     USBH1_DATA4_ CSPI7SSiD1=MX51_PAD_EIM_CS1" class=NANDF_D1= nam, 0x54c, 0x167 0, 0x0007 0), /* 7" class=NANDF_D11_=NANDF_D1= */ = 65,
698MXIx29XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATA4_ f=NA1D1_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157651_PAD/*7NANDF_D25anmDF_D13commen7">/* 7" class=NANDF_CLE_=NANDF_CLE */ = 65,
698MXIx29XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATA4_ USBH1_DATA_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x167  5, 0x007, 7* 6" 7lass=NANDF_CLE_=PATA_RESET_B */ = 65,
69cMXIx29cePm, 0x92X51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATA5_ CSPI7SSDD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157, 3, 0x997, 0), /*76" class=NANDF_WP_B_="sre3_7 */ = 65,
69cMXIx29cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATA5_ f=NA1D1_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x157, 3, 0x007),  = 65,
69cMXIx29cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATA5_ USBH1_DATA_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15760, 0x0007),  = 65,
6aGMXIx2a0MXm, 0x92XePIx1s5s="li52" name="L84">  84     USBH1_DATA6_ CSPI7SSRBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7, 0x000, 70), /* 67 class=NANDF_WP_B_=SD3_DATA2 */ = 65,
6aGMXIx2a0MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATA6_ f=NA1D1_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157  5, 0x0070), /* 67 class=NANDF_RBX_="CSPI2_SS= */ = 65,
6aGMXIx2a0MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATA6_ USBH1_DATA_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x157c, 3, 0x974, 0), /7 6" class=NANDF_RB0_="sre3_8 */ = 65,
6a4MXIx2a4MXm, 0x53c, 0x1s5s="li52" name="L84">  84     USBH1_DATA7_ ECSPI17SSRBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7 0, 0x0007 0), /* 7" class=NANDF_RB0_=NANDF_RB0 */ = 65,
6a4MXIx2a4MX5N_RE93XePIx1s5s="li52" name="L84">  84     USBH1_DATA7_ ECSPI27SSRBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7 0, 0x00070), /* 67 class=NANDF_RB0_=PATA_DMARQ */ = 65,
6a4MXIx2a4MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATA7_ f=NA1D18D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157c51_PAD/*7 0), /* 7" class=NANDF_RB0_=SD3_DATA3 */ = 65,
6a4MXIx2a4MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   USBH1_DATA7_ USBH1_DATA_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157c 5, 0x007 0), /* 7" class=NANDF_RB=_=CSPI_MOSI */ = 65,
/* 67 class=NANDF_RB=_="CSPI2_RDY */ = 65,
/7 6" class=NANDF_RB=_="sre3_9 */ = 65,
/* 7" class=NANDF_RB1_=NANDF_RB= */ = 65,
6acMXIx2acePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI17ref1i_ DI17ref1hD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1570 0x000, 70), /* 67 class=NANDF_RB1_=PATA_IORDY */ = 65,
6acMXIx2aceP4N_RE97XePIx1s5s="li52" name="L84">  84     DI17ref1i_ f=NA3_iD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157c 5, 0x0070, 0), /7 6" class=NANDF_RB1_=SD4_CMX */ = 65,
6bGMXIx2b0MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI17ref1i_ DI17ref1RBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c75, 0x9a8,70), /* 67 class=NANDF_RB2__DISP2_WAIT */ = 65,
6bGMXIx2b0MX4N_RE97XePIx1s5s="li52" name="L84">  84     DI17ref1i_ f=NA3_hD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15750, 0x0007),  = 65,
6b4MXIx2b4MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI17Di_CS_ DI17Di_CSD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15750, 0x0007c, 0), /7 6" class=NANDF_RB2_=FEC_COL */ = 65,
6b4MXIx2b4MX4N_RE980ePmPAD_EIM_A1IMXePIN_REG nam(  55   DI17Di_CS_ f=NA3_RBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c7551_PAD/*7, 0), /*76" class=NANDF_RB2_="sre3_10 */ = 65,
6b8MXIx2bXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI17D1_CS_ DI17D1_CSBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c75 5, 0x007 0), /* 7" class=NANDF_RB2_=NANDF_RB2 */ = 65,
6b8MXIx2bXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI17D1_CS_ DISP17ref1_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x167 , 0x000,7),  = 65,
6b8MXIx2bXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI17D1_CS_ DISP17ref_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 , 3, 0x07 0), /* 7" class=NANDF_RB2_=USBH3_NXT */ = 65,
6b8MXIx2bXeP4N_RE98XePIx1s5s="li52" name="L84">  84     DI17D1_CS_ f=NA3__D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x167 0, 0x00070), /* 67 class=NANDF_RB=__DISP1eWAIT */ = 65,
6bcMXIx2bceP2, 0x9aXePIx1s5s="li52" name="L84">  84     DISPB2_SER1DIN_ DISP17ref1D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x167  0x000, 7),  = 65,
6bcMXIx2bcePIN_RE9cX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISPB2_SER1DIN_ DISPB2_SER1DIND1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x167  5, 0x0070), /* 67 class=NANDF_RB3_=FEC_RX_CLK */ = 65,
6bcMXIx2bceP4N_RE98XePIx1s5s="li52" name="L84">  84     DISPB2_SER1DIN_ f=NA3__D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157, 3, 0x007, 0), /*76" class=NANDF_RB3_="sre3_1= */ = 65,
6cGMXIx2c0ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISPB2_SER1DIO_ DISP17ref_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x157 0, 0x0007 0), /* 7" class=NANDF_RB3_=NANDF_RB3 */ = 65,
6cGMXIx2c0ePIN_RE9cX51Ix1s5s="li52" name="L84">  84     DISPB2_SER1DIO_ DISPB2_SER1DIOD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157 , 1, 0x97 0), /* 7" class=NANDF_RB3_=USBH3_CLK */ = 65,
6cGMXIx2c0eP4N_RE98XePIx1s5s="li52" name="L84">  84     DISPB2_SER1DIO_ f=NA3__D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x157 51_PAD/*7),  = 65,
6c4MXIx2c4MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISPB2_SER1CLK_ DISP17ref1_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157,0, 0x0007 0), /* 7" class="sre=NAND_="sre=NAND */ = 65,
6c4MXIx2c4MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISPB2_SER1CLK_ DISP17ref_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157,, 0x000,70), /* 67 class="sre=NAND_=PATA_INTRQ */ = 65,
6c4MXIx2c4MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISPB2_SER1CLK_ DISPB2_SER1CLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157,, 3, 0x07, 0), /*76" class=NANDF_CSX_="sre3_1X */ = 65,
6c4MXIx2c4MX4N_RE990ePmPAD_EIM_A1IMXePIN_REG nam(  55   DISPB2_SER1CLK_ f=NA3__D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157,0, 0x0007 0), /* 7" class=NANDF_CS0_=NANDF_CSX */ = 65,
6c8MXIx2cXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISPB2_SER1RS_ DISP17EXT1CLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x157, 0x000, 7, 0), /*76" class=NANDF_CS1_="sre3_17 */ = 65,
6c8MXIx2cXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISPB2_SER1RS_ DISP17ref1_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x157  5, 0x007 0), /* 7" class=NANDF_CS1_=NANDF_CS= */ = 65,
6c8MXIx2cXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISPB2_SER1RS_ DISP17ref8D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158 6, 0x9148 0), /* 8" class=NANDF_CS2_=CSPI_SCLK */ = 65,
6c8MXIx2cXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISPB2_SER1RS_ DISPB2_SER1RSD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158 1, 0x9148 0), /* 8" class=NANDF_CS2_=FEC_TX_ER */ = 65,
6c8MXIx2cXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISPB2_SER1RS_ DISPB2_SER1RSD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158 2, 0x9148 0), /*86" class=NANDF_CS2_="sre3_18 */ = 65,
6c8MXIx2cXeP4N_RE99X51Ix1s5s="li52" name="L84">  84     DISPB2_SER1RS_ f=NA3_8D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158 3, 0x9148 , /* 8" class=NANDF_CS2_=NANDF_CS2 */ = 65,
6ccMXIx2ccePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi_ DISP17DATiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158 4, 0x9148 0), /* 8" class=NANDF_CS2_=PATA_CS_X */ = 65,
/8 6" class=NANDF_CS2_=SD4_CLK */ = 65,
6d4MXIx2d4MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi_ DISP17DAThD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158, 0x000, 8),  = 65,
6d8MXIx2dXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi_ DISP17DATRBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c8 70x000, 8)0), /8 6" class=NANDF_CS=_=FEC_MDC */ = 65,
6dcMXIx2dcePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT4_ DISP17DAT_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x168, 3, 0x008, 0), /*86" class=NANDF_CS3_="sre3_19 */ = 65,
6eGMXIx2e0MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT5_ DISP17DAT_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158 93, 0x008,0), /* 8" class=NANDF_CS3_=NANDF_CS3 */ = 65,
6e4MXIx2e4MX7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT6__BOOT USB_SRCD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158 1, 0x0008 0), /* 8" class=NANDF_CS3_=PATA_CS_= */ = 65,
6e4MXIx2e4MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT6_ DISP17DAT_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x158, 5, 0x008, 0), /*86" class=NANDF_CS3_=SD4_DATX */ = 65,
6e8MXIx2eXeP7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT7__BOOT EEPROM_CFGD1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x158,2, 0x9148),  = 65,
6e8MXIx2eXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT7_ DISP17DAT_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1582, 0x000,80), /* 68 class=NANDF_CS4_=FEC_TDATA= */ = 65,
6ecMXIx2eceP7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT8__BOOT SRCiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15821, 0x0008, 0), /*86" class=NANDF_CS4_="sre3_2X */ = 65,
6ecMXIx2ecePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT8_ DISP17DAT8D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158,5, 0x0008 0), /* 8" class=NANDF_CS4_=NANDF_CS4 */ = 65,
6fGMXIx2fGMX7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT9__BOOT SRC1D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x168 1, 0x0008 0), /* 8" class=NANDF_CS4_=PATA_DA_X */ = 65,
6fGMXIx2fGMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT9_ DISP17DAT9D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x168 70x000, 8, 0), /*86" class=NANDF_CS4_=SD4_DAT= */ = 65,
6f4MXIx2f4MX7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT10__BOOT SPARE_SIZED1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x168  3, 0x008 0), /* 8" class=NANDF_CS4_=USBH3_STP */ = 65,
6f4MXIx2f4MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATii_ DISP17DAT1iD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158293, 0x0080), /* 68 class=NANDF_CS5_=FEC_TDATA2 */ = 65,
/*86" class=NANDF_CS5_="sre3_2= */ = 65,
/* 8" class=NANDF_CS5_=NANDF_CS5 */ = 65,
6fcMXIx2fceP7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT1i_ BOOT MLC_SELD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158 2, 0x0008 0), /* 8" class=NANDF_CS5_=PATA_DA_= */ = 65,
6fcMXIx2fcePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATii_ DISP17DAT1hD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158 , 0x000,8, 0), /*86" class=NANDF_CS5_=SD4_DAT2 */ = 65,
7MX51_x30GMX7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT1i_ BOOT MEM_CTLiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158, 3, 0x008 0), /* 8" class=NANDF_CS5_=USBH3_DIR */ = 65,
7MX51_x30GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATii_ DISP17DAT1RBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c8,5, 0x0008, 0), /*86" class=NANDF_CS6_=CSPI_SS3 */ = 65,
7M451_x304MX7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT14_ BOOT MEM_CTL1D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x168 1, 0x000820), /* 82 class=NANDF_CS4_=PATA_DA_X */ = 65,
7M451_x304MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi4_ DISP17DAT1_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x168270x000, 82 0), /*82" class=NANDF_CS4_=SD4_DAT= */ = 65,
7M851_x30XeP7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT15_ BOOT BUS_WIDTHD1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x1682 3, 0x00820), /* 82 class=NANDF_CS4_=USBH3_STP */ = 65,
7M851_x30XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi5_ DISP17DAT1_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158293, 0x0082),  = 65,
7Mc51_x30ceP7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT16__BOOT PAGE_SIZEiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1583 3, 0x0083 0), /*83" class=NANDF_CS5_="sre3_2= */ = 65,
7Mc51_x30cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi6_ DISP17DAT1_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x15830, 0x000830), /* 83 class=NANDF_CS5_=NANDF_CS5 */ = 65,
71X51_x31GMX7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT17__BOOT PAGE_SIZE1D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16832, 0x000830), /* 83 class=NANDF_CS5_=PATA_DA_= */ = 65,
71X51_x31GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi7_ DISP17DAT1_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1583, 0x000,83 0), /*83" class=NANDF_CS5_=SD4_DAT2 */ = 65,
71451_x314MX7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT18__BOOT WEIM_MUXEDiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1583 3, 0x00830), /* 83 class=NANDF_CS5_=USBH3_DIR */ = 65,
71451_x314MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi8_ DISP17DAT18D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15835, 0x00083 0), /*83" class=NANDF_CS6_=CSPI_SS3 */ = 65,
71451_x314MX5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi8_ DISP27ref11D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16831, 0x000830), /* 83 class=NANDF_CS4_=PATA_DA_X */ = 65,
71451_x314MX4N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi8_ DISP27ref_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158370x000, 83 0), /*83" class=NANDF_CS4_=SD4_DAT= */ = 65,
71851_x31XeP7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT19__BOOT WEIM_MUXED1D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x1683 3, 0x00830), /* 83 class=NANDF_CS4_=USBH3_STP */ = 65,
71851_x31XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi9_ DISP17DAT19D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x168393, 0x0083),  = 65,
71851_x31XeP5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi9_ DISP27ref1hD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1584 3, 0x0084 0), /*84" class=NANDF_CS5_="sre3_2= */ = 65,
71851_x31XeP4N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi9_ DISP27ref_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x15840, 0x000840), /* 84 class=NANDF_CS5_=NANDF_CS5 */ = 65,
71c51_x31ceP7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT20_ BOOT MEM_TYPEiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15842, 0x000840), /* 84 class=NANDF_CS5_=PATA_DA_= */ = 65,
71c51_x31cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATii_ DISP17DAT2iD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1584, 0x000,84 0), /*84" class=NANDF_CS5_=SD4_DAT2 */ = 65,
71c51_x31ceP5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATii_ DISP27ref1RBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c84 3, 0x00840), /* 84 class=NANDF_CS5_=USBH3_DIR */ = 65,
71c51_x31ceP4N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATii_ DISP27ref_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15845, 0x00084 0), /*846" class=NANDF_CS2_=SD4_CLK */ = 65,
/* 84 class=NANDF_CS4_=PATA_DA_X */ = 65,
/*84" class=NANDF_CS4_=SD4_DAT= */ = 65,
/* 84 class=NANDF_CS4_=USBH3_STP */ = 65,
 = 65,
72451_x324MX7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT22_ BOOT LPB_FREQiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1585 3, 0x0085 0), /*85" class=NANDF_CS5_="sre3_2= */ = 65,
72451_x324MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATii_ DISP17DAThhD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15850, 0x000850), /* 85 class=NANDF_CS5_=NANDF_CS5 */ = 65,
72451_x324MX6N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATii_ DISP27Di_CSD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15852, 0x000850), /* 85 class=NANDF_CS5_=PATA_DA_= */ = 65,
72451_x324MX5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATii_ DISP27DAT1_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x1585, 0x000,85 0), /*85" class=NANDF_CS5_=SD4_DAT2 */ = 65,
72851_x32XeP7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DAT23_ BOOT LPB_FREQ1D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x1685 3, 0x00850), /* 85 class=NANDF_CS5_=USBH3_DIR */ = 65,
72851_x32XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATii_ DISP17DAT2RBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c855, 0x00085 0), /*856" class=NANDF_CS2_=SD4_CLK */ = 65,
72851_x32XeP6N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi3_ DISP27D1_CSBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c851, 0x000850), /* 85 class=NANDF_CS4_=PATA_DA_X */ = 65,
72851_x32XeP5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi3_ DISP27DAT1_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158570x000, 85 0), /*85" class=NANDF_CS4_=SD4_DAT= */ = 65,
72851_x32XeP4N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP17DATi3_ DISP27SER1CSBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c85 3, 0x00850), /* 85class=NANDF_RB1_=PATA_IORDY */ = 65,
72c51_x32cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI17refi_ DI17refRBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c8593, 0x0085),  = 65,
73451_x33GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI17ref2_ DI17refhD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1586 3, 0x0086 0), /*86" class=NANDF_CS5_="sre3_2= */ = 65,
74X51_x33XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI_GPi_ DISP17SER1CLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15860, 0x000860), /* 86 class=NANDF_CS5_=NANDF_CS5 */ = 65,
74X51_x33XeP2, 0x9aXePIx1s5s="li52" name="L84">  84     DI_GPi_ DISP2_WAITD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15862, 0x000860), /* 86 class=NANDF_CS5_=PATA_DA_= */ = 65,
74451_x33cePIN_RE9a0ePmPAD_EIM_A1IMXePIN_REG nam(  55   DI_GPi_ CSI17DATA_END1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x1686, 0x000,86 0), /*86" class=NANDF_CS5_=SD4_DAT2 */ = 65,
74451_x33cePIN_RE9cX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI_GP3_ DISP17SER1DIOD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1586 3, 0x00860), /* 86 class=NANDF_CS5_=USBH3_DIR */ = 65,
74451_x33cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI_GP3_ FEC_TX_ERD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15865, 0x00086 0), /*866" class=NANDF_CS2_=SD4_CLK */ = 65,
74851_x34X51IN_RE99XePIx1s5s="li52" name="L84">  84     DI27refi_ CSI27DATA_END1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16861, 0x000860), /* 86 class=NANDF_CS4_=PATA_DA_X */ = 65,
74851_x34X51IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI27refi_ DI27refiD1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x168670x000, 86 0), /*86" class=NANDF_CS4_=SD4_DAT= */ = 65,
74851_x34X512, 0x950ePmPAD_EIM_A1IMXePIN_REG nam(  55   DI27refi_ FEC_CRSD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1586 3, 0x00860), /* 86class=NANDF_RB1_=PATA_IORDY */ = 65,
74c51_x344MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI27ref2_ DI27refhD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158693, 0x0086),  = 65,
74c51_x344MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI27ref2_ FEC_MDCD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1587 3, 0x0087 0), /*87" class=NANDF_CS5_="sre3_2= */ = 65,
75X51_x34XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI27refi_ DI27refRBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c870, 0x000870), /* 87 class=NANDF_CS5_=NANDF_CS5 */ = 65,
75X51_x34XeP2, 0x95X51Ix1s5s="li52" name="L84">  84     DI27refi_ FEC_MDIOD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15872, 0x000870), /* 87 class=NANDF_CS5_=PATA_DA_= */ = 65,
75451_x34cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI2 DISP1CLK_ DI2 DISP1CLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1587, 0x000,87 0), /*87" class=NANDF_CS5_=SD4_DAT2 */ = 65,
75451_x34ceP2, 0x95XePIx1s5s="li52" name="L84">  84     DI27DISP1CLK_ FEC_RDATA1D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x1687 3, 0x00870), /* 87 class=NANDF_CS5_=USBH3_DIR */ = 65,
75851_x35GMX4N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI_GPi_ DI27ref1_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15875, 0x00087 0), /*876" class=NANDF_CS2_=SD4_CLK */ = 65,
75851_x35GMXIN_RE9cX51mPAD_EIM_A1IMXePIN_REG nam(  55   DI_GP4_ DISP17SER1DIND1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16871, 0x000870), /* 87 class=NANDF_CS4_=PATA_DA_X */ = 65,
75851_x35GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DI_GP4_ DISP27ref1D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x168770x000, 87 0), /*87" class=NANDF_CS4_=SD4_DAT= */ = 65,
75851_x35GMX2, 0x96X51mPAD_EIM_A1IMXePIN_REG nam(  55   DI_GP4_ FEC_RDATAhD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1587 3, 0x00870), /* 87 class=NANDF_CS4_=USBH3_STP */ = 65,
75c51_x354MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DATi_ DISP27DATiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158793, 0x0087),  = 65,
75c51_x354MX2, 0x96X51Ix1s5s="li52" name="L84">  84     DISP27DATi_ FEC_RDATARBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c88 3, 0x0088 0), /*88" class=NANDF_CS5_="sre3_2= */ = 65,
75c51_x354MX4N_RE9cXePIx1s5s="li52" name="L84">  84     DISP27DATi_ KEY_COL_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x15880, 0x000880), /* 88 class=NANDF_CS5_=NANDF_CS5 */ = 65,
75c51_x354MX5N_RE9f4MX8x1s5s="li52" name="L84">  84     DISP27DATi_ UART3_RXDD1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x15882, 0x000880), /* 88 class=NANDF_CS5_=PATA_DA_= */ = 65,
75c51_x354MXIN_RE9fXePIx1s5s="li52" name="L84">  84     DISP27DATi_ USBH31CLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1588, 0x000,88 0), /*88" class=NANDF_CS5_=SD4_DAT2 */ = 65,
76X51_x35XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DATi_ DISP27DAT1D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1588 3, 0x00880), /* 88 class=NANDF_CS5_=USBH3_DIR */ = 65,
76X51_x35XeP2, 0x97X51mPAD_EIM_A1IMXePIN_REG nam(  55   DISP27DATi_ FEC_RX_ERD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15885, 0x00088 0), /*886" class=NANDF_CS2_=SD4_CLK */ = 65,
76X51_x35XeP4N_RE9cXePIx1s5s="li52" name="L84">  84     DISP27DATi_ KEY_COL_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15881, 0x000880), /* 88 class=NANDF_CS4_=PATA_DA_X */ = 65,
76X51_x35XeP5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DATi_ UART3_TXDD1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x158870x000, 88 0), /*88" class=NANDF_CS4_=SD4_DAT= */ = 65,
76X51_x35XePIN_REa1XePIx1s5s="li52" name="L84">  84     DISP27DATi_ USBH31DIRD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1588 3, 0x00880), /* 88 class=NANDF_CS4_=USBH3_STP */ = 65,
76451_x35cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DATi_ DISP27DAThD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158893, 0x0088),  = 65,
76851_x36GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DATi_ DISP27DATRBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c89 3, 0x0089 0), /*89" class=NANDF_CS5_="sre3_2= */ = 65,
76c51_x364MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT4_ DISP27DATiD1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16890, 0x000890), /* 89 class=NANDF_CS5_=NANDF_CS5 */ = 65,
77X51_x36XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT5_ DISP27DAT_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15892, 0x000890), /* 89 class=NANDF_CS5_=PATA_DA_= */ = 65,
77451_x36cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT6_ DISP27DAT_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x1589, 0x000,89 0), /*89" class=NANDF_CS5_=SD4_DAT2 */ = 65,
77451_x36cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT6_ FEC_TDATA1D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x1689 3, 0x00890), /* 89 class=NANDF_CS5_=USBH3_DIR */ = 65,
77451_x36ceP5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT6_ f=NA1_19D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16895, 0x00089 0), /*896" class=NANDF_CS2_=SD4_CLK */ = 65,
77451_x36ceP4N_RE9dX51mPAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT6_ KEY_ROWiD1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16891, 0x000890), /* 89 class=NANDF_CS4_=PATA_DA_X */ = 65,
77451_x36cePIN_REa2X51Ix1s5s="li52" name="L84">  84     DISP27DAT6_ USBH31STPD1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x168970x000, 8 0), /* 8" class=NANDF_CS0_=NANDF_CSX */ = 65,
77851_x37GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT7_ DISP27DAT_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158, 0x000, 8, 0), /*86" class=NANDF_CS1_="sre3_17 */ = 65,
77851_x37GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT7_ FEC_TDATAhD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x158  5, 0x008 0), /* 8" class=NANDF_CS1_=NANDF_CS= */ = 65,
77851_x37GMX5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT7_ f=NA1_29D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x169 6, 0x9149 0), /* 9" class=NANDF_CS2_=CSPI_SCLK */ = 65,
77851_x37GMX4N_RE9dX51Ix1s5s="li52" name="L84">  84     DISP27DAT7_ KEY_ROW_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159 1, 0x9149 0), /* 9" class=NANDF_CS2_=FEC_TX_ER */ = 65,
77851_x37GMXIN_REa2X51mPAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT7_ USBH31NXTD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159 2, 0x9149 0), /*96" class=NANDF_CS2_="sre3_18 */ = 65,
77c51_x374MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT8_ DISP27DAT8D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159 3, 0x9149 , /* 9" class=NANDF_CS2_=NANDF_CS2 */ = 65,
77c51_x374MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT8_ FEC_TDATARBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c9 4, 0x9149 0), /* 9" class=NANDF_CS2_=PATA_CS_X */ = 65,
77c51_x374MX5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT8_ f=NA1_3iD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159 5, 0x0009 ), /9 6" class=NANDF_CS2_=SD4_CLK */ = 65,
77c51_x374MX4N_RE9dXePIx1s5s="li52" name="L84">  84     DISP27DAT8_ KEY_ROW_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x159, 0x000, 9),  = 65,
77c51_x374MXIN_RE9fXePIx1s5s="li52" name="L84">  84     DISP27DAT8_ USBH31DATAiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159 70x000, 9)0), /9 6" class=NANDF_CS=_=FEC_MDC */ = 65,
78X51_x37XeP4N_RE8fX51Ix1s5s="li52" name="L84">  84     DISP27DAT9__AUD6_RXCD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159, 3, 0x009, 0), /*96" class=NANDF_CS3_="sre3_19 */ = 65,
78X51_x37XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT9_ DISP27DAT9D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x169 93, 0x009,0), /* 9" class=NANDF_CS3_=NANDF_CS3 */ = 65,
78X51_x37XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT9_ FEC_TX_END1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x169 1, 0x0009 0), /* 9" class=NANDF_CS3_=PATA_CS_= */ = 65,
78X51_x37XeP5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT9_ f=NA1_31D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x169, 5, 0x009, 0), /*96" class=NANDF_CS3_=SD4_DATX */ = 65,
78X51_x37XePIN_REa0X51mPAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT9_ USBH31DATA1D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x169,2, 0x9149),  = 65,
78451_x37cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT1i_ DISP27DAT1iD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1592, 0x000,90), /* 69 class=NANDF_CS4_=FEC_TDATA= */ = 65,
78451_x37ceP5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DATi0_ DISP27SER1CSBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c921, 0x0009, 0), /*96" class=NANDF_CS4_="sre3_2X */ = 65,
78451_x37ceP2, 0x94XePIx1s5s="li52" name="L84">  84     DISP27DATii_ FEC_COLD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159,5, 0x0009 0), /* 9" class=NANDF_CS4_=NANDF_CS4 */ = 65,
78451_x37ceP4N_RE9dXePIx1s5s="li52" name="L84">  84     DISP27DATii_ KEY_ROW_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159 1, 0x0009 0), /* 9" class=NANDF_CS4_=PATA_DA_X */ = 65,
78451_x37cePIN_REa0X51Ix1s5s="li52" name="L84">  84     DISP27DAT10_ USBH31DATAhD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159 70x000, 9, 0), /*96" class=NANDF_CS4_=SD4_DAT= */ = 65,
78851_x380eP4N_RE8fX51mPAD_EIM_A1IMXePIN_REG nam(  55   DISP27DATi1__AUD6_TXDD1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x159  3, 0x009 0), /* 9" class=NANDF_CS4_=USBH3_STP */ = 65,
78851_x380ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT1i_ DISP27DAT11D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x169,93, 0x0090), /* 69 class=NANDF_CS5_=FEC_TDATA2 */ = 65,
78851_x380eP2, 0x96XePIx1s5s="li52" name="L84">  84     DISP27DAT1i_ FEC_RX_CLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159, 3, 0x009, 0), /*96" class=NANDF_CS5_="sre3_2= */ = 65,
78851_x380eP7N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT1i_ f=NA1_1iD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159 0, 0x0009 0), /* 9" class=NANDF_CS5_=NANDF_CS5 */ = 65,
78851_x380ePIN_REa0XePIx1s5s="li52" name="L84">  84     DISP27DAT1i_ USBH31DATARBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c9 2, 0x0009 0), /* 9" class=NANDF_CS5_=PATA_DA_= */ = 65,
78c51_x384MX4N_RE8eXePIx1s5s="li52" name="L84">  84     DISP27DATi2__AUD6_RXDD1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x159 , 0x000,9, 0), /*96" class=NANDF_CS5_=SD4_DAT2 */ = 65,
78c51_x384MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT1i_ DISP27DAT1hD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159, 3, 0x009 0), /* 9" class=NANDF_CS5_=USBH3_DIR */ = 65,
78c51_x384MX2, 0x96XePIx1s5s="li52" name="L84">  84     DISP27DATi2__FEC_RX_DVD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159,5, 0x0009, 0), /*96" class=NANDF_CS6_=CSPI_SS3 */ = 65,
78c51_x384MXIN_REa0XePIx1s5s="li52" name="L84">  84     DISP27DATi2__USBH31DATAiD1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x169 1, 0x000920), /* 92 class=NANDF_CS4_=PATA_DA_X */ = 65,
79X51_x38XeP4N_RE8fXePIx1s5s="li52" name="L84">  84     DISP27DATi3__AUD6_TXCD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159270x000, 92 0), /*92" class=NANDF_CS4_=SD4_DAT= */ = 65,
79X51_x38XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT13_ DISP27DAT1RBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c9  3, 0x00920), /* 92 class=NANDF_CS4_=USBH3_STP */ = 65,
79X51_x38XeP2, 0x97X51Ix1s5s="li52" name="L84">  84     DISP27DAT13_ FEC_TX_CLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159,93, 0x0092),  = 65,
79X51_x38XePIN_REa1X51mPAD_EIM_A1IMXePIN_REG nam(  55   DISP27DATi3__USBH31DATA_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1593 3, 0x0093 0), /*93" class=NANDF_CS5_="sre3_2= */ = 65,
79451_x38ceP4N_RE90X51mPAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT14__AUD6_TXFSBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c930, 0x000930), /* 93 class=NANDF_CS5_=NANDF_CS5 */ = 65,
79451_x38cePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT14_ DISP27DAT1_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16932, 0x000930), /* 93 class=NANDF_CS5_=PATA_DA_= */ = 65,
79451_x38ceP2, 0x95XePIx1s5s="li52" name="L84">  84     DISP27DAT14_ FEC_RDATAiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1593, 0x000,93 0), /*93" class=NANDF_CS5_=SD4_DAT2 */ = 65,
79451_x38cePIN_REa1X51Ix1s5s="li52" name="L84">  84     DISP27DAT14__USBH31DATA_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x1593 3, 0x00930), /* 93 class=NANDF_CS5_=USBH3_DIR */ = 65,
79851_x390eP4N_RE8fXePIx1s5s="li52" name="L84">  84     DISP27DAT15__AUD6_RXFSBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c935, 0x00093 0), /*93" class=NANDF_CS6_=CSPI_SS3 */ = 65,
79851_x390eP5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DATi5_ DISP17SER1CSBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c931, 0x000930), /* 93 class=NANDF_CS4_=PATA_DA_X */ = 65,
79851_x390ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT15_ DISP27DAT1_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159370x000, 93 0), /*93" class=NANDF_CS4_=SD4_DAT= */ = 65,
79851_x390ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   DISP27DAT15_ FEC_TDATAiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1593 3, 0x00930), /* 93 class=NANDF_CS4_=USBH3_STP */ = 65,
79851_x390ePIN_REa1XePIx1s5s="li52" name="L84">  84     DISP27DAT15__USBH31DATA_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159393, 0x0093),  = 65,
79c51_x394511N_RE8eX51mPAD_EIM_A1IMXePIN_REG nam(  55   SD1_CMD__AUD5_RXFSBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c94 3, 0x0094 0), /*94" class=NANDF_CS5_="sre3_2= */ = 65,
79c51_x394512, 0x91XeP2PAD_EIM_A1IMXePIN_REG nam(  55   SD1_CMD__CSPI_MOSIBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c940, 0x000940), /* 94 class=NANDF_CS5_=NANDF_CS5 */ = 65,
79c51_x39451IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD1_CMD__SD1_CMDBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c942, 0x000940), /* 94 class=NANDF_CS5_=PATA_DA_= */ = 65,
7aX51_x398511N_RE8dXePIx1s5s="li52" name="L84">  84     SD1_CLK__AUD5_RXCD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1594, 0x000,94 0), /*94" class=NANDF_CS5_=SD4_DAT2 */ = 65,
7aX51_x398512, 0x914eP2PAD_EIM_A1IMXePIN_REG nam(  55   SD1_CLK__CSPI_SCLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1594 3, 0x00940), /* 94 class=NANDF_CS5_=USBH3_DIR */ = 65,
7aX51_x39851IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD1_CLK__SD1_CLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15945, 0x00094 0), /*946" class=NANDF_CS2_=SD4_CLK */ = 65,
7a451_x39XePIN_RE8d8eP2PAD_EIM_A1IMXePIN_REG nam(  55   SD1_DATAi__AUD5_TXDD1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x15941, 0x000940), /* 94 class=NANDF_CS4_=PATA_DA_X */ = 65,
7a451_x39XeP2, 0x91XePIx1s5s="li52" name="L84">  84     SD1_DATAi__CSPI_MISOD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159470x000, 94 0), /*94" class=NANDF_CS4_=SD4_DAT= */ = 65,
7a451_x39XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD1_DATAi__SD1_DATAiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1594 3, 0x00940), /* 94 class=NANDF_CS4_=USBH3_STP */ = 65,
01XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DAi_ EIM_DAiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159493, 0x0094),  = 65,
020ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DA1_ EIM_DA1D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x1695 3, 0x0095 0), /*95" class=NANDF_CS5_="sre3_2= */ = 65,
02451IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DAi_ EIM_DAhD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15950, 0x000950), /* 95 class=NANDF_CS5_=NANDF_CS5 */ = 65,
02851IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DAi_ EIM_DARBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c952, 0x000950), /* 95 class=NANDF_CS5_=PATA_DA_= */ = 65,
7a851_x3a0ePmN_RE8d4eP2PAD_EIM_A1IMXePIN_REG nam(  55   SD1_DATA1__AUD5_RXDD1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x1595, 0x000,95 0), /*95" class=NANDF_CS5_=SD4_DAT2 */ = 65,
7a851_x3a0ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD1_DATA1__SD1_DATA1D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x1695 3, 0x00950), /* 95 class=NANDF_CS5_=USBH3_DIR */ = 65,
02XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DA4_ EIM_DA_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16955, 0x00095 0), /*956" class=NANDF_CS2_=SD4_CLK */ = 65,
03GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DAi_ EIM_DA_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15951, 0x000950), /* 95 class=NANDF_CS4_=PATA_DA_X */ = 65,
03451IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DA6_ EIM_DA_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x159570x000, 95 0), /*95" class=NANDF_CS4_=SD4_DAT= */ = 65,
03851IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DA7_ EIM_DA_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1595 3, 0x00950), /* 95class=NANDF_RB1_=PATA_IORDY */ = 65,
7ac51_x3a4511N_RE8e4eP2PAD_EIM_A1IMXePIN_REG nam(  55   SD1_DATA2__AUD5_TXCD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159593, 0x0095),  = 65,
7ac51_x3a451IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD1_DATA2__SD1_DATAhD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1596 3, 0x0096 0), /*96" class=NANDF_CS5_="sre3_2= */ = 65,
044MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DA1i_ EIM_DA1iD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15960, 0x000960), /* 96 class=NANDF_CS5_=NANDF_CS5 */ = 65,
04XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DA11_ EIM_DA11D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16962, 0x000960), /* 96 class=NANDF_CS5_=PATA_DA_= */ = 65,
03XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DA8_ EIM_DA8D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1596, 0x000,96 0), /*96" class=NANDF_CS5_=SD4_DAT2 */ = 65,
04GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DA9_ EIM_DA9D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x1696 3, 0x00960), /* 96 class=NANDF_CS5_=USBH3_DIR */ = 65,
7bX51_x3a8511N_RE8e8eP2PAD_EIM_A1IMXePIN_REG nam(  55   SD1_DATA3__AUD5_TXFSBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c965, 0x00096 0), /*966" class=NANDF_CS2_=SD4_CLK */ = 65,
7bX51_x3a8512, 0x92X51mPAD_EIM_A1IMXePIN_REG nam(  55   SD1_DATA3__CSPI_SS1D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16961, 0x000960), /* 96 class=NANDF_CS4_=PATA_DA_X */ = 65,
7bX51_x3a851IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD1_DATA3__SD1_DATARBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c9670x000, 96 0), /*96" class=NANDF_CS4_=SD4_DAT= */ = 65,
7b451_x3aXeP2, 0x92451IPAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_i__CSPI_SShD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1596 3, 0x00960), /* 96class=NANDF_RB1_=PATA_IORDY */ = 65,
7b451_x3aXeP1N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_i__f=NA1_iD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159693, 0x0096),  = 65,
7b451_x3aXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_i__SD1_CDD1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x1597 3, 0x0097 0), /*97" class=NANDF_CS5_="sre3_2= */ = 65,
7b851_x3b0eP2, 0x91XeP2PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_1__CSPI_MISOD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15970, 0x000970), /* 97 class=NANDF_CS5_=NANDF_CS5 */ = 65,
7b851_x3b0eP1N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_i_ f=NA1_1D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15972, 0x000970), /* 97 class=NANDF_CS5_=PATA_DA_= */ = 65,
7b851_x3b0ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_1__SD1_WPD1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x1697, 0x000,97 0), /*97" class=NANDF_CS5_=SD4_DAT2 */ = 65,
04XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DA1i_ EIM_DA1hD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1597 3, 0x00970), /* 97 class=NANDF_CS5_=USBH3_DIR */ = 65,
05GMXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DA1i_ EIM_DA1RBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c975, 0x00097 0), /*976" class=NANDF_CS2_=SD4_CLK */ = 65,
054MXIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DA14_ EIM_DA1_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16971, 0x000970), /* 97 class=NANDF_CS4_=PATA_DA_X */ = 65,
05XePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   EIM_DA1i_ EIM_DA1_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159770x000, 97 0), /*97" class=NANDF_CS4_=SD4_DAT= */ = 65,
7bc51_x3b4512, 0x91XeP3PAD_EIM_A1IMXePIN_REG nam(  55   SD2_CMD__CSPI_MOSIBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c97 3, 0x00970), /* 97class=NANDF_RB1_=PATA_IORDY */ = 65,
7bc51_x3b4511N_RE9b0eP2PAD_EIM_A1IMXePIN_REG nam(  55   SD2_CMD__I2C1_SCLBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c9793, 0x0097),  = 65,
7bc51_x3b451IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD2_CMD__SD2_CMDBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c98 3, 0x0098 0), /*98" class=NANDF_CS5_="sre3_2= */ = 65,
7cX51_x3b8512, 0x914eP3PAD_EIM_A1IMXePIN_REG nam(  55   SD2_CLK__CSPI_SCLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15980, 0x000980), /* 98 class=NANDF_CS5_=NANDF_CS5 */ = 65,
7cX51_x3b8511N_RE9b4eP2PAD_EIM_A1IMXePIN_REG nam(  55   SD2_CLK__I2C1_SDAD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15982, 0x000980), /* 98 class=NANDF_CS5_=PATA_DA_= */ = 65,
7cX51_x3b851IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD2_CLK__SD2_CLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1598, 0x000,98 0), /*98" class=NANDF_CS5_=SD4_DAT2 */ = 65,
7c451_x3bXeP2, 0x91XeP3PAD_EIM_A1IMXePIN_REG nam(  55   SD2_DATAi__CSPI_MISOD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1598 3, 0x00980), /* 98 class=NANDF_CS5_=USBH3_DIR */ = 65,
7c451_x3bXeP1N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD2_DATAi__SD1_DAT_D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16985, 0x00098 0), /*986" class=NANDF_CS2_=SD4_CLK */ = 65,
7c451_x3bXePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD2_DATAi__SD2_DATAiD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15981, 0x000980), /* 98 class=NANDF_CS4_=PATA_DA_X */ = 65,
7c851_x3c0eP1N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD2_DATA1__SD1_DAT_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159870x000, 98 0), /*98" class=NANDF_CS4_=SD4_DAT= */ = 65,
7c851_x3c0ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD2_DATA1__SD2_DATA1D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1598 3, 0x00980), /* 98class=NANDF_RB1_=PATA_IORDY */ = 65,
7c851_x3c0ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD2_DATA1__USBH31H2_DPD1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x169893, 0x0098),  = 65,
7cc51_x3c4eP1N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD2_DATA2__SD1_DAT_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x1599 3, 0x0099 0), /*99" class=NANDF_CS5_="sre3_2= */ = 65,
7cc51_x3c4ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD2_DATA2__SD2_DATAhD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15990, 0x000990), /* 99 class=NANDF_CS5_=NANDF_CS5 */ = 65,
7cc51_x3c4ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD2_DATA2__USBH31H2_DMD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15992, 0x000990), /* 99 class=NANDF_CS5_=PATA_DA_= */ = 65,
7dX51_x3c8eP2, 0x92451mPAD_EIM_A1IMXePIN_REG nam(  55   SD2_DATA3__CSPI_SShD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1599, 0x000,99 0), /*99" class=NANDF_CS5_=SD4_DAT2 */ = 65,
7dX51_x3c8eP1N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD2_DATA3__SD1_DAT_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1599 3, 0x00990), /* 99 class=NANDF_CS5_=USBH3_DIR */ = 65,
7dX51_x3c8ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   SD2_DATA3__SD2_DATARBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c995, 0x00099 0), /*996" class=NANDF_CS2_=SD4_CLK */ = 65,
7d451_x3cceP5N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_i__CCM_OUT_hD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x15991, 0x000990), /* 99 class=NANDF_CS4_=PATA_DA_X */ = 65,
7d451_x3ccePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_2_ f=NA1_2D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x159970x000, 99 0), /*99" class=NANDF_CS4_=SD4_DAT= */ = 65,
7d451_x3cceP2, 0x9bXeP3PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_2_ I2C2_SCLBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c99 3, 0x00990), /* 99class=NANDF_RB1_=PATA_IORDY */ = 65,
7d451_x3cceP7N_RE90XePIx1s5s="li52" name="L84">  84     f=NA1_2_ PLL1_BYPD1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x169993, 0x0099),  = 65,
7d451_x3cceP1N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_2_ PWM1 PWMOD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151GMX3, 0x001GMX3,1GMX" class=NANDF_RB1_=SD4_CMX */ = 65,
7d851_x3d0ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_3_ f=NA1_3D1=MX51_PAD_/pre>_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151GM13, 0x001GM0), 1GM class=NANDF_CS5_=NANDF_CS5 */ = 65,
7d851_x3d0eP2, 0x9bXeP3PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_3_ I2C2_SDAD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151GM23, 0x001GM0), 1GM class=NANDF_CS5_=PATA_DA_= */ = 65,
7d851_x3d0eP7N_RE91X51mPAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_3_ PLL2_BYPD1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x161GM33, 0x001GM 0), 1GM" class=NANDF_CS5_=SD4_DAT2 */ = 65,
7d851_x3d0eP1N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_3_ PWM2 PWMOD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151GM43, 0x001GM0), 1GM class=NANDF_CS5_=USBH3_DIR */ = 65,
1GM6" class=NANDF_CS2_=SD4_CLK */ = 65,
1GM class=NANDF_CS4_=PATA_DA_X */ = 65,
80451_x3d8eP4N_RE90XePIx1s5s="li52" name="L84">  84     f=NA1_i_ DISP27EXT_CLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151GM73, 0x001GM 0), 1GM" class=NANDF_CS4_=SD4_DAT= */ = 65,
80451_x3d8ePIN_RE93XePIx1s5s="li52" name="L84">  84     f=NA1_i_ EIM_RDYD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151GM83, 0x001GM0), 1GMclass=NANDF_RB1_=PATA_IORDY */ = 65,
80451_x3d8ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_4_ f=NA1__D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x161GM93, 0x001GM), 1GM6" class=NANDF_RB1_=SD4_CMX */ = 65,
80451_x3d8ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_4_ WDOG1 WDOG_BD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G1X3, 0x001G1X3,1G1X" class=NANDF_RB1_=SD4_CMX */ = 65,
80851_x3dc516N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_5__CSI2_MCLKD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G113, 0x001G10), 1G1 class=NANDF_CS5_=NANDF_CS5 */ = 65,
80851_x3dc513N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_5__DISP27ref1_D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x151G123, 0x001G10), 1G1 class=NANDF_CS5_=PATA_DA_= */ = 65,
80851_x3dc51IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_5_ f=NA1__D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G133, 0x001G1 0), 1G1" class=NANDF_CS5_=SD4_DAT2 */ = 65,
80851_x3dc51IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_5_ WDOG2 WDOG_BD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G143, 0x001G10), 1G1 class=NANDF_CS5_=USBH3_DIR */ = 65,
80c51_x3e0eP4N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_6__DISP27ref1_D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G153, 0x001G1 0), 1G16" class=NANDF_CS2_=SD4_CLK */ = 65,
80c51_x3e0ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_6_ f=NA1__D1=MX51_PAD_EIM_CS4" class=NANDF_D1= nam, 0x540, 0x151G163, 0x001G10), 1G1 class=NANDF_CS4_=PATA_DA_X */ = 65,
80c51_x3e0eP3N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_6_ REF_EN_BD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G173, 0x001G1 0), 1G1" class=NANDF_CS4_=SD4_DAT= */ = 65,
81X51_x3e4eP3N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_7__CCM_OUT_iD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G183, 0x001G10), 1G1class=NANDF_RB1_=PATA_IORDY */ = 65,
81X51_x3e4ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_7_ f=NA1__D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G193, 0x001G1), 1G16" class=NANDF_RB1_=SD4_CMX */ = 65,
81X51_x3e4eP6N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_7__SD2_WPD1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x16102X3, 0x001G2X3,1G2X" class=NANDF_RB1_=SD4_CMX */ = 65,
81X51_x3e4ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_7__SPDIF_OUT1D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G213, 0x001G20), 1G2 class=NANDF_CS5_=NANDF_CS5 */ = 65,
81451_x3e8eP2, 0x99XeP2PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_8__CSI2_DATA_END1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G223, 0x001G20), 1G2 class=NANDF_CS5_=PATA_DA_= */ = 65,
81451_x3e8ePIN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_8_ f=NA1_8D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G233, 0x001G2 0), 1G2" class=NANDF_CS5_=SD4_DAT2 */ = 65,
81451_x3e8eP6N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_8__SD2_CDBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c1G243, 0x001G20), 1G2 class=NANDF_CS5_=USBH3_DIR */ = 65,
81451_x3e8eP1N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_8__USBH31PWRBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c1G253, 0x001G2 0), 1G26" class=NANDF_CS2_=SD4_CLK */ = 65,
81851_x3ec513N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_9__CCM_OUT_1D1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G263, 0x001G20), 1G2 class=NANDF_CS4_=PATA_DA_X */ = 65,
81851_x3ec51IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_9_ DISP27D11CSBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c1G273, 0x001G2 0), 1G2" class=NANDF_CS4_=SD4_DAT= */ = 65,
81851_x3ec517N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_9_ DISP27SER1CSBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c1G283, 0x001G20), 1G2class=NANDF_RB1_=PATA_IORDY */ = 65,
81851_x3ec51IN_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_9_ f=NA1_9D1=MX51_PAD_EIM_CS2" class=NANDF_D1= nam, 0x548, 0x161G293, 0x001G2), 1G26" class=NANDF_RB1_=SD4_CMX */ = 65,
81851_x3ec516N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_9__SD2_LCTLBX51_PAD_NANDF_CS0" class=NANDF_RBX nam, 0x4f8, 0x11c103X3, 0x001G3 0), 1G3 " class=NANDF_RB1_=SD4_CMX */ = 65,
81851_x3ec511N_REGMX51_PAD_EIM_A1IMXePIN_REG nam(  55   f=NA1_9__USBH31OCD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G313, 0x001G30), 1G3 clas};D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G323, 0x001G30), 1G3 clasD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G333, 0x001G3 0), 1G3" cla_EIM_A1IMXePIN_REG nam(  Pad3" cos for the  namux subsystemD1=MX51_PAD_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G343, 0x001G30), 1G3 classtatic const structDF_RB1_=SD4_CMX  nam, 0_ na_descd="L43" clas5s= nam, 0_ na_desc" claF_RB1_=SD4_CMX 544, _ nam, 0_ adsd="L43" clas5s=544, _ nam, 0_ ads" cl[] = {D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x151G353, 0x001G3 0), 1G36" class=NANDF_CS2_=SD4_CLK */ = 65,
1G3 class=NANDF_CS4_=PATA_DA_X */ = 65,
1G3" class=NANDF_CS4_=SD4_DAT= */ = 65,
1G3class=NANDF_RB1_=PATA_IORDY */ = 65,
1G36" class=NANDF_RB1_=SD4_CMX */ = 65,
1G4 " class=NANDF_RB1_=SD4_CMX */ = 65,
1G4 class=NANDF_CS5_=NANDF_CS5 */ = 65,
1G4 class=NANDF_CS5_=PATA_DA_= */ = 65,
1G4" class=NANDF_CS5_=SD4_DAT2 */ = 65,
1G4 class=NANDF_CS5_=USBH3_DIR */ = 65,
1G46" class=NANDF_CS2_=SD4_CLK */ = 65,
1G4 class=NANDF_CS4_=PATA_DA_X */ = 65,
1G4" class=NANDF_CS4_=SD4_DAT= */ = 65,
1G4class=NANDF_RB1_=PATA_IORDY */ = 65,
1G46" class=NANDF_RB1_=SD4_CMX */ = 65,
1G5 " class=NANDF_RB1_=SD4_CMX */ = 65,
1G5 class=NANDF_CS5_=NANDF_CS5 */ = 65,
1G5 class=NANDF_CS5_=PATA_DA_= */ = 65,
1G5" class=NANDF_CS5_=SD4_DAT2 */ = 65,
1G5 class=NANDF_CS5_=USBH3_DIR */ = 65,
1G56" class=NANDF_CS2_=SD4_CLK */ = 65,
1G5 class=NANDF_CS4_=PATA_DA_X */ = 65,
1G5" class=NANDF_CS4_=SD4_DAT= */ = 65,
1G5class=NANDF_RB1_=PATA_IORDY */ = 65,
1G56" class=NANDF_RB1_=SD4_CMX */ = 65,
1G6 " class=NANDF_RB1_=SD4_CMX */ = 65,
1G6 class=NANDF_CS5_=NANDF_CS5 */ = 65,
1G6 class=NANDF_CS5_=PATA_DA_= */ = 65,
1G6" class=NANDF_CS5_=SD4_DAT2 */ = 65,
1G6 class=NANDF_CS5_=USBH3_DIR */ = 65,
1G66" class=NANDF_CS2_=SD4_CLK */ = 65,
1G6 class=NANDF_CS4_=PATA_DA_X */ = 65,
1G6" class=NANDF_CS4_=SD4_DAT= */ = 65,
1G6class=NANDF_RB1_=PATA_IORDY */ = 65,
1G66" class=NANDF_RB1_=SD4_CMX */ = 65,
1G7 " class=NANDF_RB1_=SD4_CMX */ = 65,
1G7 class=NANDF_CS5_=NANDF_CS5 */ = 65,
1G7 class=NANDF_CS5_=PATA_DA_= */ = 65,
1G7" class=NANDF_CS5_=SD4_DAT2 */ = 65,
1G7 class=NANDF_CS5_=USBH3_DIR */ = 65,
1G76" class=NANDF_CS2_=SD4_CLK */ = 65,
1G7 class=NANDF_CS4_=PATA_DA_X */ = 65,
1G7" class=NANDF_CS4_=SD4_DAT= */ = 65,
1G7class=NANDF_RB1_=PATA_IORDY */ = 65,
1G76" class=NANDF_RB1_=SD4_CMX */ = 65,
1G8 " class=NANDF_RB1_=SD4_CMX */ = 65,
1G8 class=NANDF_CS5_=NANDF_CS5 */ = 65,
1G8 class=NANDF_CS5_=PATA_DA_= */ = 65,
1G8" class=NANDF_CS5_=SD4_DAT2 */ = 65,
1G8 class=NANDF_CS5_=USBH3_DIR */ = 65,
1G86" class=NANDF_CS2_=SD4_CLK */ = 65,
1G8 class=NANDF_CS4_=PATA_DA_X */ = 65,
1G8" class=NANDF_CS4_=SD4_DAT= */ = 65,
1G8class=NANDF_RB1_=PATA_IORDY */ = 65,
1G86" class=NANDF_RB1_=SD4_CMX */ = 65,
1G9 " class=NANDF_RB1_=SD4_CMX */ = 65,
1G9 class=NANDF_CS5_=NANDF_CS5 */ = 65,
1G9 class=NANDF_CS5_=PATA_DA_= */ = 65,
1G9" class=NANDF_CS5_=SD4_DAT2 */ = 65,
1G9 class=NANDF_CS5_=USBH3_DIR */ = 65,
1G96" class=NANDF_CS2_=SD4_CLK */ = 65,
1G9 class=NANDF_CS4_=PATA_DA_X */ = 65,
1G9" class=NANDF_CS4_=SD4_DAT= */ = 65,
1G9class=NANDF_RB1_=PATA_IORDY */ = 65,
1G96" class=NANDF_RB1_=SD4_CMX */ = 65,
11MX" class=NANDF_RB1_=SD4_CMX */ = 65,
11M class=NANDF_CS5_=NANDF_CS5 */ = 65,
11M class=NANDF_CS5_=PATA_DA_= */ = 65,
11M" class=NANDF_CS5_=SD4_DAT2 */ = 65,
11M class=NANDF_CS5_=USBH3_DIR */ = 65,
11M6" class=NANDF_CS2_=SD4_CLK */ = 65,
11M class=NANDF_CS4_=PATA_DA_X */ = 65,
11M" class=NANDF_CS4_=SD4_DAT= */ = 65,
11Mclass=NANDF_RB1_=PATA_IORDY */ = 65,
11M6" class=NANDF_RB1_=SD4_CMX */ = 65,
111X" class=NANDF_RB1_=SD4_CMX */ = 65,
111 class=NANDF_CS5_=NANDF_CS5 */ = 65,
111 class=NANDF_CS5_=PATA_DA_= */ = 65,
111" class=NANDF_CS5_=SD4_DAT2 */ = 65,
111 class=NANDF_CS5_=USBH3_DIR */ = 65,
1116" class=NANDF_CS2_=SD4_CLK */ = 65,
111 class=NANDF_CS4_=PATA_DA_X */ = 65,
111" class=NANDF_CS4_=SD4_DAT= */ = 65,
111class=NANDF_RB1_=PATA_IORDY */ = 65,
1116" class=NANDF_RB1_=SD4_CMX */ = 65,
112X" class=NANDF_RB1_=SD4_CMX */ = 65,
112 class=NANDF_CS5_=NANDF_CS5 */ = 65,
112 class=NANDF_CS5_=PATA_DA_= */ = 65,
112" class=NANDF_CS5_=SD4_DAT2 */ = 65,
112 class=NANDF_CS5_=USBH3_DIR */ = 65,
1126" class=NANDF_CS2_=SD4_CLK */ = 65,
112 class=NANDF_CS4_=PATA_DA_X */ = 65,
112" class=NANDF_CS4_=SD4_DAT= */ = 65,
112class=NANDF_RB1_=PATA_IORDY */ = 65,
1126" class=NANDF_RB1_=SD4_CMX */ = 65,
113 " class=NANDF_RB1_=SD4_CMX */ = 65,
113 class=NANDF_CS5_=NANDF_CS5 */ = 65,
113 class=NANDF_CS5_=PATA_DA_= */ = 65,
113" class=NANDF_CS5_=SD4_DAT2 */ = 65,
113 class=NANDF_CS5_=USBH3_DIR */ = 65,
1136" class=NANDF_CS2_=SD4_CLK */ = 65,
113 class=NANDF_CS4_=PATA_DA_X */ = 65,
113" class=NANDF_CS4_=SD4_DAT= */ = 65,
113class=NANDF_RB1_=PATA_IORDY */ = 65,
1136" class=NANDF_RB1_=SD4_CMX */ = 65,
114 " class=NANDF_RB1_=SD4_CMX */ = 65,
114 class=NANDF_CS5_=NANDF_CS5 */ = 65,
114 class=NANDF_CS5_=PATA_DA_= */ = 65,
114" class=NANDF_CS5_=SD4_DAT2 */ = 65,
114 class=NANDF_CS5_=USBH3_DIR */ = 65,
1146" class=NANDF_CS2_=SD4_CLK */ = 65,
114 class=NANDF_CS4_=PATA_DA_X */ = 65,
114" class=NANDF_CS4_=SD4_DAT= */ = 65,
114class=NANDF_RB1_=PATA_IORDY */ = 65,
1146" class=NANDF_RB1_=SD4_CMX */ = 65,
115 " class=NANDF_RB1_=SD4_CMX */ = 65,
115 class=NANDF_CS5_=NANDF_CS5 */ = 65,
115 class=NANDF_CS5_=PATA_DA_= */ = 65,
115" class=NANDF_CS5_=SD4_DAT2 */ = 65,
115 class=NANDF_CS5_=USBH3_DIR */ = 65,
1156" class=NANDF_CS2_=SD4_CLK */ = 65,
115 class=NANDF_CS4_=PATA_DA_X */ = 65,
115" class=NANDF_CS4_=SD4_DAT= */ = 65,
115class=NANDF_RB1_=PATA_IORDY */ = 65,
1156" class=NANDF_RB1_=SD4_CMX */ = 65,
116 " class=NANDF_RB1_=SD4_CMX */ = 65,
116 class=NANDF_CS5_=NANDF_CS5 */ = 65,
116 class=NANDF_CS5_=PATA_DA_= */ = 65,
116" class=NANDF_CS5_=SD4_DAT2 */ = 65,
116 class=NANDF_CS5_=USBH3_DIR */ = 65,
1166" class=NANDF_CS2_=SD4_CLK */ = 65,
116 class=NANDF_CS4_=PATA_DA_X */ = 65,
116" class=NANDF_CS4_=SD4_DAT= */ = 65,
116class=NANDF_RB1_=PATA_IORDY */ = 65,
1166" class=NANDF_RB1_=SD4_CMX */ = 65,
117 " class=NANDF_RB1_=SD4_CMX */ = 65,
117 class=NANDF_CS5_=NANDF_CS5 */ = 65,
117 class=NANDF_CS5_=PATA_DA_= */ = 65,
117" class=NANDF_CS5_=SD4_DAT2 */ = 65,
117 class=NANDF_CS5_=USBH3_DIR */ = 65,
1176" class=NANDF_CS2_=SD4_CLK */ = 65,
117 class=NANDF_CS4_=PATA_DA_X */ = 65,
117" class=NANDF_CS4_=SD4_DAT= */ = 65,
117class=NANDF_RB1_=PATA_IORDY */ = 65,
1176" class=NANDF_RB1_=SD4_CMX */ = 65,
118 " class=NANDF_RB1_=SD4_CMX */ = 65,
118 class=NANDF_CS5_=NANDF_CS5 */ = 65,
118 class=NANDF_CS5_=PATA_DA_= */ = 65,
118" class=NANDF_CS5_=SD4_DAT2 */ = 65,
118 class=NANDF_CS5_=USBH3_DIR */ = 65,
1186" class=NANDF_CS2_=SD4_CLK */ = 65,
118 class=NANDF_CS4_=PATA_DA_X */ = 65,
118" class=NANDF_CS4_=SD4_DAT= */ = 65,
118class=NANDF_RB1_=PATA_IORDY */ = 65,
 = 65,
rl-im4x51DISPB2_SER1DIa" cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1511893, 0x00118), 1186" class=NANDF_RB1_=SD4_CMX */ = 65,
119 " class=NANDF_RB1_=SD4_CMX */ = 65,
119 class=NANDF_CS5_=NANDF_CS5 */ = 65,
119 class=NANDF_CS5_=PATA_DA_= */ = 65,
119" class=NANDF_CS5_=SD4_DAT2 */ = 65,
119 class=NANDF_CS5_=USBH3_DIR */ = 65,
1196" class=NANDF_CS2_=SD4_CLK */ = 65,
119 class=NANDF_CS4_=PATA_DA_X */ = 65,
119" class=NANDF_CS4_=SD4_DAT= */ = 65,
119class=NANDF_RB1_=PATA_IORDY */ = 65,
1196" class=NANDF_RB1_=SD4_CMX */ = 65,
12MX" class=NANDF_RB1_=SD4_CMX */ = 65,
12M class=NANDF_CS5_=NANDF_CS5 */ = 65,
12M class=NANDF_CS5_=PATA_DA_= */ = 65,
12M" class=NANDF_CS5_=SD4_DAT2 */ = 65,
12M class=NANDF_CS5_=USBH3_DIR */ = 65,
12M6" class=NANDF_CS2_=SD4_CLK */ = 65,
12M class=NANDF_CS4_=PATA_DA_X */ = 65,
12M" class=NANDF_CS4_=SD4_DAT= */ = 65,
12Mclass=NANDF_RB1_=PATA_IORDY */ = 65,
12M6" class=NANDF_RB1_=SD4_CMX */ = 65,
121X" class=NANDF_RB1_=SD4_CMX */ = 65,
121 class=NANDF_CS5_=NANDF_CS5 */ = 65,
121 class=NANDF_CS5_=PATA_DA_= */ = 65,
121" class=NANDF_CS5_=SD4_DAT2 */ = 65,
121 class=NANDF_CS5_=USBH3_DIR */ = 65,
1216" class=NANDF_CS2_=SD4_CLK */ = 65,
121 class=NANDF_CS4_=PATA_DA_X */ = 65,
121" class=NANDF_CS4_=SD4_DAT= */ = 65,
121class=NANDF_RB1_=PATA_IORDY */ = 65,
1216" class=NANDF_RB1_=SD4_CMX */ = 65,
122X" class=NANDF_RB1_=SD4_CMX */ = 65,
122 class=NANDF_CS5_=NANDF_CS5 */ = 65,
122 class=NANDF_CS5_=PATA_DA_= */ = 65,
122" class=NANDF_CS5_=SD4_DAT2 */ = 65,
122 class=NANDF_CS5_=USBH3_DIR */ = 65,
1226" class=NANDF_CS2_=SD4_CLK */ = 65,
122 class=NANDF_CS4_=PATA_DA_X */ = 65,
122" class=NANDF_CS4_=SD4_DAT= */ = 65,
122class=NANDF_RB1_=PATA_IORDY */ = 65,
1226" class=NANDF_RB1_=SD4_CMX */ = 65,
123 " class=NANDF_RB1_=SD4_CMX */ = 65,
123 class=NANDF_CS5_=NANDF_CS5 */ = 65,
123 class=NANDF_CS5_=PATA_DA_= */ = 65,
123" class=NANDF_CS5_=SD4_DAT2 */ = 65,
123 class=NANDF_CS5_=USBH3_DIR */ = 65,
1236" class=NANDF_CS2_=SD4_CLK */ = 65,
123 class=NANDF_CS4_=PATA_DA_X */ = 65,
123" class=NANDF_CS4_=SD4_DAT= */ = 65,
 =commen122" naDISP2_DAT1i" cl),D_16" class=NANDF_CS2_=SDDP2_DAWla),D.c#L7212383,20Eam, 0x544, 0x1512373, 0x001ATi" cl)m4x51DISP25s="li5e" A2=NANDF_D1= nam, 0x544, 0x1512333, 0x00123 -im4x51DISP1_DAT2id="L5DPATA_Wcl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0x1512263, /spaCTRL/2L/spa_D13 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
1236" 5 class=NA2DF_CS5_=USBH3_DIR */ = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
123" c116 class=2ANDF_CS5_=NANDF_CS5 */ = 65,
 = 65,
 =commen122" na116" class2NANDF_CS5_=SD4_DAT2 */ = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 = 65,
 };cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0xc17 " clas2_RB1_=SD4_CMX */ cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0xc16 class=2S5_=NANDF_CS5 */ static structa hrefCTRL/spaiv, 0__D1= na_soc_info_CS3" class=NAN, 0__D1= na_soc_info/a> = hrefCTRL/spaiv, 0_D1_D1= na_info_CS3" class=NAN, 0_D1_D1= na_info/a> == {cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0xc16 class=2S5_=PATA_DA_= */ = 65,
 ==  hrefCTRL/spaiv, 0_D1_D1= na_pads_CS3" class=NAN, 0_D1_D1= na_pads/a> Wcl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0xc16" class2NDF_CS5_=SD4_DAT2 */ = 65. hrefCTRL/spaivn_D1s_CS3" class=NANn_D1s/a> ==  hrefCTRL/spaivARRAY_SIZE_CS3" class=NANARRAY_SIZE clas5s="li5e" naUSB, 0_D1_D1= na_pads_CS3" class=NAN, 0_D1_D1= na_pads/a> _Wcl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0xc16 class=2DF_CS5_=USBH3_DIR */ = 65. hrefCTRL/spaiv_D1_regs_CS3" class=NAN_D1_regs/a> ==  hrefCTRL/spaiv, 0_D1_D1_regs_CS3" class=NAN, 0_D1_D1_regs/a> Wcl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0xc166" clas2ANDF_CS2_=SD4_CLK */ = 65. hrefCTRL/spaivn_D1_regs_CS3" class=NANn_D1_regs/a> ==  hrefCTRL/spaivARRAY_SIZE_CS3" class=NANARRAY_SIZE clas5s="li5e" naUSB, 0_D1_D1_regs_CS3" class=NAN, 0_D1_D1_regs/a> _Wcl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0xc16 class=2DF_CS4_=PATA_DA_X */2= 65,
static structa hrefCTRL/spaivof_device_id_CS3" class=NANof_device_id/a> = hrefCTRL/spaiv, 0_D1_D1= na_of_match_CS3" class=NAN, 0_D1_D1= na_of_match/a> []= hrefCTRL/spaiv__devinitdata_CS3" class=NAN__devinitdata/a> == {cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0xNANDF_RB1_2SD4_CMX */2= 65,
 ==  spanCS3" clastring">"fsl,, 0x5-iomuxc", }Wcl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0xNANDF_RB1_2SD4_CMX */2= 65,
/* sentspal */ }cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0xN16 class=2NANDF_CS5 */ = 65};cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0xclass=NAND2_CS5_=PATA_DA_= */ = hrefCTRL/spaiv, 0_D1_D1= na_probe_CS3" class=NAN, 0_D1_D1= na_probe classtructa hrefCTRL/spaivplatform_device_CS3" class=NAN_latform_device/a> =* hrefCTRL/spaivpdev_CS3" class=NAN_dev/a> _cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0xc16 class=2_CS5_=USBH3_DIR */ = 65,
returna hrefCTRL/spaiv, 0__D1= na_probe_CS3" class=NAN, 01_D1= na_probe clas hrefCTRL/spaivpdev_CS3" class=NAN_dev/a> , & hrefCTRL/spaiv, 0_D1_D1= na_info_CS3" class=NAN, 0_D1_D1= na_info/a> );cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 0xc16 class=2_CS4_=PATA_DA_X */ = hrefCTRL/spaiv, 0_D1_D1= na_dS3" c_CS3" class=NAN, 0_D1_D1= na_dS3" c/a> == {cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 03" class=NA3DF_RB1_=SD4_CMX */ = 65,
. hrefCTRL/spaivdS3" c_CS3" class=NANdS3" c/a> == {cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 03"1class=NA3DD4_CMX */ = 65,
/a> = 65. hrefCTRL/spaivnL/s_CS3" class=NANnL/s/a> ==  spanCS3" clastring">", 0x5-_D1= na",cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 03"2class=NA3DANDF_CS5 */ = 65,
/a> = 65. hrefCTRL/spaivown c_CS3" class=NANown c/a> ==  hrefCTRL/spaivTHIS_MODULE_CS3" class=NANTHIS_MODULE/a> Wcl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 03ass=NANDF_3S5_=PATA_DA_= */ = 65,
 = 65. hrefCTRL/spaivof_match_table_CS3" class=NANof_match_table/a> ==  hrefCTRL/spaivof_match_ptc_CS3" class=NANof_match_ptc clas5s="li5e" naUSB, 0_D1_D1= na_of_match_CS3" class=NAN, 0_D1_D1= na_of_match/a> _Wcl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 03lass=NANDF3CS5_=SD4_DAT2 */ = 65,
 = 65. hrefCTRL/spaiv_robe_CS3" class=NANprobe cla==  hrefCTRL/spaiv, 0_D1_D1= na_probe_CS3" class=NAN, 0_D1_D1= na_probe claWcl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 03a6s=NANDF_3SF_CS2_=SD4_CLK */ = 65. hrefCTRL/spaivremove_CS3" class=NANremove cla==  hrefCTRL/spaiv__devexit_p_CS3" class=NAN__devexit_p clas5s="li5e" naUSB, 01_D1= na_remove_CS3" class=NAN, 01_D1= na_remove/a> _Wcl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 03l7s=NANDF_3SCS4_=PATA_DA_X */ = hrefCTRL/spaiv, 0_D1_D1= na_init_CS3" class=NAN, 0_D1_D1= na_init clasvoid_cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 03class=NAND3_RB1_=SD4_CMX */ = 65,
 );cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 03ass=NANDF_3S5_=NANDF_CS5 */ = hrefCTRL/spaiv, 0_D1_D1= na_exit_CS3" class=NAN, 0_D1_D1= na_exit clasvoid_cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 03c6s=NANDF_3_CS2_=SD4_CLK */ {cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 03c7s=NANDF_3ANDF_CS4_=PATA_DA_X */ = 65,
 );cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 03aass=NANDF3NANDF_CS4_=SD4_DAT= */1216" 3lass=NANDF_RB1_=SD4_CMX *3"Dong Aisheng <dong.aisheng@RB1aro.org>");cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 031lass=NAND3=NANDF_RB1_=SD4_CMX */"Freescale IDF_D _D1= na CS3" c");cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 031ss=NANDF_3ANDF_CS5_=NANDF_CS5 */"GPL v2");cl),D_EIM_CS3" class=NANDF_D1= nam, 0x544, 031ss=NANDF_3ANDF_CS5_=PATA_DA_= */


The origB1al LXR software by the l),D_EIM_http://sourceforge.net/projects/lxc_>LXR community/a> , this experimental " clion by l),D_EIM_mailto:lxc@RB1ux.no">lxc@RB1ux.no/a> .
lxc.RB1ux.no kindly host d by l),D_EIM_http://www.redpill-RB1pro.no">Redpill LB1pro AS/a> , provider of LB1ux consulting and operations services sD1=e 1995.