linux/drivers/clocksource/cyclone.c
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v v12/a>#include <linux/clocksource.h2/a>>
v v22/a>#include <linux/string.h2/a>>
v v32/a>#include <linux/errno.h2/a>>
v v42/a>#include <linux/timex.h2/a>>
v v52/a>#include <linux/init.h2/a>>
v v62/a>pv v72/a>#include <asm/pgtable.h2/a>>
v v82/a>#include <asm/io.h2/a>>
v v92/a>pv 6.27a>#include <asm/mach_timer.h2/a>>
v 112/a>pv 122/a>#definev2a href="+code=CYCLONE_CBAR_ADDR" class="sref">CYCLONE_CBAR_ADDR2/a>io v v 0xFEB00CD0io v v2spa	 class="comment">/* base address ptr */2/spa	  v 132/a>#definev2a href="+code=CYCLONE_PMCC_OFFSET" class="sref">CYCLONE_PMCC_OFFSET2/a>io v 0x51A0io v v v v2spa	 class="comment">/* offset to control register */2/spa	  v 142/a>#definev2a href="+code=CYCLONE_MPCS_OFFSET" class="sref">CYCLONE_MPCS_OFFSET2/a>io v 0x51A8io v v v v2spa	 class="comment">/* offset to select register */2/spa	  v 152/a>#definev2a href="+code=CYCLONE_MPMC_OFFSET" class="sref">CYCLONE_MPMC_OFFSET2/a>io v 0x51D0io v v v v2spa	 class="comment">/* offset to count register */2/spa	  v 162/a>#definev2a href="+code=CYCLONE_TIMER_FREQ" class="sref">CYCLONE_TIMER_FREQ2/a>io v v99780000 v v v v2spa	 class="comment">/* 100Mhz, but not really */2/spa	  v 172/a>#definev2a href="+code=CYCLONE_TIMER_MASK" class="sref">CYCLONE_TIMER_MASK2/a>io v v2a href="+code=CLOCKSOURCE_MASK" class="sref">CLOCKSOURCE_MASK2/a>(32)v2spa	 class="comment">/* 32 bit mask */2/spa	  v 182/a>pv 192/a>int 2a href="+code=use_cyclone" class="sref">use_cyclone2/a>i= 0;
v 2.27a>static void 2a href="+code=__iomem" class="sref">__iomem2/a>i*2a href="+code=cyclone_ptr" class="sref">cyclone_ptr2/a>;
v 212/a>pv 2227a>static 2a href="+code=cycle_t" class="sref">cycle_t2/a>i2a href="+code=read_cyclone" class="sref">read_cyclone2/a>(struct 2a href="+code=clocksource" class="sref">clocksource2/a>i*2a href="+code=cs" class="sref">cs2/a>)pv 232/a>{pv 242/a>io v v  return (2a href="+code=cycle_t" class="sref">cycle_t2/a>)2a href="+code=readl" class="sref">readl2/a>(2a href="+code=cyclone_ptr" class="sref">cyclone_ptr2/a>);
v 252/a>}
v 262/a>pv 2727a>static struct 2a href="+code=clocksource" class="sref">clocksource2/a>i2a href="+code=clocksource_cyclone" class="sref">clocksource_cyclone2/a>i= {pv 282/a>io v v  .2a href="+code=namp" class="sref">namp2/a>io v v     =v2spa	 class="string">"cyclone"2/spa	 ,pv 292/a>io v v  .2a href="+code=rating" class="sref">rating2/a>io v v   = 250,pv 302/a>io v v  .2a href="+code=read" class="sref">read2/a>io v v     =v2a href="+code=read_cyclone" class="sref">read_cyclone2/a>,pv 312/a>io v v  .2a href="+code=mask" class="sref">mask2/a>io v v     =v2a href="+code=CYCLONE_TIMER_MASK" class="sref">CYCLONE_TIMER_MASK2/a>,pv 322/a>io v v  .2a href="+code=flags" class="sref">flags2/a>io v v    =v2a href="+code=CLOCK_SOURCE_IS_CONTINUOUS" class="sref">CLOCK_SOURCE_IS_CONTINUOUS2/a>,pv 332/a>};
v 342/a>pv 3527a>static int 2a href="+code=__init" class="sref">__init2/a>i2a href="+code=init_cyclone_clocksource" class="sref">init_cyclone_clocksource2/a>(void)pv 362/a>{pv 372/a>io v v  unsigned longi2a href="+code=base" class="sref">base2/a>;v v v2spa	 class="comment">/* saved 1v 382/a>io v v  unsigned longi2a href="+code=offset" class="sref">offset2/a>;
v 392/a>io v v  2a href="+code=u32" class="sref">u322/a>i2a href="+code=__iomem" class="sref">__iomem2/a>* volatilev2a href="+code=cyclone_timer" class="sref">cyclone_timer2/a>;v v 2spa	 class="comment">/* Cyclone MPMC0 register */2/spa	  v 402/a>io v v  2a href="+code=u32" class="sref">u322/a>i2a href="+code=__iomem" class="sref">__iomem2/a>* 2a href="+code=reg" class="sref">reg2/a>;
v 412/a>io v v  int 2a href="+code=i" class="sref">i2/a>;
v 422/a>pv 432/a>io v v  2spa	 class="comment">/* make sure we're on a summit box: */2/spa	  v 442/a>io v v  if (!2a href="+code=use_cyclone" class="sref">use_cyclone2/a>)pv 452/a>io v v          return -2a href="+code=ENODEV" class="sref">ENODEV2/a>;
v 462/a>pv 472/a>io v v  2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_INFO" class="sref">KERN_INFO2/a>i2spa	 class="string">"Summit chipset: Starting Cyclone Counter.\n"2/spa	 );
v 482/a>pv 492/a>io v v  2spa	 class="comment">/* find base address: */2/spa	  v 502/a>io v v  2a href="+code=offset" class="sref">offset2/a> =v2a href="+code=CYCLONE_CBAR_ADDR" class="sref">CYCLONE_CBAR_ADDR2/a>;
v 512/a>io v v  2a href="+code=reg" class="sref">reg2/a> =v2a href="+code=ioremap_nocache" class="sref">ioremap_nocache2/a>(2a href="+code=offset" class="sref">offset2/a>, sizeof(2a href="+code=reg" class="sref">reg2/a>));
v 522/a>io v v  if (!2a href="+code=reg" class="sref">reg2/a>) {pv 532/a>io v v          2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_ERR" class="sref">KERN_ERR2/a>i2spa	 class="string">"Summit chipset: Could not find 1v 542/a>io v v          return -2a href="+code=ENODEV" class="sref">ENODEV2/a>;
v 552/a>io v v  }
v 562/a>io v v  2spa	 class="comment">/* even on 64bit systems, this is only 32bits: */2/spa	  v 572/a>io v v  2a href="+code=base" class="sref">base2/a> =v2a href="+code=readl" class="sref">readl2/a>(2a href="+code=reg" class="sref">reg2/a>);
v 582/a>io v v  2a href="+code=iounmap" class="sref">iounmap2/a>(2a href="+code=reg" class="sref">reg2/a>);
v 592/a>io v v  if (!2a href="+code=base" class="sref">base2/a>) {pv 602/a>io v v          2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_ERR" class="sref">KERN_ERR2/a>i2spa	 class="string">"Summit chipset: Could not find 1v 612/a>io v v          return -2a href="+code=ENODEV" class="sref">ENODEV2/a>;
v 622/a>io v v  }
v 632/a>pv 642/a>io v v  2spa	 class="comment">/* setup PMCC: */2/spa	  v 652/a>io v v  2a href="+code=offset" class="sref">offset2/a> =v2a href="+code=base" class="sref">base2/a> +v2a href="+code=CYCLONE_PMCC_OFFSET" class="sref">CYCLONE_PMCC_OFFSET2/a>;
v 662/a>io v v  2a href="+code=reg" class="sref">reg2/a> =v2a href="+code=ioremap_nocache" class="sref">ioremap_nocache2/a>(2a href="+code=offset" class="sref">offset2/a>, sizeof(2a href="+code=reg" class="sref">reg2/a>));
v 672/a>io v v  if (!2a href="+code=reg" class="sref">reg2/a>) {pv 682/a>io v v          2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_ERR" class="sref">KERN_ERR2/a>i2spa	 class="string">"Summit chipset: Could not find 1v 692/a>io v v          return -2a href="+code=ENODEV" class="sref">ENODEV2/a>;
v 702/a>io v v  }
v 712/a>io v v  2a href="+code=writel" class="sref">writel2/a>(0x00000001,2a href="+code=reg" class="sref">reg2/a>);
v 722/a>io v v  2a href="+code=iounmap" class="sref">iounmap2/a>(2a href="+code=reg" class="sref">reg2/a>);
v 732/a>pv 742/a>io v v  2spa	 class="comment">/* setup MPCS: */2/spa	  v 752/a>io v v  2a href="+code=offset" class="sref">offset2/a> =v2a href="+code=base" class="sref">base2/a> +v2a href="+code=CYCLONE_MPCS_OFFSET" class="sref">CYCLONE_MPCS_OFFSET2/a>;
v 762/a>io v v  2a href="+code=reg" class="sref">reg2/a> =v2a href="+code=ioremap_nocache" class="sref">ioremap_nocache2/a>(2a href="+code=offset" class="sref">offset2/a>, sizeof(2a href="+code=reg" class="sref">reg2/a>));
v 772/a>io v v  if (!2a href="+code=reg" class="sref">reg2/a>) {pv 782/a>io v v          2a href="+code=printk" class="sref">printk2/a>(2a href="+code=KERN_ERR" class="sref">KERN_ERR2/a>i2spa	 class="string">"Summit chipset: Could not find 1v 792/a>io v v          return -2a href="+code=ENODEV" class="sref">ENODEV2/a>;
v 802/a>io v v  }
v 812/a>io v v  2a href="+code=writel" class="sref">writel2/a>(0x00000001,2a href="+code=reg" class="sref">reg2/a>);
v 822/a>io v v  2a href="+code=iounmap" class="sref">iounmap2/a>(2a href="+code=reg" class="sref">reg2/a>);
v 832/a>pv 842/a>io v v  2spa	 class="comment">/* map i	 cyclone_timer: */2/spa	  v 852/a>io v v  2a href="+code=offset" class="sref">offset2/a> =v2a href="+code=base" class="sref">base2/a> +v2a href="+code=CYCLONE_MPMC_OFFSET" class="sref">CYCLONE_MPMC_OFFSET2/a>;
v 862/a>io v v  2a href="+code=cyclone_timer" class="sref">cyclone_timer2/a> =v2a href="+code=ioremap_nocache" class="sref">ioremap_nocache2/a>(2a href="+code=offset" class="sref">offset2/a>, sizeof(2a href="+code=u64" class="sref">u642/a>));
v 84s="sref0cline" na"line" namptiL8ne" namp">v 652/a>io
/
rs/clocksource/cyclone.c#L87" idtiL8lockso1/id CBAR 1, sizeof(2a drivers/clockso="sers/clockso="ser2_OFric/io.h|include/asm-h8300/io.h|include>offset2/a>, sizeof(2a href="+cod
2glude/asm-v850/pcyclone.c#L87" idtiL8lockso1/id CBAamptiL32">v 322/a>io v 850/pcyclonref">u642/a>));9cksou9use_cyclone2/a>i= 0;
v 822/quick tesFSET2one.c#L41"its tickL78code=iounmap" class="sref">iounmap2/a>(2a href="+cod9" class=9sref">writel2/a>(0x00009001,29offset" classforad_cyclone2/a>(stlone.c#L40" idtiL40" f">CL/clocksource/cyclone.c#L40" idtiL40" um/io 3L/clocksource/cyclone.c#L40" idtiL40" ++)emap_nocache" class="sref">ioremap_nocache9f="drive9s/clocksource/cyclone.c9L82" 9ptiL53">v 532/a>io v code=u32" class="sref">u322/a>i2a href="+code=__iomem" col="string">"ol= }
cyclone_timer2/a> =v2a href="+code=ioio.h|include/asm-h8300/io.h|include>offset2=reg" cl9ss="sref">reg2/a>);
/ers/clocksource/cycstalource/cyclone.c#stalo }
(32)v2spa	 class="comme9a	  v 862/a>io9v v  97a	 class="comment">/wh#L38L56" class="linestalource/cyclone.c#stalo }
<--ers/clocksource/cyclone.c#L43" idtiL43" cl9/a>(2a h9ef="+code=offset" class9"sref9>offset2/a>, sizeof(2/a>io v code=u32" classbarriclone_timer2/a> =barriclidtiLoio.h|include/asm-h8300/io.h|include>offset2sm-ppc/ioo.h|include/asm-s390/io.asm-b9lude/asm-sh/io.h|include/asm-sh64/io.h|include/aasm-sparc//io.h|include/asm-sparc64asm-64aa	 class="comment">/ef8L56" class="lineocksource/cyclone.c#L56" idtiL56" class="lines="sref">cyclone_timer2/a> =v2a href="+code=io = href="drivers/clol="string">"ol= }
ioremap_nocache10ch_timer.0h|include/asm-sparc/mach01sm-64namptiL60">v 602/a>io/a>io v code=u32" class64" class="sref">u642/a>));
v 84s="sref0cline" na"li.c#L" nam/a>ioL78! DISABLED
/
rs/clocksource/cyclone.c#L87" idtiL8lockso1/id CBAR 1v 602/a>io/a>io v code=u32" class  }
cyclone_timer2/a> =v2a href="+code=ioio.h|include/asm-h8300/io.h|include>offset10s="line" 0namptiL11">v 112/a>p/a>io v code=u32" classe" namptiL85">v 852/a>io v v  2a href="+code=offset" class="sreNULL>v 852/a>io v vNULLric/io.h|include/asm-h8300/io.h|include>offset10ss ptr */02/spa	  v 532/a>io v         , sizeof(2a drivers/clockso="sers/clockso="ser2_OFric/io.h|include/asm-h8300/io.h|include>offset10egister *0/2/spa	  /#L87" idtiL8lockso1/id CBAamptiL32">v 322/10register 0*/2/spa	  v 322/10nt regist0er */2/spa	  cs2/a>)pv 382/a>io v v  unsigned lL87" idtiL8lockso1/id CBAamptiL32">v 322/10source/cy0clone.c#L17" idtiL17" cl08sm-64ine" namptiL17">v 172/a>#definev2a href="+code=0CYCLONE_T0IMER_MASK" class="sref">09sm-64ackfin/io.h|i, sizeoset" class="sres25">v 252/a 652/a>i_hztiL38">v 382/a>i25">v 252/a 652/a>i_hzrce/c&set" class="sres25">v 252/a5" class="line" namptiL25">v 252/a>}
/t" class="sref">/a>io v code=u32" classL15" class="line" namptiL15">v 152/a>#definev2a href="+oio.h|include/asm-h8300/io.h|include>offset1ach_timer.hh|include/asm-sparc/mach_1sm-6r.h|in#L87" idtiL8lockso1/id CBAamptiL32">v 322/1m-um/mach__timer.h|include/asm-v8500/mac11a href="+code=__iomem" class="sref">__iomem2/a1ss="line"  namptiL11">v 112/a>pv 332/a>};
offset1ass ptr *//2/spa	  
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