linux/Documentation/ia64/IRQ-redir.txt
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   1IRQ affinity on IA64 platforms
   2------------------------------
   3                           07.01.2002, Erich Focht <efocht@ess.nec.de>
   4
   5
   6By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
   7controlled. The behavior on IA64 platforms is slightly different from
   8that described in Documentation/IRQ-affinity.txt for i386 systems.
   9
  10Because of the usage of SAPIC mode and physical destination mode the
  11IRQ target is one particular CPU and cannot be a mask of several
  12CPUs. Only the first non-zero bit is taken into account.
  13
  14
  15Usage examples:
  16
  17The target CPU has to be specified as a hexadecimal CPU mask. The
  18first non-zero bit is the selected CPU. This format has been kept for
  19compatibility reasons with i386.
  20
  21Set the delivery mode of interrupt 41 to fixed and route the
  22interrupts to CPU #3 (logical CPU number) (2^3=0x08):
  23     echo "8" >/proc/irq/41/smp_affinity
  24
  25Set the default route for IRQ number 41 to CPU 6 in lowest priority
  26delivery mode (redirectable):
  27     echo "r 40" >/proc/irq/41/smp_affinity
  28
  29The output of the command
  30     cat /proc/irq/IRQ#/smp_affinity
  31gives the target CPU mask for the specified interrupt vector. If the CPU
  32mask is preceded by the character "r", the interrupt is redirectable
  33(i.e. lowest priority mode routing is used), otherwise its route is
  34fixed.
  35
  36
  37
  38Initialization and default behavior:
  39
  40If the platform features IRQ redirection (info provided by SAL) all
  41IO-SAPIC interrupts are initialized with CPU#0 as their default target
  42and the routing is the so called "lowest priority mode" (actually
  43fixed SAPIC mode with hint). The XTP chipset registers are used as hints
  44for the IRQ routing. Currently in Linux XTP registers can have three
  45values:
  46        - minimal for an idle task,
  47        - normal if any other task runs,
  48        - maximal if the CPU is going to be switched off.
  49The IRQ is routed to the CPU with lowest XTP register value, the
  50search begins at the default CPU. Therefore most of the interrupts
  51will be handled by CPU #0.
  52
  53If the platform doesn't feature interrupt redirection IOSAPIC fixed
  54routing is used. The target CPUs are distributed in a round robin
  55manner. IRQs will be routed only to the selected target CPUs. Check
  56with
  57        cat /proc/interrupts
  58
  59
  60
  61Comments:
  62
  63On large (multi-node) systems it is recommended to route the IRQs to
  64the node to which the corresponding device is connected.
  65For systems like the NEC AzusA we get IRQ node-affinity for free. This
  66is because usually the chipsets on each node redirect the interrupts
  67only to their own CPUs (as they cannot see the XTP registers on the
  68other nodes).
  69
  70
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