linux/sound/pci/azt3328.h
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   1#ifndef __SOUND_AZT3328_H
   2#define __SOUND_AZT3328_H
   3
   4/* "PU" == "power-up value", as tested on PCI168 PCI rev. 10
   5 * "WRITE_ONLY"  == register does not indicate actual bit values */
   6
   7/*** main I/O area port indices ***/
   8/* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */
   9#define AZF_IO_SIZE_CTRL        0x80
  10#define AZF_IO_SIZE_CTRL_PM     0x70
  11
  12/* the driver initialisation suggests a layout of 4 areas
  13 * within the main card control I/O:
  14 * from 0x00 (playback codec), from 0x20 (recording codec)
  15 * and from 0x40 (most certainly I2S out codec).
  16 * And another area from 0x60 to 0x6f (DirectX timer, IRQ management,
  17 * power management etc.???). */
  18
  19#define AZF_IO_OFFS_CODEC_PLAYBACK      0x00
  20#define AZF_IO_OFFS_CODEC_CAPTURE       0x20
  21#define AZF_IO_OFFS_CODEC_I2S_OUT       0x40
  22
  23#define IDX_IO_CODEC_DMA_FLAGS       0x00 /* PU:0x0000 */
  24     /* able to reactivate output after output muting due to 8/16bit
  25      * output change, just like 0x0002.
  26      * 0x0001 is the only bit that's able to start the DMA counter */
  27  #define DMA_RESUME                    0x0001 /* paused if cleared? */
  28     /* 0x0002 *temporarily* set during DMA stopping. hmm
  29      * both 0x0002 and 0x0004 set in playback setup. */
  30     /* able to reactivate output after output muting due to 8/16bit
  31      * output change, just like 0x0001. */
  32  #define DMA_RUN_SOMETHING1            0x0002 /* \ alternated (toggled) */
  33     /* 0x0004: NOT able to reactivate output */
  34  #define DMA_RUN_SOMETHING2            0x0004 /* / bits */
  35  #define SOMETHING_ALMOST_ALWAYS_SET   0x0008 /* ???; can be modified */
  36  #define DMA_EPILOGUE_SOMETHING        0x0010
  37  #define DMA_SOMETHING_ELSE            0x0020 /* ??? */
  38  #define SOMETHING_UNMODIFIABLE        0xffc0 /* unused? not modifiable */
  39#define IDX_IO_CODEC_IRQTYPE     0x02 /* PU:0x0001 */
  40  /* write back to flags in case flags are set, in order to ACK IRQ in handler
  41   * (bit 1 of port 0x64 indicates interrupt for one of these three types)
  42   * sometimes in this case it just writes 0xffff to globally ACK all IRQs
  43   * settings written are not reflected when reading back, though.
  44   * seems to be IRQ, too (frequently used: port |= 0x07 !), but who knows? */
  45  #define IRQ_SOMETHING                 0x0001 /* something & ACK */
  46  #define IRQ_FINISHED_DMABUF_1         0x0002 /* 1st dmabuf finished & ACK */
  47  #define IRQ_FINISHED_DMABUF_2         0x0004 /* 2nd dmabuf finished & ACK */
  48  #define IRQMASK_SOME_STATUS_1         0x0008 /* \ related bits */
  49  #define IRQMASK_SOME_STATUS_2         0x0010 /* / (checked together in loop) */
  50  #define IRQMASK_UNMODIFIABLE          0xffe0 /* unused? not modifiable */
  51  /* start address of 1st DMA transfer area, PU:0x00000000 */
  52#define IDX_IO_CODEC_DMA_START_1 0x04
  53  /* start address of 2nd DMA transfer area, PU:0x00000000 */
  54#define IDX_IO_CODEC_DMA_START_2 0x08
  55  /* both lengths of DMA transfer areas, PU:0x00000000
  56     length1: offset 0x0c, length2: offset 0x0e */
  57#define IDX_IO_CODEC_DMA_LENGTHS 0x0c
  58#define IDX_IO_CODEC_DMA_CURRPOS 0x10 /* current DMA position, PU:0x00000000 */
  59  /* offset within current DMA transfer area, PU:0x0000 */
  60#define IDX_IO_CODEC_DMA_CURROFS 0x14
  61#define IDX_IO_CODEC_SOUNDFORMAT 0x16 /* PU:0x0010 */
  62  /* all unspecified bits can't be modified */
  63  #define SOUNDFORMAT_FREQUENCY_MASK    0x000f
  64  #define SOUNDFORMAT_XTAL1             0x00
  65  #define SOUNDFORMAT_XTAL2             0x01
  66    /* all _SUSPECTED_ values are not used by Windows drivers, so we don't
  67     * have any hard facts, only rough measurements.
  68     * All we know is that the crystal used on the board has 24.576MHz,
  69     * like many soundcards (which results in the frequencies below when
  70     * using certain divider values selected by the values below) */
  71    #define SOUNDFORMAT_FREQ_SUSPECTED_4000     0x0c | SOUNDFORMAT_XTAL1
  72    #define SOUNDFORMAT_FREQ_SUSPECTED_4800     0x0a | SOUNDFORMAT_XTAL1
  73    #define SOUNDFORMAT_FREQ_5510               0x0c | SOUNDFORMAT_XTAL2
  74    #define SOUNDFORMAT_FREQ_6620               0x0a | SOUNDFORMAT_XTAL2
  75    #define SOUNDFORMAT_FREQ_8000               0x00 | SOUNDFORMAT_XTAL1 /* also 0x0e | SOUNDFORMAT_XTAL1? */
  76    #define SOUNDFORMAT_FREQ_9600               0x08 | SOUNDFORMAT_XTAL1
  77    #define SOUNDFORMAT_FREQ_11025              0x00 | SOUNDFORMAT_XTAL2 /* also 0x0e | SOUNDFORMAT_XTAL2? */
  78    #define SOUNDFORMAT_FREQ_SUSPECTED_13240    0x08 | SOUNDFORMAT_XTAL2 /* seems to be 6620 *2 */
  79    #define SOUNDFORMAT_FREQ_16000              0x02 | SOUNDFORMAT_XTAL1
  80    #define SOUNDFORMAT_FREQ_22050              0x02 | SOUNDFORMAT_XTAL2
  81    #define SOUNDFORMAT_FREQ_32000              0x04 | SOUNDFORMAT_XTAL1
  82    #define SOUNDFORMAT_FREQ_44100              0x04 | SOUNDFORMAT_XTAL2
  83    #define SOUNDFORMAT_FREQ_48000              0x06 | SOUNDFORMAT_XTAL1
  84    #define SOUNDFORMAT_FREQ_SUSPECTED_66200    0x06 | SOUNDFORMAT_XTAL2 /* 66200 (13240 * 5); 64000 may have been nicer :-\ */
  85  #define SOUNDFORMAT_FLAG_16BIT        0x0010
  86  #define SOUNDFORMAT_FLAG_2CHANNELS    0x0020
  87
  88
  89/* define frequency helpers, for maximum value safety */
  90enum azf_freq_t {
  91#define AZF_FREQ(rate) AZF_FREQ_##rate = rate
  92  AZF_FREQ(4000),
  93  AZF_FREQ(4800),
  94  AZF_FREQ(5512),
  95  AZF_FREQ(6620),
  96  AZF_FREQ(8000),
  97  AZF_FREQ(9600),
  98  AZF_FREQ(11025),
  99  AZF_FREQ(13240),
 100  AZF_FREQ(16000),
 101  AZF_FREQ(22050),
 102  AZF_FREQ(32000),
 103  AZF_FREQ(44100),
 104  AZF_FREQ(48000),
 105  AZF_FREQ(66200),
 106#undef AZF_FREQ
 107};
 108
 109/** DirectX timer, main interrupt area (FIXME: and something else?) **/ 
 110#define IDX_IO_TIMER_VALUE      0x60 /* found this timer area by pure luck :-) */
 111  /* timer countdown value; triggers IRQ when timer is finished */
 112  #define TIMER_VALUE_MASK              0x000fffffUL
 113  /* activate timer countdown */
 114  #define TIMER_COUNTDOWN_ENABLE        0x01000000UL
 115  /* trigger timer IRQ on zero transition */
 116  #define TIMER_IRQ_ENABLE              0x02000000UL
 117  /* being set in IRQ handler in case port 0x00 (hmm, not port 0x64!?!?)
 118   * had 0x0020 set upon IRQ handler */
 119  #define TIMER_IRQ_ACK                 0x04000000UL
 120#define IDX_IO_IRQSTATUS        0x64
 121  /* some IRQ bit in here might also be used to signal a power-management timer
 122   * timeout, to request shutdown of the chip (e.g. AD1815JS has such a thing).
 123   * OPL3 hardware contains several timers which confusingly in most cases
 124   * are NOT routed to an IRQ, but some designs (e.g. LM4560) DO support that,
 125   * so I wouldn't be surprised at all to discover that AZF3328
 126   * supports that thing as well... */
 127
 128  #define IRQ_PLAYBACK  0x0001
 129  #define IRQ_RECORDING 0x0002
 130  #define IRQ_I2S_OUT   0x0004 /* this IS I2S, right!? (untested) */
 131  #define IRQ_GAMEPORT  0x0008 /* Interrupt of Digital(ly) Enhanced Game Port */
 132  #define IRQ_MPU401    0x0010
 133  #define IRQ_TIMER     0x0020 /* DirectX timer */
 134  #define IRQ_UNKNOWN2  0x0040 /* probably unused, or possibly OPL3 timer? */
 135  #define IRQ_UNKNOWN3  0x0080 /* probably unused, or possibly OPL3 timer? */
 136#define IDX_IO_66H              0x66    /* writing 0xffff returns 0x0000 */
 137  /* this is set to e.g. 0x3ff or 0x300, and writable;
 138   * maybe some buffer limit, but I couldn't find out more, PU:0x00ff: */
 139#define IDX_IO_SOME_VALUE       0x68
 140  #define IO_68_RANDOM_TOGGLE1  0x0100  /* toggles randomly */
 141  #define IO_68_RANDOM_TOGGLE2  0x0200  /* toggles randomly */
 142  /* umm, nope, behaviour of these bits changes depending on what we wrote
 143   * to 0x6b!!
 144   * And they change upon playback/stop, too:
 145   * Writing a value to 0x68 will display this exact value during playback,
 146   * too but when stopped it can fall back to a rather different
 147   * seemingly random value). Hmm, possibly this is a register which
 148   * has a remote shadow which needs proper device supply which only exists
 149   * in case playback is active? Or is this driver-induced?
 150   */
 151
 152/* this WORD can be set to have bits 0x0028 activated (FIXME: correct??);
 153 * actually inhibits PCM playback!!! maybe power management??: */
 154#define IDX_IO_6AH              0x6A /* WRITE_ONLY! */
 155  /* bit 5: enabling this will activate permanent counting of bytes 2/3
 156   * at gameport I/O (0xb402/3) (equal values each) and cause
 157   * gameport legacy I/O at 0x0200 to be _DISABLED_!
 158   * Is this Digital Enhanced Game Port Enable??? Or maybe it's Testmode
 159   * for Enhanced Digital Gameport (see 4D Wave DX card): */
 160  #define IO_6A_SOMETHING1_GAMEPORT     0x0020
 161  /* bit 8; sure, this _pauses_ playback (later resumes at same spot!),
 162   * but what the heck is this really about??: */
 163  #define IO_6A_PAUSE_PLAYBACK_BIT8     0x0100
 164  /* bit 9; sure, this _pauses_ playback (later resumes at same spot!),
 165   * but what the heck is this really about??: */
 166  #define IO_6A_PAUSE_PLAYBACK_BIT9     0x0200
 167        /* BIT8 and BIT9 are _NOT_ able to affect OPL3 MIDI playback,
 168         * thus it suggests influence on PCM only!!
 169         * However OTOH there seems to be no bit anywhere around here
 170         * which is able to disable OPL3... */
 171  /* bit 10: enabling this actually changes values at legacy gameport
 172   * I/O address (0x200); is this enabling of the Digital Enhanced Game Port???
 173   * Or maybe this simply switches off the NE558 circuit, since enabling this
 174   * still lets us evaluate button states, but not axis states */
 175  #define IO_6A_SOMETHING2_GAMEPORT      0x0400
 176        /* writing 0x0300: causes quite some crackling during
 177         * PC activity such as switching windows (PCI traffic??
 178         * --> FIFO/timing settings???) */
 179        /* writing 0x0100 plus/or 0x0200 inhibits playback */
 180        /* since the Windows .INF file has Flag_Enable_JoyStick and
 181         * Flag_Enable_SB_DOS_Emulation directly together, it stands to reason
 182         * that some other bit in this same register might be responsible
 183         * for SB DOS Emulation activation (note that the file did NOT define
 184         * a switch for OPL3!) */
 185#define IDX_IO_6CH              0x6C    /* unknown; fully read-writable */
 186#define IDX_IO_6EH              0x6E
 187        /* writing 0xffff returns 0x83fe (or 0x03fe only).
 188         * writing 0x83 (and only 0x83!!) to 0x6f will cause 0x6c to switch
 189         * from 0000 to ffff. */
 190
 191/* further I/O indices not saved/restored and not readable after writing,
 192 * so probably not used */
 193
 194
 195/*** Gameport area port indices ***/
 196/* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */ 
 197#define AZF_IO_SIZE_GAME                0x08
 198#define AZF_IO_SIZE_GAME_PM             0x06
 199
 200enum {
 201        AZF_GAME_LEGACY_IO_PORT = 0x200
 202};
 203
 204#define IDX_GAME_LEGACY_COMPATIBLE      0x00
 205        /* in some operation mode, writing anything to this port
 206         * triggers an interrupt:
 207         * yup, that's in case IDX_GAME_01H has one of the
 208         * axis measurement bits enabled
 209         * (and of course one needs to have GAME_HWCFG_IRQ_ENABLE, too) */
 210
 211#define IDX_GAME_AXES_CONFIG            0x01
 212        /* NOTE: layout of this register awfully similar (read: "identical??")
 213         * to AD1815JS.pdf (p.29) */
 214
 215  /* enables axis 1 (X axis) measurement: */
 216  #define GAME_AXES_ENABLE_1            0x01
 217  /* enables axis 2 (Y axis) measurement: */
 218  #define GAME_AXES_ENABLE_2            0x02
 219  /* enables axis 3 (X axis) measurement: */
 220  #define GAME_AXES_ENABLE_3            0x04
 221  /* enables axis 4 (Y axis) measurement: */
 222  #define GAME_AXES_ENABLE_4            0x08
 223  /* selects the current axis to read the measured value of
 224   * (at IDX_GAME_AXIS_VALUE):
 225   * 00 = axis 1, 01 = axis 2, 10 = axis 3, 11 = axis 4: */
 226  #define GAME_AXES_READ_MASK           0x30
 227  /* enable to have the latch continuously accept ADC values
 228   * (and continuously cause interrupts in case interrupts are enabled);
 229   * AD1815JS.pdf says it's ~16ms interval there: */
 230  #define GAME_AXES_LATCH_ENABLE        0x40
 231  /* joystick data (measured axes) ready for reading: */
 232  #define GAME_AXES_SAMPLING_READY      0x80
 233
 234  /* NOTE: other card specs (SiS960 and others!) state that the
 235   * game position latches should be frozen when reading and be freed
 236   * (== reset?) after reading!!!
 237   * Freezing most likely means disabling 0x40 (GAME_AXES_LATCH_ENABLE),
 238   *  but how to free the value? */
 239  /* An internet search for "gameport latch ADC" should provide some insight
 240   * into how to program such a gameport system. */
 241
 242  /* writing 0xf0 to 01H once reset both counters to 0, in some special mode!?
 243   * yup, in case 6AH 0x20 is not enabled
 244   * (and 0x40 is sufficient, 0xf0 is not needed) */
 245
 246#define IDX_GAME_AXIS_VALUE     0x02
 247        /* R: value of currently configured axis (word value!);
 248         * W: trigger axis measurement */
 249
 250#define IDX_GAME_HWCONFIG       0x04
 251        /* note: bits 4 to 7 are never set (== 0) when reading!
 252         * --> reserved bits? */
 253  /* enables IRQ notification upon axes measurement ready: */
 254  #define GAME_HWCFG_IRQ_ENABLE                 0x01
 255  /* these bits choose a different frequency for the
 256   *  internal ADC counter increment.
 257   * hmm, seems to be a combo of bits:
 258   * 00 --> standard frequency
 259   * 10 --> 1/2
 260   * 01 --> 1/20
 261   * 11 --> 1/200: */
 262  #define GAME_HWCFG_ADC_COUNTER_FREQ_MASK      0x06
 263
 264  /* FIXME: these values might be reversed... */
 265  #define GAME_HWCFG_ADC_COUNTER_FREQ_STD       0
 266  #define GAME_HWCFG_ADC_COUNTER_FREQ_1_2       1
 267  #define GAME_HWCFG_ADC_COUNTER_FREQ_1_20      2
 268  #define GAME_HWCFG_ADC_COUNTER_FREQ_1_200     3
 269
 270  /* enable gameport legacy I/O address (0x200)
 271   * I was unable to locate any configurability for a different address: */
 272  #define GAME_HWCFG_LEGACY_ADDRESS_ENABLE      0x08
 273
 274/*** MPU401 ***/
 275#define AZF_IO_SIZE_MPU         0x04
 276#define AZF_IO_SIZE_MPU_PM      0x04
 277
 278/*** OPL3 synth ***/
 279/* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */
 280#define AZF_IO_SIZE_OPL3        0x08
 281#define AZF_IO_SIZE_OPL3_PM     0x06
 282/* hmm, given that a standard OPL3 has 4 registers only,
 283 * there might be some enhanced functionality lurking at the end
 284 * (especially since register 0x04 has a "non-empty" value 0xfe) */
 285
 286/*** mixer I/O area port indices ***/
 287/* (only 0x22 of 0x40 bytes saved/restored by Windows driver)
 288 * UNFORTUNATELY azf3328 is NOT truly AC97 compliant: see main file intro */
 289#define AZF_IO_SIZE_MIXER       0x40
 290#define AZF_IO_SIZE_MIXER_PM    0x22
 291
 292  #define MIXER_VOLUME_RIGHT_MASK       0x001f
 293  #define MIXER_VOLUME_LEFT_MASK        0x1f00
 294  #define MIXER_MUTE_MASK               0x8000
 295#define IDX_MIXER_RESET         0x00 /* does NOT seem to have AC97 ID bits */
 296#define IDX_MIXER_PLAY_MASTER   0x02
 297#define IDX_MIXER_MODEMOUT      0x04
 298#define IDX_MIXER_BASSTREBLE    0x06
 299  #define MIXER_BASSTREBLE_TREBLE_VOLUME_MASK   0x000e
 300  #define MIXER_BASSTREBLE_BASS_VOLUME_MASK     0x0e00
 301#define IDX_MIXER_PCBEEP        0x08
 302#define IDX_MIXER_MODEMIN       0x0a
 303#define IDX_MIXER_MIC           0x0c
 304  #define MIXER_MIC_MICGAIN_20DB_ENHANCEMENT_MASK       0x0040
 305#define IDX_MIXER_LINEIN        0x0e
 306#define IDX_MIXER_CDAUDIO       0x10
 307#define IDX_MIXER_VIDEO         0x12
 308#define IDX_MIXER_AUX           0x14
 309#define IDX_MIXER_WAVEOUT       0x16
 310#define IDX_MIXER_FMSYNTH       0x18
 311#define IDX_MIXER_REC_SELECT    0x1a
 312  #define MIXER_REC_SELECT_MIC          0x00
 313  #define MIXER_REC_SELECT_CD           0x01
 314  #define MIXER_REC_SELECT_VIDEO        0x02
 315  #define MIXER_REC_SELECT_AUX          0x03
 316  #define MIXER_REC_SELECT_LINEIN       0x04
 317  #define MIXER_REC_SELECT_MIXSTEREO    0x05
 318  #define MIXER_REC_SELECT_MIXMONO      0x06
 319  #define MIXER_REC_SELECT_MONOIN       0x07
 320#define IDX_MIXER_REC_VOLUME    0x1c
 321#define IDX_MIXER_ADVCTL1       0x1e
 322  /* unlisted bits are unmodifiable */
 323  #define MIXER_ADVCTL1_3DWIDTH_MASK    0x000e
 324  #define MIXER_ADVCTL1_HIFI3D_MASK     0x0300 /* yup, this is missing the high bit that official AC97 contains, plus it doesn't have linear bit value range behaviour but instead acts weirdly (possibly we're dealing with two *different* 3D settings here??) */
 325#define IDX_MIXER_ADVCTL2       0x20 /* subset of AC97_GENERAL_PURPOSE reg! */
 326  /* unlisted bits are unmodifiable */
 327  #define MIXER_ADVCTL2_LPBK            0x0080 /* Loopback mode -- Win driver: "WaveOut3DBypass"? mutes WaveOut at LineOut */
 328  #define MIXER_ADVCTL2_MS              0x0100 /* Mic Select 0=Mic1, 1=Mic2 -- Win driver: "ModemOutSelect"?? */
 329  #define MIXER_ADVCTL2_MIX             0x0200 /* Mono output select 0=Mix, 1=Mic; Win driver: "MonoSelectSource"?? */
 330  #define MIXER_ADVCTL2_3D              0x2000 /* 3D Enhancement 1=on */
 331  #define MIXER_ADVCTL2_POP             0x8000 /* Pcm Out Path, 0=pre 3D, 1=post 3D */
 332  
 333#define IDX_MIXER_SOMETHING30H  0x30 /* used, but unknown??? */
 334
 335/* driver internal flags */
 336#define SET_CHAN_LEFT   1
 337#define SET_CHAN_RIGHT  2
 338
 339/* helper macro to align I/O port ranges to 32bit I/O width */
 340#define AZF_ALIGN(x) (((x) + 3) & (~3))
 341
 342#endif /* __SOUND_AZT3328_H  */
 343
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