linux/drivers/scsi/mesh.c
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   1/*
   2 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
   3 * bus adaptor found on Power Macintosh computers.
   4 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
   5 * controller.
   6 *
   7 * Paul Mackerras, August 1996.
   8 * Copyright (C) 1996 Paul Mackerras.
   9 *
  10 * Apr. 21 2002  - BenH         Rework bus reset code for new error handler
  11 *                              Add delay after initial bus reset
  12 *                              Add module parameters
  13 *
  14 * Sep. 27 2003  - BenH         Move to new driver model, fix some write posting
  15 *                              issues
  16 * To do:
  17 * - handle aborts correctly
  18 * - retry arbitration if lost (unless higher levels do this for us)
  19 * - power down the chip when no device is detected
  20 */
  21#include <linux/module.h>
  22#include <linux/kernel.h>
  23#include <linux/delay.h>
  24#include <linux/types.h>
  25#include <linux/string.h>
  26#include <linux/blkdev.h>
  27#include <linux/proc_fs.h>
  28#include <linux/stat.h>
  29#include <linux/interrupt.h>
  30#include <linux/reboot.h>
  31#include <linux/spinlock.h>
  32#include <asm/dbdma.h>
  33#include <asm/io.h>
  34#include <asm/pgtable.h>
  35#include <asm/prom.h>
  36#include <asm/irq.h>
  37#include <asm/hydra.h>
  38#include <asm/processor.h>
  39#include <asm/machdep.h>
  40#include <asm/pmac_feature.h>
  41#include <asm/pci-bridge.h>
  42#include <asm/macio.h>
  43
  44#include <scsi/scsi.h>
  45#include <scsi/scsi_cmnd.h>
  46#include <scsi/scsi_device.h>
  47#include <scsi/scsi_host.h>
  48
  49#include "mesh.h"
  50
  51#if 1
  52#undef KERN_DEBUG
  53#define KERN_DEBUG KERN_WARNING
  54#endif
  55
  56MODULE_AUTHOR("Paul Mackerras (paulus@samba.org)");
  57MODULE_DESCRIPTION("PowerMac MESH SCSI driver");
  58MODULE_LICENSE("GPL");
  59
  60static int sync_rate = CONFIG_SCSI_MESH_SYNC_RATE;
  61static int sync_targets = 0xff;
  62static int resel_targets = 0xff;
  63static int debug_targets = 0;   /* print debug for these targets */
  64static int init_reset_delay = CONFIG_SCSI_MESH_RESET_DELAY_MS;
  65
  66module_param(sync_rate, int, 0);
  67MODULE_PARM_DESC(sync_rate, "Synchronous rate (0..10, 0=async)");
  68module_param(sync_targets, int, 0);
  69MODULE_PARM_DESC(sync_targets, "Bitmask of targets allowed to set synchronous");
  70module_param(resel_targets, int, 0);
  71MODULE_PARM_DESC(resel_targets, "Bitmask of targets allowed to set disconnect");
  72module_param(debug_targets, int, 0644);
  73MODULE_PARM_DESC(debug_targets, "Bitmask of debugged targets");
  74module_param(init_reset_delay, int, 0);
  75MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
  76
  77static int mesh_sync_period = 100;
  78static int mesh_sync_offset = 0;
  79static unsigned char use_active_neg = 0;  /* bit mask for SEQ_ACTIVE_NEG if used */
  80
  81#define ALLOW_SYNC(tgt)         ((sync_targets >> (tgt)) & 1)
  82#define ALLOW_RESEL(tgt)        ((resel_targets >> (tgt)) & 1)
  83#define ALLOW_DEBUG(tgt)        ((debug_targets >> (tgt)) & 1)
  84#define DEBUG_TARGET(cmd)       ((cmd) && ALLOW_DEBUG((cmd)->device->id))
  85
  86#undef MESH_DBG
  87#define N_DBG_LOG       50
  88#define N_DBG_SLOG      20
  89#define NUM_DBG_EVENTS  13
  90#undef  DBG_USE_TB              /* bombs on 601 */
  91
  92struct dbglog {
  93        char    *fmt;
  94        u32     tb;
  95        u8      phase;
  96        u8      bs0;
  97        u8      bs1;
  98        u8      tgt;
  99        int     d;
 100};
 101
 102enum mesh_phase {
 103        idle,
 104        arbitrating,
 105        selecting,
 106        commanding,
 107        dataing,
 108        statusing,
 109        busfreeing,
 110        disconnecting,
 111        reselecting,
 112        sleeping
 113};
 114
 115enum msg_phase {
 116        msg_none,
 117        msg_out,
 118        msg_out_xxx,
 119        msg_out_last,
 120        msg_in,
 121        msg_in_bad,
 122};
 123
 124enum sdtr_phase {
 125        do_sdtr,
 126        sdtr_sent,
 127        sdtr_done
 128};
 129
 130struct mesh_target {
 131        enum sdtr_phase sdtr_state;
 132        int     sync_params;
 133        int     data_goes_out;          /* guess as to data direction */
 134        struct scsi_cmnd *current_req;
 135        u32     saved_ptr;
 136#ifdef MESH_DBG
 137        int     log_ix;
 138        int     n_log;
 139        struct dbglog log[N_DBG_LOG];
 140#endif
 141};
 142
 143struct mesh_state {
 144        volatile struct mesh_regs __iomem *mesh;
 145        int     meshintr;
 146        volatile struct dbdma_regs __iomem *dma;
 147        int     dmaintr;
 148        struct  Scsi_Host *host;
 149        struct  mesh_state *next;
 150        struct scsi_cmnd *request_q;
 151        struct scsi_cmnd *request_qtail;
 152        enum mesh_phase phase;          /* what we're currently trying to do */
 153        enum msg_phase msgphase;
 154        int     conn_tgt;               /* target we're connected to */
 155        struct scsi_cmnd *current_req;          /* req we're currently working on */
 156        int     data_ptr;
 157        int     dma_started;
 158        int     dma_count;
 159        int     stat;
 160        int     aborting;
 161        int     expect_reply;
 162        int     n_msgin;
 163        u8      msgin[16];
 164        int     n_msgout;
 165        int     last_n_msgout;
 166        u8      msgout[16];
 167        struct dbdma_cmd *dma_cmds;     /* space for dbdma commands, aligned */
 168        dma_addr_t dma_cmd_bus;
 169        void    *dma_cmd_space;
 170        int     dma_cmd_size;
 171        int     clk_freq;
 172        struct mesh_target tgts[8];
 173        struct macio_dev *mdev;
 174        struct pci_dev* pdev;
 175#ifdef MESH_DBG
 176        int     log_ix;
 177        int     n_log;
 178        struct dbglog log[N_DBG_SLOG];
 179#endif
 180};
 181
 182/*
 183 * Driver is too messy, we need a few prototypes...
 184 */
 185static void mesh_done(struct mesh_state *ms, int start_next);
 186static void mesh_interrupt(struct mesh_state *ms);
 187static void cmd_complete(struct mesh_state *ms);
 188static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd);
 189static void halt_dma(struct mesh_state *ms);
 190static void phase_mismatch(struct mesh_state *ms);
 191
 192
 193/*
 194 * Some debugging & logging routines
#de1imesh.19L76" id="L76" class="line" name="L761">bs01;
 175#ifdef MES">bs11;
tgt1;
 175#ifdindriva href="+code=dbglogme="L135"> 135        e=scsi_cmnd" clasad class="sref">u32asad case_m clat;d;2mesh_s2100};2 135        e=scsi_cmnd" cl class="sref">u32       90#undef  dmBeware:="coyou enable this> *t will crash       s.mesh.c#L2" na2s="s3/5ef=hase_mismatch2ting,2MODULmftb %0quot;Initial  :delay" class="sref">init_res=s="string">&qu" class="sref">debclass="sref">u32  ) :d> *u32  offset" class="sref">mesh_sync_offse2aing,2 1792sing,2u32     set_dma_cmds(struct mesh_state  clas=mesh_state" cla>  93        char    > *static voref="t;mesh_s2113};2 172        struct u32  off>mesh_statemesh_target mesh_state 154        int     N_DBG_2> 1142 178        struct u32 =mesh_state" claslplass="sref">u32slp    =N_DBG_SLOG" class="sref">N_DBG_2>ing,2u32u32  ef="+code=device" cl" class="sref">dbglog u32  ef="+code=device" cl" c176        int     N_DBG_2>ing,2u32slp    off>mesh_statedbglog mesh_state        int     N_DBG_2>ing,2u32  93        char    _delay" class="sre>  93        char    *u32u32  offe=scsi_cmnd" clasad class="sref">u32asad case_m> *u32mesh_phase dess="sref">mesh_statemsg_phase mesh_stateu8      2_bad,2u32u8     offe=scsi_cmnd" clss="sref">mesh_state__iomem *u82_ping2u32u8     offe=scsi_cmnd" clss="sref">mesh_state__iomem *u82_13};2u32u8     offe=scsi_cmnd" clss="sref">mesh_state 154        int     2_ 1142u32  99        intoffe=scsi_cmnd" cl189static voref="+ref="+code=phase" class="sref">2_ing,2u32slp    off=mesh_state" clatlplass="sref">u322_one,2u32  ef="+code=device" cl" c176        int     log[u32  ef="+code=device" cl" c176        int     mesh_sync_offse2128};2u32  ef="+code=device" cl"> 177        int     log[u32  ef="+code=device" cl"> 177        int     2get {2mesh_state        int     log[mesh_state        int     mesh_sync_offse2rams;2mesh_state 177        int     log[mesh_state 177        int     mesh_sync_offse2r 1142set_dma_cmds(struct mesh_state *u8mesh_s2_log;2 172        struct u32  off>mesh_statemesh_target u8N_DBG_2LOG];2 178        struct u32lp    +ref="+code=phase" class="sref">2/a>#endif2u32i    +ref="+code=phase" class="sref">2/bad,2u32  ef="+code=device" cl"> 177        int     2/ 1142u32i    offe=scsi_cmnd" cltplass="sref">u32  ef="+code=device" cl" c176        int     u32  ef="+code=device" cl"> 177        int     mesh_sync_offse2intr;2u32i    oclasfst;u32i    o+ffe=scsi_cmnd" cllog" class="sref">log[mesh_sync_offse2idone2u32  ef="+code=device" cl"> 177        int     mesh_sync_offse2host;2mesh_s2next;2u32lp    off>u32  ef="+code=device" cl" class="sref">dbglog u32i    e=N_DBG_SLOG" class="sref">N_DBG_2st_q;2u8 etstmesh_state" claKERN>cmd) && KERN>cmdMODULm>N_n cl %d: bs=%.2x%.2x ph=%.2x ="string">&quode=sdtr_sent" class="sref">sdtr2tail;2u8u32lp    ef="+code=device" cl class="sref">u8     , mesh_state" clalplass="sref">u32lp    ef="+code=device" cl class="sref">u8     , mesh_state" clalplass="sref">u32lp    ef="+code=device" cl class="sref">u8       *  90#undef  u8 etstmICENSE" class="sref">MODULtb=%10u ="string">&quo mesh_state" clalplass="sref">u32lp    ef="+code=device" clbclass="sref">u32  ) * 1792*/2u8 etstmesh_state" clalplass="sref">u32lp    ef="+code=device" cl>  93        char    > mesh_state" clalplass="sref">u32lp    ef="+code=device" cl">  99        int) *u8 etstmICENSE" class="sref">MODUL\nquot;Initial bus reset delay (0=no reset)"2rted;2u32i    octarffe=scsi_cmnd" cllog" class="sref">log[u32i    offset" class="sref">mesh_sync_offse2stat;2u32i    o!ffe=scsi_cmnd" cltplass="sref">u32  ef="+code=device" cl" c176        int     ;2set_dma_cmds(struct mesh_statemesh_s2gout;2 178        struct u32lp    +ref="+code=phase" class="sref">2gout;2u32i    +ref="+code=phase" class="sref">2[16];22;2mesh_state 177        int     2pace;2u32i    offe=scsi_cmnd" clss="sref">mesh_state        int     mesh_state 177        int     mesh_sync_offse2size;2u32i    oclasfst;u32i    o+ffe=scsi_cmnd" cllog" class="sref">log[mesh_sync_offse2sgin;2mesh_state 177        int     mesh_sync_offse2mdev;2mesh_s2pdev;2u32lp    off>mesh_statedbglog u32i    e=N_DBG_SLOG" class="sref">N_DBG_2H_DBG2u8 etstmesh_state" claKERN>cmd) && KERN>cmdMODULm>N_n cl: bs=%.2x%.2x ph=%.2x t%d ="string">&quode=sdtr_sent" class="sref">sdtr2g_ix;2u32lp    ef="+code=device" cl class="sref">u8     , mesh_state" clalplass="sref">u32lp    ef="+code=device" cl class="sref">u8     , mesh_state" clalplass="sref">u32lp    ef="+code=device" cl class="sref">u8      u32lp    ef="+code=device" clbclass="sref">u8     bus reset delay (0=no reset)"2_log;2  90#undef  u8 etstmICENSE" class="sref">MODULtb=%10u ="string">&quo mesh_state" clalplass="sref">u32lp    ef="+code=device" clbclass="sref">u32  ) * 1402180};2u8 etstmesh_state" clalplass="sref">u32lp    ef="+code=device" cl>  93        char    > mesh_state" clalplass="sref">u32lp    ef="+code=device" cl">  99        int) *u8 etstmICENSE" class="sref">MODUL\nquot;Initial bus reset delay (0=no reset)"2/*2u32i    octarffe=scsi_cmnd" cllog" class="sref">log[u32i    offset" class="sref">mesh_sync_offse2*/2u32i    o!ffe=scsi_cmnd" clss="sref">mesh_state        int     22>ms);2 175#ifdindriva hre class="line" name="d 178        strlogt_dma_cmds" class="sref">set_dma_cmds(struct mesh_state  clas=mesh_state" cla>  93        char    > *static voref="t; 175#ifdindriva hre class="line" name="dump 178        strump 17t_dma_cmds" class="sref">set_dma_cmds(struct mesh_state *u8     b   175#ifdindriva hre class="line" name="dumps 178        strumps 17t_dma_cmds" class="sref">set_dma_cmds(struct mesh_state#de12mesh.29L76" id="L76" class="line" name="L762">bs02;
dmef bs12;
tgt2;
mesh_staKWORDtmesh_state" cla189static voref="> mesh_state" claclass="sref">u32bef="> mesh_state" claclass="sref">u32cef="> mesh_state" cla">  99        int)L132" ((tmesh_state" cla189static voref=") clasclas 24) + (tmesh_state" claclass="sref">u32bef=") clasclas 16) + (tmesh_state" claclass="sref">u32cef=") clasclas 8) + (mesh_state" cla">  99        int)t;d;3setrump      volatile struct t_dma_cmds" class="sref">set_dma_cmds(struct mesh_statemesh_s3a4e {3 144        volatile struct mesh_regs         int   r    offe=scsi_cmnd" clss="sref">mesh_state__iomem *,3 146        volatile struct dbdma_regs scsi_cmm  intoffe=scsi_cmnd" clss="sref">mesh_state__iomem *u8 172        struct u32  *u8 etstmesh_state" claKERN>cmd) && KERN>cmdMODULm>N_: ref=" at %p, ef=" at %p,     at %p\nquot;Initial ode=sdtr_sent" class="sref">sdtr3eing,3mesh_state +code=__iomem" c/a>        int   r    > +code=__iomem" cs="sref">scsi_cmm  intbus reset delay (0=no reset)"3e00};3u8 etstmesh_state" claKERN>cmd) && KERN>cmdMODUL21" ct=%4x seq=%2x bs=%4x fc=%2x quot;Initial s reset delay (0=no reset)"3e2>d;3MODULexc=%2x err=%2x im=%2x int=%2x sp=%2x\nquot;Initial ode=sdtr_sent" class="sref">sdtr3ese {3        int   r    ef="+code=device" cl">unt_hilass="sref">u32">unt_hi    oclasclas 8) + class="line" nas/a>        int   r    ef="+code=device" cl">unt_lolass="sref">u32">unt_loe +code=__iomem" c/a>        int   r    ef="+code=device" clshrefn      void    *de=sdtr_sent" class="sref">sdtr3e4e {3        int   r    ef="+code=device" cl us_  u8        int   r    ef="+code=device" cl us_  u8 +code=__iomem" c/a>        int   r    ef="+code=device" clfifo158        int   fifo158de=sdtr_sent" class="sref">sdtr3eing,3        int   r    ef="+code=device" clexceptioss="sref">u8exceptios  +code=__iomem" c/a>        int   r    ef="+code=device" clerro/a>        int  erro/  +code=__iomem" c/a>        int   r    ef="+code=device" cl u8  +code=__iomem" c/a>        int   r    ef="+code=device" cl static void de=sdtr_sent" class="sref">sdtr3eing,3        int   r    ef="+code=device" clsync_parass="sref">mesh_stsync_parass intbus reset delay (0=no reset)"3e7ng,3 166t>        int   r    ef="+code=device" clfifo158        int   fifo158u8 etstmesh_state" claKERN>cmd) && KERN>cmdMODUL2fifo    <=%.2x\nquot;Initial oclass="line" nain_e="L166"> 166t>        int   r    ef="+code=device" clfifo>        int   fifoe,3u8 etstmesh_state" claKERN>cmd) && KERN>cmdMODUL21"       sdtr3last,3 135in_lee=t>scsi_cmm  intef="+code=device" cls mesh_sts  +code=__iomem" in_lee="L135"> 135in_lee=t>scsi_cmm  intef="+code=device" clcmdptrlass="sref">u32"mdptre,3u8 etstmesh_state" claKERN>cmd) && KERN>cmdMODUL21"      =%d a> sdtr3l2>d;3mesh_stateu8      mesh_statemsg_phase mesh_state 154        int     mesh_state 156        int     u8 etstmesh_state" claKERN>cmd) && KERN>cmdMODUL21"    _  =%d  f="+ =%d ="+code==%d\nquot;Initial ode=sdtr_sent" class="sref">sdtr3l4e {3mesh_state        int     mesh_state 158        int     mesh_state 164        int     (class="line" natass="sref">u8u8u8mesh_s3_ing,3u32  off>mesh_statemesh_target u8N_DBG_3_one,3u32  ef="+code=device" clcurrent_1        int   urrent_1  offfe=scsi_cmnd" cllULLa>        int  lULLeN_DBG_3_ing,3u8 etstmesh_state" claKERN>cmd) && KERN>cmdMODUL21" ef="+c %d: req=%p goes_de==%d saveda hr=%d\nquot;Initial ode=sdtr_sent" class="sref">sdtr3> 1293u8u32  ef="+code=device" clcurrent_1        int   urrent_1  o mesh_state" clatplass="sref">u32  ef="+code=device" cl           int       o mesh_state" clatplass="sref">u32  ef="+code=device" clsaveda hr="sref">mesh_stsaveda href="tus reset delay (0=no reset)"3get {3}   193;3 "L193"> 193,3 175#ifdindriva hre class="line" name="        int   tclass="line" name="L144"> 144        volatile struct mesh_regs         int   r    t;mesh_s3LOG];3 166t>        int   r    ef="+code=device" clt scsi_cmm  1933 193;3scsi_cmm set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd * na2s="s3/5ef=hase_mismatch3adone3mesh_s3host;3scsi_cmnd ef="+code=device" cls  185static vois  18/a> *tmesh_state" clacss="sref">scsi_cmnd *;3 *scsi_cmm t_dma_cmds" class="sref">set_dma_cmds(struct mesh_statemesh_s3ount;3 144        volatile struct mesh_regs         int   r    offe=scsi_cmnd" clss="sref">mesh_state__iomem *;3 146        volatile struct dbdma_regs scsi_cmm  intoffe=scsi_cmnd" clss="sref">mesh_state__iomem *        int   t+code=__iomem" c/a>        int   r    t*        int  udelayt100t* 135out_lee=t>scsi_cmm  intef="+code=device" clc  trola>        int     trole t+code=__iomem" RUNa>        int  RUNe        int  PAUSEe        int  FLUSHe        int  WAKE+cod)eclasclas 16);5" ="L193" class="line" nam stop     msh.c#L2" na2s="s3/5ef=hase_mismatch3g_DBG3 166t>        int   r    ef="+code=device" clexceptioss="sref">u8exceptios  0xff);5"  ="L193" class="line" nam clear all exceptios bits msh.c#L2" na2s="s3/5ef=hase_mismatch3gted;3 166t>        int   r    ef="+code=device" clerro/a>        int  erro/  0xff);5"  5"  ="L193" class="line" nam clear all erro/ bits msh.c#L2" na2s="s3/5ef=hase_mismatch3gunt;3 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_RESETef <    void    *        int   t+code=__iomem" c/a>        int   r    t*        int  udelayt10t* 166t>        int   r    ef="+code=device" cl u8  +code=__iomem" INT_ERRORs="sref">u8INT_ERROR" id=| +code=__iomem" INT_EXCEPTIONa>        int  INT_EXCEPTION" id=| +code=__iomem" INT_CMDDONEa>        int  INT_CMDDONE    t* 166t>        int   r    ef="+code=device" clsource is="sref">scsi_cmsource is  +code=__iomem" ss="sref">mesh_statescsi_cmhostescsi_cmshis is    t* 166t>        int   r    ef="+code=device" clshl_timede=a>        int  shl_timede=  25);5"  ="L193" class="line" nam 250ms msh.c#L2" na2s="s3/5ef=hase_mismatch3pdev;3 166t>        int   r    ef="+code=device" clsync_parass="sref">mesh_stsync_parass int> +code=__iomem" ASYNC_PARAMS="sref">mesh_stASYNC_PARAMS    t*        int  init_1mesh_s3_log;3u8 etstmesh_state" claKERN>INFOs="sref">u8KERN>INFO+code=ICENSE" class="sref">MODULm>N_: performsre *];3#endif3 166t>        int   r    ef="+code=device" cl us_  u8 +code=__iomem" BS1_RSTass="sref">u8        int   t+code=__iomem" c/a>        int   r    t*        int  udelayt30);5"  5"  118" ="L125" m"L193" class="line" nam leave it    ctarff25us msh.c#L2" na2s="s3/5ef=hase_mismatch31ase;3 166t>        int   r    ef="+code=device" cl us_  u8 0);5"  5m"L193" class="line" nam negf=" RST msh.c#L2" na2s="s3/5ef=hase_mismatch31dev;3        int   t+code=__iomem" c/a>        int   r    t*bus to erse back msh.c#L2" na2s="s3/5ef=hase_mismatch31log;3u32msleept+code=__iomem" init_1        int  init_1 166t>        int   r    ef="+code=device" cl static void  0xff);5"  ="L193" class="line" nam clear all "+code=me bits msh.c#L2" na2s="s3/5ef=hase_mismatch3>*3 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_FLUSHFIFOs="sref">u8SEQ_FLUSHFIFO+cod)*        int   t+code=__iomem" c/a>        int   r    t*        int  udelayt1t*#de13mesh.396" id="L176" class="line" naout_e="L166"> 166t>        int   r    ef="+code=device" clsync_parass="sref">mesh_stsync_parass int> +code=__iomem" ASYNC_PARAMS="sref">mesh_stASYNC_PARAMS    t*bs03;
 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_ENBRESELa>        int  SEQ_ENBRESEL    t*;3;
tgt3;
mesh_stateu8       175#ifdidlv/a> *d;4mesh_statemsg_phase static voissg_n 18/a> *scsi_cmm set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd * na2s="s3/5ef=hase_mismatch4ting,4mesh_s4ting,4 144        volatile struct mesh_regs         int   r    offe=scsi_cmnd" clss="sref">mesh_state__iomem *mesh_s4t7ng,4<
u8 +code=__iomem" is="sref">scsi_cmis    us reset delaclass="sref">mesh_s4t8ng,4<
scsi_cmis    offe=scsi_cmnd" class="sref">scsi_cmnd ef="+code=device" cldevi      void    *scsi_cmis    us reset delaclass="sref">mesh_s4eing,4mesh_state        int   urrent_1  offe=scsi_cmnd" class="sref">scsi_cmnd us reset delaclass="sref">mesh_s4e1>d;4mesh_statemesh_target scsi_cmis    ].code=device" cld          int       offe=scsi_cmnd" class="sref">scsi_cmnd ef="+code=device" clsc_   u8sc_     offfe=scsi_cmnd" clDMA_TO_DEVICEa>        int  DMA_TO_DEVICE/a> us reset delaclass="sref">mesh_s4e2>d;4mesh_statemesh_target scsi_cmis    ].code=device" clcurrent_1        int   urrent_1  offe=scsi_cmnd" class="sref">scsi_cmnd us reset delaclass="sref">mesh_s4ese {4u8t+code=__iomem" ass="sref">scsi_cmnd *)e=mesh_state" class="sref">mesh_s4eing,4u32i    +ref="+code=phase" class="sref">4e7ng,4u8 etstmesh_state" claKERN>cmd) && KERN>cmdMODULm>N_ ref=": %p  hr=%d nd<=="string">&quo mesh_state" claass="sref">scsi_cmnd > +code=__iomem" is="sref">scsi_cmis    t*(class="line" nailass="sref">u32i    offsesmesh_state" clailass="sref">u32i    oclasfe=scsi_cmnd" class="sref">scsi_cmnd ef="+code=device" clnd<_less="sref">u8nd<_les    + ++u32i    * na2s="s3/5ef=hase_mismatch4eing,4u8 etstmICENSE" class="sref">MODUL2%x="string">&quo mesh_state" claass="sref">scsi_cmnd ef="+code=device" clndef">ms, struchref="+c u32i    et*u8 etstmICENSE" class="sref">MODUL2use_sg=%d buffn =%p buffles=%u\nquot;Initial ode=sdtr_sent" class="sref">sdtr4g_in,4        int   t t+code=__iomem" ass="sref">scsi_cmnd *o mesh_state" clat scsi_cmt t+code=__iomem" ass="sref">scsi_cmnd *o mesh_state" clat scsi_cmt t+code=__iomem" ass="sref">scsi_cmnd *)* 1404l4e {4mesh_state        int     4ging,4u32ialictmICENSE" class="sref">MODULm>N_: double DMA ref=" !\nquot;Initial bus reset delay (0=no reset)"4_ing,4mesh_stateu8      u8arbitratsre    +ref="+code=phase" class="sref">4_done4mesh_statemsg_phase static voissg_n 18/a> *mesh_state 156        int     mesh_sync_offse4> 1294mesh_state        int     mesh_sync_offse4>_in,4mesh_state 164        int     mesh_sync_offse4>2>d;4mesh_state 164        int  reft_"> 164mesh_sync_offse4>se {4mesh_state        int  expect_1mesh_sync_offse4>4e {4mesh_state 154        int     scsi_cmis    us reset delaclass="sref">mesh_s4>ing,4mesh_statemesh_target scsi_cmis    ].code=device" clsaveda hr="sref">mesh_stsaveda href="offset" class="sref">mesh_sync_offse4>ing,4mesh_statemesh_stsef=ef="offe=scsi_cmnd" clDID_OKass="sref">u8mesh_s4>one,4mesh_stateu8abortsreef="offset" class="sref">mesh_sync_offse4>done4u8ef mesh_statemesh_target scsi_cmis    ].code=device" cln_ 178        stn_ 17ef="offset" class="sref">mesh_sync_offse4LOG];4        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULref=" nd<==#37;x="string">&quo (int) mesh_state" claass="sref">scsi_cmnd bus reset delay (0=no reset)"4/a>#endif4 1404/bad,4        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULabout to arb> *sdtr4/ 1144mesh_staKWORDtmesh_state" clas/a>        int   r    ef="+code=device" cl static void  mesh_state" clas/a>        int   r    ef="+code=device" clexceptioss="sref">u8exceptios  +code=__iomem" c/a>        int   r    ef="+code=device" clerro/a>        int  erro/  +code=__iomem" c/a>        int   r    ef="+code=device" clfifo158        int   fifo158,4 166t>        int   r    ef="+code=device" cl static void  mesh_state" claINT_CMDDONEa>        int  INT_CMDDONE    t* 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_ENBRESELa>        int  SEQ_ENBRESEL    t*        int   t+code=__iomem" c/a>        int   r    t*        int  udelayt1t* 166t>        int   r    ef="+code=device" cl us_  u8u8        int  BS1_SEL/a> *)e=mesh_state" class="sref">mesh_s4tail;4 1934it -e="L193"> 193 {4        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULbusy b4 arb> *sdtr4*_DBG4mesh_staKWORDtmesh_state" clas/a>        int   r    ef="+code=device" cl static void  mesh_state" clas/a>        int   r    ef="+code=device" clexceptioss="sref">u8exceptios de=sdtr_sent" class="sref">sdtr4*done4        int   r    ef="+code=device" clerro/a>        int  erro/  +code=__iomem" c/a>        int   r    ef="+code=device" clfifo158        int   fifo158;4(class="line" natass="sref">u8u8u8mesh_s4stat;4 166t>        int   r    ef="+code=device" cl us_  u8u8        int  BS1_SEL/a> *)offf0* na2s="s3/5ef=hase_mismatch4st_q;4;4 166t>        int   r    ef="+code=device" cl static void mesh_s4s/4        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODUL* *sdtr4sase;4mesh_staKWORDtmesh_state" clas/a>        int   r    ef="+code=device" cl static void  mesh_state" clas/a>        int   r    ef="+code=device" clexceptioss="sref">u8exceptios de=sdtr_sent" class="sref">sdtr4gout;4        int   r    ef="+code=device" clerro/a>        int  erro/  +code=__iomem" c/a>        int   r    ef="+code=device" clfifo158        int   fifo158;4static void tmesh_state" class="sref">mesh_state4mesh_stateu8      u8arbitratsre    * na2s="s3/5ef=hase_mismatch4sdone4;4        int  udelayt1t* 166t>        int   r    ef="+code=device" cl us_  u8u8        int  BS1_SEL/a> *)e=mesh_state" class="sref">mesh_s4s/4mesh_statemesh_stsef=ef="offe=scsi_cmnd" clDID_BUS_BUSYass="sref">u8mesh_s4pdev;4mesh_stateu8       175#ifdidlv/a> * 185static voice 18tmesh_state" class="sref">mesh_state 0t* 166t>        int   r    ef="+code=device" cldest is="sref">scsi_cmdest is  +code=__iomem" c/a>        int   r    ef="+code=device" clsource is="sref">scsi_cmsource is the bus to bd freeh.c#L2" na2s="s3/5ef=hase_mismatch4>ply;4#de14mesh.49L76" ="L194" class="line" na"L132" =* is srysre to 1tgt4;
 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_DISRESELa>        int  SEQ_DISRESEL d;5 166t>        int   r    ef="+code=device" cl static void mesh_s5f1>d;5        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODUL* *sdtr5f2>d;5mesh_staKWORDtmesh_state" clas/a>        int   r    ef="+code=device" cl static void  mesh_state" clas/a>        int   r    ef="+code=device" clexceptioss="sref">u8exceptios de=sdtr_sent" class="sref">sdtr5f3>d;5        int   r    ef="+code=device" clerro/a>        int  erro/  +code=__iomem" c/a>        int   r    ef="+code=device" clfifo158        int   fifo158 {5static void tmesh_state" class="sref">mesh_state,5mesh_stateu8      u8arbitratsre    * na2s="s3/5ef=hase_mismatch5ting,5,5<
        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULafter i *sdtr5f8ng,5<
mesh_staKWORDtmesh_state" clas/a>        int   r    ef="+code=device" cl static void  mesh_state" clas/a>        int   r    ef="+code=device" clexceptioss="sref">u8exceptios de=sdtr_sent" class="sref">sdtr5f9ng,5<
        int   r    ef="+code=device" clerro/a>        int  erro/  +code=__iomem" c/a>        int   r    ef="+code=device" clfifo158        int   fifo158,5 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_ARBITRATEa>        int  SEQ_ARBITRATEe {5(class="line" natass="sref">u8u8u8mesh_s5eing,5 166t>        int   r    ef="+code=device" cl static void mesh_s5eing,5,5        int  udelayt1t*        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULafter arb> *sdtr5last,5mesh_staKWORDtmesh_state" clas/a>        int   r    ef="+code=device" cl static void  mesh_state" clas/a>        int   r    ef="+code=device" clexceptioss="sref">u8exceptios  class="line" nac/a>        int   r    ef="+code=device" clerro/a>        int  erro/  +code=__iomem" c/a>        int   r    ef="+code=device" clfifo158        int   fifo158,5 166t>        int   r    ef="+code=device" cl static void  166t>        int   r    ef="+code=device" cl us_  u8        int  BS1_SEL/a> *s reset delay (0=no reset)"5g2>d;5 166t>        int   r    ef="+code=device" cl us_  u8u8BS0_IOemesh_s5gse {5        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODUL1 *sdtr5ling,5mesh_staKWORDtmesh_state" clas/a>        int   r    ef="+code=device" cl static void  mesh_state" clas/a>        int   r    ef="+code=device" clexceptioss="sref">u8exceptios  class="line" nac/a>        int   r    ef="+code=device" clerro/a>        int  erro/  +code=__iomem" c/a>        int   r    ef="+code=device" clfifo158        int   fifo158,5 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_RESETef         int  SEQ_RESETef ,5        int   t+code=__iomem" c/a>        int   r    t*        int  udelayt10t* 166t>        int   r    ef="+code=device" cl static void  mesh_state" claINT_ERRORstatic void         int  INT_CMDDONE    t* 166t>        int   r    ef="+code=device" cl u8  mesh_state" claINT_ERRORstatic void         int  INT_CMDDONE    t* 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_ENBRESELa>        int  SEQ_ENBRESEL    t*        int   t+code=__iomem" c/a>        int   r    t*(class="line" natass="sref">u8u8 166t>        int   r    ef="+code=device" cl static void u8        int  udelayt1t*        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODUL="sed res+c after arb> *sdtr5>ing,5mesh_staKWORDtmesh_state" clas/a>        int   r    ef="+code=device" cl static void  mesh_state" clas/a>        int   r    ef="+code=device" clexceptioss="sref">u8exceptios  class="line" nac/a>        int   r    ef="+code=device" clerro/a>        int  erro/  +code=__iomem" c/a>        int   r    ef="+code=device" clfifo158        int   fifo158one,5mesh_stef  166t>        int   r    ef="+code=device" cl static void  166t>        int   r    ef="+code=device" cl us_  u8        int  BS1_SEL/a> *s reset delay (0=no reset)"5_log;5 166t>        int   r    ef="+code=device" cl us_  u8u8BS0_IOemesh_s5LOG];5u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_: comesh_s5L_in,5MODUL2to 1,5 1405next;5tne" name="L144"> 144     static voicemesh_state5mesh_s5ount;5 144ms, struc"sre_ndef" id=*mesh_state" claass="sref">scsi_cmnd > *mesh_state" claprevs="sref">u8 eev/a> > *mesh_state" clanexts="sref">u8next/a> us reset delay (0=no reset)"5stat;5mesh_stateu8       175#ifdidlv/a>  || +code=__iomem" mesh_state        int   urrent_1  o!ffe=scsi_cmnd" clNULLa>        int  NULL mesh_s5eply;5u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULinappro etate sdtr5s/5mesh_stateu8       +code=__iomem" cs="sref">mesh_state;5;5mesh_stateu8       175#ifdidlv/a> )f=mesh_state" class="sref">mesh_s5edone5u8 eev/a> offe=scsi_cmnd" clNULLa>        int  NULL ;5(class="line" naass="sref">scsi_cmnd offe=scsi_cmnd" clss="sref">mesh_state        int  rhrefst_/ scsi_cmnd offtne" name="L144"> 144ms, struc"sre_ndef" id=*) mesh_state" claass="sref">scsi_cmnd ef="+code=device" clhost_scribblver> 175#ifdhost_scribblv/a> )f=mesh_state" class="sref">mesh_s5pace;5scsi_cmnd offfe=scsi_cmnd" clNULLa>        int  NULL mesh_s5pt_q;5;5mesh_statemesh_target scsi_cmnd ef="+code=device" cldevi  8        strevi      ef="+code=device" cl s="sref">scsi_cmis    ].code=device" clcurrent_1        int   urrent_1  offfe=scsi_cmnd" clNULLa>        int  NULL mesh_s5p/5;5u8 eev/a> offe=scsi_cmnd" class="sref">scsi_cmnd us reset delay (0=no reset)"5sout;5u8next/a> offtne" name="L144"> 144ms, struc"sre_ndef" id=*) mesh_state" claass="sref">scsi_cmnd ef="+code=device" clhost_scribblver> 175#ifdhost_scribblv/a> us reset delay (0=no reset)"5s_DBG5u8 eev/a> offfe=scsi_cmnd" clNULLa>        int  NULL mesh_s5pdone5mesh_state        int  rhrefst_/ u8next/a> us reset delay (0=no reset)"5punt;5#endif5u8 eev/a> ef="+code=device" clhost_scribblver> 175#ifdhost_scribblv/a> offtvoid *) mesh_state" clanexts="sref">u8next/a> us reset delay (0=no reset)"5180};5u8next/a> offfe=scsi_cmnd" clNULLa>        int  NULL mesh_s51ply;5mesh_state        int  rhrefst_/tail u8 eev/a> us reset delay (0=no reset)"51/5scsi_cmcemesh_state mesh_state" claass="sref">scsi_cmnd tus reset delay (0=no reset)"51dev;5 185static voice 18tne" name="L144"> 144     static voicemesh_state * 144u8"ef="_next mesh_s51unt;5mesh_s5>ms);5 144ms, struc"sre_ndef" id=*mesh_state" claass="sref">scsi_cmnd us reset delay (0=no reset)"5>80};5 144mesh_targep mesh_statemesh_target mesh_statescsi_cmnonn_et<    ]us reset delay (0=no reset)"5>ply;5scsi_cmnd offe=scsi_cmnd" clss="sref">mesh_state        int   urrent_1  us reset delay (0=no reset)"5>ase;5mesh_state        int   urrent_1  offe=scsi_cmnd" clNULLa>        int  NULL dev;5mesh_targep         int   urrent_1  offe=scsi_cmnd" clNULLa>        int  NULL out;5href="+code=mesh_st>#de15mesh.596" id="L156" if (class="line" naass="sref">scsi_cmnd )f=mesh_state" class="sref">mesh_s5>ms);5;
scsi_cmnd ef="+code=device" clresul<="sref">scsi_cmresul offtclass="line" namesh_statemesh_stsef=ef="o<< 16) + class="line" naass="sref">scsi_cmnd ef="+code=device" clSCpsref">mesh_targSCp/a> .code=device" clS mesh_targS done5;
mesh_statemesh_stsef=ef="offfe=scsi_cmnd" clDID_OK="sref">mesh_stDID_OK mesh_s5">tgt5;
scsi_cmnd ef="+code=device" clresul<="sref">scsi_cmresul o+fftclass="line" naass="sref">scsi_cmnd ef="+code=device" clSCpsref">mesh_targSCp/a> .code=device" clMessag85static voiMessag8ef="o<< 8tus reset delay (0=no reset)"6f">d;6mesh_stDEBUG_TARGETtmesh_state" claass="sref">scsi_cmnd ))f=mesh_state" class="sref">mesh_s6f1>d;6u8 etstmesh_state" claKERN>DEBUGs="sref">u8KERN>DEBUG" id=mICENSE" class="sref">MODULce 18: resul#37;x, data_ptr=%d, buflen=%d\nquot;Initial ode=sdtr_sent" class="sref">sdtr6f2>d;6scsi_cmnd ef="+code=device" clresul<="sref">scsi_cmresul > +code=__iomem" cs="sref">mesh_state        strata_ptr/a> > +code=__iomem" "sre_bufflen">ms, struc"sre_bufflentmesh_state" claass="sref">scsi_cmnd ))us reset delay (0=no reset)"6f3>d;6d;6scsi_cmnd ef="+code=device" clndef">ms, strucndef" id[0] fff0f|| +code=__iomem" ass="sref">scsi_cmnd ef="+code=device" clndef">ms, strucndef" id[0] fff0x12f|| +code=__iomem" ass="sref">scsi_cmnd ef="+code=device" clndef">ms, strucndef" id[0] fff3)mesh_state" class="sref">mesh_s6ting,6scsi_cmnd ef="+code=device" clrerefst_buffer8        strerefst_buffer" id=!ff0*e=mesh_state" class="sref">mesh_s6t7ng,6<
        stb/a> offe=scsi_cmnd" class="sref">scsi_cmnd ef="+code=device" clrerefst_buffer8        strerefst_buffer" idus reset delay (0=no reset)"6f8ng,6<
u8 etstmesh_state" claKERN>DEBUGs="sref">u8KERN>DEBUG" id=mICENSE" class="sref">MODULbufferoff>#37;xf>#37;xf>#37;xf>#37;xf>#37;xf>#37;xf>#37;xf>#37;x\nquot;Initial ode=sdtr_sent" class="sref">sdtr6f9ng,6<
        stb/a> [0]> +code=__iomem" b8        stb/a> [1]> +code=__iomem" b8        stb/a> [2]> +code=__iomem" b8        stb/a> [3]> +code=__iomem" b8        stb/a> [4]> +code=__iomem" b8        stb/a> [5]> +code=__iomem" b8        stb/a> [6]> +code=__iomem" b8        stb/a> [7])us reset delay (0=no reset)"6eing,6 1406e2>d;6scsi_cmnd ef="+code=device" clSCpsref">mesh_targSCp/a> .code=device" clshis_residuala>        int  shis_residual" id=-ffe=scsi_cmnd" clss="sref">mesh_state        strata_ptr/a> us reset delay (0=no reset)"6e4>d;6 144scsi_cmcetmesh_state" class="sref">mesh_state mesh_state" claass="sref">scsi_cmnd tus reset delay (0=no reset)"6eing,6u8"ef="_next mesh_s6e7ng,6 166t>mesh_stateme="sref">scsi_cmce class="line" naSEQ_ENBRESELa>        int  SEQ_ENBRESEL    t*        int   t+code=__iomem" cs="sref">mesh_stateme="sref">scsi_cmce        int  udelayt1t*mesh_stateu8       175#ifdidlv/a> *tmesh_state" clamesh_state 175#ifdiniver" id=void class="line" naadd_sdar_msef="sref">u8add_sdar_msetne" name="L144"> 144     static voicemesh_state,6mesh_s6_one,6 144 175#ifdi/a> offe=scsi_cmnd" clss="sref">mesh_statemesh_stn_mseout/a> *mesh_statemesh_stmseout/a> amesh_state" clais/> 175#ifdi/a> ]offe=scsi_cmnd" clEXTENDED_MESSAGEs/> 175#ifdEXTENDED_MESSAGE/a> *mesh_statemesh_stmseout/a> amesh_state" clais/> 175#ifdi/a> +1]off3*mesh_statemesh_stmseout/a> amesh_state" clais/> 175#ifdi/a> +2]offe=scsi_cmnd" clEXTENDED_SDTRs="sref">u8EXTENDED_SDTR/a> *mesh_statemesh_stmseout/a> amesh_state" clais/> 175#ifdi/a> +3]offe=scsi_cmnd" clcescsi_cmce /4*mesh_statemesh_stmseout/a> amesh_state" clais/> 175#ifdi/a> +4]offtclass="line" naALLOW_SYNCs/> 175#ifdALLOW_SYNCt+code=__iomem" cs="sref">mesh_statescsi_cmnonn_et<    )?fe=scsi_cmnd" clcestatic voicemesh_statemesh_stn_mseout/a> offe=scsi_cmnd" clis/> 175#ifdi/a> o+ 5*tne" name="L144"> 144     static voicemesh_state * 144scsi_cmperios/a> > * 144static voioffs+c    *s reset delay (0=no reset)"6>done6mesh_s6_log;6 144mesh_targep mesh_statemesh_target mesh_statescsi_cmnonn_et<    ]us reset delay (0=no reset)"6LOG];6 144mesh_stae 144mesh_st__iomem" id=*mesh_state" clas/a>        int   r    offe=scsi_cmnd" clss="sref">mesh_stateme="sref">scsi_cmce,6 144u8ve class="line" naar    void    * us reset delay (0=no reset)"6/bad,6mesh_targep static voisdar_   185static voisdar_> 18/a> us reset delay (0=no reset)"6/4e {6static voioffs+c     fff0)e=mesh_state" class="sref">mesh_s6>ing,6        int  SYNC_OFFt+code=__iomem" tpsref">mesh_targep mesh_stsync_parass    **s reset delay (0=no reset)"6a_DBG6 144u8 etstmesh_state" claKERN>INFOs="sref">u8KERN>INFO" id=mICENSE" class="sref">MODULm>N_: ef="+c %d now a ynchronous\nquot;Initial ode=sdtr_sent" class="sref">sdtr6adone6 144mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"6/log;6mesh_targep mesh_stsync_parass    offe=scsi_cmnd" clASYNC_PARAMS="sref">mesh_stASYNC_PARAMS/a> us reset delay (0=no reset)"6next;6 166t>        int   r    ef="+code=device" clsync_parass="sref">mesh_stsync_parass    > class="line" naASYNC_PARAMS="sref">mesh_stASYNC_PARAMS/a> )us reset delay (0=no reset)"6st_q;6;6u8vemesh_statescsi_cmnlk_freqe 144scsi_cmperios/a> us reset delay (0=no reset)"6tdone6u8vemesh_s6ount;6u8ve;6 offtclass="line" namesh_statescsi_cmnlk_freqe6mesh_s6sase;6u8veu8ve,6u8ve6 144u8ve offttclass="line" namesh_statescsi_cmnlk_freqeu8ve;6static voioffs+c     &="+f15*s reset delay (0=no reset)"6pt_q;6static voioffs+c     ff15; 5" m"L193" class="line" nam can't happena*sh.c#L2" na2s="s3/5ef=hase_mismatch6pply;6mesh_targep mesh_stsync_parass    offe=scsi_cmnd" clSYNC_PARAMS="sref">mesh_stSYNC_PARAMS/a> (class="line" naoffs+c5static voioffs+c    > class="line" navs="sref">u8ve6 166t>        int   r    ef="+code=device" clsync_parass="sref">mesh_stsync_parass    > class="line" natpsref">mesh_targep mesh_stsync_parass    *us reset delay (0=no reset)"6pase;6u8 etstmesh_state" claKERN>INFOs="sref">u8KERN>INFO" id=mICENSE" class="sref">MODULm>N_: ef="+c %d  ynchronousaac %d.%d MB/s\nquot;Initial ode=sdtr_sent" class="sref">sdtr6sout;6 144mesh_statescsi_cmnonn_et<    > class="line" naar    void    * /10> class="line" naar    void    * %10t*u8"ef="_ clastne" name="L144"> 144     static voicemesh_state;6mesh_s6/a>#endif6 144 175#ifdi/a> > +code=__iomem" "eq="sref">scsi_cmseqe +code=__iomem" nb8        stnb/a> us reset delay (0=no reset)"6180};6 144mesh_stae 144mesh_st__iomem" id=*mesh_state" clas/a>        int   r    offe=scsi_cmnd" clss="sref">mesh_stateme="sref">scsi_cmce;6 144mesh_stdbdma regs" id=m="L144"> 144mesh_st__iomem" id=*mesh_state" class="sref">scsi_cmc offe=scsi_cmnd" clss="sref">mesh_statemesh_stdmae6 144ms, struc"sre_ndef" id=*mesh_state" claass="sref">scsi_cmnd offe=scsi_cmnd" clss="sref">mesh_state        int   urrent_1  us reset delay (0=no reset)"61ase;6 144mesh_targep mesh_statemesh_target mesh_statescsi_cmnonn_et<    ]us reset delay (0=no reset)"61dev;6;6        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODUL"ef="_ clas nmo/exc/fc/seqoff>#37;.8xquot;Initial ode=sdtr_sent" class="sref">sdtr6/_DBG6mesh_staKWORDtmesh_state" class="sref">mesh_statemesh_stn_mseout/a> > mesh_state" clas/a>        int   r    ef="+code=device" clexceptioss="sref">u8exceptios  class="line" nac/a>        int   r    ef="+code=device" clfifo158        int   fifo158 class="line" nac/a>        int   r    ef="+code=device" clrhrefn      void    *6 166t>        int   r    ef="+code=device" cl static void  mesh_state" claINT>ERRORs="sref">u8INT>ERROR" id=| +code=__iomem" INT>EXCEPTIONs="sref">u8INT>EXCEPTION" id=| +code=__iomem" INT>CMDDONEs/> 175#ifdINT>CMDDONE    *us reset delay (0=no reset)"61unt;6scsi_cmseqe        stuse_acty (_ne7emesh_statemesh_stn_mseout/a> ?fe=scsi_cmnd" clSEQ_ATNs="sref">u8SEQ_ATN/a> : 0t*mesh_stateu8mse clas    *e=mesh_state" class="sref">mesh_s6>80};6static voicsg_n 18/a> :mesh_state" class="sref">mesh_s6>ply;6*6u8ssg_is/a> :mesh_state" class="sref">mesh_s6>dev;6 166t>        int   r    ef="+code=device" cl58 175#ifd58 0t*#de16mesh.696" id="L156" ="L125" mesh_state" claout_e="L166"> 166t>        int   r    ef="+code=device" cl58        int   58 1t* 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_MSGINs="sref">u8SEQ_MSGINescsi_cmseqemesh_stateu8n_mseisetgt6;
d;7mesh_stmse_out/a> :mesh_state" class="sref">mesh_s7f2>d;7mesh_statemesh_stn_mseout/a> o<= 0)e=mesh_state" class="sref">mesh_s7f8ng,7<
u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_: mse_out but n_mseout=%d\nquot;Initial ode=sdtr_sent" class="sref">sdtr7f9ng,7<
mesh_statemesh_stn_mseout/a> t* 144mesh_staetmesh_state" class="sref">mesh_statemesh_stateu8mse clas    offe=scsi_cmnd" clssg_n 185static voicsg_n 18/a> *d;7u8ALLOW_DEBUGtmesh_state" class="sref">mesh_statescsi_cmnonn_et<    ))e=mesh_state" class="sref">mesh_s7eing,7u8 etstmesh_state" claKERN>DEBUGs="sref">u8KERN>DEBUG" id=mICENSE" class="sref">MODULcesdtr7eing,7mesh_statemesh_stn_mseout/a> t*(class="line" nais/> 175#ifdi/a> off0a class="line" nais/> 175#ifdi/a> o< class="line" nass="sref">mesh_statemesh_stn_mseout/a> ; ++class="line" nais/> 175#ifdi/a> *s reset delay (0=no reset)"7>ing,7u8 etstmICENSE" class="sref">MODULf>#37;xquot;Initial o class="line" nacs="sref">mesh_statemesh_stmseout/a> amesh_state" clais/> 175#ifdi/a> ]t*u8 etstmICENSE" class="sref">MODUL\nquot;Initial t*        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULmseout csg=>#37;.8xquot;Initial o2mesh_state" claeKWORD="sref">mesh_staKWORDtmesh_state" class="sref">mesh_statemesh_stn_mseout/a> > mesh_state" class="sref">mesh_statemesh_stmseout/a> a0]ode=sdtr_sent" class="sref">sdtr7l2>d;7mesh_statemesh_stmseout/a> a1]> +code=__iomem" ss="sref">mesh_statemesh_stmseout/a> a2]))us reset delay (0=no reset)"7gse {7 166t>        int   r    ef="+code=device" cl58 175#ifd58 0t* 144 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_FLUSHFIFOs="sref">u8SEQ_FLUSHFIFO/a> t*        int   t+code=__iomem" c/a>        int   r    t*        int  udelayt1t* 166t>        int   r    ef="+code=device" clbus           int  bus   u8BS0_ATN    *efff0)e=mesh_state" class="sref">mesh_s7>2>d;7        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULbus0 wasf>#37;.2x explicitly claert4ng ATNquot;Initial o class="line" nac/a>        int   r    ef="+code=device" clbus           int  bus    166t>        int   r    ef="+code=device" clbus           int  bus   u8BS0_ATN    *; m"L193" class="line" nam explicit ATN *sh.c#L2" na2s="s3/5ef=hase_mismatch7>4>d;7        int   t+code=__iomem" c/a>        int   r    t*        int  udelayt1t* 166t>        int   r    ef="+code=device" cl58        int   58 1t* 144 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_MSGOUTs="sref">u8SEQ_MSGOUTescsi_cmseqe 166t>        int   r    ef="+code=device" clbus           int  bus           strlogtmesh_state" class="sref">mesh_statemICENSE" class="sref">MODULhace: afterfexplicit ATN bus0=>#37;.2xquot;Initial oclass="line" nac/a>        int   r    ef="+code=device" clbus           int  bus   mesh_statemesh_stn_mseout/a> offf1)e=mesh_state" class="sref">mesh_s7/bad,7tmesh_state" class="sref">mesh_statemesh_s7next;7 166t>        int   r    ef="+code=device" cl58        int   58 class="line" namesh_statemesh_stn_mseout/a> o- 1t* 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_MSGOUTs="sref">u8SEQ_MSGOUTescsi_cmseqe(class="line" nais/> 175#ifdi/a> off0a class="line" nais/> 175#ifdi/a> o< class="line" nass="sref">mesh_statemesh_stn_mseout/a> o- 1; ++class="line" nais/> 175#ifdi/a> *s reset delay (0=no reset)"7*/7 166t>        int   r    ef="+code=device" clfifoa>        int  fifo/a> > mesh_state" class="sref">mesh_statemesh_stmseout/a> amesh_state" clais/> 175#ifdi/a> ]t*,7mesh_s7tdone7u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_ bug: "ef="_ clas mse clas=%d\nquot;Initial ode=sdtr_sent" class="sref">sdtr7ount;7mesh_stateu8mse clas    *us reset delay (0=no reset)"7stat;7mesh_stateu8      mesh_s7s/7scsi_cmselect4ng" id:mesh_state" class="sref">mesh_s7sase;7 166t>        int   r    ef="+code=device" cldest_is="sref">scsi_cmdest_is/a> > mesh_state" class="sref">mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"7sing,7 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_SELECTs="sref">u8SEQ_SELECTeu8SEQ_ATN/a> )us reset delay (0=no reset)"7sing,77scsi_cmnoliaL14ng" id:mesh_state" class="sref">mesh_s7sdone7 166t>        int   r    ef="+code=device" clsync_parass="sref">mesh_stsync_parass    > class="line" natpsref">mesh_targep mesh_stsync_parass    *us reset delay (0=no ref">mesh_s7sunt;7 166t>        int   r    ef="+code=device" cl58 175#ifd58 0t*scsi_cmnd te=mesh_state" class="sref">mesh_s7pt_q;7 166t>        int   r    ef="+code=device" cl58        int   58 class="line" naass="sref">scsi_cmnd ef="+code=device" cl5md_less="sref">u85md_les    *us reset delay (0=no ref">mesh_s7pply;7 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_COMMAND="sref">mesh_stSEQ_COMMANDescsi_cmseqe(class="line" nais/> 175#ifdi/a> off0a class="line" nais/> 175#ifdi/a> o< class="line" naass="sref">scsi_cmnd ef="+code=device" cl5md_less="sref">u85md_les    ; ++class="line" nais/> 175#ifdi/a> *s reset delay (0=no reset)"7pase;7 166t>        int   r    ef="+code=device" clfifoa>        int  fifo/a> > mesh_state" claass="sref">scsi_cmnd ef="+code=device" cl5mef">ms, strucndef" idamesh_state" clais/> 175#ifdi/a> ]t*mesh_s7sout;7 166t>        int   r    ef="+code=device" cl58        int   58 6t* 144 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_COMMAND="sref">mesh_stSEQ_COMMANDescsi_cmseqe(class="line" nais/> 175#ifdi/a> off0a class="line" nais/> 175#ifdi/a> o< 6; ++class="line" nais/> 175#ifdi/a> *s reset delay (0=no reset)"7punt;7 166t>        int   r    ef="+code=device" clfifoa>        int  fifo/a> > 0t*;7scsi_cmdata4ng" id:mesh_state" class="sref">mesh_s71/7mesh_statescsi_cmdma "ef="es/a> te=mesh_state" class="sref">mesh_s71dev;7mesh_stshc_dma ndtmesh_state" class="sref">mesh_state mesh_state" claass="sref">scsi_cmnd t*scsi_cmc ef="+code=device" cl5mdpar    void    * mesh_state" clavirt_to_phys="sref">mesh_stvirt_to_phystmesh_state" class="sref">mesh_statemesh_stdma nd))us reset delay (0=no reset)"7/_DBG7scsi_cmc ef="+code=device" cl5ontrol="sref">scsi_cmnontrole tmesh_state" claRUNs="sref">u8RUN/a> o<< 16)=| +code=__iomem" RUNs="sref">u8RUN/a> )us reset delay (0=no reset)"7/done7mesh_statescsi_cmdma "ef="es/a>  ff1us reset delay (0=no reset)"7/unt;7ms);7        stnb/a> offe=scsi_cmnd" clss="sref">mesh_state        int   dma15880};7        stnb/a> o&="+f0xfff0*s reset delay (0=no reset)"7>ply;7        stnb/a> off0xfff0;s reset delay (0=no reset)"7>/7mesh_state        int   dma158        stnb/a> us reset delay (0=no reset)"7>ase;7mesh_state        stnb/a> us reset delay (0=no reset)"7>dev;7 166t>        int   r    ef="+code=device" cl58        int   58 class="line" nanb8        stnb/a> )us reset delay (0=no reset)"7>out;7href="+code=mesh_st>#de17mesh.796" id="L156" ="L125" mesh_state" claout_e="L166"> 166t>        int   r    ef="+code=device" cl58 175#ifd58 class="line" nanb8        stnb/a> o&="+&="+f8)us reset delay (0=no reset)"7>_DBG7;
 166t>        int   r    ef="+code=device" clshrefn      void    * t+code=__iomem" tpsref">mesh_targep mesh_stdata_goes_out done7;
u8SEQ_DATAOUT" id: class="line" naSEQ_DATAINs="sref">u8SEQ_DATAIN/a> te+ class="line" naSEQ_DMA_MODEs="sref">u8SEQ_DMA_MODEescsi_cmseqetgt7;
d;8scsi_cms mesh_s8f1>d;8 166t>        int   r    ef="+code=device" cl58 175#ifd58 0t* 166t>        int   r    ef="+code=device" cl58        int   58 1t* 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_STATUS="sref">mesh_stSEQ_STATUSescsi_cmseqed;8scsi_cmbusfree4ng" id:mesh_state" class="sref">mesh_s8f6>d;8#de18h.c#L806" id="L118" casefe=scsi_cmnd" cldisnonnect4ng="sref">scsi_cmdisnonnect4ng" id:mesh_state" class="sref">mesh_s8f7>d;8<
 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_ENBRESEL="sref">mesh_stSEQ_ENBRESELe        int   t+code=__iomem" c/a>        int   r    t*        int  udelayt1t*        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULenbresel *#37;.8xquot;Initial omesh_staKWORDtmesh_state" clas/a>        int   r    ef="+code=device" cl static void  mesh_state" clas/a>        int   r    ef="+code=device" clexceptioss="sref">u8exceptios  class="line" nac/a>        int   r    ef="+code=device" clodeo/a>        int  odeo/         int   r    ef="+code=device" clfifo158        int   fifo158d;8 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_BUSFREEs="sref">u8SEQ_BUSFREE    t*,8mesh_s8eing,8u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_: "ef="_ clas called with  clas=%d\nquot;Initial ode=sdtr_sent" class="sref">sdtr8e7ng,8mesh_stateu8      d;8        strumps 17tmesh_state" class="sref">mesh_state,8,8d;8d;8u8get_mseistne" name="L144"> 144     static voicemesh_stated;8mesh_s8ging,8 144mesh_stae 144mesh_st__iomem" id=*mesh_state" clas/a>        int   r    offe=scsi_cmnd" clss="sref">mesh_stateme="sref">scsi_cmcemesh_s8ging,8 144 175#ifdi/a> > +code=__iomem" ss="sref">u8nemesh_s8g7ng,8u8ne        int   r    ef="+code=device" clfifo158        int   fifo158mesh_s8g9ng,8u8nemesh_s8> 1298 175#ifdi/a> offe=scsi_cmnd" clss="sref">mesh_stateu8n_mseisemesh_s8>_in,8mesh_stateu8n_mseise 175#ifdi/a> o+ class="line" nass="sref">u8nemesh_s8>2>d;8(a class="line" nans="sref">u8neu8nese {8mesh_stateu8ssgise 175#ifdi/a> ++]offe=scsi_cmnd" clin_e="L166"> 166t>        int   r    ef="+code=device" clfifoa>        int  fifo/a> )us reset delay (0=no reset)"8>4>d;8ing,8ing,8 144scsi_cmcsgis_lesgtetne" name="L144"> 144     static voicemesh_statedone8mesh_s8>9ng,8 144        stb/a> > +code=__iomem" ss="sref">u8nemesh_s8LOG];8u8ne,8mesh_stateu8n_mseisemesh_s8> 1428        stb/a> offe=scsi_cmnd" clss="sref">mesh_stateu8ssgised;8        stb/a> offf1)e=mesh_state" class="sref">mesh_s8>ing,8u8nemesh_stateu8n_mseisemesh_stateu8ssgise,8        stb/a> o>        stb/a> o>lt;= 0x2f)e=mesh_state" class="sref">mesh_s8>done8u8ne;8;8,8u8nemesh_s8*/8d;8,8scsi_cmreselec"estne" name="L144"> 144     static voicemesh_state,8mesh_s8*_DBG8 144mesh_stae 144mesh_st__iomem" id=*mesh_state" clas/a>        int   r    offe=scsi_cmnd" clss="sref">mesh_stateme="sref">scsi_cmcemesh_s8*done8 144ms, struc"sre_5mef" id=*mesh_state" claass="sref">scsi_cmnd us reset delaclass="sref">mesh_s8*9ng,8 144mesh_staemesh_targep mesh_s8stat;8 144        stb/a> > +code=__iomem" c="sref">mesh_stesh_i> mesh_state" claprevs="sref">u8 eev mesh_s8st_q;8mesh_stateu8      mesh_s8s/8mesh_s8sase;8,8scsi_cmarbitrat4ng" id:mesh_state" class="sref">mesh_s8sing,8scsi_cmnd offe=scsi_cmnd" clss="sref">mesh_statescsi_cmcurrne" req mesh_stNULL mesh_s8s_DBG8scsi_cmnd ef="+code=device" clhost_scribblrs/atic void  off(void *)fe=scsi_cmnd" clss="sref">mesh_statescsi_cmrhrefst_q mesh_s8s9ng,8mesh_statescsi_cmrhrefst_q mesh_stNULL mesh_s8pace;8mesh_statescsi_cmrhrefst_qtail/a> offe=scsi_cmnd" class="sref">scsi_cmnd us reset delaclass="sref">mesh_s8pt_q;8mesh_statescsi_cmrhrefst_q scsi_cmnd us reset delaclass="sref">mesh_s8pail;8mesh_targep mesh_statemesh_sttgtsescsi_cmnd ef="+code=device" cldevi      void    * ef="+code=device" clis="sref">scsi_cmis/a> ]us reset delay (0=no reset)"8p/8mesh_targep scsi_cmcurrne" req mesh_stNULL ;8;8;8scsi_cmbusfree4ng" id:mesh_state" class="sref">mesh_s8s_DBG8mesh_stateu8      scsi_cmreselec"4ng 8 144tmesh_state" class="sref">mesh_state 0t*#endif8scsi_cmdisnonnect4ng" id:mesh_state" class="sref">mesh_s8180};8;8mesh_s81/8u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_: reselec"es i85 clas %d/%d tgt %d\nquot;Initial ode=sdtr_sent" class="sref">sdtr81ase;8mesh_stateu8mse clas    > mesh_state" class="sref">mesh_stateu8       mesh_state" class="sref">mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"81dev;8        strumplogtmesh_state" class="sref">mesh_state mesh_state" class="sref">mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"81out;8        strumps 17tmesh_state" class="sref">mesh_state88;8mesh_statescsi_cmdma "ef="es/a> te=mesh_state" class="sref">mesh_s8>ms);8u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_: reselec"es with DMA "ef="es !\nquot;Initial )us reset delay (0=no reset)"8>80};8tmesh_state" class="sref">mesh_stateply;8/8mesh_statescsi_cmcurrne" req mesh_stNULL ase;8mesh_stateu8      scsi_cmdata4ng" idus reset delay (0=no reset)"8>dev;8mesh_stateu8mse clas    offe=scsi_cmnd" clssg_iss="sref">u8ssg_isemesh_s8>out;8href="+code=mesh_st>#de18mesh.896" id="L156" mesh_state" class="sref">mesh_statemesh_stn_mseout/a> of 0;s reset delay (0=no reset)"8>_DBG8;
mesh_statemesh_streft_n_mseout/a> of 0;s reset delay (0=no reset)"8>done8;
u8 eev mesh_statescsi_cmnonn_et<    ;s reset delay (0=no reset)"8>unt;8;
d;9 166t>        int   r    ef="+code=device" clbus           int  bus    te>        int  BS1_BSY/a> te=ff0)e=mesh_state" class="sref">mesh_s9f4>d;9 144mesh_staed;9mesh_staed;9#de19h.c#L906" id="L156" ="L125" mesh_state" claout_e="L166"> 166t>        int   r    ef="+code=device" cl static void  mesh_state" claINT>ERRORs="sref">u8INT>ERROR" id=| +code=__iomem" INT>EXCEPTIONs="sref">u8INT>EXCEPTION" id=| +code=__iomem" INT>CMDDONEs="sref">u8INT>CMDDONEed;9<
mesh_staet+code=__iomem" c/a>        int   r    t*        int  udelayt1t* 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_ENBRESEL="sref">mesh_stSEQ_ENBRESELemesh_staet+code=__iomem" c/a>        int   r    t*        int  udelayt5t*        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULextra resel err/exc/fcoff>#37;.6xquot;Initial omesh_staKWORDt0> class="line" nac/a>        int   r    ef="+code=device" clodeo/a>        int  odeo/  mesh_state" clas/a>        int   r    ef="+code=device" clexceptioss="sref">u8exceptios  class="line" nac/a>        int   r    ef="+code=device" clfifo158        int   fifo158d;9,9 166t>        int   r    ef="+code=device" cl static void  mesh_state" claINT>ERRORs="sref">u8INT>ERROR" id=| +code=__iomem" INT>EXCEPTIONs="sref">u8INT>EXCEPTION" id=| +code=__iomem" INT>CMDDONEs="sref">u8INT>CMDDONEe,9mesh_staet+code=__iomem" c/a>        int   r    t*        int  udelayt1t* 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_ENBRESEL="sref">mesh_stSEQ_ENBRESELemesh_staet+code=__iomem" c/a>        int   r    t*        int  udelayt1t* 166t>        int   r    ef="+code=device" clsync_parass="sref">mesh_stsync_parass    > class="line" naASYNC_PARAMS="sref">mesh_stASYNC_PARAMS    t*d;9 166t>        int   r    ef="+code=device" clfifo158        int   fifo158mesh_s9g7ng,9u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_: reselec"ios but nothsre i85fifo?\nquot;Initial )us reset delay (0=no reset)"9ging,9 144mesh_statescsi_cmnonn_et<    offe=scsi_cmnd" clss="sref">mesh_statescsi_cmthss_is    ;s reset delay (0=no reset)"9g9ng,9mesh_stbogus    ;s reset delay (0=no reset)"9> 1299_in,9mesh_s9>se {9mesh_stb    offe=scsi_cmnd" clin_e="L166"> 166t>        int   r    ef="+code=device" clfifoa>        int  fifo/a> )us reset delay (0=no reset)"9>4>d;9        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULreseldataf>#37;xquot;Initial o e=scsi_cmnd" clb="sref">mesh_stb    )us reset delay (0=no reset)"9>ing,9 166t>        int   r    ef="+code=device" clfifo158        int   fifo158ing,9(class="line" nac="sref">mesh_stesh_ioff0a class="line" nac="sref">mesh_stesh_io< 8; ++class="line" nac="sref">mesh_stesh_i)s reset delaclass="sref">mesh_s9>one,9        stb/a> o>mesh_stesh_i))e!ff0o>mesh_stesh_io!ffe=scsi_cmnd" clss="sref">mesh_statescsi_cmthss_is    )s reset delaclass="sref">mesh_s9>ing,99ng,9        stb/a> o!ff(1o<< class="line" nac="sref">mesh_stesh_i) +f(1o<< class="line" nass="sref">mesh_statescsi_cmthss_is    ))e=mesh_state" class="sref">mesh_s9LOG];9u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_: bad reselec"ios dataf>#37;x\nquot;Initial o e=scsi_cmnd" clb="sref">mesh_stb    )us reset delay (0=no reset)"9L_in,9mesh_statescsi_cmnonn_et<    offe=scsi_cmnd" clss="sref">mesh_statescsi_cmthss_is    ;s reset delay (0=no reset)"9/bad,9mesh_stbogus    ;s reset delay (0=no reset)"9> 1429d;9ing,9ing,9mesh_statescsi_cmnonn_et<    offe=scsi_cmnd" clc="sref">mesh_stesh_i;s reset delay (0=no reset)"9next;9mesh_targep mesh_statemesh_sttgtsemesh_stesh_i]us reset delay (0=no reset)"9st_q;9 166t>        int   r    ef="+code=device" clsync_parass="sref">mesh_stsync_parass    > class="line" natpsref">mesh_targep mesh_stsync_parass    )us reset delay (0=no reset)"9sbad,9mesh_stALLOW_DEBUGtmesh_state" clac="sref">mesh_stesh_i))e=mesh_state" class="sref">mesh_s9*/9u8 etstmesh_state" claKERN>DEBUG="sref">mesh_stKERN>DEBUG" id=mICENSE" class="sref">MODULm>N_: reselec"ed by tf="+c %d\nquot;Initial o class="line" nac="sref">mesh_stesh_i)us reset delay (0=no reset)"9s4>d;9u8 etstmesh_state" claKERN>DEBUG="sref">mesh_stKERN>DEBUG" id=mICENSE" class="sref">MODULm>N_: saved_par=%x goes_out=%d cmd=%p\nquot;Initial ode=sdtr_sent" class="sref">sdtr9sing,9mesh_targep mesh_stsaved_par    > class="line" natpsref">mesh_targep mesh_stdata_goes_out  class="line" natpsref">mesh_targep scsi_cmcurrne" req ,99mesh_statescsi_cmcurrne" req mesh_targep scsi_cmcurrne" req 9mesh_targep scsi_cmcurrne" req mesh_stNULL mesh_s9*9ng,9u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_: reselec"es by tgt %d but no cmd!\nquot;Initial o class="line" nac="sref">mesh_stesh_i)us reset delay (0=no reset)"9stat;9mesh_stbogus    ;s reset delay (0=no reset)"9st_q;9;9mesh_statemesh_stdata_par mesh_targep mesh_stsaved_par    ;s reset delay (0=no reset)"9s/9        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULresel  eev tgt=%dquot;Initial o class="line" naprevs="sref">u8 eev d;9        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULresel err/exc=>#37;.4xquot;Initial o e=scsi_cmnd" cleKWORD="sref">mesh_staKWORDt0> 0> class="line" nac/a>        int   r    ef="+code=device" clodeo/a>        int  odeo/  mesh_state" clas/a>        int   r    ef="+code=device" clexceptioss="sref">u8exceptios ,9mesh_stsef="_ clastmesh_state" class="sref">mesh_state,99mesh_stbogus    :mesh_state" class="sref">mesh_s9s9ng,9        strumplogtmesh_state" class="sref">mesh_state mesh_state" class="sref">mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"9pace;9        strumps 17tmesh_state" class="sref">mesh_state;9mesh_statemesh_stdata_par ;9mesh_statescsi_cmabortfng 9mesh_stsef="_ clastmesh_state" class="sref">mesh_state;9;9;9mesh_stdo aborttne" name="L144"> 144     static voicemesh_state9mesh_s9pdone9mesh_statemesh_stmseout/a> [0]offe=scsi_cmnd" clABORT="sref">mesh_stABORT    ;s reset delay (0=no reset)"9punt;9mesh_statemesh_stn_mseout/a> of 1us reset delay (0=no reset)"9/a>#endif9mesh_statescsi_cmabortfng };9mesh_statemesh_stsef<    offe=scsi_cmnd" clDID_ABORT="sref">mesh_stDID_ABORT    ;s reset delay (0=no reset)"91ply;9        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULabortquot;Initial o 0t*;9;9tne" name="L144"> 144     static voicemesh_state;9mesh_s9/_DBG9 144scsi_cmet<    ;s reset delay (0=no reset)"9/done9 144mesh_staemesh_targep mesh_s9/unt;9 144ms, struc"sre_5mef" id=*mesh_state" claass="sref">scsi_cmnd us reset delaclass="sref">mesh_s9>ms);9 144mesh_stae 144mesh_st__iomem" id=*mesh_state" clas/a>        int   r    offe=scsi_cmnd" clss="sref">mesh_stateme="sref">scsi_cmcemesh_s9>80};9(class="line" nact<="sref">scsi_cmet<    off0a class="line" nact<="sref">scsi_cmet<    o< 8; ++class="line" nact<="sref">scsi_cmet<    )e=mesh_state" class="sref">mesh_s9>/9mesh_targep mesh_statemesh_sttgtsescsi_cmet<    ]us reset delay (0=no reset)"9>ase;9scsi_cmnd offe=scsi_cmnd" cltpsref">mesh_targep scsi_cmcurrne" req mesh_stNULL mesh_s9>dev;9scsi_cmnd ef="+code=device" clresul<="sref">scsi_cmresul<    offe=scsi_cmnd" clDID_RESET="sref">mesh_stDID_RESET    o<< 16us reset delay (0=no reset)"9>out;9href="+code=mesh_st>#de19mesh.996" id="L156" ="L125" 25"     mesh_state" clatpsref">mesh_targep scsi_cmcurrne" req mesh_stNULL _DBG9;
 144scsi_cmcetmesh_state" class="sref">mesh_state mesh_state" claass="sref">scsi_cmnd t*unt;9;
mesh_statemesh_sttgtsescsi_cmet<    ].e="L144"> 144static voi"dtr   mesh_stdo "dtr d;10f">d href="drivers/scsi/10f">>10f"" id="L159" ="L147" +code=__iomem" ss="sref">mesh_statemesh_sttgtsescsi_cmet<    ].e="L144"> 144mesh_stsync_parass    offe=scsi_cmnd" clASYNC_PARAMS="sref">mesh_stASYNC_PARAMS    us /pre>mdoers/95/c6/0410f6f3307568a502785e2234a514f4ff80_3/10f">> reset delay (0=no reset)"10f1>d;10fa href="drivers/scsi/me10fa >10f1" id="L151" }s reset delay (0=no reset)"10f2>d;10fa href="drivers/scsi/me10fa >10f2" id="L132" mesh_state" class="sref">mesh_statescsi_cmcurrne" req mesh_stNULL d;10fa href="drivers/scsi/me10fa >10f3" id="L132" while ((class="line" naass="sref">scsi_cmnd offe=scsi_cmnd" clss="sref">mesh_statescsi_cmrhrefst_q mesh_stNULL mesh_s10f4>d;10fa href="drivers/scsi/me10fa >10f4" id="L134" ="L125" e=scsi_cmnd" clss="sref">mesh_statescsi_cmrhrefst_q  144ms, struc"sre_5mef" id=*)fe=scsi_cmnd" class="sref">scsi_cmnd ef="+code=device" clhost_scribblrs/atic void  us reset delay (0=no reset)"10f5>d;10fa href="drivers/scsi/me10fa >10f5" id="L132" ="L125" e=scsi_cmnd" class="sref">scsi_cmnd ef="+code=device" clresul<="sref">scsi_cmresul<    offe=scsi_cmnd" clDID_RESET="sref">mesh_stDID_RESET    o<< 16us reset delay (0=no reset)"10f6>d;10fref="+code=mesh_st>#de110fre>10f6" id="L156" ="L125" mesh_state" clacescsi_cmcetmesh_state" class="sref">mesh_state mesh_state" claass="sref">scsi_cmnd t*10f7" id="L147" }s reset delay (0=no reset)"10f8>d;10f
mesh_stateu8      10f9" id="L159" mesh_state" class="sref">mesh_stateu8mse clas    offe=scsi_cmnd" clssg_noers/atic void d;10 166t>        int   r    ef="+code=device" cl static void  mesh_state" claINT>ERRORs="sref">u8INT>ERROR" id=| +code=__iomem" INT>EXCEPTIONs="sref">u8INT>EXCEPTION" id=| +code=__iomem" INT>CMDDONEs="sref">u8INT>CMDDONEed;10 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_FLUSHFIFO    void    *d;10mesh_staet+code=__iomem" c/a>        int   r    t*10<3" id="L163" e=scsi_cmnd" cludelaya>        int  udelayt1t*10<4" id="L134" e=scsi_cmnd" clout_e="L166"> 166t>        int   r    ef="+code=device" clsync_parass="sref">mesh_stsync_parass    > class="line" naASYNC_PARAMS="sref">mesh_stASYNC_PARAMS    t*10<5" id="L132" mesh_state" claout_e="L166"> 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" naSEQ_ENBRESEL="sref">mesh_stSEQ_ENBRESELe10<6" id}s reset delay (0=no reset)"10<7>d;1010<8" id  static void " id=m="L144"> 144static void t* 144 void *m="L144"> 144scsi_cmdev_ised;10mesh_s102">d;10 144mesh_stflags" id*10<1" id="L151" ne" name="L144"> 144     static voicemesh_statescsi_cmdev_ise10<2" id="L151" ne" name="L144"> 144u8dev mesh_state10<3" id="L163" 10<4" id="L134" e=scsi_cmnd" clspin_lock_"rqsave    void    *t+code=__iomem" devs="sref">u8dev  class="line" naflags="sref">mesh_stflags" idt*10<5" id="L132" mesh_state" clasestatic void te=scsi_cmnd" clss="sref">mesh_state10<6" id="L156" mesh_state" claspin_unlock_"rqrestore    void    *t+code=__iomem" devs="sref">u8dev  class="line" naflags="sref">mesh_stflags" idt*10<7" id="L147" return +code=__iomem" IRQ_HANDLED="sref">mesh_stIRQ_HANDLEDe10<8" id}s reset delay (0=no reset)"1029>d;10d;10        int  handle_odeo/tne" name="L144"> 144     static voicemesh_stated;10mesh_s1032>d;10 144mesh_stodee class="line" naexc="sref">mesh_stoxce mesh_state" claa8        int   5810<3" id="L163" vol 144mesh_stae 144mesh_st__iomem" id=*mesh_state" clas/a>        int   r    offe=scsi_cmnd" clss="sref">mesh_stateme="sref">scsi_cmced;10d;10mesh_stodee 166t>        int   r    ef="+code=device" clodeo/a>        int  odeo/ 10<6" id="L156" mesh_state" claexc="sref">mesh_stoxce 166t>        int   r    ef="+code=device" cloxceptioss="sref">u8exceptios 10<7" id="L147" mesh_state" claout_e="L166"> 166t>        int   r    ef="+code=device" cl static void  mesh_state" claINT>ERRORs="sref">u8INT>ERROR" id=| +code=__iomem" INT>EXCEPTIONs="sref">u8INT>EXCEPTION" id=| +code=__iomem" INT>CMDDONEs="sref">u8INT>CMDDONEed;10        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULedeo/ err/exc/fc/cl=>#37;.8xquot;Initial o10<9" id="L159" ="L14mesh_state" claeKWORD="sref">mesh_staKWORDte="L144"> 144mesh_stodee class="line" naexc="sref">mesh_stoxce mesh_state" clas/a>        int   r    ef="+code=device" clfifo158        int   fifo158 mesh_state" clas/a>        int   r    ef="+code=device" cl58        int   58d;10mesh_stodeemesh_stERR_SCSIRESETemesh_s1041>d;1010<2" id="L132" ="L125" e=scsi_cmnd" clprtsu8 etstmesh_state" claKERN>INFO    void    *INFO" id=mICENSE" class="sref">MODULm>N_: SCSI bus reset=detec"es: quot;Initial  na2s="s3/5ef=hase_mismatch10<3>d;10MODULwaitfng end...quot;Initial )us reset delay (0=no reset)"10<4>d;10 166t>        int   r    ef="+code=device" clbus           int  bus    te>mesh_stBS1_RST/a> te!ff0*s reset delay (0=no reset)"1045>d;10        int  udelayt1t*10<6" id="L156" ="L125" mesh_state" claprtsu8 etstmICENSE" class="sref">MODULdoer\nquot;Initial )us reset delay (0=no reset)"10<7>d;10te=scsi_cmnd" clss="sref">mesh_state10<8" id="L118" ="L125" e"L193" class="line" nam rhrefst_q is empty, no poi10<9" id="L159" ="L147" returnus reset delay (0=no reset)"105">d;10d;10mesh_stodeemesh_stERR_UNEXPDISCemesh_s1052>d;1010<3" id="L132" ="L125" if (class="line" naoxc="sref">mesh_stoxcemesh_stEXC_RESELECTEDemesh_s1054>d;10mesh_streselec"este=scsi_cmnd" clss="sref">mesh_state10<5" id="L132" ="L125" ="L125"freturnus reset delay (0=no reset)"1056>d;10d;10mesh_statescsi_cmabortfng mesh_s1058>d;10u8 etstmesh_state" claKERN>WARNING="sref">mesh_stKERN>WARNING" id=mICENSE" class="sref">MODULm>N_: tf="+c %d aborted\nquot;Initial ode=sdtr_sent" class="sref">sdtr10<9>d;10mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"106">d;10        strumplogtmesh_state" class="sref">mesh_state mesh_state" class="sref">mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"10<1>d;10        strumps 17tmesh_state" class="sref">mesh_stated;10d;10 166t>        int   r    ef="+code=device" cl static void  mesh_state" claINT>CMDDONEs="sref">u8INT>CMDDONEed;10mesh_statemesh_stsef<    offe=scsi_cmnd" clDID_ABORT="sref">mesh_stDID_ABORT    ;s reset delay (0=no reset)"10<5>d;10tmesh_state" class="sref">mesh_state 1t*10<6" id="L156" ="L125" returnus reset delay (0=no reset)"1067>d;10d;10mesh_stodeemesh_stERR_PARITY mesh_s1069>d;10mesh_stateu8mse clas    offfe=scsi_cmnd" clssg_iss="sref">u8ssg_is mesh_s107">d;10u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_: ssg parity edeo/, tf="+c %d\nquot;Initial omesh_state" class="sref">mesh_s1071>d;10mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"1072>d;10mesh_statemesh_stmseout/a> [0]offe=scsi_cmnd" clMSG_PARITY>ERRORs="sref">u8MSG_PARITY>ERROR    ;s reset delay (0=no reset)"1073>d;10mesh_statemesh_stn_mseout/a> of 1us reset delay (0=no reset)"10<4>d;10mesh_stateu8mse clas    offe=scsi_cmnd" clssg_in_bas="sref">scsi_cmcsg_in_bas    ;s reset delay (0=no reset)"1075>d;10scsi_cmnss comple"etmesh_state" class="sref">mesh_stated;10d;10d;10mesh_statemesh_stsef<    offfe=scsi_cmnd" clDID_OK="sref">mesh_stDID_OK mesh_s1079>d;10u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_: parity edeo/, tf="+c %d\nquot;Initial omesh_state" class="sref">mesh_s108">d;10mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"1081>d;10mesh_statemesh_stsef<    offe=scsi_cmnd" clDID_PARITY="sref">mesh_stDID_PARITY    ;s reset delay (0=no reset)"1082>d;10d;10        int   58        int   r    ef="+code=device" cl58        int   58lt;< 8) +fmesh_state" clas/a>        int   r    ef="+code=device" cl58        int   58d;10        int   58mesh_s1085>d;10scsi_cmnss comple"etmesh_state" class="sref">mesh_stated;10mesh_s1087>d;1010<8" id="L118" ="L125" 25"     e=scsi_cmnd" clout_e="L166"> 166t>        int   r    ef="+code=device" clshrefn      void    * class="line" nas/a>        int   r    ef="+code=device" clshrefn      void    *d;10d;10d;10d;10mesh_stodeeu8ERR_SEQERR mesh_s1093>d;10mesh_stoxcemesh_stEXC_RESELECTEDemesh_s1094>d;1010<5" id="L194" class="line" na"L132" ==================="+c the bus just after the tf="+c reselec"s us.=*sh.c#L2" na2s="s3/5ef=hase_mismatch1096>d;10href="+code=mesh_st>#de110hre>10<6" id="L156" ="L125" 25"        144mesh_staed;10;
 144mesh_staed;10;
mesh_streselec"este=scsi_cmnd" clss="sref">mesh_state10<9" id="L159" ="L147" "L125" 2returnus reset delay (0=no reset)"11f">d;11f">d href="drivers/scsi/11f">>11f"" id="L159" ="L147" }s reset delay (0=no reset)"11f1>d;11fa href="drivers/scsi/me11fa >1101" id="L151" ="L125" if (class="line" naoxc="sref">mesh_stoxcemesh_stEXC_PHASEMMemesh_s11f2>d;11fa href="drivers/scsi/me11fa >1102" id="L132" ="L125"  "L125"    144mesh_staed;11fa href="drivers/scsi/me11fa >1103" id="L132" ="L125" 125"  = mesh_state" clasemesh_staed;11fa href="drivers/scsi/me11fa >11f4" id="L134" ="L125" 125"  = mesh_state" cla clas_mismatce="sref">scsi_cm clas_mismatcete=scsi_cmnd" clss="sref">mesh_state11f5" id="L132" ="L125" "L125" 2returnus reset delay (0=no reset)"11f6>d;11fref="+code=mesh_st>#de111fre>11f6" id="L156" ="L125" }s reset delay (0=no reset)"11f7>d;11f
u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_: shrefn   edeo/ (ede=%x exc=>#37;x)\nquot;Initial omesh_state" class="sref">mesh_s11f8>d;11f
mesh_stodee class="line" naexc="sref">mesh_stoxce11f9" id="L159" } elsee=mesh_state" class="sref">mesh_s111">d;11u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_: unknown edeo/ %x (exc=>#37;x)\nquot;Initial o class="line" naode="sref">mesh_stodee class="line" naexc="sref">mesh_stoxce1111" id="L151" }s reset delay (0=no reset)"11<2>d;11mesh_staete=scsi_cmnd" clss="sref">mesh_state11<3" id="L163" e=scsi_cmnd" cldump 178        strumplogtmesh_state" class="sref">mesh_state mesh_state" class="sref">mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"11<4>d;11mesh_stateu8      scsi_cmselec"fnge 166t>        int   r    ef="+code=device" clbus           int  bus    te>mesh_stBS1_BSY/a> t)e=mesh_state" class="sref">mesh_s11<5>d;111116" id="L156" ="L125" mesh_state" clado abort="sref">mesh_stdo abortte=scsi_cmnd" clss="sref">mesh_state1117" id="L147" ="L125" class="line" napclas_mismatce="sref">scsi_cm clas_mismatcete=scsi_cmnd" clss="sref">mesh_state1118" id="L118" ="L125" returnus reset delay (0=no reset)"11<9>d;11d;11mesh_statemesh_stsef<    offe=scsi_cmnd" clDID_ERRORs="sref">u8DID_ERRORed;11tmesh_state" class="sref">mesh_state 1t*11<2" id}s reset delay (0=no reset)"1123>d;11d;11u8handle_oxceptiostne" name="L144"> 144     static voicemesh_stated;11mesh_s1126>d;11 144mesh_stoxce11<7" id="L147" vol 144mesh_stae 144mesh_st__iomem" id=*mesh_state" clas/a>        int   r    offe=scsi_cmnd" clss="sref">mesh_stateme="sref">scsi_cmced;11d;11mesh_stoxce 166t>        int   r    ef="+code=device" cloxceptioss="sref">u8exceptios d;11 166t>        int   r    ef="+code=device" cl static void  mesh_state" claINT>EXCEPTIONs="sref">u8INT>EXCEPTION" id=| +code=__iomem" INT>CMDDONEs="sref">u8INT>CMDDONEed;11mesh_stoxcemesh_stEXC_RESELECTEDemesh_s1132>d;11 144mesh_staed;11mesh_staed;11mesh_streselec"este=scsi_cmnd" clss="sref">mesh_state11<5" id="L132" } elseeif (class="line" naoxc="sref">mesh_stoxcemesh_stEXC_ARBLOSTemesh_s1136>d;11u8 etstmesh_state" claKERN>DEBUG="sref">mesh_stKERN>DEBUG" id=mICENSE" class="sref">MODULm>N_: lost arbitratios\nquot;Initial )us reset delay (0=no reset)"1137>d;11mesh_statemesh_stsef<    offe=scsi_cmnd" clDID_BUS_BUSY="sref">mesh_stDID_BUS_BUSYed;11tmesh_state" class="sref">mesh_state 1t*1139" id="L159" } elseeif (class="line" naoxc="sref">mesh_stoxcemesh_s114">d;1111<1" id="L151" ="L125" elass="line" nass="sref">mesh_statemesh_stsef<    offe=scsi_cmnd" clDID_BAD_TARGET="sref">mesh_stDID_BAD_TARGETed;11tmesh_state" class="sref">mesh_state 1t*11<3" id="L132" } elseeif (class="line" naoxc="sref">mesh_stoxcemesh_stEXC_PHASEMMemesh_s11<4>d;111145" id="L194" class="line" na"L132" ===========find out what ic wan"s and=do it.=*sh.c#L2" na2s="s3/5ef=hase_mismatch1146>d;11scsi_cm clas_mismatcete=scsi_cmnd" clss="sref">mesh_state11<7" id="L147" } elsee=mesh_state" class="sref">mesh_s1148>d;11u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=mICENSE" class="sref">MODULm>N_: can't cope with exceptios %x\nquot;Initial o class="line" naoxc="sref">mesh_stoxce11<9" id="L159" ="L147" mesh_state" clasa hrrump regs="sref">mesh_staete=scsi_cmnd" clss="sref">mesh_stated;11        strumplogtmesh_state" class="sref">mesh_state mesh_state" class="sref">mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"1151>d;11mesh_stdo abortte=scsi_cmnd" clss="sref">mesh_state11<2" id="L132" ="L125" eesh_state" clapclas_mismatce="sref">scsi_cm clas_mismatcete=scsi_cmnd" clss="sref">mesh_state11<3" id="L132" }s reset delay (0=no reset)"1154>d;11d;11d;11u8handle_msgistne" name="L144"> 144     static voicemesh_stated;11mesh_s1158>d;11 144 mesh_state" cla" cl="sref">scsi_cmnodr" id*11<9" id="L159" ne" name="L144"> 144ms, struc"sre_5mef" id=*mesh_state" cla"ss="sref">scsi_cmnd offe=scsi_cmnd" clss="sref">mesh_statescsi_cmcurrne" req d;11 144   tf="+c5static voicestatic voitp/a> off>mesh_statemesh_sttgtsemesh_statescsi_cmnonn_et<    ]*11<1" id1162" id="L132" if (class="line" nass="sref">mesh_stateu8n_msgisofff0*11<3" id="L132" ="L125" returnus reset delay (0=no reset)"1164>d;11scsi_cmnodr" idoffe=scsi_cmnd" clss="sref">mesh_stateu8msgis[0]*11<5" id="L132" if (class="line" naALLOW>DEBUG="sref">mesh_stALLOW>DEBUGte=scsi_cmnd" clss="sref">mesh_statescsi_cmnonn_et<    ))e=mesh_state" class="sref">mesh_s1166>d;11u8 etstmesh_state" claKERN>DEBUG="sref">mesh_stKERN>DEBUG" id=mICENSE" class="sref">MODULgoc %d ">msage bytes:quot;Initial o class="line" nass="sref">mesh_stateu8n_msgist*1167" id="L147" ="L125" (class="line" naistatic void mesh_stateu8n_msgis; ++class="line" naistatic void 1168" id="L118" ="L125" 25"     e=scsi_cmnd" clprtsu8 etstmICENSE" class="sref">MODUL %xquot;Initial o class="line" nass="sref">mesh_stateu8msgis[class="line" naistatic void 11<9" id="L159" ="L147" e=scsi_cmnd" clprtsu8 etstmICENSE" class="sref">MODUL\nquot;Initial )us reset delay (0=no reset)"117">d;11d;11        strlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULmsgis ssg=>#37;.8xquot;Initial o11<2" id="L132" ="L12mesh_state" claeKWORD="sref">mesh_staKWORDte="L144"> 144mesh_stateu8n_msgis> mesh_state" cla" cl="sref">scsi_cmnodr" ido class="line" nass="sref">mesh_stateu8msgis[1]o class="line" nass="sref">mesh_stateu8msgis[2]))us reset delay (0=no reset)"1173>d;11d;11mesh_state        int  expec" replyed;11 144mesh_statemesh_stn_mseout/a> of 0as reset delay (0=no reset)"11<6>d;11mesh_stateu8n_msgiso< class="line" nassgin_lengte="sref">scsi_cmcsgin_lengtete=scsi_cmnd" clss="sref">mesh_state11<7" id="L147" ="L125" goco e=scsi_cmnd" clrejec"="sref">mesh_strejec" 1178" id="L118" if (class="line" na"ss="sref">scsi_cmnd *11<9" id="L159" ="L147" class="line" na"ss="sref">scsi_cmnd ef="+code=device" clSCp5static voiSCp/a> .mesh_state" clae>msage="sref">mesh_sta>msage" idoffe=scsi_cmnd" cl" cl="sref">scsi_cmnodr" id*d;11scsi_cmnodr" id)e=mesh_state" class="sref">mesh_s1181>d;11u8COMMAND_COMPLETE" id:mesh_state" class="sref">mesh_s1182>d;1111<3" id="L132" casefe=scsi_cmnd" clEXTENDED_MESSAGEs="sref">u8EXTENDED_MESSAGE" id:mesh_state" class="sref">mesh_s1184>d;11mesh_stateu8msgis[2])e=mesh_state" class="sref">mesh_s1185>d;11u8EXTENDED_MODIFY_DATA_POINTER" id:mesh_state" class="sref">mesh_s1186>d;11 144mesh_state        int  data_pt/" id=+fftmesh_state" class="sref">mesh_stateu8msgis[3]o>lt;< 24) +fmesh_state" class="sref">mesh_stateu8msgis[6]mesh_state" class="sref">mesh_s1187>d;11mesh_stateu8msgis[4]o>lt;< 16) +ftmesh_state" class="sref">mesh_stateu8msgis[5]o>lt;< 8)*11<8" id="L118" ="L125" 25"     break*11<9" id="L159" ="L147" casefe=scsi_cmnd" clEXTENDED_SDTRs="sref">u8EXTENDED_SDTR" id:mesh_state" class="sref">mesh_s119">d;11static voitp/a> ef="+code=device" cl dtr   static voi dtr           int    dtr  e/a" id)e=mesh_state" class="sref">mesh_s1191>d;111192" id="L132" ="L125"  "L125" "L125"  m=scsi_cmnd" cladd_ dtr msg>        int   add_ dtr msgte=scsi_cmnd" clss="sref">mesh_state11<3" id="L132" ="L125" 25"     "L125"  m"L193" class="line" nam limit period=to at least his value,h.c#L2" na2s="s3/5ef=hase_mismatch1194>d;111195" id="L132" ="L125" "L125" 222222222if (class="line" nass="sref">mesh_statemesh_stmseout/a> [3]o>lt;fmesh_state" class="sref">mesh_stateu8msgis[3]*#de111hre>11<6" id="L156" ="L125" 25"     25"     "L125"  mlass="line" nass="sref">mesh_statemesh_stmseout/a> [3]offe=scsi_cmnd" clss="sref">mesh_stateu8msgis[3]*11<7" id="L147" ="L125" 25"     22222222if (class="line" nass="sref">mesh_statemesh_stmseout/a> [4]o>="+ mesh_state" class="sref">mesh_stateu8msgis[4]*11<8" id="L118" ="L125" 25"     25"     "L125"  mlass="line" nass="sref">mesh_statemesh_stmseout/a> [4]offe=scsi_cmnd" clss="sref">mesh_stateu8msgis[4]*11<9" id="L159" ="L147" "L125" 2"L125"  mlass="line" naset_ dtr>        int    et_ dtrtmesh_state" class="sref">mesh_state mlass="line" nass="sref">mesh_statemesh_stmseout/a> [3]> mlass="line" nass="sref">mesh_statemesh_stmseout/a> [4]t*d;12f">d href="drivers/scsi/12f">>12f"" id="L159" ="L147" 25"     "L125"  mlass="line" nass="sref">mesh_stateu8mse clas    offe=scsi_cmnd" clssg_out="sref">mesh_stmse_out/a> *1201" id="L151" ="L125"         } elsee=mesh_state" class="sref">mesh_s12f2>d;12fa href="drivers/scsi/me12fa >1202" id="L132" ="L125"  "L125" "L125"  mlass="line" naset_ dtr>        int    et_ dtrtmesh_state" class="sref">mesh_state mlass="line" nass="sref">mesh_stateu8msgis[3]> mlass="line" nass="sref">mesh_stateu8msgis[4]t*1203" id="L132" ="L125" 125"  = }s reset delay (0=no reset)"12f4>d;12fa href="drivers/scsi/me12fa >12f4" id="L134" ="L125" 125"  = break*12f5" id="L132" ="L125" default:mesh_state" class="sref">mesh_s12f6>d;12fref="+code=mesh_st>#de112fre>12f6" id="L156" ="L125"         goco e=scsi_cmnd" clrejec"="sref">mesh_strejec" 1207" id="L147" ="L125" }s reset delay (0=no reset)"12f8>d;12f
12f9" id="L159" casefe=scsi_cmnd" clSAVE_POINTERS5static voiSAVE_POINTERS" id:mesh_state" class="sref">mesh_s121">d;12static voitp/a> ef="+code=device" cl aved_pt/a>        int   aved_pt/    offe=scsi_cmnd" clss="sref">mesh_state        int  data_pt/" id*1211" id="L151" ="L125" break*12<2" id="L132" casefe=scsi_cmnd" clRESTORE_POINTERS5static voiRESTORE_POINTERS" id:mesh_state" class="sref">mesh_s1213>d;12 144mesh_state        int  data_pt/" id=ffe=scsi_cmnd" cltp5static voitp/a> ef="+code=device" cl aved_pt/a>        int   aved_pt/    *1214" id="L134" ="L125" break*1215" id="L132" casefe=scsi_cmnd" clDISCONNECT="sref">mesh_stDISCONNECT" id:mesh_state" class="sref">mesh_s1216>d;12mesh_stateu8      scsi_cmdisnonnec"fng    *1217" id="L147" ="L125" break*1218" id="L118" casefe=scsi_cmnd" clABORT="sref">mesh_stABORT    :mesh_state" class="sref">mesh_s1219>d;12d;12mesh_stMESSAGE_REJECT    :mesh_state" class="sref">mesh_s1221>d;12static voitp/a> ef="+code=device" cl dtr   static voi dtr           int    dtr  e/a" id)mesh_state" class="sref">mesh_s1222>d;12        int    et_ dtrtmesh_state" class="sref">mesh_state 0> 0t*1223" id="L132" ="L125" break*1224" id="L147" casefe=scsi_cmnd" clNOP="sref">mesh_stNOP    :mesh_state" class="sref">mesh_s1225>d;1212<6" id="L156" default:mesh_state" class="sref">mesh_s1227>d;12u8IDENTIFY_BASE" id=>lt;ffe=scsi_cmnd" cl" cl="sref">scsi_cmnodr" ido>scsi_cmnodr" ido>lt;ffe=scsi_cmnd" clIDENTIFY_BASEs="sref">u8IDENTIFY_BASE" id=+ 7)e=mesh_state" class="sref">mesh_s1228>d;12scsi_cmnd =fffe=scsi_cmnd" clNULL="sref">mesh_stNULL" id)e=mesh_state" class="sref">mesh_s1229>d;12mesh_stdo abortte=scsi_cmnd" clss="sref">mesh_stated;12mesh_stateu8mse clas    offe=scsi_cmnd" clssg_out="sref">mesh_stmse_out/a> *1231" id="L151" ="L125"         } elseeif (cesh_state" claa8cl="sref">scsi_cmnodr" ido!ffe=scsi_cmnd" cl"ss="sref">scsi_cmnd ef="+code=device" cldevi      void    * ef="+code=device" clluss="sref">u8lus" id=+ e=scsi_cmnd" clIDENTIFY_BASEs="sref">u8IDENTIFY_BASE" id)e=mesh_state" class="sref">mesh_s1232>d;12u8 etstmesh_state" claKERN>WARNING="sref">mesh_stKERN>WARNING" id=mICENSE" class="sref">MODULm>N_: lun mismatce quot;Initial mesh_state" class="sref">mesh_s1233>d;12MODUL(%d !ff%d) on reselec"ios from quot;Initial mesh_state" class="sref">mesh_s1234>d;12MODULtf="+c %d\nquot;Initial o e=scsi_cmnd" cl" cl="sref">scsi_cmnodr" ido- e=scsi_cmnd" clIDENTIFY_BASEs="sref">u8IDENTIFY_BASE" ido1235" id="L132" ="L125" "L125" 222222222L125"  mlass="line" na"ss="sref">scsi_cmnd ef="+code=device" cldevi      void    * ef="+code=device" clluss="sref">u8lus" id> mesh_state" class="sref">mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"1236>d;12d;121238" id="L118" ="L125" }s reset delay (0=no reset)"1239>d;12mesh_strejec" d;12d;12d;12d;12mesh_strejec" mesh_s12<4>d;12u8 etstmesh_state" claKERN>WARNING="sref">mesh_stKERN>WARNING" id=mICENSE" class="sref">MODULm>N_: rejec"fng ">msage from tf="+c %d:quot;Initial o1245" id="L132" ="L125"mesh_state" class="sref">mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"1246>d;12(class="line" naistatic void mesh_stateu8n_msgis; ++class="line" naistatic void 1247" id="L147" ="L125" class="line" naprtsu8 etstmICENSE" class="sref">MODUL %xquot;Initial o class="line" nass="sref">mesh_stateu8msgis[class="line" naistatic void 12<8" id="L118" class="line" naprtsu8 etstmICENSE" class="sref">MODUL\nquot;Initial )us reset delay (0=no reset)"12<9>d;12mesh_statemesh_stmseout/a> [0]offe=scsi_cmnd" clMESSAGE_REJECT="sref">mesh_stMESSAGE_REJECT    us reset delay (0=no reset)"125">d;12mesh_statemesh_stn_mseout/a> of 1us reset delay (0=no reset)"1251>d;12mesh_stateu8mse clas    offe=scsi_cmnd" clssg_out="sref">mesh_stmse_out/a> *1252" id}s reset delay (0=no reset)"1253>d;12d;12mesh_s1255>d;12mesh_s1256>d;1212<7" id  mesh_st et_dma_ndtne" name="L144"> 144     static voicemesh_state 144ms, struc"sre_5mef" id=*mesh_state" cla"ss="sref">scsi_cmnd *12<8" id=mesh_state" class="sref">mesh_s12<9>d;12 144 mesh_state" cladma_nd<    void    * mesh_state" clatotal5static voitotale mesh_state" claoff5static voioffe mesh_state" cladtot    void    * *d;12 144        int    catterlisa" id=*mesh_state" clascl5static voiscl/a> *1261" id="L118" ne" name="L144"> 144mesh_stdnd*1262" ids reset delay (0=no reset)"1263>d;12mesh_statemesh_sttgtsemesh_statescsi_cmnonn_et<    ].mesh_state" cladata_goes_out="sref">mesh_stdata_goes_out    ?s reset delay (0=no reset)"1264>d;12u8OUTPUT_MORE u8INPUT_MORE*12<5" id="L132" mesh_state" cladndmesh_stdndoffe=scsi_cmnd" clss="sref">mesh_statemesh_stdma_nd*12<6" id="L156" mesh_state" cladtot    void    * of 0as reset delay (0=no reset)"1267>d;12scsi_cmnd *e=mesh_state" class="sref">mesh_s1268>d;12 144scsi_cmnseg*12<9" idd;12scsi_cmnd ef="+code=device" clSCp5static voiSCp/a> .mesh_state" clathis residual5static voithis residualoffe=scsi_cmnd" cl"sre_buffless="sref">u8"sre_bufflestmesh_state" cla"ss="sref">scsi_cmnd **1271" id12<2" id="L132" ="L127" +code=__iomem" nseg="sref">scsi_cmnsegoffe=scsi_cmnd" cl"sre_dma_map5static voi"sre_dma_maptmesh_state" cla"ss="sref">scsi_cmnd **1273" id="L132" ="L125" e="L144"> 144u8BUG_ONtmesh_state" clanseg="sref">scsi_cmnsego< 0t*1274" id1275" id="L132" ="L125" if (class="line" nanseg="sref">scsi_cmnseg*e=mesh_state" class="sref">mesh_s12<6>d;12 144static voitotaled;12 144static voioffemesh_state        int  data_pt/" id*1278" ids reset delay (0=no reset)"1279>d;12 144scsi_cmssre_for_eaca  gtmesh_state" cla"ss="sref">scsi_cmnd > mesh_state" clascl5static voiscl/a> > mesh_state" clanseg="sref">scsi_cmnseg> mesh_state" claistatic void mesh_s128">d;12        int  dma_add/offe=scsi_cmnd" cl"g_dma_add/ess="sref">mesh_st g_dma_add/esstmesh_state" clascl5static voiscl/a> t*1281" id="L151" ="L125" 25"     "L125"  mlass="line" nauu8dma_lesoffe=scsi_cmnd" cl"g_dma_less="sref">u8"g_dma_lestmesh_state" clascl5static voiscl/a> t*12<2" id="L132" ="L125"                 1283" id="L132" ="L125" "L125" 25"     "e="L144"> 144static voitotalestatic voiscl/a> ef="+code=device" cllengte="sref">scsi_cmlengte*12<4" id="L134" ="L125"                 if (class="line" naoff5static voioffeu8dma_les*e=mesh_state" class="sref">mesh_s1285>d;12 144static voioffeu8dma_les*12<6" id="L156" ="L125" ="L132"                 continue*12<7" id="L147" ="L125" 25"             }s reset delay (0=no reset)"1288>d;12u8dma_leso>="+ 0xffff*12<9" id="L159" ="L147"                         class="line" napanic="sref">mesh_stpanictmICENSE" class="sref">MODULm>N_:  catterlisa eleine"of="+ff64kquot;Initial )us reset delay (0=no reset)"129">d;12mesh_stdndef="+code=device" clreq_cou/a>        int   req_cou/ae mesh_state" cladma_less="sref">u8dma_leso- e=scsi_cmnd" cloff5static voioffed;12mesh_stdndef="+code=device" cl="liand="sref">scsi_cmnoliande mesh_state" cladma_nd<    void    *d;12mesh_stdndef="+code=device" clphy_add/a>        int  phy_add/e mesh_state" cladma_add/a>        int  dma_add/o+ e=scsi_cmnd" cloff5static voioffed;12mesh_stdndef="+code=device" clxfer   mesh_stxfer   d;12mesh_stdnd*1295" id="L132" ="L125" "L125" 222222222mesh_state" cladtot    void    * o+ffe=scsi_cmnd" cldma_less="sref">u8dma_leso- e=scsi_cmnd" cloff5static voioffe#de112hre>12<6" id="L156" ="L125" 25"     25"     e="L144"> 144static voioffed;12;
d;12;
d;12;
d;13f">d href="drivers/scsi/13f">>13f"" id="L159" if (class="line" nadtot    void    * offf0*e=mesh_state" class="sref">mesh_s13f1>d;13fa href="drivers/scsi/me13fa >1301" id="L151" ="L125" m"L193" class="line" nam Either the tf="+c has olasrun our buffer,h.c#L2" na2s="s3/5ef=hase_mismatch13f2>d;13fa href="drivers/scsi/me13fa >1302" id="L194" class="line" na"L132" ===========or the caller didn't provide a buffer.=*sh.c#L2" na2s="s3/5ef=hase_mismatch13f3>d;13fa href="drivers/scsi/me13fa >1303" id="L132" ="L125"    144   extra_buf="sref">mesh_sta>   extra_bufe1304" id13f5" id="L132" ="L125" mesh_state" cladtot    void    * of sizeofte=scsi_cmnd" cls>   extra_buf="sref">mesh_sta>   extra_bufed;13fref="+code=mesh_st>#de113fre>13f6" id="L156" ="L125" class="line" nast_lemesh_stdndef="+code=device" clreq_cou/a>        int   req_cou/ae mesh_state" cladtot    void    * )us reset delay (0=no reset)"13f7>d;13f
mesh_stdndef="+code=device" clphy_add/a>        int  phy_add/e mesh_state" clavirt_to_phys="sref">mesh_stvirt_to_phystmesh_state" clas>   extra_buf="sref">mesh_sta>   extra_bufed;13f
mesh_stdndef="+code=device" clxfer   mesh_stxfer   d;13f
mesh_stdnd*d;13d;13mesh_stOUTPUT_LASTo- e=scsi_cmnd" clOUTPUT_MOREs="sref">u8OUTPUT_MORE 13<2" id="L132" class="line" nast_lemesh_stdnd[-1].mesh_state" cla="liand="sref">scsi_cmnoliande mesh_state" cladma_nd<    void    *d;13static voicems+ctmesh_state" cladndmesh_stdnd> 0> sizeoft*mesh_state" cladndmesh_stdnd))us reset delay (0=no reset)"13<4>d;13mesh_stdndef="+code=device" cl="liand="sref">scsi_cmnoliande mesh_state" claDBDMA_STOP="sref">mesh_stDBDMA_STOPed;13mesh_state        int   dma_nou/aoffe=scsi_cmnd" cldtot    void    * *13}s reset delay (0=no reset)"13<7>d;13d;13tne" name="L144"> 144     static voicemesh_stated;13mesh_s132">d;13 144mesh_stdbdma_regs" id=code=device" cl__iocem="sref">mesh_st__iocem" id=*mesh_state" clasd="sref">scsi_cmdmesh_state*1321" id="L151" vol 144mesh_stcemesh_st__iocem" id=*mesh_state" clas/a>        int  m/    offe=scsi_cmnd" clss="sref">mesh_statemesh_stce*1322" id="L132" ne" name="L144"> 144ms, struc"sre_5mef" id=*mesh_state" cla"ss="sref">scsi_cmnd offe=scsi_cmnd" clss="sref">mesh_statescsi_cmnurren" req*1323" id="L132" * 144 mesh_state" clanb    void    **1324" id1325" id="L132" if (!e=scsi_cmnd" clss="sref">mesh_statemesh_sttgtsemesh_statescsi_cmnonn_et<    ].mesh_state" cladata_goes_out="sref">mesh_stdata_goes_out    *e=mesh_state" class="sref">mesh_s1326>d;131327" id="L147" ="L125" e="L144"> 144d;13="+ 0o>t>        int  m/    ef="+code=device" clfifo_nou/a>        int   fifo_nou/a    *e!= 0s reset delay (0=no reset)"1329>d;13scsi_cmdmesh_st  u8ACTIVE    *e!= 0*e=mesh_state" class="sref">mesh_s133">d;13d;13        int  udelayt1)us reset delay (0=no reset)"1332>d;13d;13d;13scsi_cmdstatic voicontrole mesh_state" claRUNs="sref">u8RUNelt;< 16);L125" c"L193" class="line" nam turn=off RUN bit *sh.c#L2" na2s="s3/5ef=hase_mismatch13<5>d;13 fftmesh_state" clas/a>        int  m/    ef="+code=device" clnou/a_histatic void lt;< 8) +fmesh_state" clas/a>        int  m/    ef="+code=device" clnou/a_lostatic void d;13scsi_cmdlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULhalt_dma fc/nou/a=%.6xquot;Initial o1337" id="L147" ="L12mesh_state" claMKWORD="sref">mesh_stMKWORDt0o class="line" nas/a>        int  m/    ef="+code=device" clfifo_nou/a>        int   fifo_nou/a    > 0> mesh_state" clanb    void    *))us reset delay (0=no reset)"1338>d;13mesh_statemesh_sttgtsemesh_statescsi_cmnonn_et<    ].mesh_state" cladata_goes_out="sref">mesh_stdata_goes_out    *s reset delay (0=no reset)"1339>d;13 +ffe=scsi_cmnd" cls/a>        int  m/    ef="+code=device" clfifo_nou/a>        int   fifo_nou/a    us reset delay (0=no reset)"134">d;1313<1" id="L194" class="line" na"L132" ===to/from the tf="+c.=*sh.c#L2" na2s="s3/5ef=hase_mismatch13<2>d;13mesh_state        int  data_pt/" id=-ffe=scsi_cmnd" clnb    void    **1343" id="L132" mesh_state" cladlog="sref">scsi_cmdlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULdata_pt/ %xquot;Initial o class="line" nass="sref">mesh_state        int  data_pt/" id)us reset delay (0=no reset)"13<4>d;13mesh_state        int  data_pt/" id=< 0te=mesh_state" class="sref">mesh_s1345>d;13u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=cICENSE" class="sref">MODULm>N_: halt_dma: data_pt/=%d (nb=%d, ms=%p)\nquot;Initial omesh_state" class="sref">mesh_s1346>d;13mesh_state        int  data_pt/" id> mesh_state" clanb    void    *o class="line" nass="sref">mesh_stated;13mesh_state        int  data_pt/" id=ff0as reset delay (0=no reset)"1348>d;13mesh_stMESH_DBG" id1349" id="L159" ="L147" mesh_state" cladumplog="sref">scsi_cmdumplogtmesh_state" class="sref">mesh_state mesh_state" class="sref">mesh_statescsi_cmnonn_et<    )us reset delay (0=no reset)"135">d;13scsi_cmdumpslogtmesh_state" class="sref">mesh_stated;131352" id="L132" } elseeif (cesh_state" claass="sref">scsi_cmnd o>u8"sre_bufflestmesh_state" cla"ss="sref">scsi_cmnd *o>1353" id="L132" ="L125" 25"class="line" nass="sref">mesh_state        int  data_pt/" id=&="+ mesh_state" cla"sre_buffless="sref">u8"sre_bufflestmesh_state" cla"ss="sref">scsi_cmnd *te=mesh_state" class="sref">mesh_s1354>d;13u8 etstmesh_state" claKERN>DEBUG="sref">mesh_stKERN>DEBUG" id=cICENSE" class="sref">MODULm>N_: tf="+c %d olasrun, quot;Initial mesh_state" class="sref">mesh_s1355>d;13MODULdata_pt/=%x total=%x goes_out=%d\nquot;Initial omesh_state" class="sref">mesh_s1356>d;13mesh_statescsi_cmnonn_et<    o class="line" nass="sref">mesh_state        int  data_pt/" id> mesh_state" clascre_buffless="sref">u8"sre_bufflestmesh_state" cla"ss="sref">scsi_cmnd *omesh_state" class="sref">mesh_s1357>d;13mesh_statemesh_sttgtsemesh_statescsi_cmnonn_et<    ].mesh_state" cladata_goes_out="sref">mesh_stdata_goes_out    *a na2s="s3/5ef=hase_mismatch1358>d;13d;13static voi"sre_dma_unmaptmesh_state" cla"ss="sref">scsi_cmnd *a na2s="s3/5ef=hase_mismatch136">d;13mesh_stated;13d;13d;13u8 clas_mismatcetne" name="L144"> 144     static voicemesh_stated;13mesh_s1365>d;13 144mesh_stcemesh_st__iocem" id=*mesh_state" clas/a>        int  m/    offe=scsi_cmnd" clss="sref">mesh_statemesh_stce*mesh_s1366>d;13 144u8      mesh_s1367>d;13d;13scsi_cmdlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODUL     mm ch/cl/seq/fc=%.8xquot;Initial o1369" id="L159" ="L14mesh_state" claMKWORD="sref">mesh_stMKWORDtmesh_state" clas/a>        int  m/    ef="+code=device" clnou/a_histatic void         int  m/    ef="+code=device" clnou/a_lostatic void         int  m/    ef="+code=device" clsequen      void    *        int  m/    ef="+code=device" clfifo_nou/a>        int   fifo_nou/a    **a na2s="s3/5ef=hase_mismatch137">d;13u8      t>        int  m/    ef="+code=device" clbus           int  bus    *o> 144u8BS0_PHASE mesh_s1371>d;13mesh_stateu8mse clas    offfe=scsi_cmnd" clssg_out_xxxs="sref">u8mse_out_xxx/a> o>u8      mesh_stBP_MSGOUT/a> *o=mesh_state" class="sref">mesh_s1372>d;13msage, without ATN=*sh.c#L2" na2s="s3/5ef=hase_mismatch1373>d;13 144t>        int  m/    ef="+code=device" clnou/a_lostatic void d;13t>        int  m/    ef="+code=device" clsequen      void    *mesh_stSEQ_MSGOUT + class="line" nauas_acty (_neg="sref">scsi_cmuas_acty (_neg/a> *a na2s="s3/5ef=hase_mismatch13<5>d;13 144tmesh_state" clas/a>        int  m/    *a na2s="s3/5ef=hase_mismatch13<6>d;13        int  udelayt1)us reset delay (0=no reset)"1377>d;13t>        int  m/    ef="+code=device" clfifo>        int   fifo    o class="line" nass="sref">mesh_statemesh_stmseout/a> [class="line" nass="sref">mesh_statemesh_stn_mseout/a> -1]t*1378" id="L118" ="L125" mesh_state" class="sref">mesh_stateu8mse clas    offe=scsi_cmnd" clssg_out_ clts="sref">u8mse_out_ clt mesh_s1379>d;13d;13d;1313<2" id="L132" if (class="line" nass="sref">mesh_stateu8mse clas    offfe=scsi_cmnd" clssg_iss="sref">u8msg_is*e=mesh_state" class="sref">mesh_s1383>d;13u8get_mseistmesh_state" class="sref">mesh_stated;13mesh_stateu8n_msgis*s reset delay (0=no reset)"1385>d;13u8handle_mseistmesh_state" class="sref">mesh_stated;13d;13d;13mesh_stated;13tmesh_state" class="sref">mesh_stated;13        int  m/    ef="+code=device" clfifo_nou/a>        int   fifo_nou/a    *e=mesh_state" class="sref">mesh_s1391>d;13t>        int  m/    ef="+code=device" clsequen      void    *mesh_stSEQ_FLUSHFIFOed;13 144tmesh_state" clas/a>        int  m/    *a na2s="s3/5ef=hase_mismatch1393>d;13        int  udelayt1)us reset delay (0=no reset)"1394>d;13d;13d;13href="+code=mesh_st>#de113hre>1396" id="L156" mesh_state" class="sref">mesh_stateu8mse clas    offe=scsi_cmnd" clssg_nonss="sref">u8mse_nons mesh_s1397>d;13;
u8      mesh_s1398>d;13;
u8BP_DATAIN" id:mesh_state" class="sref">mesh_s1399>d;13;
mesh_statemesh_sttgtsemesh_statescsi_cmnonn_et<    ].mesh_state" cladata_goes_out="sref">mesh_stdata_goes_out    =ff0as reset delay (0=no reset)"14f">d;14f">d href="drivers/scsi/14f">>140"" id="L159" ="L147" +code=__iomem" ss="sref">mesh_stateu8      mesh_stdatasre mesh_s14f1>d;14fa href="drivers/scsi/me14fa >1401" id="L151" ="L125" break*mesh_s14f2>d;14fa href="drivers/scsi/me14fa >1402" id="L118" c   fe=scsi_cmnd" clBP_DATAOUT="sref">mesh_stBP_DATAOUT" id:mesh_state" class="sref">mesh_s14f3>d;14fa href="drivers/scsi/me14fa >1403" id="L132" ="L125" code=device" clss="sref">mesh_statemesh_sttgtsemesh_statescsi_cmnonn_et<    ].mesh_state" cladata_goes_out="sref">mesh_stdata_goes_out    =ff1us reset delay (0=no reset)"14f4>d;14fa href="drivers/scsi/me14fa >1404" id="L134" ="L125" mesh_state" class="sref">mesh_stateu8      mesh_stdatasre mesh_s14f5>d;14fa href="drivers/scsi/me14fa >14f5" id="L132" ="L125" break*mesh_s14f6>d;14fref="+code=mesh_st>#de114fre>14f6" id="L156" c   fe=scsi_cmnd" clBP_COMMAND="sref">mesh_stBP_COMMAND" id:mesh_state" class="sref">mesh_s14f7>d;14f
mesh_stateu8      mesh_stnoliandsre mesh_s14f8>d;14f
mesh_s14f9>d;14f
mesh_stBP_STATUS" id:mesh_state" class="sref">mesh_s141">d;14mesh_stateu8      mesh_st  mesh_s14<1>d;14mesh_s1412>d;14u8BP_MSGIN" id:mesh_state" class="sref">mesh_s1413>d;14mesh_stateu8mse clas    offe=scsi_cmnd" clssg_iss="sref">u8msg_is*mesh_s1414>d;14mesh_stateu8n_msgis=ff0as reset delay (0=no reset)"1415>d;14mesh_s1416>d;14mesh_stBP_MSGOUT/a> :mesh_state" class="sref">mesh_s1417>d;14mesh_stateu8mse clas    offe=scsi_cmnd" clssg_outs="sref">u8mse_out*mesh_s1418>d;14mesh_statemesh_stn_mseout/a> offf0*e=mesh_state" class="sref">mesh_s1419>d;14mesh_statemesh_stabortsre mesh_s142">d;14mesh_stdo_aborttmesh_state" class="sref">mesh_stated;14mesh_s1422>d;14mesh_statemesh_st clt_n_mseout/a> offf0*e=mesh_state" class="sref">mesh_s1423>d;14u8 etstmesh_state" claKERN>DEBUG="sref">mesh_stKERN>DEBUG" idmesh_state" class="sref">mesh_s1424>d;14MODULm>N_: no mse to repeat\nquot;Initial )us reset delay (0=no reset)"1425>d;14mesh_statemesh_stmseout/a> [0]offe=scsi_cmnd" clNOP="sref">mesh_stNOPed;14mesh_statemesh_st clt_n_mseout/a> off1us reset delay (0=no reset)"1427>d;14d;14mesh_statemesh_stn_mseout/a> of class="line" nass="sref">mesh_statemesh_st clt_n_mseout/a> us reset delay (0=no reset)"1429>d;14d;14d;14mesh_s1432>d;14mesh_s1433>d;14u8 etstmesh_state" claKERN>DEBUG="sref">mesh_stKERN>DEBUG" id=cICENSE" class="sref">MODULm>N_: unknown "sre  clas %x\nquot;Initial o e=scsi_cmnd" cl class="sref">u8      d;14mesh_statemesh_st   of class="line" naDID>ERRORs="sref">u8DID>ERROR/a> us reset delay (0=no reset)"14<5>d;14 144u8metmesh_state" class="sref">mesh_stated;14d;14d;14d;14u8"tf=t_ clastmesh_state" class="sref">mesh_stated;14d;141442" id  static voicmd_complea8tne" name="L144"> 144     static voicemesh_stated;14mesh_s14<4>d;14 144mesh_stcemesh_st__iocem" id=*mesh_state" clas/a>        int  m/    offe=scsi_cmnd" clss="sref">mesh_statemesh_stce*mesh_s14<5>d;14 144ms, struc"sre_5mef" id=*mesh_state" cla"ss="sref">scsi_cmnd offe=scsi_cmnd" clss="sref">mesh_statescsi_cmnurren" req*1446" id="L156" ne" name="L144"> 144mesh_stcestatic voitp/a> off>mesh_statemesh_sttgtsemesh_statescsi_cmnonn_et<    ]*1447" id="L147" * 144scsi_cmseq> mesh_state" clan="sref">mesh_stn> mesh_state" clat    void    *d;14d;14scsi_cmdlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULcmd_complea8 fc=%xquot;Initial o class="line" nas/a>        int  m/    ef="+code=device" clfifo_nou/a>        int   fifo_nou/a    *as reset delay (0=no reset)"145">d;14scsi_cmseqoffe=scsi_cmnd" cluas_acty (_neg="sref">scsi_cmuas_acty (_neg/a>  + (class="line" nass="sref">mesh_statemesh_stn_mseout/a> ? class="line" naSEQ_ATNs="sref">u8SEQ_ATN/a> : 0*as reset delay (0=no reset)"1451>d;14mesh_stateu8mse clas    *e=mesh_state" class="sref">mesh_s1452>d;14u8mse_out_xxx/a> :mesh_state" class="sref">mesh_s1453>d;141454" id="L134" ="L125" mesh_state" class="sref">mesh_stateu8n_msgis=ff0as reset delay (0=no reset)"1455>d;14mesh_stateu8mse clas    offe=scsi_cmnd" clssg_iss="sref">u8msg_is*mesh_s1456>d;141457" ids reset delay (0=no reset)"1458>d;14u8msg_is:mesh_state" class="sref">mesh_s1459>d;14msage bytes in fifo *sh.c#L2" na2s="s3/5ef=hase_mismatch146">d;14u8get_mseistmesh_state" class="sref">mesh_stated;14mesh_stnoffe=scsi_cmnd" clssgin_lengta="sref">mesh_stcsgin_lengtatmesh_state" class="sref">mesh_stated;14mesh_stateu8n_msgis=< mesh_state" clan="sref">mesh_stn*e=mesh_state" class="sref">mesh_s1463>d;14t>        int  m/    ef="+code=device" clnou/a_lostatic void mesh_stno- e=scsi_cmnd" clss="sref">mesh_stateu8n_msgis*us reset delay (0=no reset)"1464>d;14t>        int  m/    ef="+code=device" clsequen      void    *u8SEQ_MSGIN/a>  + mesh_state" claseq="sref">scsi_cmseq*us reset delay (0=no reset)"1465>d;14mesh_s1466>d;14mesh_stateu8mse clas    offe=scsi_cmnd" clssg_nonss="sref">u8mse_nons mesh_s1467>d;14u8handle_mseistmesh_state" class="sref">mesh_stated;14u8"tf=t_ clastmesh_state" class="sref">mesh_stated;14d;14mesh_s1471>d;141472" id="L118" c   fe=scsi_cmnd" clssg_in_bad="sref">scsi_cmdsg_in_bad:mesh_state" class="sref">mesh_s1473>d;14 144t>        int  m/    ef="+code=device" clsequen      void    *mesh_stSEQ_FLUSHFIFOed;14tmesh_state" clas/a>        int  m/    *a na2s="s3/5ef=hase_mismatch14<5>d;14 144        int  udelayt1)us reset delay (0=no reset)"14<6>d;14t>        int  m/    ef="+code=device" clnou/a_lostatic void d;14t>        int  m/    ef="+code=device" clsequen      void    *u8SEQ_MSGIN/a>  + mesh_state" claSEQ_ATNs="sref">u8SEQ_ATN/a>  + class="line" nauas_acty (_neg="sref">scsi_cmuas_acty (_neg/a> *a na2s="s3/5ef=hase_mismatch1478>d;14mesh_s1479>d;14mesh_s148">d;14u8mse_out:mesh_state" class="sref">mesh_s1481>d;1414<2" id="L194" class="line" na"L132" =========* To "+c the righc timing on ATN=wrt ACK, we haveh.c#L2" na2s="s3/5ef=hase_mismatch1483>d;1414<4" id="L194" class="line" na"L132" =========* clae=te<, then drop ATN.  To do this we firlt 14<5" id="L194" class="line" na"L132" =========* issue a SEQ_MSGOUT with ATN=and wait for REQ, 14<6" id="L194" class="line" na"L132" =========* then change the noliand to a SEQ_MSGOUT w/o ATN. 1487" id="L194" class="line" na"L132" =========* If we don't see REQ in a reasonable time, weh.c#L2" na2s="s3/5ef=hase_mismatch1488>d;1414<9" id="L194" class="line" na"L132" =========* wait for the  clas mismatce=intasrupt, then d;141491" id="L194" class="line" na"L132" =========*sh.c#L2" na2s="s3/5ef=hase_mismatch1492>d;14 144t>        int  m/    ef="+code=device" clnou/a_lostatic void d;14t>        int  m/    ef="+code=device" clsequen      void    *mesh_stSEQ_MSGOUT + class="line" nauas_acty (_neg="sref">scsi_cmuas_acty (_neg/a>  + mesh_state" claSEQ_ATNs="sref">u8SEQ_ATN/a> )us reset delay (0=no reset)"1494>d;141495" id="L132" ="L125" while (tmesh_state" clain_8    void    *t>        int  m/    ef="+code=device" clbus           int  bus    *o> 144        int  BS0_REQ/a> *offf0o>1496>d;14href="+code=mesh_st>#de114hre>1496" id="L156" ="L125" ="L125" code=device" cludelaya>        int  udelayt1)us reset delay (0=no reset)"1497>d;14;
scsi_cmdlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULlclt_mbyte=asr/exc/fc/nl=%.8xquot;Initial o1498" id="L118" ="L125"      mesh_state" claMKWORD="sref">mesh_stMKWORDtmesh_state" clas/a>        int  m/    ef="+code=device" clasro/a>        int  asro/e        int  m/    ef="+code=device" claxceptioss="sref">u8axceptiose1499" id="L159" ="L147" "L125"      mesh_state" clas/a>        int  m/    ef="+code=device" clfifo_nou/a>        int   fifo_nou/a    o class="line" nas/a>        int  m/    ef="+code=device" clnou/a_lostatic void d;15f">d href="drivers/scsi/15f">>150"" id="L159" ="L147" if (class="line" nain_8    void    *t>        int  m/    ef="+code=device" clintasrupt    void    * *o>ERRORs="sref">u8INT>ERROR" id=| class="line" naINT>EXCEPTIONs="sref">u8INT>EXCEPTIONemesh_s15f1>d;15fa href="drivers/scsi/me15fa >1501" id="L151" ="L125" 5"      m"L193" class="line" nam whoops, tf="+c didn't do what we expected *sh.c#L2" na2s="s3/5ef=hase_mismatch15f2>d;15fa href="drivers/scsi/me15fa >1502" id="L132" ="L125" ="L147" code=device" clss="sref">mesh_statemesh_st clt_n_mseout/a> offe=scsi_cmnd" clss="sref">mesh_statemesh_stn_mseout/a> a na2s="s3/5ef=hase_mismatch15f3>d;15fa href="drivers/scsi/me15fa >1503" id="L132" ="L125" ="L147" code=device" clss="sref">mesh_statemesh_stn_mseout/a> of 0as reset delay (0=no reset)"15f4>d;15fa href="drivers/scsi/me15fa >1504" id="L134" ="L125" ="L147" if (class="line" nain_8    void    *t>        int  m/    ef="+code=device" clintasrupt    void    * *o>ERRORs="sref">u8INT>ERROR" id*e=mesh_state" class="sref">mesh_s15f5>d;15fa href="drivers/scsi/me15fa >15f5" id="L132" ="L125" ="L125" ="L147" code=device" clprtsu8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=cICENSE" class="sref">MODULm>N_: asro/ %x in mse_out\nquot;Initial omesh_state" class="sref">mesh_s15f6>d;15fref="+code=mesh_st>#de115fre>1506" id="L156" ="L125" ="L125"                class="line" nain_8    void    *t>        int  m/    ef="+code=device" clasro/a>        int  asro/e1507" id="L147" ="L125"                 class="line" nahandle_asro/a>        int  handle_asro/tmesh_state" class="sref">mesh_stated;15f
d;15f
d;15t>        int  m/    ef="+code=device" claxceptioss="sref">u8axceptioseu8EXC_PHASEMMed;15u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=cICENSE" class="sref">MODULm>N_: axc %x in mse_out\nquot;Initial omesh_state" class="sref">mesh_s1512>d;15t>        int  m/    ef="+code=device" claxceptioss="sref">u8axceptiosed;15d;15u8 etstmesh_state" claKERN>DEBUG="sref">mesh_stKERN>DEBUG" id=cICENSE" class="sref">MODULm>N_: bs0=%x in mse_out\nquot;Initial omesh_state" class="sref">mesh_s1515>d;15t>        int  m/    ef="+code=device" clbus           int  bus    *)us reset delay (0=no reset)"1516>d;15u8handle_axceptiostmesh_state" class="sref">mesh_stated;15d;15d;15t>        int  m/    ef="+code=device" clbus           int  bus    *o> 144        int  BS0_REQ/a> *o=mesh_state" class="sref">mesh_s152">d;15t>        int  m/    ef="+code=device" clsequen      void    *mesh_stSEQ_MSGOUT + class="line" nauas_acty (_neg="sref">scsi_cmuas_acty (_neg/a> *a na2s="s3/5ef=hase_mismatch1521>d;15tmesh_state" clas/a>        int  m/    *a na2s="s3/5ef=hase_mismatch1522>d;15        int  udelayt1)us reset delay (0=no reset)"1523>d;15t>        int  m/    ef="+code=device" clfifo>        int   fifo    o class="line" nass="sref">mesh_statemesh_stmseout/a> [class="line" nass="sref">mesh_statemesh_stn_mseout/a> -1]t*1524" id="L134" ="L125"         class="line" nass="sref">mesh_stateu8mse clas    offe=scsi_cmnd" clssg_out_ clts="sref">u8mse_out_ clt mesh_s1525>d;15mesh_s1526>d;15t>        int  m/    ef="+code=device" clsequen      void    *u8SEQ_MSGIN/a>  + mesh_state" clauas_acty (_neg="sref">scsi_cmuas_acty (_neg/a>  + mesh_state" claSEQ_ATNs="sref">u8SEQ_ATN/a> )us reset delay (0=no reset)"1527>d;15mesh_stateu8mse clas    offe=scsi_cmnd" clssg_out_xxxs="sref">u8mse_out_xxx/a> us reset delay (0=no reset)"1528>d;15d;15mesh_s153">d;15mesh_s1531>d;15u8mse_out_ clt mesh_s1532>d;15 144mesh_statemesh_st clt_n_mseout/a> offe=scsi_cmnd" clss="sref">mesh_statemesh_stn_mseout/a> a na2s="s3/5ef=hase_mismatch1533>d;15mesh_statemesh_stn_mseout/a> of 0as reset delay (0=no reset)"1534>d;15mesh_stateu8mse clas    offe=scsi_cmnd" clss="sref">mesh_state        int  expect_replyeu8msg_is:fe=scsi_cmnd" clssg_nonss="sref">u8mse_nons mesh_s15<5>d;15 144u8"tf=t_ clastmesh_state" class="sref">mesh_stated;15mesh_s1537>d;15d;15u8mse_nons mesh_s1539>d;15mesh_stateu8      mesh_s154">d;15u8idls mesh_s1541>d;15u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=cICENSE" class="sref">MODULm>N_: intasrupt in idls  clas?\nquot;Initial )us reset delay (0=no reset)"15<2>d;15scsi_cmdumpslogtmesh_state" class="sref">mesh_stated;15d;15mesh_st electsre mesh_s1545>d;15scsi_cmdlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULSelectsre  clas at noliand compleaionquot;Initial o0*as reset delay (0=no reset)"1546>d;15mesh_statemesh_stmseout/a> [0]offe=scsi_cmnd" clIDENTIFYs="sref">u8IDENTIFYtmesh_state" claALLOW_RESELs="sref">u8ALLOW_RESELtmesh_state" class="sref">mesh_statescsi_cmnonn_et<    )omesh_state" class="sref">mesh_s1547>d;15scsi_cmnd ? class="line" na"ss="sref">scsi_cmnd ef="+code=device" cldevi      void    *u8lus:f0*)us reset delay (0=no reset)"1548>d;15mesh_statemesh_stn_mseout/a> of 1us reset delay (0=no reset)"15<9>d;15mesh_state        int  expect_replyed;15mesh_statemesh_stabortsre mesh_s1551>d;15mesh_statemesh_stmseout/a> [0]offe=scsi_cmnd" clABORT="sref">mesh_stABORT mesh_s1552>d;15mesh_statemesh_stn_mseout/a> ++*mesh_s1553>d;15static voitp/a> ef="+code=device" clsdtr   static voisdtr   mesh_s1554>d;15msage *sh.c#L2" na2s="s3/5ef=hase_mismatch1555>d;15mesh_stadd_sdtr_msetmesh_state" class="sref">mesh_stated;15mesh_state        int  expect_replyed;15static voitp/a> ef="+code=device" clsdtr   static voisdtr           int   sdtr  e/a mesh_s1558>d;15d;15mesh_stateu8mse clas    offe=scsi_cmnd" clssg_outs="sref">u8mse_out*mesh_s156">d;151561" id="L194" class="line" na"L132" =================* We need to wait for REQ before droppsre ATN. 1562" id="L194" class="line" na"L132" =================* We wait for at most 30us, then fall back to 1563" id="L194" class="line" na"L132" =================* a scheme where we issue a SEQ_COMMAND with ATN, 1564" id="L194" class="line" na"L132" =================* which will gf=h us a  clas mismatce=intasrupt/ac#L2" na2s="s3/5ef=hase_mismatch1565>d;15msage. 1566" id="L194" class="line" na"L132" =================*sh.c#L2" na2s="s3/5ef=hase_mismatch1567>d;151568" id="L118" ="L125"         while (tmesh_state" clain_8    void    *t>        int  m/    ef="+code=device" clbus           int  bus    *o> 144        int  BS0_REQ/a> *offf0*e=mesh_state" class="sref">mesh_s1569>d;15mesh_s157">d;15scsi_cmdlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULimpatine" for reqquot;Initial o class="line" nass="sref">mesh_statemesh_stn_mseout/a> )us reset delay (0=no reset)"1571>d;15mesh_stateu8mse clas    offe=scsi_cmnd" clssg_nonss="sref">u8mse_nons mesh_s1572>d;15mesh_s1573>d;15d;15        int  udelayt1)us reset delay (0=no reset)"15<5>d;15d;15mesh_s1577>d;15mesh_stdatasre mesh_s1578>d;15mesh_state        int   dma_nou/a" id=!ff0*e=mesh_state" class="sref">mesh_s1579>d;15 144u8"tf=t_ clastmesh_state" class="sref">mesh_stated;15d;15d;151583" id="L194" class="line" na"L132" =================* We c194"+c a  clas mismatce=here if the tf="+c" c#L2" na2s="s3/5ef=hase_mismatch1584>d;1515<5" id="L194" class="line" na"L132" =================* had a noliand compleae=intasrupt.  Then, if weh.c#L2" na2s="s3/5ef=hase_mismatch1586>d;151587" id="L194" class="line" na"L132" =================* asro/ intasrupt.  Which isn't so bad axcept thac" c#L2" na2s="s3/5ef=hase_mismatch1588>d;15mh actually executes the" c#L2" na2s="s3/5ef=hase_mismatch1589>d;15d;151591" id="L194" class="line" na"L132" =================*sh.c#L2" na2s="s3/5ef=hase_mismatch1592>d;15t>        int  m/    ef="+code=device" clsequen      void    *d;15t>        int  m/    ef="+code=device" clintasrupt    void    * omesh_state" class="sref">mesh_s1594>d;15ERRORs="sref">u8INT>ERROR" id=| class="line" naINT>EXCEPTIONs="sref">u8INT>EXCEPTIONeCMDDONEs="sref">u8INT>CMDDONEed;15u8halt_dmatmesh_state" class="sref">mesh_stated;15href="+code=mesh_st>#de115hre>1596" id="L156" ="L125" ="L125" break*mesh_s1597>d;15;
mesh_st  mesh_s1598>d;15;
scsi_cmnd *e=mesh_state" class="sref">mesh_s1599>d;15;
scsi_cmnd ef="+code=device" clSCp5static voiSCp/a> .code=device" clS static voiS         int  m/    ef="+code=device" clfifo>        int   fifo    *mesh_s16f">d;16f">d href="drivers/scsi/16f">>160"" id="L159" ="L147" ="L125"         if (class="line" naDEBUG_TARGET="sref">mesh_stDEBUG_TARGETtmesh_state" cla"ss="sref">scsi_cmnd *)s reset delay (0=no reset)"16f1>d;16fa href="drivers/scsi/me16fa >1601" id="L151" ="L125" 5"      "L125"          mesh_state" claprtsu8 etstmesh_state" claKERN>DEBUG="sref">mesh_stKERN>DEBUG" id=cICENSE" class="sref">MODULm>N_:   mesh_s16f2>d;16fa href="drivers/scsi/me16fa >1602" id="L132" ="L125" ="L147" "L147" "L125"          mesh_state" cla"ss="sref">scsi_cmnd ef="+code=device" clSCp5static voiSCp/a> .code=device" clS static voiS d;16fa href="drivers/scsi/me16fa >1603" id="L132" ="L125" ="L147" }s reset delay (0=no reset)"16f4>d;16fa href="drivers/scsi/me16fa >1604" id="L134" ="L125" ="L147" e=scsi_cmnd" clss="sref">mesh_stateu8mse clas    offe=scsi_cmnd" clssg_iss="sref">u8msg_is*mesh_s16f5>d;16fa href="drivers/scsi/me16fa >16f5" id="L132" ="L125" ="L125" break*mesh_s16f6>d;16fref="+code=mesh_st>#de116fre>1606" id="L156" ="L125" c   fe=scsi_cmnd" clbusfreesref"sref">mesh_stbusfreesre mesh_s16f7>d;16f
u8metmesh_state" class="sref">mesh_state 1)us reset delay (0=no reset)"16f8>d;16f
d;16f
mesh_stdisnonnectsre mesh_s161">d;16mesh_statescsi_cmcurrne"_req    offe=scsi_cmnd" clNULLs="sref">u8NULL*mesh_s1611>d;16mesh_stateu8      u8idls mesh_s1612>d;16u8metmesh_state" class="sref">mesh_stated;16d;16mesh_s1615>d;16mesh_s1616>d;16d;16mesh_stateu8      mesh_s1618>d;16 144u8"tf=t_ clastmesh_state" class="sref">mesh_stated;16mesh_s162">d;16d;16d;16d;16d;161625" id="L194" class="line" na* Called by midlayer with host locked to queue a newh.c#L2" na2s="s3/5ef=hase_mismatch1626>d;161627" id="L194" class="line" na*sh.c#L2" na2s="s3/5ef=hase_mismatch1628>d;16u8sets="uct e=scsi_cmnd" cl_mis_cmns="sref">scsi_cm_mis_cmns" id=*mesh_state" cla"ss="sref">scsi_cmnd , void (*mesh_state" cladonss="sref">u8dons)ts="uct e=scsi_cmnd" cl_mis_cmns="sref">scsi_cm_mis_cmns" id=**)s reset delay (0=no reset)"1629>d;16mesh_s163">d;16static voimemesh_statemesh_s1631>d;161632" id="L132" mesh_state" cla"ss="sref">scsi_cmnd ef="+code=device" cl_mis_donss="sref">u8_mis_dons u8dons*mesh_s1633>d;16scsi_cmnd ef="+code=device" clhost_scribblss="sref">u8host_scribbls    offe=scsi_cmnd" clNULLs="sref">u8NULL*mesh_s1634>d;16mesh_s1635>d;16mesh_statestatic voimescsi_cmnd ef="+code=device" cldevi      void    *u8hosteu8hostdata*mesh_s1636>d;16mesh_s1637>d;16mesh_statescsi_cmrequelt_qeu8NULL)s reset delay (0=no reset)"1638>d;16 144mesh_statescsi_cmrequelt_qescsi_cmnd *mesh_s1639>d;16d;16 144mesh_statescsi_cmrequelt_qtail/a> ef="+code=device" clhost_scribblss="sref">u8host_scribbls    off(void *) class="line" na"ss="sref">scsi_cmnd *mesh_s1641>d;16 144mesh_statescsi_cmrequelt_qtail/a> of class="line" na"ss="sref">scsi_cmnd *mesh_s16<2>d;16d;16mesh_stateu8      u8idls d;16u8metmesh_state" class="sref">mesh_stated;16d;16d;16d;16d;16mesh_stDEF_SCSI_QCMDtmesh_state" claseu8sed;16mesh_s1651>d;161652" id="L194" class="line" na* Called to handle intasrupts, either call by the intasrupt/ac#L2" na2s="s3/5ef=hase_mismatch1653>d;161654" id="L194" class="line" na*=axceptiosal circum  1655" id="L194" class="line" na*sh.c#L2" na2s="s3/5ef=hase_mismatch1656>d;16ts="uct e=scsi_cmnd" clmestatic voimemesh_stated;16mesh_s1658>d;16mesh_staemesh_st__iomem" id=*mesh_state" clas/a>        int  m/    offe=scsi_cmnd" clss="sref">mesh_statemesh_stae *mesh_s1659>d;16        int  int//a> *mesh_s166">d;16mesh_s1661>d;16mesh_s1662>d;16mesh_stALLOW_DEBUGtmesh_state" class="sref">mesh_statescsi_cmnonn_et<    ))s reset delay (0=no reset)"1663>d;16u8 etstmesh_state" claKERN>DEBUG="sref">mesh_stKERN>DEBUG" id=cICENSE" class="sref">MODULm>N_ intr, bs0=%x int=%x axc=%x arr=%x quot;Initial s reset delay (0=no reset)"1664>d;16MODUL     =%d mse clas=%d\nquot;Initial ofe=scsi_cmnd" cls/a>        int  m/    ef="+code=device" clbus           int  bus    omesh_state" class="sref">mesh_s1665>d;16        int  m/    ef="+code=device" clintasrupt    void    * o class="line" nas/a>        int  m/    ef="+code=device" claxceptioss="sref">u8axceptiose        int  m/    ef="+code=device" clarro/a>        int  asro/emesh_s1666>d;16mesh_stateu8      mesh_stateu8mse clas    )us reset delay (0=no reset)"1667>d;16d;16        int  int//a> offe=scsi_cmnd" clin_8    void    *t>        int  m/    ef="+code=device" clintasrupt    void    * *)=!ff0*e=mesh_state" class="sref">mesh_s1669>d;16scsi_cmdlogtmesh_state" class="sref">mesh_state mICENSE" class="sref">MODULintasrupt intr/asr/axc/seq=%.8xquot;Initial ofmesh_state" class="sref">mesh_s167">d;16mesh_stMKWORDtmesh_state" claint/a>        int  int//a> o class="line" nas/a>        int  m/    ef="+code=device" clarro/a>        int  asro/e        int  m/    ef="+code=device" claxceptioss="sref">u8axceptiose        int  m/    ef="+code=device" clsequen      void    *d;16        int  int//a> o>ERRORs="sref">u8INT>ERROR" id*e=mesh_state" class="sref">mesh_s1672>d;16        int  handle_asro/tmesh_state" class="sref">mesh_stated;16        int  int//a> o>EXCEPTIONs="sref">u8INT>EXCEPTIONemesh_s1674>d;16u8handle_axceptiostmesh_state" class="sref">mesh_stated;16        int  int//a> o>CMDDONEs="sref">u8INT>CMDDONEemesh_s1676>d;16t>        int  m/    ef="+code=device" clintasrupt    void    * o class="line" naINT>CMDDONEs="sref">u8INT>CMDDONEed;16scsi_cmnd<_compleaetmesh_state" class="sref">mesh_stated;16d;16d;16d;161682" id="L194" class="line" n/* Todo: here we c194at least try to remove the noliand from the" c#L2" na2s="s3/5ef=hase_mismatch1683>d;1616<4" id="L194" class="line" na* ATN until the bus g+cs freed. 16<5" id="L194" class="line" na*sh.c#L2" na2s="s3/5ef=hase_mismatch1686>d;16mesh_staets="uct e=scsi_cmnd" cl_mis_cmns="sref">scsi_cm_mis_cmns" id=*mesh_state" cla"ss="sref">scsi_cmnd )s reset delay (0=no reset)"1687>d;16mesh_s1688>d;16static voimemesh_statestatic voimescsi_cmnd ef="+code=device" cldevi      void    *u8hosteu8hostdata/a> *mesh_s1689>d;16mesh_s169">d;16u8 etstmesh_state" claKERN>DEBUG="sref">mesh_stKERN>DEBUG" id=cICENSE" class="sref">MODULm>N_ abort(%p)\nquot;Initial ofe=scsi_cmnd" cl"ss="sref">scsi_cmnd )*mesh_s1691>d;16 144mesh_staetmesh_state" class="sref">mesh_stated;16scsi_cmdumplogtmesh_state" class="sref">mesh_state mlass="line" na"ss="sref">scsi_cmnd ef="+code=device" cldevi      void    *scsi_cmi )*mesh_s1693>d;16scsi_cmdumpslogtmesh_state" class="sref">mesh_stated;16mesh_stFAILED/a> *mesh_s1695>d;16d;16href="+code=mesh_st>#de116hre>1696" idmesh_s1697>d;16;
1698" id="L194" class="line" na* Called by the midlayer with the lock held to reset the" c#L2" na2s="s3/5ef=hase_mismatch1699>d;16;
d;17f">d href="drivers/scsi/17f">>170"" id="L194" class="line" na* The midlayer will wait for devi  s to come back, we don't need 1701" id="L194" class="line" na* to do thac ourselves 1702" id="L194" class="line" na*sh.c#L2" na2s="s3/5ef=hase_mismatch17f3>d;17fa href="drivers/scsi/me17fa >1703" id  mesh_staets="uct e=scsi_cmnd" cl_mis_cmns="sref">scsi_cm_mis_cmns" id=*mesh_state" cla"ss="sref">scsi_cmnd )s reset delay (0=no reset)"17f4>d;17fa href="drivers/scsi/me17fa >1704" id=mesh_state" class="sref">mesh_s17f5>d;17fa href="drivers/scsi/me17fa >17f5" id="L132" s="uct e=scsi_cmnd" clmestatic voimemesh_statestatic voimescsi_cmnd ef="+code=device" cldevi      void    *u8hosteu8hostdata/a> *mesh_s17f6>d;17fref="+code=mesh_st>#de117fre>1706" id="L156" volmesh_staemesh_st__iomem" id=*mesh_state" clas/a>        int  m/    offe=scsi_cmnd" clss="sref">mesh_statemesh_stae *mesh_s17f7>d;17f
mesh_stdbdma_regs" id=c=scsi_cmnd" cl__iomem="sref">mesh_st__iomem" id=*mesh_state" class="sref">scsi_cmd offe=scsi_cmnd" clss="sref">mesh_stateu8dma*mesh_s17f8>d;17f
mesh_stflags*mesh_s17f9>d;17f
mesh_s171">d;17u8 etstmesh_state" claKERN>DEBUG="sref">mesh_stKERN>DEBUG" id=cICENSE" class="sref">MODULm>N_ host_reset\nquot;Initial )us reset delay (0=no reset)"1711>d;171712" id="L132" mesh_state" claspin_lock_irqsav     void    *tmesh_state" class="sref">mesh_stateu8hosteu8host_locke mlass="line" naflags="sref">mesh_stflags)us reset delay (0=no reset)"1713>d;17d;171715" id="L132" mesh_state" claout_lescsi_cmd ef="+code=device" clcontrol="sref">scsi_cmnontrole tmesh_state" claRUNs="sref">u8RUNeu8PAUSEemesh_stFLUSHeu8WAKEe1716" id="L156" class="line" naout_8    void    *t>        int  m/    ef="+code=device" claxceptioss="sref">u8axceptiose1717" id="L147" class="line" naout_8    void    *t>        int  m/    ef="+code=device" clarro/a>        int  asro/e1718" id="L118" class="line" naout_8    void    *t>        int  m/    ef="+code=device" clsequen      void    *mesh_stSEQ_RESETMESH)us reset delay (0=no reset)"1719>d;17        int   metmesh_state" clas/a>        int  m/    )us reset delay (0=no reset)"172">d;17        int  udelayt1)us reset delay (0=no reset)"1721>d;17 144t>        int  m/    ef="+code=device" clintr_masks="sref">u8intr_mask/a> o class="line" naINT>ERRORs="sref">u8INT>ERROR" id=| class="line" naINT>EXCEPTIONs="sref">u8INT>EXCEPTIONeCMDDONEs="sref">u8INT>CMDDONEed;17t>        int  m/    ef="+code=device" clsource_is="sref">scsi_cmsource_is/a> o class="line" nass="sref">mesh_stateu8hostescsi_cmthis_ised;17t>        int  m/    ef="+code=device" clsel_timeout="sref">mesh_stsel_timeout/a> o 25);4"  ="L194" class="line" n/* 250ms=*sh.c#L2" na2s="s3/5ef=hase_mismatch1724>d;17t>        int  m/    ef="+code=device" clsync_parass="sref">mesh_stsync_parass/a> o class="line" naASYNC_PARAMS="sref">mesh_stASYNC_PARAMSed;17d;171727" id="L147" class="line" naout_8    void    *t>        int  m/    ef="+code=device" clbus           int  bus    o class="line" naBS1_RST="sref">mesh_stBS1_RSTe1728" id="L118" class="line" name        int   metmesh_state" clas/a>        int  m/    )us reset delay (0=no reset)"1729>d;17        int  udelayt30); ="L125"        156" c"L194" class="line" n/* leave it os for f="+= 25us=*sh.c#L2" na2s="s3/5ef=hase_mismatch173">d;17t>        int  m/    ef="+code=device" clbus           int  bus    o 0); ="L1c"L194" class="line" n/* negate RST=*sh.c#L2" na2s="s3/5ef=hase_mismatch1731>d;171732" id="L132" m"L194" class="line" n/* Compleae=pending noliands=*sh.c#L2" na2s="s3/5ef=hase_mismatch1733>d;17mesh_sthandle_resettmesh_state" class="sref">mesh_stated;17d;17tmesh_state" class="sref">mesh_stateu8hosteu8host_locke mlass="line" naflags="sref">mesh_stflags)us reset delay (0=no reset)"1736>d;17mesh_stSUCCESS*mesh_s1737>d;17d;17d;17        int  set_sets="uct e=scsi_cmnd" clmestatic voimemesh_statestatic voi"tfa8" id)s reset delay (0=no reset)"174">d;17mesh_s1741>d;17mesh_staachver_istmesh_state" clapowe/aacs="sref">u8 owe/aac" id))s reset delay (0=no reset)"1742>d;17d;17static voi"tfa8" id)e=mesh_state" class="sref">mesh_s17<4>d;17tmesh_state" claPMAC_FTR_MESH_ENABLEs="sref">u8PMAC_FTR_MESH_ENABLE/a> o class="line" nasacio_get_of_n" n="sref">mesh_staacio_get_of_n" ntmesh_state" class="sref">mesh_statescsi_cmd 1)us reset delay (0=no reset)"1745>d;17static voissleept200*as reset delay (0=no reset)"1746>d;17mesh_s17<7>d;17tmesh_state" claPMAC_FTR_MESH_ENABLEs="sref">u8PMAC_FTR_MESH_ENABLE/a> o class="line" nasacio_get_of_n" n="sref">mesh_staacio_get_of_n" ntmesh_state" class="sref">mesh_statescsi_cmd 0*as reset delay (0=no reset)"1748>d;17 144static voissleept10*as reset delay (0=no reset)"1749>d;17d;17d;171752" ids reset delay (0=no reset)"1753>d;17 144static voiCONFIG_PM" ids reset delay (0=no reset)"1754>d;17static voimets="uct e=scsi_cmnd" clmacio_dev="sref">scsi_cmdacio_dev" id=*mesh_state" clasdev="sref">scsi_cmdu8pm_sescsi_cmsed;17mesh_s1756>d;17static voimemesh_statestatic voimeu8sacio_get_drvdatatmesh_state" clasdev="sref">scsi_cmdd;17mesh_stflags*mesh_s1758>d;17d;17scsi_cmse        int  avne"" id)e=mesh_state" class="sref">mesh_s176">d;17mesh_stPM_EVENT_SUSPEND" id:mesh_state" class="sref">mesh_s1761>d;17u8PM_EVENT_HIBERNATE" id:mesh_state" class="sref">mesh_s1762>d;17u8PM_EVENT_FREEZE" id:mesh_state" class="sref">mesh_s1763>d;17mesh_s1764>d;17mesh_s1765>d;17d;17d;17mesh_stateu8      mesh_st leepsre" id)s reset delay (0=no reset)"1768>d;17d;17mesh_s177">d;17mesh_stsmis_block_requeltstmesh_state" class="sref">mesh_stateu8hosted;17 144tmesh_state" class="sref">mesh_stateu8hosteu8host_locke mlass="line" naflags="sref">mesh_stflags)us reset delay (0=no reset)"1772>d;17mesh_stateu8      u8idls mesh_s1773>d;17tmesh_state" class="sref">mesh_stateu8hosteu8host_locke mlass="line" naflags="sref">mesh_stflags)us reset delay (0=no reset)"1774>d;17 144static voissleept10*as reset delay (0=no reset)"17<5>d;17 144tmesh_state" class="sref">mesh_stateu8hosteu8host_locke mlass="line" naflags="sref">mesh_stflags)as reset delay (0=no reset)"17<6>d;17d;17mesh_stateu8      mesh_st leepsre" idas reset delay (0=no reset)"17<8>d;17tmesh_state" class="sref">mesh_stateu8hosteu8host_locke mlass="line" naflags="sref">mesh_stflags)us reset delay (0=no reset)"17<9>d;17mesh_stdisable_irqtmesh_state" class="sref">mesh_state        int  mt)&int/)us reset delay (0=no reset)"178">d;17        int  set_setmesh_state" class="sref">mesh_stated;171782" id="L132" return 0as reset delay (0=no reset)"1783>d;17d;17mesh_s1785>d;17static voimets="uct e=scsi_cmnd" clmacio_dev="sref">scsi_cmdacio_dev" id=*mesh_state" clasdev="sref">scsi_cmdd;17mesh_s1787>d;17static voimemesh_statestatic voimeu8sacio_get_drvdatatmesh_state" clasdev="sref">scsi_cmdd;17mesh_stflags*mesh_s1789>d;17mesh_s179">d;17mesh_stateu8      mesh_st leepsre" id)s reset delay (0=no reset)"1791>d;17d;17d;17        int  set_setmesh_state" class="sref">mesh_stated;17tmesh_state" class="sref">mesh_stated;17tmesh_state" class="sref">mesh_stateu8hosteu8host_locke mlass="line" naflags="sref">mesh_stflags)as reset delay (0=no reset)"1796>d;17href="+code=mesh_st>#de117hre>1796" id="L156" class="line" nameu8metmesh_state" class="sref">mesh_stated;17;
tmesh_state" class="sref">mesh_stateu8hosteu8host_locke mlass="line" naflags="sref">mesh_stflags)us reset delay (0=no reset)"1798>d;17;
mesh_stenable_irqtmesh_state" class="sref">mesh_state        int  mt)&int/)us reset delay (0=no reset)"1799>d;17;
mesh_stsmis_unblock_requeltstmesh_state" class="sref">mesh_stateu8hosted;18f">d href="drivers/scsi/18f">>180"" idmesh_s18f1>d;18fa href="drivers/scsi/me18fa >1801" id="L151" return 0as reset delay (0=no reset)"18f2>d;18fa href="drivers/scsi/me18fa >1802" id}s reset delay (0=no reset)"18f3>d;18fa href="drivers/scsi/me18fa >1803" ids reset delay (0=no reset)"18f4>d;18fa href="drivers/scsi/me18fa >1804" id#endif m"L194" class="line" n/* CONFIG_PM=*sh.c#L2" na2s="s3/5ef=hase_mismatch18f5>d;18fa href="drivers/scsi/me18fa >1805" ids reset delay (0=no reset)"18f6>d;18fref="+code=mesh_st>#de118fre>1806" id="L194" class="line" namh.c#L2" na2s="s3/5ef=hase_mismatch18f7>d;18f
1808" id="L194" class="line" na* CDROMs),=and reboot to MacOS, it g+cs confused, poor t&ing. 1809" id="L194" class="line" na* So, os reboot we reset the SCSI bus. d;181811" id  u8sets="uct e=scsi_cmnd" clmacio_dev="sref">scsi_cmdacio_dev" id=*mesh_state" clasdev="sref">scsi_cmdd;18mesh_s1813>d;18static voimemesh_statestatic voimeu8sacio_get_drvdatatmesh_state" clasdev="sref">scsi_cmdd;18mesh_staemesh_st__iomem" id=*mesh_state" clas/a>        int  m/    as reset delay (0=no reset)"1815>d;18mesh_stflags*mesh_s1816>d;18mesh_s1817>d;18u8 etstmesh_state" claKERN>INFOs="sref">u8KERN>INFO" id=cICENSE" class="sref">MODULresetting MESH "sre bus(es)\nquot;Initial )as reset delay (0=no reset)"1818>d;18tmesh_state" class="sref">mesh_stateu8hosteu8host_locke mlass="line" naflags="sref">mesh_stflags)as reset delay (0=no reset)"1819>d;18        int  m/    offe=scsi_cmnd" clss="sref">mesh_statemesh_stae *mesh_s182">d;18t>        int  m/    ef="+code=device" clintr_masks="sref">u8intr_mask/a> o 0*as reset delay (0=no reset)"1821>d;18 144t>        int  m/    ef="+code=device" clintasrupt    void    * o class="line" naINT>ERRORs="sref">u8INT>ERROR" id=| class="line" naINT>EXCEPTIONs="sref">u8INT>EXCEPTIONeCMDDONEs="sref">u8INT>CMDDONEed;18t>        int  m/    ef="+code=device" clbus           int  bus    o class="line" naBS1_RST="sref">mesh_stBS1_RSTed;18        int   metmesh_state" clas/a>        int  m/    )us reset delay (0=no reset)"1824>d;18        int  udelayt30);s reset delay (0=no reset)"1825>d;18t>        int  m/    ef="+code=device" clbus           int  bus    o 0);s reset delay (0=no reset)"1826>d;18tmesh_state" class="sref">mesh_stateu8hosteu8host_locke mlass="line" naflags="sref">mesh_stflags)us reset delay (0=no reset)"1827>d;18d;18d;18d;18mesh_s1831>d;18static voi"mis_host_templfa8" id=c=scsi_cmnd" clmestatic voimemesh_s1832>d;18u8 eoc_scsi" id="L151" ="L125"       ==cICENSE" class="sref">MODULm>N_quot;Initial omesh_state" class="sref">mesh_s1833>d;18u8scsi" id="L151" ="L125"            ==cICENSE" class="sref">MODULMESHquot;Initial omesh_state" class="sref">mesh_s1834>d;18u8queuenoliand" id="L151" ="L125"    ffe=scsi_cmnd" clsestatic voimemesh_state" class="sref">mesh_s1835>d;18        int  a_ abort_handle/" id="L151" ="L125"ffe=scsi_cmnd" clsemesh_stae>mesh_state" class="sref">mesh_s1836>d;18        int  a_ host_reset_handle/" id="L151" ="ffe=scsi_cmnd" clsemesh_stae>mesh_state" class="sref">mesh_s1837>d;18static voican queue" id="L151" ="L125"       ==20>mesh_state" class="sref">mesh_s1838>d;18scsi_cmthis_isemesh_state" class="sref">mesh_s1839>d;18static voi"g_tablesiz8" id="L151" ="L125"    ffe=scsi_cmnd" clSG_ALL5static voiSG_ALL>mesh_state" class="sref">mesh_s184">d;18u8cmd_per_lusemesh_state" class="sref">mesh_s1841>d;18mesh_stuse_cluNtassreemesh_stDISABLE_CLUSTERING>mesh_state" class="sref">mesh_s1842>d;18d;18d;18static voimets="uct e=scsi_cmnd" clmacio_dev="sref">scsi_cmdacio_dev" id=*mesh_state" clasdev="sref">scsi_cmdscsi_cmof_devi  _is" id=*mesh_state" clasatca="sref">mesh_staatca" id)s reset delay (0=no reset)"1845>d;18mesh_s1846>d;18mesh_stdevi  _n" n" id=*mesh_state" clasemesh_stae "ffe=scsi_cmnd" clsacio_get_of_n" n="sref">mesh_staacio_get_of_n" ntmesh_state" clasdev="sref">scsi_cmdd;18scsi_cmpci_dev" id* e=scsi_cmnd" clpdev="sref">scsi_cmpdev" id=ffe=scsi_cmnd" clsacio_get_pci_dev="sref">scsi_cmsacio_get_pci_devtmesh_state" clasdev="sref">scsi_cmdd;18mesh_sttgte mlass="line" naminpe/a>        int  minpe//a> *mesh_s1849>d;18static voicfp/a> *mesh_s185">d;18static voimemesh_statemesh_s1851>d;18u8Smis_Host" id=*mesh_state" claseu8semesh_s1852>d;18mesh_s1853>d;18u8dma_addr_t" id=c=scsi_cmnd" cldma_cmd_bus="sref">mesh_stdma_cmd_busemesh_s1854>d;18mesh_s1855>d;18scsi_cmd        int  bus" idef="+code=device" clchip5static voichip" idef="+code=device" cltyp     void    *mesh_s1856>d;18scsi_cmsacio_heathrow" id:mesh_state" class="sref">mesh_s1857>d;18u8sacio_gatwick" id:mesh_state" class="sref">mesh_s1858>d;18u8sacio_paddsretos" id:mesh_state" class="sref">mesh_s1859>d;18mesh_stuse_actcla_nee" id=ff0as reset delay (0=no reset)"186">d;18mesh_s1861>d;18mesh_s1862>d;18mesh_stuse_actcla_nee" id=ffe=scsi_cmnd" clSEQ_ACTIVE_NEG="sref">mesh_stSEQ_ACTIVE_NEGemesh_s1863>d;18d;18mesh_s1865>d;18        int  sacio_resource_coue"tmesh_state" clasdev="sref">scsi_cmd        int  sacio_irq_coue"tmesh_state" clasdev="sref">scsi_cmdmesh_s1866>d;18u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=cICENSE" class="sref">MODULm>N_: expectedf2 addrs=and 2 intrsquot;Initial mesh_state" class="sref">mesh_s1867>d;18MODUL (got %d,%d)\nquot;Initial o class="line" nasacio_resource_coue" >        int  sacio_resource_coue"tmesh_state" clasdev="sref">scsi_cmdmesh_state" class="sref">mesh_s1868>d;18        int  sacio_irq_coue"tmesh_state" clasdev="sref">scsi_cmdd;18scsi_cmENODEVemesh_s187">d;18d;181872" id="L132" if (class="line" nasacio_requelt_resources="sref">mesh_staacio_requelt_resourcestmesh_state" clasdev="sref">scsi_cmdMODULm>N_quot;Initial )o!ff0)f=mesh_state" class="sref">mesh_s1873>d;18u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=cICENSE" class="sref">MODULm>N_: unable to requelt memory resourcesquot;Initial )as reset delay (0=no reset)"1874>d;18scsi_cmEBUSYemesh_s1875>d;18d;18u8seu8smis_host_alloct>static voimestatic voimed;18u8sestatic voiNULL" id)f=mesh_state" class="sref">mesh_s18<8>d;18 144u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=cICENSE" class="sref">MODULm>N_: couldn't regiNtas hostquot;Initial )as reset delay (0=no reset)"1879>d;18u8out_relelasemesh_s188">d;18d;18d;181883" id#if !mesh_state" cladefvers="sref">scsi_cmdefverstmesh_state" claMODULEs="sref">u8MODULE" id)s reset delay (0=no reset)"1884>d;18u8sote_smis_hosttmesh_state" clasemesh_stae o class="line" naseu8sed;18d;18mesh_s1887>d;18u8seu8b    u8macio_resource_"tf=ttmesh_state" clasdev="sref">scsi_cmdd;18u8semesh_stirqoffe=scsi_cmnd" clsacio_irq="sref">mesh_stsacio_irqtmesh_state" clasdev="sref">scsi_cmdd;18mesh_statestatic voimeu8seu8hostdataemesh_s189">d;18u8sacio_set_drvdatatmesh_state" clasdev="sref">scsi_cmdmesh_stated;18 144mesh_stateu8hosteu8semesh_s1892>d;18mesh_statescsi_cmdscsi_cmdmesh_s1893>d;18mesh_statescsi_cmpdev" id=ffe=scsi_cmnd" cl dev="sref">scsi_cmpdev" id*mesh_s1894>d;18mesh_s1895>d;18mesh_statemesh_stae =ffe=scsi_cmnd" clioremap5static voiioremaptmesh_state" clasacio_resource_"tf=ts="sref">u8macio_resource_"tf=ttmesh_state" clasdev="sref">scsi_cmdd;18href="+code=mesh_st>#de118hre>1896" id="L156" if (class="line" nass="sref">mesh_statemesh_stae =fffe=scsi_cmnd" clNULL5static voiNULL" id)f=mesh_state" class="sref">mesh_s1897>d;18;
u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=cICENSE" class="sref">MODULm>N_: can't map regiNtass\nquot;Initial )as reset delay (0=no reset)"1898>d;18;
u8out_fres" id*mesh_s1899>d;18;
mesh_s19f">d;19f">d href="drivers/scsi/19f">>190"" id="L159" code=device" clss="sref">mesh_stateu8dma/a> =ffe=scsi_cmnd" clioremap5static voiioremaptmesh_state" clasacio_resource_"tf=ts="sref">u8macio_resource_"tf=ttmesh_state" clasdev="sref">scsi_cmdd;19fa href="drivers/scsi/me19fa >1901" id="L151" if (code=device" clss="sref">mesh_stateu8dma/a> =fffe=scsi_cmnd" clNULL5static voiNULL" id)f=mesh_state" class="sref">mesh_s19f2>d;19fa href="drivers/scsi/me19fa >1902" id="L132" ="L125" mesh_state" claprtsu8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=cICENSE" class="sref">MODULm>N_: can't map regiNtass\nquot;Initial )as reset delay (0=no reset)"19f3>d;19fa href="drivers/scsi/me19fa >1903" id="L132" ="L125" mesh_state" claiounmap5static voiiounmaptmesh_state" class="sref">mesh_statemesh_stae )as reset delay (0=no reset)"19f4>d;19fa href="drivers/scsi/me19fa >1904" id="L134" ="L125" goto mesh_state" claout_fress="sref">u8out_fres" id*mesh_s19f5>d;19fa href="drivers/scsi/me19fa >1905" id="L132" }s reset delay (0=no reset)"19f6>d;19fref="+code=mesh_st>#de119fre>1906" idmesh_s19f7>d;19f
mesh_statemeint/a>        int  mt)&int/offe=scsi_cmnd" clsacio_irq="sref">mesh_stsacio_irqtmesh_state" clasdev="sref">scsi_cmdd;19f
mesh_state        int  dmaint/offe=scsi_cmnd" clsacio_irq="sref">mesh_stsacio_irqtmesh_state" clasdev="sref">scsi_cmdd;19f
mesh_s191">d;191911" id="L194" class="line" naaaaaaaaa* +1 to allow for aligning. 1912" id="L194" class="line" naaaaaaaaa*sh.c#L2" na2s="s3/5ef=hase_mismatch1913>d;19mesh_statestatic voidma_cmd_tiz8eu8sestatic voi"g_tablesiz8" id=+f2)f* siz8ofts="uct e=scsi_cmnd" cldbdma_cmd5static voidbdma_cmd/a> )as reset delay (0=no reset)"1914>d;19mesh_s1915>d;191916" id="L194" class="line" naaaaaaaaa* enough or until we g+c some sacio-specific =hasions1917" id="L194" class="line" n aaaaaaaa*sh.c#L2" na2s="s3/5ef=hase_mismatch1918>d;19        int   ci_alloc_consiNtae"tmesh_state" clasacio_get_pci_dev="sref">scsi_cmsacio_get_pci_devtmesh_state" clasdev="sref">scsi_cmdmesh_state" class="sref">mesh_s1919>d;19mesh_statestatic voidma_cmd_tiz8emesh_state" class="sref">mesh_s192">d;19mesh_stdma_cmd_bused;19static voiNULL" id)f=mesh_state" class="sref">mesh_s1922>d;19u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=cICENSE" class="sref">MODULm>N_: can't allocate DMA table\nquot;Initial )as reset delay (0=no reset)"1923>d;19static voiout_unmap" id*mesh_s1924>d;19d;19mesh_staemset(code=device" cldma_cmd_tia      void    *mesh_statestatic voidma_cmd_tiz8ed;19mesh_s1927>d;19mesh_statemesh_stdma_cmdtestatic voidbdma_cmd/a> =*) class="line" naDBDMA_ALIGNs="sref">u8DBDMA_ALIGN(code=device" cldma_cmd_tia      void    *d;19mesh_statemesh_s1929>d;19mesh_statemesh_stdma_cmd_busemesh_stdma_cmd_busemesh_statemesh_stdma_cmdted;19mesh_s1931>d;19 144mesh_statemesh_stcurrae"_reqestatic voiNULL" id*mesh_s1932>d;19mesh_sttgtemesh_sttgtemesh_sttgtemesh_s1933>d;19mesh_statemesh_sttgtsemesh_sttgtestatic voisdtr "tfa8emesh_s1934>d;19mesh_statemesh_sttgtsemesh_sttgtemesh_stsync_parassemesh_stASYNC_PARAMS" id*mesh_s1935>d;19mesh_statemesh_sttgtsemesh_sttgtemesh_stcurrae"_reqestatic voiNULL" id*mesh_s1936>d;19d;19d;19static voicfp/a> =ffe=scsi_cmnd" clof_get_propertya>        int  of_get_propertytmesh_state" clasemesh_stae o cICENSE" class="sref">MODULclock-frequencyquot;Initial o class="line" naNULL5static voiNULL" id)))s reset delay (0=no reset)"1939>d;19mesh_statemesh_stclk_freq/a> =ff*mesh_state" clacfp5static voicfp/a> *mesh_s194">d;19mesh_s1941>d;19u8 etstmesh_state" claKERN>INFOs="sref">u8KERN>INFO" id=cICENSE" class="sref">MODULm>N_:  cluming 50MHz clock frequency\nquot;Initial )as reset delay (0=no reset)"1942>d;19mesh_statemesh_stclk_freq/a> =ff50000000as reset delay (0=no reset)"1943>d;19d;19mesh_s1945>d;191946" id="L194" class="line" naaaaaaaaa* me1947" id="L194" class="line" n aaaaaaaa*sh.c#L2" na2s="s3/5ef=hase_mismatch19<8>d;19        int  minpe//a> =ff1000000000 / tmesh_state" class="sref">mesh_statemesh_stclk_freq/a> =/ 5); c"L194" class="line" n/* nsa*sh.c#L2" na2s="s3/5ef=hase_mismatch19<9>d;19u8se        int  minpe//a> )s reset delay (0=no reset)"195">d;19u8se        int  minpe//a> *mesh_s1951>d;191952" id="L132" m"L194" class="line" n/* Powe/ up the chipa*sh.c#L2" na2s="s3/5ef=hase_mismatch1953>d;19        int  set_setmesh_state" class="sref">mesh_stated;19mesh_s1955>d;191956" id="L156" class="line" nametmesh_state" class="sref">mesh_stated;19d;191959" id="L159" if (class="line" narequelt_irq="sref">mesh_strequelt_irqtmesh_state" class="sref">mesh_statemeint/a>        int  mt)&int/o class="line" nado_seMODULMESHquot;Initial o class="line" nass="sref">mesh_statemesh_s196">d;19u8 etstmesh_state" claKERN>ERRs="sref">u8KERN>ERR" id=cICENSE" class="sref">MODULMESH: can't g+c irq %d\nquot;Initial o class="line" nass="sref">mesh_state        int  mt)&int/)us reset delay (0=no reset)"1961>d;19u8out_shutdows/a> *mesh_s1962>d;19d;19d;191965" id="L132" if (class="line" nasmis_add hosts="sref">u8smis_add hosttmesh_state" claseu8sescsi_cmdscsi_cmofdev" id.code=device" cldev="sref">scsi_cm1966" id="L156" ="L125" goto mesh_state" claout_relelas_irq="sref">mesh_stout_relelas_irq/a> *mesh_s1967>d;19u8smis_"s19 hosttmesh_state" claseu8sed;19d;19d;19mesh_s1971>d;19mesh_stout_relelas_irq/a> :mesh_state" class="sref">mesh_s1972>d;19mesh_stfres_irqtmesh_state" class="sref">mesh_statemeint/a>        int  mt)&int/o class="line" nass="sref">mesh_stated;19u8out_shutdows/a> :mesh_state" class="sref">mesh_s1974>d;191975" id="L194" class="line" naaaaaaaaa* at reboot if the bus was set to "ynchronous m cl already1976" id="L194" class="line" naaaaaaaaa*sh.c#L2" na2s="s3/5ef=hase_mismatch1977>d;19u8setmesh_state" clasdev="sref">scsi_cmdd;19        int  set_setmesh_state" class="sref">mesh_stated;19        int   ci_fres_consiNtae"tmesh_state" clasacio_get_pci_dev="sref">scsi_cmsacio_get_pci_devtmesh_state" clasdev="sref">scsi_cmd mesh_state" class="sref">mesh_statestatic voidma_cmd_tiz8emesh_state" class="sref">mesh_s198">d;19mesh_statemesh_statemesh_stdma_cmd_bused;19static voiout_unmap" id:mesh_state" class="sref">mesh_s1982>d;19static voiiounmaptmesh_state" class="sref">mesh_stateu8dma/a> )as reset delay (0=no reset)"1983>d;19static voiiounmaptmesh_state" class="sref">mesh_statemesh_stae )as reset delay (0=no reset)"1984>d;19u8out_fres" id:mesh_state" class="sref">mesh_s1985>d;19u8smis_host_puttmesh_state" claseu8sed;19u8out_relelasemesh_s1987>d;19mesh_staacio_relelas_resourcestmesh_state" clasdev="sref">scsi_cmdd;19d;19scsi_cmENODEVemesh_s199">d;19d;191992" id  u8sets="uct e=scsi_cmnd" clmacio_dev="sref">scsi_cmdacio_dev" id=*mesh_state" clasdev="sref">scsi_cmd1993" id=mesh_state" class="sref">mesh_s1994>d;19static voimemesh_statestatic voimeu8sacio_get_drvdatatmesh_state" clasdev="sref">scsi_cmdd;19u8Smis_Host" id=*mesh_state" claseu8semesh_stateu8hosted;19href="+code=mesh_st>#de119hre>1996" idmesh_s1997>d;19;
u8smis_removs hosttmesh_state" claseu8sed;19;
d;19;
mesh_stfres_irqtmesh_state" class="sref">mesh_statemeint/a>        int  mt)&int/o class="line" nass="sref">mesh_stated;20f">d href="drivers/scsi/20f">>20f"" ids /pre>> reset delay (0=no reset)"20f1>d;20fa href="drivers/scsi/me20fa >20f1" id="L151" e"L194" class="line" n/* Reset "sre bus *sh.c#L2" na2s="s3/5ef=hase_mismatch20f2>d;20fa href="drivers/scsi/me20fa >20f2" id="L132" mesh_state" claseu8setmesh_state" clasdev="sref">scsi_cmdd;20fa href="drivers/scsi/me20fa >20f3" ids reset delay (0=no reset)"20f4>d;20fa href="drivers/scsi/me20fa >20f4" id="L147" c"L194" class="line" n/* Shut dows chipa>20f5" id="L132" mesh_state" claset_se        int  set_setmesh_state" class="sref">mesh_stated;20fref="+code=mesh_st>#de120fre>20f6" idmesh_s20f7>d;20f
20f8" id="L118" class="line" naiounmap5static voiiounmaptmesh_state" class="sref">mesh_statemesh_stae )as reset delay (0=no reset)"20f9>d;20f
static voiiounmaptmesh_state" class="sref">mesh_stateu8dma/a> )as reset delay (0=no reset)"201">d;20mesh_s2011>d;2020<2" id="L132" mesh_state" clapci_fres_consiNtae" >        int   ci_fres_consiNtae"tmesh_state" clasacio_get_pci_dev="sref">scsi_cmsacio_get_pci_devtmesh_state" clasdev="sref">scsi_cmd mesh_state" class="sref">mesh_statestatic voidma_cmd_tiz8emesh_state" class="sref">mesh_s20<3>d;20mesh_statemesh_statemesh_stdma_cmd_bused;20mesh_s20<5>d;2020<6" id="L156" class="line" namacio_relelas_resources="sref">mesh_staacio_relelas_resourcestmesh_state" clasdev="sref">scsi_cmdd;20d;20u8smis_host_puttmesh_state" claseu8sed;20mesh_s202">d;20d;20d;20mesh_s2023>d;20d;20u8of_devics_id" id mesh_state" clasemesh_staemesh_s20<5>d;20mesh_s20<6>d;20mesh_s20<7>d;20mesh_stscsi" id="L132" ="L==cICENSE" class="sref">MODULm>N_quot;Initial >mesh_state" class="sref">mesh_s2028>d;20mesh_state" class="sref">mesh_s2029>d;20mesh_s203">d;20MODUL"srequot;Initial >mesh_state" class="sref">mesh_s2031>d;20MODULchrp,">me0quot;Initial mesh_state" class="sref">mesh_s20<2>d;20mesh_state" class="sref">mesh_s2033>d;20mesh_state" class="sref">mesh_s2034>d;20d;20u8MODULE_DEVICE_TABLE" id=tmesh_state" claofs="sref">u8ofemesh_staed;20mesh_s2037>d;20scsi_cmdacio_doclas" id mesh_state" clasescsi_cmdemesh_s2038>d;20mesh_s2039>d;20scsi_cmdoclasemesh_s204">d;20mesh_stscsi" id="L132" ="L==cICENSE" class="sref">MODULm>N_quot;Initial >mesh_state" class="sref">mesh_s2041>d;20scsi_cmownas" id="L151" ="ffe=scsi_cmnd" clTHIS_MODULEs="sref">u8THIS_MODULEemesh_state" class="sref">mesh_s2042>d;20u8of_matca_tableemesh_staemesh_state" class="sref">mesh_s2043>d;20mesh_state" class="sref">mesh_s2044>d;20u8probe" id="L151" ="ffe=scsi_cmnd" clseu8semesh_state" class="sref">mesh_s2045>d;20u8removs"L151" ="ffe=scsi_cmnd" clseu8se>mesh_state" class="sref">mesh_s2046>d;20u8shutdows151" ="ffe=scsi_cmnd" clseu8se>mesh_state" class="sref">mesh_s2047>d;20u8CONFIG_PM" idmesh_s2048>d;20u8suspend" id="L147" ffe=scsi_cmnd" clseu8se>mesh_state" class="sref">mesh_s2049>d;20mesh_stresusi"L151" ="ffe=scsi_cmnd" clsemesh_stse>mesh_state" class="sref">mesh_s205">d;20d;20d;20mesh_s2053>d;20d;20 e=scsi_cmnd" clinit_aemesh_stinit_aetvoid) na2s="s3/5ef=hase_mismatch20<5>d;20mesh_s2056>d;20mesh_s2057>d;2020<8" id="L156" if (code=device" clsync_rfa85static voisync_rfa8" id=f="+ 10) na2s="s3/5ef=hase_mismatch20<9>d;20static voisync_rfa8" id=ff10as reset delay (0=no reset)"206">d;20static voisync_rfa8" id=f="+ 0)f=mesh_state" class="sref">mesh_s20<1>d;20u8 etstmesh_state" claKERN>INFOs="sref">u8KERN>INFO" id=cICENSE" class="sref">MODULm>N_: configured for synchronous %d MB/s\nquot;Initial ,=mesh_state" clasync_rfa85static voisync_rfa8" id)us reset delay (0=no reset)"2062>d;20u8sestatic voisync_rfa8" id;47" c"L194" class="line" n/* nsa*sh.c#L2" na2s="s3/5ef=hase_mismatch20<3>d;20mesh_staed;20d;20u8 etstmesh_state" claKERN>INFOs="sref">u8KERN>INFO" id=cICENSE" class="sref">MODULm>N_: configured for asynchronous\nquot;Initial )as reset delay (0=no reset)"20<6>d;20mesh_s2067>d;20scsi_cmdacio_regiNtas_doclast>scsi_cmded;20d;20mesh_s207">d;20 e=scsi_cmnd" clexit_aemesh_stexit_aetvoid) na2s="s3/5ef=hase_mismatch2071>d;20mesh_s2072>d;20scsi_cmdacio_unregiNtas_doclast>scsi_cmded;20d;20mesh_s2075>d;20tmesh_state" clainit_aemesh_stinit_ae)as reset delay (0=no reset)"2076>d;20tmesh_state" claexit_aemesh_stexit_ae)as reset delay (0=no reset)"2077>d;20
The original LXR software by the reset dehttp://sourceforge.net/projects/lxs">LXR ="liunityelxs@iveux.noe lxs.iveux.no kindly hosted by reset dehttp://www.redpill-ivepro.no">Redpill Lvepro ASe