linux/drivers/rtc/rtc-cmos.c
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   1/*
   2 * RTC class driver for "CMOS RTC":  PCs, ACPI, etc
   3 *
   4 * Copyright (C) 1996 Paul Gortmaker (drivers/char/rtc.c)
   5 * Copyright (C) 2006 David Brownell (convert to new framework)
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License
   9 * as published by the Free Software Foundation; either version
  10 * 2 of the License, or (at your option) any later version.
  11 */
  12
  13/*
  14 * The original "cmos clock" chip was an MC146818 chip, now obsolete.
  15 * That defined the register interface now provided by all PCs, some
  16 * non-PC systems, and incorporated into ACPI.  Modern PC chipsets
  17 * integrate an MC146818 clone in their southbridge, and boards use
  18 * that instead of discrete clones like the DS12887 or M48T86.  There
  19 * are also clones that connect using the LPC bus.
  20 *
  21 * That register API is also used directly by various other drivers
  22 * (notably for integrated NVRAM), infrastructure (x86 has code to
  23 * bypass the RTC framework, directly reading the RTC during boot
  24 * and updating minutes/seconds for systems using NTP synch) and
  25 * utilities (like userspace 'hwclock', if no /dev node exists).
  26 *
  27 * So **ALL** calls to CMOS_READ and CMOS_WRITE must be done with
  28 * interrupts disabled, holding the global rtc_lock, to exclude those
  29 * other drivers and utilities on correctly configured systems.
  30 */
  31#include <linux/kernel.h>
  32#include <linux/module.h>
  33#include <linux/init.h>
  34#include <linux/interrupt.h>
  35#include <linux/spinlock.h>
  36#include <linux/platform_device.h>
  37#include <linux/mod_devicetable.h>
  38#include <linux/log2.h>
  39#include <linux/pm.h>
  40#include <linux/of.h>
  41#include <linux/of_platform.h>
  42
  43/* this is for "generic access to PC-style RTC" using CMOS_READ/CMOS_WRITE */
  44#include <asm-generic/rtc.h>
  45
  46struct cmos_rtc {
  47        struct rtc_device       *rtc;
  48        struct device           *dev;
  49        int                     irq;
  50        struct resource         *iomem;
  51
  52        void                    (*wake_on)(struct device *);
  53        void                    (*wake_off)(struct device *);
  54
  55        u8                      enabled_wake;
  56        u8                      suspend_ctrl;
  57
  58        /* newer hardware extends the original register set */
  59        u8                      day_alrm;
  60        u8                      mon_alrm;
  61        u8                      century;
  62};
  63
  64/* both platform and pnp busses use negative numbers for invalid irqs */
  65#define is_valid_irq(n)         ((n) > 0)
  66
  67static const char driver_name[] = "rtc_cmos";
  68
  69/* The RTC_INTR register may have e.g. RTC_PF set even if RTC_PIE is clear;
  70 * always mask it against the irq enable bits in RTC_CONTROL.  Bit values
  71 * are the same: PF==PIE, AF=AIE, UF=UIE; so RTC_IRQMASK works with both.
  72 */
  73#define RTC_IRQMASK     (RTC_PF | RTC_AF | RTC_UF)
  74
  75static inline int is_intr(u8 rtc_intr)
  76{
  77        if (!(rtc_intr & RTC_IRQF))
  78                return 0;
  79        return rtc_intr & RTC_IRQMASK;
  80}
  81
  82/*----------------------------------------------------------------*/
  83
  84/* Much modern x86 hardware has HPETs (10+ MHz timers) which, because
  85 * many BIOS programmers don't set up "sane mode" IRQ routing, are mostly
  86 * used in a broken "legacy replacement" mode.  The breakage includes
  87 * HPET #1 hijacking the IRQ for this RTC, and being unavailable for
  88 * other (better) use.
  89 *
  90 * When that broken mode is in use, platform glue provides a partial
  91 * emulation of hardware RTC IRQ facilities using HPET #1.  We don't
  92 * want to use HPET for anything except those IRQs though...
  93 */
  94#ifdef CONFIG_HPET_EMULATE_RTC
  95#include <asm/hpet.h>
  96#else
  97
  98static inline int is_hpet_enabled(void)
  99{
 100        return 0;
 101}
 102
 103static inline int hpet_mask_rtc_irq_bit(unsigned long mask)
 104{
 105        return 0;
 106}
 107
 108static inline int hpet_set_rtc_irq_bit(unsigned long mask)
 109{
 110        return 0;
 111}
 112
 113static inline int
 114hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
 115{
 116        return 0;
 117}
 118
 119static inline int hpet_set_periodic_freq(unsigned long freq)
 120{
 121        return 0;
 122}
 123
 124static inline int hpet_rtc_dropped_irq(void)
 125{
 126        return 0;
 127}
 128
 129static inline int hpet_rtc_timer_init(void)
 130{
 131        return 0;
 132}
 133
 134extern irq_handler_t hpet_rtc_interrupt;
 135
 136static inline int hpet_register_irq_handler(irq_handler_t handler)
 137{
 138        return 0;
 139}
 140
 141static inline int hpet_unregister_irq_handler(irq_handler_t handler)
 142{
 143        return 0;
 144}
 145
 146#endif
 147
 148/*----------------------------------------------------------------*/
 149
 150#ifdef RTC_PORT
 151
 152/* Most newer x86 systems have two register banks, the first used
 153 * for RTC and NVRAM and the second only for NVRAM.  Caller must
 154 * own rtc_lock ... and we won't worry about access during NMI.
 155 */
 156#define can_bank2       true
 157
 158static inline unsigned char cmos_read_bank2(unsigned char addr)
 159{
 160        outb(addr, RTC_PORT(2));
 161        return inb(RTC_PORT(3));
 162}
 163
 164static inline void cmos_write_bank2(unsigned char val, unsigned char addr)
 165{
 166        outb(addr, RTC_PORT(2));
 167        outb(val, RTC_PORT(3));
 168}
 169
 170#else
 171
 172#define can_bank2       false
 173
 174static inline unsigned char cmos_read_bank2(unsigned char addr)
 175{
 176        return 0;
 177}
 178
 179static inline void cmos_write_bank2(unsigned char val, unsigned char addr)
 180{
 181}
 182
 183#endif
 184
 185/*----------------------------------------------------------------*/
 186
 187static int cmos_read_time(struct device *dev, struct rtc_time *t)
 188{
 189        /* REVISIT:  if the clock has a "century" register, use
 190         * that instead of the heuristic in get_rtc_time().
 191         * That'll make Y3K compatility (year > 2070) easy!
 192         */
 193        get_rtc_time(t);
 194        return 0;
 195}
 196
 197static int cmos_set_time(struct device *dev, struct rtc_time *t)
 198{
 199        /* REVISIT:  set the "century" register if available
 200         *
 201         * NOTE: this ignores the issue whereby updating the seconds
 202         * takes effect exactly 500ms after we write the register.
 203         * (Also queueing and other delays before we get this far.)
 204         */
 205        return set_rtc_time(t);
 206}
 207
 208static int cmos_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 209{
 210        struct cmos_rtc *cmos = dev_get_drvdata(dev);
 211        unsigned char   rtc_control;
 212
 213        if (!is_valid_irq(cmos->irq))
 214                return -EIO;
 215
 216        /* Basic alarms only support hour, minute, and seconds fields.
 217         * Some also support day and month, for alarms up to a year in
 218         * the future.
 219         */
 220        t->time.tm_mday = -1;
 221        t->time.tm_mon = -1;
 222
 223        spin_lock_irq(&rtc_lock);
 224        t->time.tm_sec = CMOS_READ(RTC_SECONDS_ALARM);
 225        t->time.tm_min = CMOS_READ(RTC_MINUTES_ALARM);
 226        t->time.tm_hour = CMOS_READ(RTC_HOURS_ALARM);
 227
 228        if (cmos->day_alrm) {
 229                /* ignore upper bits on readback per ACPI spec */
 230                t->time.tm_mday = CMOS_READ(cmos->day_alrm) & 0x3f;
 231                if (!t->time.tm_mday)
 232                        t->time.tm_mday = -1;
 233
 234                if (cmos->mon_alrm) {
 235                        t->time.tm_mon = CMOS_READ(cmos->mon_alrm);
 236                        if (!t->time.tm_mon)
 237                                t->time.tm_mon = -1;
 238                }
 239        }
 240
 241        rtc_control = CMOS_READ(RTC_CONTROL);
 242        spin_unlock_irq(&rtc_lock);
 243
 244        if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
 245                if (((unsigned)t->time.tm_sec) < 0x60)
 246                        t->time.tm_sec = bcd2bin(t->time.tm_sec);
 247                else
 248                        t->time.tm_sec = -1;
 249                if (((unsigned)t->time.tm_min) < 0x60)
 250                        t->time.tm_min = bcd2bin(t->time.tm_min);
 251                else
 252                        t->time.tm_min = -1;
 253                if (((unsigned)t->time.tm_hour) < 0x24)
 254                        t->time.tm_hour = bcd2bin(t->time.tm_hour);
 255                else
 256                        t->time.tm_hour = -1;
 257
 258                if (cmos->day_alrm) {
 259                        if (((unsigned)t->time.tm_mday) <= 0x31)
 260                                t->time.tm_mday = bcd2bin(t->time.tm_mday);
 261                        else
 262                                t->time.tm_mday = -1;
 263
 264                        if (cmos->mon_alrm) {
 265                                if (((unsigned)t->time.tm_mon) <= 0x12)
 266                                        t->time.tm_mon = bcd2bin(t->time.tm_mon)-1;
 267                                else
 268                                        t->time.tm_mon = -1;
 269                        }
 270                }
 271        }
 272        t->time.tm_year = -1;
 273
 274        t->enabled = !!(rtc_control & RTC_AIE);
 275        t->pending = 0;
 276
 277        return 0;
 278}
 279
 280static void cmos_checkintr(struct cmos_rtc *cmos, unsigned char rtc_control)
 281{
 282        unsigned char   rtc_intr;
 283
 284        /* NOTE after changing RTC_xIE bits we always read INTR_FLAGS;
 285         * allegedly some older rtcs need that to handle irqs properly
 286         */
 287        rtc_intr = CMOS_READ(RTC_INTR_FLAGS);
 288
 289        if (is_hpet_enabled())
 290                return;
 291
 292        rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF;
 293        if (is_intr(rtc_intr))
 294                rtc_update_irq(cmos->rtc, 1, rtc_intr);
 295}
 296
 297static void cmos_irq_enable(struct cmos_rtc *cmos, unsigned char mask)
 298{
 299        unsigned char   rtc_control;
 300
 301        /* flush any pending IRQ status, notably for update irqs,
 302         * before we enable new IRQs
 303         */
 304        rtc_control = CMOS_READ(RTC_CONTROL);
 305        cmos_checkintr(cmos, rtc_control);
 306
 307        rtc_control |= mask;
 308        CMOS_WRITE(rtc_control, RTC_CONTROL);
 309        hpet_set_rtc_irq_bit(mask);
 310
 311        cmos_checkintr(cmos, rtc_control);
 312}
 313
 314static void cmos_irq_disable(struct cmos_rtc *cmos, unsigned char mask)
 315{
 316        unsigned char   rtc_control;
 317
 318        rtc_control = CMOS_READ(RTC_CONTROL);
 319        rtc_control &= ~mask;
 320        CMOS_WRITE(rtc_control, RTC_CONTROL);
 321        hpet_mask_rtc_irq_bit(mask);
 322
 323        cmos_checkintr(cmos, rtc_control);
 324}
 325
 326static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 327{
 328        struct cmos_rtc *cmos = dev_get_drvdata(dev);
 329       unsigned char   mon, mday, hrs, min, sec, rtc_control;
 330
 331        if (!is_valid_irq(cmos->irq))
 332                return -EIO;
 333
 334        mon = t->time.tm_mon + 1;
 335        mday = t->time.tm_mday;
 336        hrs = t->time.tm_hour;
 337        min = t->time.tm_min;
 338        sec = t->time.tm_sec;
 339
 340        rtc_control = CMOS_READ(RTC_CONTROL);
 341        if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
 342                /* Writing 0xff means "don't care" or "match all".  */
 343                mon = (mon <= 12) ? bin2bcd(mon) : 0xff;
 344                mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff;
 345                hrs = (hrs < 24) ? bin2bcd(hrs) : 0xff;
 346                min = (min < 60) ? bin2bcd(min) : 0xff;
 347                sec = (sec < 60) ? bin2bcd(sec) : 0xff;
 348        }
 349
 350        spin_lock_irq(&rtc_lock);
 351
 352        /* next rtc irq must not be from previous alarm setting */
 353        cmos_irq_disable(cmos, RTC_AIE);
 354
 355        /* update alarm */
 356        CMOS_WRITE(hrs, RTC_HOURS_ALARM);
 357        CMOS_WRITE(min, RTC_MINUTES_ALARM);
 358        CMOS_WRITE(sec, RTC_SECONDS_ALARM);
 359
 360        /* the system may support an "enhanced" alarm */
 361        if (cmos->day_alrm) {
 362                CMOS_WRITE(mday, cmos->day_alrm);
 363                if (cmos->mon_alrm)
 364                        CMOS_WRITE(mon, cmos->mon_alrm);
 365        }
 366
 367        /* FIXME the HPET alarm glue currently ignores day_alrm
 368         * and mon_alrm ...
 369         */
 370        hpet_set_alarm_time(t->time.tm_hour, t->time.tm_min, t->time.tm_sec);
 371
 372        if (t->enabled)
 373                cmos_irq_enable(cmos, RTC_AIE);
 374
 375        spin_unlock_irq(&rtc_lock);
 376
 377        return 0;
 378}
 379
 380static int cmos_alarm_irq_enable(struct device *dev, unsigned int enabled)
 381{
 382        struct cmos_rtc *cmos = dev_get_drvdata(dev);
 383        unsigned long   flags;
 384
 385        if (!is_valid_irq(cmos->irq))
 386                return -EINVAL;
 387
 388        spin_lock_irqsave(&rtc_lock, flags);
 389
 390        if (enabled)
 391                cmos_irq_enable(cmos, RTC_AIE);
 392        else
 393                cmos_irq_disable(cmos, RTC_AIE);
 394
 395        spin_unlock_irqrestore(&rtc_lock, flags);
 396        return 0;
 397}
 398
 399#if defined(CONFIG_RTC_INTF_PROC) || defined(CONFIG_RTC_INTF_PROC_MODULE)
 400
 401static int cmos_procfs(struct device *dev, struct seq_file *seq)
 402{
 403        struct cmos_rtc *cmos = dev_get_drvdata(dev);
 404        unsigned char   rtc_control, valid;
 405
 406        spin_lock_irq(&rtc_lock);
 407        rtc_control = CMOS_READ(RTC_CONTROL);
 408        valid = CMOS_READ(RTC_VALID);
 409        spin_unlock_irq(&rtc_lock);
 410
 411        /* NOTE:  at least ICH6 reports battery status using a different
 412         * (non-RTC) bit; and SQWE is ignored on many current systems.
 413         */
 414        return seq_printf(seq,
 415                        "periodic_IRQ\t: %s\n"
 416                        "update_IRQ\t: %s\n"
 417                        "HPET_emulated\t: %s\n"
 418                        // "square_wave\t: %s\n"
 419                        "BCD\t\t: %s\n"
 420                        "DST_enable\t: %s\n"
 421                        "periodic_freq\t: %d\n"
 422                        "batt_status\t: %s\n",
 423                        (rtc_control & RTC_PIE) ? "yes" : "no",
 424                        (rtc_control & RTC_UIE) ? "yes" : "no",
 425                        is_hpet_enabled() ? "yes" : "no",
 426                        // (rtc_control & RTC_SQWE) ? "yes" : "no",
 427                        (rtc_control & RTC_DM_BINARY) ? "no" : "yes",
 428                        (rtc_control & RTC_DST_EN) ? "yes" : "no",
 429                        cmos->rtc->irq_freq,
 430                        (valid & RTC_VRT) ? "okay" : "dead");
 431}
 432
 433#else
 434#define cmos_procfs     NULL
 435#endif
 436
 437static const struct rtc_class_ops cmos_rtc_ops = {
 438        .read_time              = cmos_read_time,
 439        .set_time               = cmos_set_time,
 440        .read_alarm             = cmos_read_alarm,
 441        .set_alarm              = cmos_set_alarm,
 442        .proc                   = cmos_procfs,
 443        .alarm_irq_enable       = cmos_alarm_irq_enable,
 444};
 445
 446/*----------------------------------------------------------------*/
 447
 448/*
 449 * All these chips have at least 64 bytes of address space, shared by
 450 * RTC registers and NVRAM.  Most of those bytes of NVRAM are used
 451 * by boot firmware.  Modern chips have 128 or 256 bytes.
 452 */
 453
 454#define NVRAM_OFFSET    (RTC_REG_D + 1)
 455
 456static ssize_t
 457cmos_nvram_read(struct file *filp, struct kobject *kobj,
 458                struct bin_attribute *attr,
 459                char *buf, loff_t off, size_t count)
 460{
 461        int     retval;
 462
 463        if (unlikely(off >= attr->size))
 464                return 0;
 465        if (unlikely(off < 0))
 466                return -EINVAL;
 467        if ((off + count) > attr->size)
 468                count = attr->size - off;
 469
 470        off += NVRAM_OFFSET;
 471        spin_lock_irq(&rtc_lock);
 472        for (retval = 0; count; count--, off++, retval++) {
 473                if (off < 128)
 474                        *buf++ = CMOS_READ(off);
 475                else if (can_bank2)
 476                        *buf++ = cmos_read_bank2(off);
 477                else
 478                        break;
 479        }
 480        spin_unlock_irq(&rtc_lock);
 481
 482        return retval;
 483}
 484
 485static ssize_t
 486cmos_nvram_write(struct file *filp, struct kobject *kobj,
 487                struct bin_attribute *attr,
 488                char *buf, loff_t off, size_t count)
 489{
 490        struct cmos_rtc *cmos;
 491        int             retval;
 492
 493        cmos = dev_get_drvdata(container_of(kobj, struct device, kobj));
 494        if (unlikely(off >= attr->size))
 495                return -EFBIG;
 496        if (unlikely(off < 0))
 497                return -EINVAL;
 498        if ((off + count) > attr->size)
 499                count = attr->size - off;
 500
 501        /* NOTE:  on at least PCs and Ataris, the boot firmware uses a
 502         * checksum on part of the NVRAM data.  That's currently ignored
 503         * here.  If userspace is smart enough to know what fields of
 504         * NVRAM to update, updating checksums is also part of its job.
 505         */
 506        off += NVRAM_OFFSET;
 507        spin_lock_irq(&rtc_lock);
 508        for (retval = 0; count; count--, off++, retval++) {
 509                /* don't trash RTC registers */
 510                if (off == cmos->day_alrm
 511                                || off == cmos->mon_alrm
 512                                || off == cmos->century)
 513                        buf++;
 514                else if (off < 128)
 515                        CMOS_WRITE(*buf++, off);
 516                else if (can_bank2)
 517                        cmos_write_bank2(*buf++, off);
 518                else
 519                        break;
 520        }
 521        spin_unlock_irq(&rtc_lock);
 522
 523        return retval;
 524}
 525
 526static struct bin_attribute nvram = {
 527        .attr = {
 528                .name   = "nvram",
 529                .mode   = S_IRUGO | S_IWUSR,
 530        },
 531
 532        .read   = cmos_nvram_read,
 533        .write  = cmos_nvram_write,
 534        /* size gets set up later */
 535};
 536
 537/*----------------------------------------------------------------*/
 538
 539static struct cmos_rtc  cmos_rtc;
 540
 541static irqreturn_t cmos_interrupt(int irq, void *p)
 542{
 543        u8              irqstat;
 544        u8              rtc_control;
 545
 546        spin_lock(&rtc_lock);
 547
 548        /* When the HPET interrupt handler calls us, the interrupt
 549         * status is passed as arg1 instead of the irq number.  But
 550         * always clear irq status, even when HPET is in the way.
 551         *
 552         * Note that HPET and RTC are almost certainly out of phase,
 553         * giving different IRQ status ...
 554         */
 555        irqstat = CMOS_READ(RTC_INTR_FLAGS);
 556        rtc_control = CMOS_READ(RTC_CONTROL);
 557        if (is_hpet_enabled())
 558                irqstat = (unsigned long)irq & 0xF0;
 559        irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF;
 560
 561        /* All Linux RTC alarms should be treated as if they were oneshot.
 562         * Similar code may be needed in system wakeup paths, in case the
 563         * alarm woke the system.
 564         */
 565        if (irqstat & RTC_AIE) {
 566                rtc_control &= ~RTC_AIE;
 567                CMOS_WRITE(rtc_control, RTC_CONTROL);
 568                hpet_mask_rtc_irq_bit(RTC_AIE);
 569
 570                CMOS_READ(RTC_INTR_FLAGS);
 571        }
 572        spin_unlock(&rtc_lock);
 573
 574        if (is_intr(irqstat)) {
 575                rtc_update_irq(p, 1, irqstat);
 576                return IRQ_HANDLED;
 577        } else
 578                return IRQ_NONE;
 579}
 580
 581#ifdef  CONFIG_PNP
 582#define INITSECTION
 583
 584#else
 585#define INITSECTION     __init
 586#endif
 587
 588static int INITSECTION
 589cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq)
 590{
 591        struct cmos_rtc_board_info      *info = dev->platform_data;
 592        int                             retval = 0;
 593        unsigned char                   rtc_control;
 594        unsigned                        address_space;
 595
 596        /* there can be only one ... */
 597        if (cmos_rtc.dev)
 598                return -EBUSY;
 599
 600        if (!ports)
 601                return -ENODEV;
 602
 603        /* Claim I/O ports ASAP, minimizing conflict with legacy driver.
 604         *
 605         * REVISIT non-x86 systems may instead use memory space resources
 606         * (needing ioremap etc), not i/o space resources like this ...
 607         */
 608        ports = request_region(ports->start,
 609                        resource_size(ports),
 610                        driver_name);
 611        if (!ports) {
 612                dev_dbg(dev, "i/o registers already in use\n");
 613                return -EBUSY;
 614        }
 615
 616        cmos_rtc.irq = rtc_irq;
 617        cmos_rtc.iomem = ports;
 618
 619        /* Heuristic to deduce NVRAM size ... do what the legacy NVRAM
 620         * driver did, but don't reject unknown configs.   Old hardware
 621         * won't address 128 bytes.  Newer chips have multiple banks,
 622         * though they may not be listed in one I/O resource.
 623         */
 624#if     defined(CONFIG_ATARI)
 625        address_space = 64;
 626#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \
 627                        || defined(__sparc__) || defined(__mips__) \
 628                        || defined(__powerpc__)
 629        address_space = 128;
 630#else
 631#warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes.
 632        address_space = 128;
 633#endif
 634        if (can_bank2 && ports->end > (ports->start + 1))
 635                address_space = 256;
 636
 637        /* For ACPI systems extension info comes from the FADT.  On others,
 638         * board specific setup provides it as appropriate.  Systems where
 639         * the alarm IRQ isn't automatically a wakeup IRQ (like ACPI, and
 640         * some almost-clones) can provide hooks to make that behave.
 641         *
 642         * Note that ACPI doesn't preclude putting these registers into
 643         * "extended" areas of the chip, including some that we won't yet
 644         * expect CMOS_READ and friends to handle.
 645         */
 646        if (info) {
 647                if (info->rtc_day_alarm && info->rtc_day_alarm < 128)
 648                        cmos_rtc.day_alrm = info->rtc_day_alarm;
 649                if (info->rtc_mon_alarm && info->rtc_mon_alarm < 128)
 650                        cmos_rtc.mon_alrm = info->rtc_mon_alarm;
 651                if (info->rtc_century && info->rtc_century < 128)
 652                        cmos_rtc.century = info->rtc_century;
 653
 654                if (info->wake_on && info->wake_off) {
 655                        cmos_rtc.wake_on = info->wake_on;
 656                        cmos_rtc.wake_off = info->wake_off;
 657                }
 658        }
 659
 660        cmos_rtc.dev = dev;
 661        dev_set_drvdata(dev, &cmos_rtc);
 662
 663        cmos_rtc.rtc = dref">space,  662
 654                  ref">dev, &dref">space, cmos_rtc);
 565        if (;
cmos_rtc.irqstat)) {
 566                ;
cmos_rtc.cmos_rtc);
 567  goto663        dev;
 658        }
 569
 660        ;
dev, &cmos_rtc.cmos-> 531
 572        spin_lock_irq(&rtc_lock);
 573
 537         5rqAD a    ted et default cer1024Hz in use\L573"> 573
 645 573
 606     iRAM databeented claedinclud>/* NOTE: be lass=" ALI mob registers into
 607 uce N08
 638
 639         */
 660        cmos_rtc.cmos->address024>rtc_lock);
 661        < classs="period">tf clef="+code=info" classs="period">tf cl="lineea>;
cmos_rtc.cmos->add">rtc_lock);
 572        CMOS_WRITE(< claREF_CLCK_32KHZode=CMOS_WRITE" claREF_CLCK_32KHZme="L| 0x06tc_control, add">rtc_lock);
 583
 537         5rqh RTC registers */
 625        < clas petdisef">+code=cmos_rtc" clas petdisef">="linref">dev, &RTC_AIE);
 636
 617        rtc_control = CMOS_READ(RTC_CONTROL);
 618
 629        spin_unlock_irq(&rtc_lock);
 580
 561        
 642
 623         */
 74        if (CMOS_READ(wake_on &= (rtc_control & irqstat)) {
 635                <  hr631"de=driver_name"  hr631"ev_set_drvdata(dev,  566                dev;
 567  goto663        dev;
 658        }
 599
 600        if (CMOS_READ(irqstat)) {
 601  >cmos->dev;
 602
 6L600"> 600        if (is_hpet_>irqstat)) {
 654          f">ports, int dev;
 615
 656                        dev;
 627          orts, int  = cmosn");
 648          00        if (irqstat)) {
 609                  orts, int ;
dev, )) {
 610          09                  oef">dev,  601                  goto663        dev;
 612          58        }
 613  77        } else
 654                        cmos"sref">dev;
 615
 566                CMOS_READ( 662
 627                  0re61        dev, &cmos_rtc.cmos-> 662
 648          66                cmos_rtc.cmos_rtc);
 649                if ( 610                        dev_dbg(dev,  601          goto663        dev;
 612  58        }
 658        }
 53ontrol = dev;
 615
 596        /* NOTE:uot;firTE:b6s=" ofstic toent">         */
 617        cmos_rtc.resef"              addr-"              dev;
 608        +code=cmos_rtc"sysfs_cms sh_bin_fi">="linref">dev, &dev->dev, &dev;
 6              if ( 570                dev_dbg(dev, ?y%dalready in use\tc_control, dev;
 601  goto663        dev;
 658        }
 583
 53ontrol = dev,  583
 635                dev, &cmos_rtc.cmos-> 662
 566  a>        if (!CMOS_READ(dev,  662
 627          orts, int cmos_rtc.dev,  662
 648                        cmos_rtc.dev,  662
 609           ef">dev,  583
 570                cmos_rtc.dev, dev,  583
 601  >cmos->cmos_rtc.restL583"> 583
 612                is_hpetf?sref">dev, dev, dev;
 583
 5       >retval = 0;
 615
         662
 597        if (CMOS_READ( 662
 648  CMOS_READ(CMOS_READ(cmos_rtc.cmos_rtc);
 589 662
 660        cmos_rtc.dev = dev;
 661        ;
cmos_rtc.cmos_rtc);
 589 662
 663        ;
ports->resource_size( 5       _control,         }
 636
 void660        resovoid"L662"> 662
)) {
 629        spin_lock_irq(&rtc_lock);
 660        +code=cmos_rtc" clas petdisef">="linref">dev, &rtc_lock);
 661        spin_unlock_irq(&rtc_lock);
        }
 583
 void660        <__exef="+code=__init"__exefme="L60        +code=cmos_rtc" clasdo_remov>pin_u ports, int addr*>cmos-> 583
)) {
 5 ports, int dev = <  hrgf="+code=dev_set_drvdata" clags="sref">dev_set_drvdata( 5 ports, int < class="=resource_size" class="srefr*>cmos->ports;
 618
 629        reso">rtc_lock);
 580
 661        _bin_fi">+code=cmos_rtc"sysfs_remov>_bin_fi">="linref">dev, &dev->dev, &dev;
 602
 697        if (CMOS_READ(< cla+code=cmos_rtc" claass=sref">cmos->irqstat)) {
 654  CMOS_READ(CMOS_READ(< cla+code=cmos_rtc" claass=sref">cmos->, cmos->cmos_rtc);
 635                ;
cmosn");
 558        }
        }
 608        ;
cmos->cmos_rtc);
 629        cmos->dev = dev;
 580
 661        cmos->dev;
 572        ;
ports->resource_size( 663        cmos->dev = dev;
dev;
 625        < cla+code=cmos_rtc" claass=sref">cmos->dev = dev;
 625        dev_set_drvdata(dev = cmos_rtev;
        }
 618
         618
 580
 f">ports, int < classuspa href="+code=end" classuspa hpin_u ports, int addr*>cmos-> 583
)) {
 6 ports, int dev = <  hrgf="+code=dev_set_drvdata" clags="sref">dev_set_drvdata(  unsigned char> 625        dev;
 615
 596               mightabe automaticevan  lass="oent">         */
 617        spin_lock_irq(&rtc_lock);
 608        < cla+code=cmos_rtc" claass=sref">cmos->dev =  = CMOS_READ(RTC_CONTROL);
 6              if (CMOS_READ(irqstat)) {
 570  unsigned char> 625        dev;
 531
 612                if (( 583
 6L600"> 6L608"> 608         = (dev;
 654          } else
 655                         = dev;
 656            if ((dev;
 627  control = CMOS_WRITE(, RTC_CONTROL);
 618
 609  96                 */
 610                CMOS_READ( 601  orts, int 96ef="dcmos.c#L5a hrecheckf">9="lineea>;
, );
 658        }
 663        spin_unlock_irq(&rtc_lock);
dev;
 565        if ((irqstat)) {
 566                < cla+code=cmos_rtc" claass=sref">cmos->i_toma+code=cmos_rtc"sref">i_tomaass=tc_1>rtc_lock);
 627  65        if (< cla+code=cmos_rtc" claass=sref">cmos-> 583
 648          a>        if (< cla+code=cmos_rtc" claass=sref">cmos-> 649          } else
 610                        _ clttoma+code=cmos_rtc"sref">_ clttomaref">CMOS_READ(< cla+code=cmos_rtc" claass=sref">cmos->rtc_lock);
 658        }
 602
 663        Cef">dev,  583
 654                        dev, &cmos_rtc.cmos-> 662
 655          /a>        if ((?sref">dev, dev,  583
 656                        );
        }
 6       >retval = 0;
        }
 580
                 */
 642 ACPI spact">         */
 623         */
 623less.  S athentt"> hardwaret">         */
 645
 606         */
 >cmos->ports, int < claspowercef+code=cmos_rtc" claspowercefpin_u ports, int addr*>cmos-> 583
)) {
 6       _control, < classuspa href="+code=end" classuspa hpin_ut_drvdata(        }
 531
 f">ports, int < clasresucode=driver_name" clasresucopin_u ports, int addr*>cmos-> 583
)) {
 5 ports, int dev = <  hrgf="+code=dev_set_drvdata" clags="sref">dev_set_drvdata( 6unsigned char> 625         = cmos->rtc_lock);
 636
 596         any 5rqh prcliousherac8"v"oent">         */
 665        if ((irqstat)) {
 649  unsigned char> 625        dev;
 580
 601  65        if (< cla+code=cmos_rtc" claass=sref">cmos->i_toma+code=cmos_rtc"sref">i_tomaass=">irqstat)) {
 612          65        if (< cla+code=cmos_rtc" claass=sref">cmos-> 583
 6L600"> 6L608"> 6                      < cla+code=cmos_rtc" claass=sref">cmos->( 654                  } else
 655                                _ clttoma+code=cmos_rtc"disef">_ clttomaref">CMOS_READ(< cla+code=cmos_rtc" claass=sref">cmos->rtc_lock);
 656                        < cla+code=cmos_rtc" claass=sref">cmos->i_toma+code=cmos_rtc"sref">i_tomaass=tc_>retval = 0;
 627  58        }
 618
 609  93        spin_lock_irq(&rtc_lock);
 610  do>irqstat)) {
 601  09  93        CMOS_WRITE(, RTC_CONTROL);
 612                        CMOS_WRITE(();
 583
 654                         = CMOS_READ();
 655                                if ((|tCMOS_READ(dev;
 656          65        if (!is_hpetf|| a>        if (!96ef="dcmos.c#L5a hf">9ref">CMOS_READ( 583
 627                  break"sref">dev;
 618
 609           ef">dev, is_>         */
 623 toma All Lme ths ef">s>         */
                 */
 612                        < claupd sh_ef="+code=rtc_irq" claupd sh_ef=ref">CMOS_READ(< cla+code=cmos_rtc" claass=sref">cmos->, dev;
 6L600"> 6L608"> 608        (dev;
 654  L608"> 608        CMOS_READ(dev;
 635  } whilet/a>        if ((dev;
 566                spin_unlock_irq(&rtc_lock);
 658        }
 618
 629        Cef">dev,  583
 610                        dev, &cmos_rtc.cmos-> 662
 601  09  93        );
 602
 6       >retval = 0;
        }
 615
 >cmos->CMOS_READ(< cla_pm_opa+code=cmos_rtc" cla_pm_opaass=tc_control, < classuspa href="+code=end" classuspa hpin_tc_control, );
        }
        } else
 >cmos->ports, int < claspowercef+code=cmos_rtc" claspowercefpin_u ports, int addr*>cmos-> 583
)) {
 6       ->cmos->dev;
        }
dev;
dev;
 636
dev,          */
 618
dev, 
s verCPna   ally on platform_busends to handle.
 623
        s; so PNPevenmore  
 642
 623 hardwareready  probpan.  Ancian  PCsinclunds to handle.
 623
 645         */
 636
         636
 618
 618include/"L5ux/acpi.hL599" id=fREAD""L5ux/acpi.hme="ref"L618"> 618
 580
 >cmos->(&cmos->< ontex=cmos_interrupt" ontex=ass="L583"> 583
)) {
 6 ports, int addr*>cmos-> =  618
dev;
 529        ();
 5t_drvdata(();
 617        _evan "+code=dev_dbg"acpi_disef">_evan ass=et_drvdata();
 6       t_drvdata( 618
        }
 580
 >cmos->        ports, int addr*>cmos-> 583
)) {
 663        ((&(& 6 ef">dev,          */
 645  cl PET inteveninL58lled,/t"> Fixed_ cl evan  lhouldt">         */
 606d. Otherwhentt">  cl All Levenset will itNbe sref">iends to handle.
dev,          */
 608        ();
 629        _evan "+code=dev_dbg"acpi_disef">_evan ass=et_drvdata();
        }
 531
 void660        ports, int addr*>cmos-> 583
)) {
 608        ();
 529        _evan "+code=dev_dbg"acpi_sref">_evan ass=et_drvdata();
        }
        }
 void660        ports, int addr*>cmos-> 583
)) {
 660        _evan "+code=dev_dbg"acpi_disef">_evan ass=et_drvdata();
        }
 602
 623
 ready iver ="dready .  Hereted findt">         */
 623( and p23< extra  d.  Thvenhelps its  an>
         */
 645 now-obsolete mc146818 didome thathave, and informs itt">         */
 606
dev,          */
  ports, int (& 618
 void660        <__ clinef="+code=__init"__ clinefme="        } else
, int ports, int addr*>cmos-> 583
)) {
 665        if (href="+code=end"acpi_disef">hass="L583"> 583
 654        "L618"> 618
 615
 5t_drvdata((& 617        cmos_rtc.rtc_lock);
 608        cmos_rtc. = rtc_lock);
 6L623"> 623 ACPI tef">sa*nt">         */
 665        if (cmos_rtc.c_conta>        if (!cmos_rtc. 612  _irq(&(dev,  583
 6L600"> 6L608"> 608        cmos_rtc.rtc_lock);
 654  a>        if (cmos_rtc. 658        }
 636
 617        cmos_rtc. = cmos_rtc. = 0;
 608        cmos_rtc. = cmos_rtc. 629        cmos_rtc. = cmos_rtc. = 0;
 580
 6L623"> 623         */
 665        if (cmos_rtc. t_drvdata( 583
 6L600"> 6_irq(&(dev, dtoma from S4already in use\">rtc_lock);
dev;
 529        cmos->dev, & 618
 636
 596                 */
 608        < clif"5inef_tomatiref="+code=dev" clif"5inef_tomatiass=et_drvdata(rtc_lock);
        }
 580
        } else
 602
 void660        <__ clinef="+code=__init"__ clinefme="        } else
, int ports, int addr*>cmos-> 583
)) {
        }
        }
dev;
         531
 618include/"L5ux/pnp.hL599" id=fREAD""L5ux/pnp.hme="ref"L618"> 618
 583
 f">ports, int <__ clinef="+code=__init"__ clinefme="        } else
, int ports, int addr*>cmos->ports, int addr*>cmos-> 583
)) {
 617        dev, &cmos-> 618
 618
 665        if ((c_conta>        if (!( 583
10/rme="L603"> 6L600"> 6_6         machL59s contain a PNPean ryN08  cl, butt">      /pre>
583"> 583
10/ame="96         IRQ. I  lhould Alwaysube saf9/tot">         */
10/ame="L642"> 64210/ame="L623"> 623         */
10/ame="L654"> 654        617        dev, &cmos-> 583
10/ame="L655"> 655                                ( 618
10/ame="L566"> 5        } else
10/ame="L627"> 627        617        dev, &cmos-> 583
10/ame="L648"> 648                                ( 583
10/ame="L609"> 609                                ( 618
10c#me="58        }
10came="L531"> 531
10came="L588"> void660        <__exef="+code=__init"__exefme="Lorts, int ports, int addr*>cmos-> 583
10came="irqstat)) {
10c4me="L608"> 608        dev, &cmos-> 618
10c5me="58        }
10came="L636"> 636
10came="#ifdef 572         636
10came="L618"> 618
10c9me="L588"> f">ports, int ports, int addr*>cmos->cmos-> 583
10c#me="irqstat)) {
10came="L601"> 6       _control, < classuspa href="+code=end" classuspa hpin_uref">dev, &cmos-> 618
10c2me="58        }
10came="L583"> 583
10came="L588"> f">ports, int ports, int addr*>cmos-> 583
10came="irqstat)) {
10c6me="L601"> 6       _control, < clasresucode=driver_name" clasresucopin_uref">dev, &cmos-> 618
10c7me="58        }
10came="L618"> 618
10c9me="#        } else
10c#me="#defL59/orts, int  608         618
10c1me="#defL59/orts, int  618
10c2me="#< hifsref">dev;
10came="L583"> 583
10came="L588"> void660        < claspnp_shutdow=request_region" claspnp_shutdow=pin_u ports, int addr*>cmos-> 583
10came="irqstat)) {
10c6me="L601"> 665        if ( = c_conta>        if (!< claspowercef+code=cmos_rtc" claspowercefpin_uref">dev, &cmos-> 583
10came="L627"> 627        "L618"> 618
10came="L618"> 618
10came="L629"> 629         618
10c#me="58        }
10came="L531"> 531
10came="L588"> const  ports, int addrorts, int add[] =>irqstat)) {
10came="L603"> 6{ ">cmos_rtc.dev,  583
10c4me="L603"> 6{ ">cmos_rtc.dev,  583
10c5me="L603"> 6{ ">cmos_rtc.dev,  583
10c6me="L603"> 6{ },L583"> 583
10c7me="5"L618"> 618
10c8me="orts, int ( 618
10came="        } else
10c#me="L588">  ports, int )) {
10came="L601"> 6">cmos_rtc.< claref="+code=end" clame="L627"> 627<= (char *)ports, int  583
10c2me="L601"> 6">cmos_rtc.ref="+code=end"ih_tef">me="L601"> c_control = addtL583"> 583
10c3me="L601"> 6">cmos_rtc. 627<= orts, int  583
10c4me="L601"> 6">cmos_rtc. 627<= orts, int <__exef_pref="+code=dev"__exef_pass=et_drvdata( 583
10c5me="L601"> 6">cmos_rtc. 627<= orts, int  583
10came="L636"> 636
10came="L597"> 596                 */
10c8me="L601"> 6">cmos_rtc. 627<= orts, int  583
10c9me="L601"> 6">cmos_rtc. 6= orts, int  583
10c#me="L601"> 6">cmos_rtc., int  583
10c1me="5"L618"> 618
10came="L602"> 602
10c3me="#< hif 596                 */
10came="sref">dev;
10c5me="#ifdef 72        dev;
10c6me="L588"> const  ports, int add[] =>irqstat)) {
10came="L597"> 5irqstat)) {
10came="L648"> 648  ">cmos_rtc.de=driver_name" ass=tc_cef">dev,  583
10c9me="L601"> 6},L583"> 583
10c#me="L603"> 6{ },L583"> 583
10c1me="5"L618"> 618
10c2me="orts, int (add""L618"> 618
10came="L583"> 583
10came="L588"> orts, int <__inef="+code=__init"__inefme=" void660        < clasof_inef="+code=__init" clasof_inefpin_u ports, int addr*>cmos-> 583
10came="irqstat)) {
10c6me="L603"> 6 ports, int (ref="+code=dev" cl"L5_na>(>addr*>cmos->(ref="+code=dev"na>(>addr= orts, int cmos->(ass="L618"> 618
10c7me="L603"> 6 ports, int , int  618
10came="L648"> 6f">ports, int  618
10c9me="L601"> 6const orts, int <__bec#L632" id=_READ"__bec#>addr*>cmos-> 618
10c#me="L583"> 583
10came="L601"> 665        if (!(ref="+code=dev"na>(>add"L583"> 583
10came="L612"> 612        "L618"> 618
10came="L583"> 583
10c4me="L608"> 608        , int ((ref="+code=dev"na>(>add, Cef">dev,  618
10c5me="L601"> 665         583
10c6me="L612"> 612  72        (( 618
10came="8        }
10came="L608"> 608        , int ((ref="+code=dev"na>(>add, Cef">dev,  618
10came="L629"> 665        if ( 583
10c#me="L612"> 612  72        (( 618
10came="L531"> 531
10c2me="L608"> 608        dev, & 618
10came="L663"> 663         = dev, & 618
10c4me="L629"> 665        if (irqstat)) {
10came="L655"> 655   ports, int , int )) {
10c6me="L612"> 612          ">cmos_rtc. 583
10came="L627"> 627          ">cmos_rtc. 583
10came="L648"> 648  5"L618"> 618
10came="L609"> 609  >cmos_rtc.dev, & 618
11/rme="L603"> 658        }
110ame="58        }
1102me="#        } else
110ame="L588"> >cmos_rtc.        < clasof_inef="+code=__init" clasof_inefpin_u ports, int addr*>cmos->11/ame="#defL59/orts, int add                618
11/ame="#< hifsref">dev;
110ame="L606"> 606         */
110ame="8        }
11/ame="96         cl dd="L5,rwhentPNPmisnds to handle.
11/ame="L606"> 606
11c#me=" ef">dev,          */
11came="L531"> 531
11came="L588"> f">ports, int <__inef="+code=__init"__inefme=" orts, int ports, int addr*>cmos-> 583
11came="irqstat)) {
11c4me="L608"> 608        cmos-> 618
111ame="L565"> 529        < clasa hresettiref="+code=dev"a hrea hresettipin_uref">dev, &cmos-> 618
1116me="L601"> 6       _control, < clasdo_prob5ref="+code=dev"a hredo_prob5pin_uref">dev, &cmos-> 583
111ame="L627"> 627          orts, int cmos-> 583
111ame="L648"> 648          orts, int cmos-> 618
111ame="58        }
112#me="L583"> 583
11came="L588"> f">ports, int <__exef="+code=__init"__exefme="Lorts, int ports, int addr*>cmos-> 583
112ame="irqstat)) {
112ame="L663"> 663        dev, &cmos-> 618
1124me="L601"> 6       >retval = 0;
1125me="58        }
112ame="L636"> 636
11c7me="L588"> void660        < clasplatform_shutdow=request_region" clasplatform_shutdow=pin_u ports, int addr*>cmos-> 583
11came="irqstat)) {
112ame="L629"> 665        if ( = c_conta>        if (!< claspowercef+code=cmos_rtc" claspowercefpin_uref">dev, &cmos-> 583
113#me="L612"> 612        "L618"> 618
113ame="L531"> 531
1132me="L608"> 608         618
11came="58        }
113ame="sref">dev;
113ame="L645"> 645         */
11c6me="08        ef">dev, rtc_lock);
113ame="8        }
113ame="L588">  ports, int 1139me="L601"> 6">cmos_rtc. 627<= orts, int <__exef_pref="+code=dev"__exef_pass=et_drvdata( 583
114#me="L601"> 6">cmos_rtc. 627<= orts, int  583
114ame="L601"> 6">cmos_rtc.114ame="L612"> 612  ">cmos_rtc.< claref="+code=end" clame="L627"> 627<= (char *)ports, int  583
11came="#ifdef 72         636
11c4me="L603"> 612  ">cmos_rtc. 612dev, &< claspm_opa+code=cmos_rtc" claspm_opaass=tL583"> 583
114ame="#< hifsref">dev;
1146me="L612"> 612  ">cmos_rtc.ref="+code=end"of_match_tef">me=" c_control = addtL583"> 583
114ame="L627"> 658        }
11c8me="5"L618"> 618
11came="        } else
1150me="#ifdef 72        115ame="L588"> 72        , int  618
1152me="#< hifsref">dev;
115ame="L588"> >cmos_rtc., int  618
115ame="sref">dev;
11c5me="L588"> f">ports, int <__inef="+code=__init"__inefme=" orts, int  583
115ame="irqstat)) {
11came="L597"> 5f">ports, int retval = 0;
115ame="L618"> 618
11c9me="#ifdef 572        11c#me="L601"> 6orts, int , int dev, &< claspnp_alse
116ame="L601"> 665, int "L583"> 583
116ame="L612"> 612  orts, int  618
11c3me="#< hifL618"> 618
11came="sref">dev;
1165me="L601"> 665        if (!< clas="dref="+code=end"a hre="dme="">cmos_rtc.1166me="L612"> 612  72        , int dev, &< clasplatform_alse
 583
116ame="L627"> 627                                 orts, int rtc_lock);
11came="L648"> 648  65, int "L583"> 583
116ame="L609"> 609          orts, int  618
117rme="L603"> 658        }
117ame="L531"> 531
1172me="L601"> 665, int "L583"> 583
1173me="L609"> 609         >retval = 0;
117ame="sref">dev;
1175me="#ifdef 572        11c6me="L603"> 665        if ( 583
117ame="L627"> 627  a>        if (dev, &< claspnp_alse
117ame="#< hifsref">dev;
11c9me="L601"> 6       _control, rtc_lock);
118#me="58        }
11came="_control, (rtc_lock);
118ame="L602"> 602
118ame="L588"> void660        <__exef="+code=__init"__exefme="Lorts, int  583
11c4me="irqstat)) {
1185me="#ifdef 572        1186me="L603"> 665        if ( 583
118ame="L627"> 627  a>        if (dev, &< claspnp_alse
118ame="#< hifsref">dev;
11came="L629"> 665        if ( 583
11c#me="L612"> 612  72        dev, &< clasplatform_alse
rtc_lock);
119ame="58        }
1192me="orts, int (rtc_lock);
119ame="L583"> 583
119ame="sref">dev;
11came="08        ef">dev, rtc_lock);
1196me="08        ef">dev, rtc_lock);
11came="08        ef">dev, rtc_lock);
11came="


The original LXR software by:uot 72 http://sourL5forge.net/projects/lxrr>LXR > mailto:lxr@"L5ux.no">lxr@"L5ux.nome=""
lxr."L5ux.no kindly hosted by:72 http://www.rehpill-"L5pro.no">Rehpill LL5pro ASpin_, provid < of LL5ux6consultpan/and oper88"ons ser="L5s since 1995.