linux/drivers/pinctrl/pinctrl-u300.c
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   1/*
   2 * Driver for the U300 pin controller
   3 *
   4 * Based on the original U300 padmux functions
   5 * Copyright (C) 2009-2011 ST-Ericsson AB
   6 * Author: Martin Persson <martin.persson@stericsson.com>
   7 * Author: Linus Walleij <linus.walleij@linaro.org>
   8 *
   9 * The DB3350 design and control registers are oriented around pads rather than
  10 * pins, so we enumerate the pads we can mux rather than actual pins. The pads
  11 * are connected to different pins in different packaging types, so it would
  12 * be confusing.
  13 */
  14#include <linux/init.h>
  15#include <linux/module.h>
  16#include <linux/platform_device.h>
  17#include <linux/io.h>
  18#include <linux/slab.h>
  19#include <linux/err.h>
  20#include <linux/pinctrl/pinctrl.h>
  21#include <linux/pinctrl/pinmux.h>
  22#include <linux/pinctrl/pinconf.h>
  23#include <linux/pinctrl/pinconf-generic.h>
  24#include "pinctrl-coh901.h"
  25
  26/*
  27 * Register definitions for the U300 Padmux control registers in the
  28 * system controller
  29 */
  30
  31/* PAD MUX Control register 1 (LOW) 16bit (R/W) */
  32#define U300_SYSCON_PMC1LR                                      0x007C
  33#define U300_SYSCON_PMC1LR_MASK                                 0xFFFF
  34#define U300_SYSCON_PMC1LR_CDI_MASK                             0xC000
  35#define U300_SYSCON_PMC1LR_CDI_CDI                              0x0000
  36#define U300_SYSCON_PMC1LR_CDI_EMIF                             0x4000
  37/* For BS335 */
  38#define U300_SYSCON_PMC1LR_CDI_CDI2                             0x8000
  39#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO                   0xC000
  40/* For BS365 */
  41#define U300_SYSCON_PMC1LR_CDI_GPIO                             0x8000
  42#define U300_SYSCON_PMC1LR_CDI_WCDMA                            0xC000
  43/* Common defs */
  44#define U300_SYSCON_PMC1LR_PDI_MASK                             0x3000
  45#define U300_SYSCON_PMC1LR_PDI_PDI                              0x0000
  46#define U300_SYSCON_PMC1LR_PDI_EGG                              0x1000
  47#define U300_SYSCON_PMC1LR_PDI_WCDMA                            0x3000
  48#define U300_SYSCON_PMC1LR_MMCSD_MASK                           0x0C00
  49#define U300_SYSCON_PMC1LR_MMCSD_MMCSD                          0x0000
  50#define U300_SYSCON_PMC1LR_MMCSD_MSPRO                          0x0400
  51#define U300_SYSCON_PMC1LR_MMCSD_DSP                            0x0800
  52#define U300_SYSCON_PMC1LR_MMCSD_WCDMA                          0x0C00
  53#define U300_SYSCON_PMC1LR_ETM_MASK                             0x0300
  54#define U300_SYSCON_PMC1LR_ETM_ACC                              0x0000
  55#define U300_SYSCON_PMC1LR_ETM_APP                              0x0100
  56#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK                      0x00C0
  57#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC                    0x0000
  58#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF                      0x0040
  59#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM                     0x0080
  60#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB                0x00C0
  61#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK                      0x0030
  62#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC                    0x0000
  63#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF                      0x0010
  64#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM                     0x0020
  65#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI                      0x0030
  66#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK                      0x000C
  67#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC                    0x0000
  68#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF                      0x0004
  69#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM                     0x0008
  70#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI                      0x000C
  71#define U300_SYSCON_PMC1LR_EMIF_1_MASK                          0x0003
  72#define U300_SYSCON_PMC1LR_EMIF_1_STATIC                        0x0000
  73#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0                        0x0001
  74#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1                        0x0002
  75#define U300_SYSCON_PMC1LR_EMIF_1                               0x0003
  76/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
  77#define U300_SYSCON_PMC1HR                                      0x007E
  78#define U300_SYSCON_PMC1HR_MASK                                 0xFFFF
  79#define U300_SYSCON_PMC1HR_MISC_2_MASK                          0xC000
  80#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO                      0x0000
  81#define U300_SYSCON_PMC1HR_MISC_2_MSPRO                         0x4000
  82#define U300_SYSCON_PMC1HR_MISC_2_DSP                           0x8000
  83#define U300_SYSCON_PMC1HR_MISC_2_AAIF                          0xC000
  84#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK                      0x3000
  85#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO                  0x0000
  86#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF                      0x1000
  87#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP                       0x2000
  88#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF                      0x3000
  89#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK                      0x0C00
  90#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO                  0x0000
  91#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC                       0x0400
  92#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP                       0x0800
  93#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF                      0x0C00
  94#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK                    0x0300
  95#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO                0x0000
  96#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI                     0x0100
  97#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF                    0x0300
  98#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK                    0x00C0
  99#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO                0x0000
 100#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI                     0x0040
 101#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF                    0x00C0
 102#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK                       0x0030
 103#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO                   0x0000
 104#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI                        0x0010
 105#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP                        0x0020
 106#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF                       0x0030
 107#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK                     0x000C
 108#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO                 0x0000
 109#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0                    0x0004
 110#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS                  0x0008
 111#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF                     0x000C
 112#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK                     0x0003
 113#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO                 0x0000
 114#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0                    0x0001
 115#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF                     0x0003
 116/* Padmux 2 control */
 117#define U300_SYSCON_PMC2R                                       0x100
 118#define U300_SYSCON_PMC2R_APP_MISC_0_MASK                       0x00C0
 119#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO                   0x0000
 120#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM                 0x0040
 121#define U300_SYSCON_PMC2R_APP_MISC_0_MMC                        0x0080
 122#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2                       0x00C0
 123#define U300_SYSCON_PMC2R_APP_MISC_1_MASK                       0x0300
 124#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO                   0x0000
 125#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM                 0x0100
 126#define U300_SYSCON_PMC2R_APP_MISC_1_MMC                        0x0200
 127#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2                       0x0300
 128#define U300_SYSCON_PMC2R_APP_MISC_2_MASK                       0x0C00
 129#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO                   0x0000
 130#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM                 0x0400
 131#define U300_SYSCON_PMC2R_APP_MISC_2_MMC                        0x0800
 132#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2                       0x0C00
 133#define U300_SYSCON_PMC2R_APP_MISC_3_MASK                       0x3000
 134#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO                   0x0000
 135#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM                 0x1000
 136#define U300_SYSCON_PMC2R_APP_MISC_3_MMC                        0x2000
 137#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2                       0x3000
 138#define U300_SYSCON_PMC2R_APP_MISC_4_MASK                       0xC000
 139#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO                   0x0000
 140#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM                 0x4000
 141#define U300_SYSCON_PMC2R_APP_MISC_4_MMC                        0x8000
 142#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO                   0xC000
 143/* TODO: More SYSCON registers missing */
 144#define U300_SYSCON_PMC3R                                       0x10C
 145#define U300_SYSCON_PMC3R_APP_MISC_11_MASK                      0xC000
 146#define U300_SYSCON_PMC3R_APP_MISC_11_SPI                       0x4000
 147#define U300_SYSCON_PMC3R_APP_MISC_10_MASK                      0x3000
 148#define U300_SYSCON_PMC3R_APP_MISC_10_SPI                       0x1000
 149/* TODO: Missing other configs */
 150#define U300_SYSCON_PMC4R                                       0x168
 151#define U300_SYSCON_PMC4R_APP_MISC_12_MASK                      0x0003
 152#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO                  0x0000
 153#define U300_SYSCON_PMC4R_APP_MISC_13_MASK                      0x000C
 154#define U300_SYSCON_PMC4R_APP_MISC_13_CDI                       0x0000
 155#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA                      0x0004
 156#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2                     0x0008
 157#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO                  0x000C
 158#define U300_SYSCON_PMC4R_APP_MISC_14_MASK                      0x0030
 159#define U300_SYSCON_PMC4R_APP_MISC_14_CDI                       0x0000
 160#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA                      0x0010
 161#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2                      0x0020
 162#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO                  0x0030
 163#define U300_SYSCON_PMC4R_APP_MISC_16_MASK                      0x0300
 164#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13               0x0000
 165#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS             0x0100
 166#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N       0x0200
 167
 168#define DRIVER_NAME "pinctrl-u300"
 169
 170/*
 171 * The DB3350 has 467 pads, I have enumerated the pads clockwise around the
 172 * edges of the silicon, finger by finger. LTCORNER upper left is pad 0.
 173 * Data taken from the PadRing chart, arranged like this:
 174 *
 175 *   0 ..... 104
 176 * 466        105
 177 *   .        .
 178 *   .        .
 179 * 358        224
 180 *  357 .... 225
 181 */
 182#define U300_NUM_PADS 467
 183
 184/* Pad names for the pinmux subsystem */
 185static const struct pinctrl_pin_desc u300_pads[] = {
 186        /* Pads along the top edge of the chip */
 187        PINCTRL_PIN(0, "P PAD VDD 28"),
 188        PINCTRL_PIN(1, "P PAD GND 28"),
 189        PINCTRL_PIN(2, "PO SIM RST N"),
 190        PINCTRL_PIN(3, "VSSIO 25"),
 191        PINCTRL_PIN(4, "VSSA ADDA ESDSUB"),
 192        PINCTRL_PIN(5, "PWR VSSCOMMON"),
 193        PINCTRL_PIN(6, "PI ADC I1 POS"),
 194        PINCTRL_PIN(7, "PI ADC I1 NEG"),
 195        PINCTRL_PIN(8, "PWR VSSAD0"),
 196        PINCTRL_PIN(9, "PWR VCCAD0"),
 197        PINCTRL_PIN(10, "PI ADC Q1 NEG"),
 198        PINCTRL_PIN(11, "PI ADC Q1 POS"),
 199        PINCTRL_PIN(12, "PWR VDDAD"),
 200        PINCTRL_PIN(13, "PWR GNDAD"),
 201        PINCTRL_PIN(14, "PI ADC I2 POS"),
 202        PINCTRL_PIN(15, "PI ADC I2 NEG"),
 203        PINCTRL_PIN(16, "PWR VSSAD1"),
 204        PINCTRL_PIN(17, "PWR VCCAD1"),
 205        PINCTRL_PIN(18, "PI ADC Q2 NEG"),
 206        PINCTRL_PIN(19, "PI ADC Q2 POS"),
 207        PINCTRL_PIN(20, "VSSA ADDA ESDSUB"),
 208        PINCTRL_PIN(21, "PWR VCCGPAD"),
 209        PINCTRL_PIN(22, "PI TX POW"),
 210        PINCTRL_PIN(23, "PWR VSSGPAD"),
 211        PINCTRL_PIN(24, "PO DAC I POS"),
 212        PINCTRL_PIN(25, "PO DAC I NEG"),
 213        PINCTRL_PIN(26, "PO DAC Q POS"),
 214        PINCTRL_PIN(27, "PO DAC Q NEG"),
 215        PINCTRL_PIN(28, "PWR VSSDA"),
 216        PINCTRL_PIN(29, "PWR VCCDA"),
 217        PINCTRL_PIN(30, "VSSA ADDA ESDSUB"),
 218        PINCTRL_PIN(31, "P PAD VDDIO 11"),
 219        PINCTRL_PIN(32, "PI PLL 26 FILTVDD"),
 220        PINCTRL_PIN(33, "PI PLL 26 VCONT"),
 221        PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"),
 222        PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"),
 223        PINCTRL_PIN(36, "VDDA PLL ESD"),
 224        PINCTRL_PIN(37, "VSSA PLL ESD"),
 225        PINCTRL_PIN(38, "VSS PLL"),
 226        PINCTRL_PIN(39, "VDDC PLL"),
 227        PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"),
 228        PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"),
 229        PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"),
 230        PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"),
 231        PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"),
 232        PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"),
 233        PINCTRL_PIN(46, "P PAD VSSIO 11"),
 234        PINCTRL_PIN(47, "P PAD VSSIO 12"),
 235        PINCTRL_PIN(48, "PI POW RST N"),
 236        PINCTRL_PIN(49, "VDDC IO"),
 237        PINCTRL_PIN(50, "P PAD VDDIO 16"),
 238        PINCTRL_PIN(51, "PO RF WCDMA EN 4"),
 239        PINCTRL_PIN(52, "PO RF WCDMA EN 3"),
 240        PINCTRL_PIN(53, "PO RF WCDMA EN 2"),
 241        PINCTRL_PIN(54, "PO RF WCDMA EN 1"),
 242        PINCTRL_PIN(55, "PO RF WCDMA EN 0"),
 243        PINCTRL_PIN(56, "PO GSM PA ENABLE"),
 244        PINCTRL_PIN(57, "PO RF DATA STRB"),
 245        PINCTRL_PIN(58, "PO RF DATA2"),
 246        PINCTRL_PIN(59, "PIO RF DATA1"),
 247        PINCTRL_PIN(60, "PIO RF DATA0"),
 248        PINCTRL_PIN(61, "P PAD VDD 11"),
 249        PINCTRL_PIN(62, "P PAD GND 11"),
 250        PINCTRL_PIN(63, "P PAD VSSIO 16"),
 251        PINCTRL_PIN(64, "P PAD VDDIO 18"),
 252        PINCTRL_PIN(65, "PO RF CTRL STRB2"),
 253        PINCTRL_PIN(66, "PO RF CTRL STRB1"),
 254        PINCTRL_PIN(67, "PO RF CTRL STRB0"),
 255        PINCTRL_PIN(68, "PIO RF CTRL DATA"),
 256        PINCTRL_PIN(69, "PO RF CTRL CLK"),
 257        PINCTRL_PIN(70, "PO TX ADC STRB"),
 258        PINCTRL_PIN(71, "PO ANT SW 2"),
 259        PINCTRL_PIN(72, "PO ANT SW 3"),
 260        PINCTRL_PIN(73, "PO ANT SW 0"),
 261        PINCTRL_PIN(74, "PO ANT SW 1"),
 262        PINCTRL_PIN(75, "PO M CLKRQ"),
 263        PINCTRL_PIN(76, "PI M CLK"),
 264        PINCTRL_PIN(77, "PI RTC CLK"),
 265        PINCTRL_PIN(78, "P PAD VDD 8"),
 266        PINCTRL_PIN(79, "P PAD GND 8"),
 267        PINCTRL_PIN(80, "P PAD VSSIO 13"),
 268        PINCTRL_PIN(81, "P PAD VDDIO 13"),
 269        PINCTRL_PIN(82, "PO SYS 1 CLK"),
 270        PINCTRL_PIN(83, "PO SYS 2 CLK"),
 271        PINCTRL_PIN(84, "PO SYS 0 CLK"),
 272        PINCTRL_PIN(85, "PI SYS 0 CLKRQ"),
 273        PINCTRL_PIN(86, "PO PWR MNGT CTRL 1"),
 274        PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"),
 275        PINCTRL_PIN(88, "PO RESOUT2 RST N"),
 276        PINCTRL_PIN(89, "PO RESOUT1 RST N"),
 277        PINCTRL_PIN(90, "PO RESOUT0 RST N"),
 278        PINCTRL_PIN(91, "PI SERVICE N"),
 279        PINCTRL_PIN(92, "P PAD VDD 29"),
 280        PINCTRL_PIN(93, "P PAD GND 29"),
 281        PINCTRL_PIN(94, "P PAD VSSIO 8"),
 282        PINCTRL_PIN(95, "P PAD VDDIO 8"),
 283        PINCTRL_PIN(96, "PI EXT IRQ1 N"),
 284        PINCTRL_PIN(97, "PI EXT IRQ0 N"),
 285        PINCTRL_PIN(98, "PIO DC ON"),
 286        PINCTRL_PIN(99, "PIO ACC APP I2C DATA"),
 287        PINCTRL_PIN(100, "PIO ACC APP I2C CLK"),
 288        PINCTRL_PIN(101, "P PAD VDD 12"),
 289        PINCTRL_PIN(102, "P PAD GND 12"),
 290        PINCTRL_PIN(103, "P PAD VSSIO 14"),
 291        PINCTRL_PIN(104, "P PAD VDDIO 14"),
 292        /* Pads along the right edge of the chip */
 293        PINCTRL_PIN(105, "PIO APP I2C1 DATA"),
 294        PINCTRL_PIN(106, "PIO APP I2C1 CLK"),
 295        PINCTRL_PIN(107, "PO KEY OUT0"),
 296        PINCTRL_PIN(108, "PO KEY OUT1"),
 297        PINCTRL_PIN(109, "PO KEY OUT2"),
 298        PINCTRL_PIN(110, "PO KEY OUT3"),
 299        PINCTRL_PIN(111, "PO KEY OUT4"),
 300        PINCTRL_PIN(112, "PI KEY IN0"),
 301        PINCTRL_PIN(113, "PI KEY IN1"),
 302        PINCTRL_PIN(114, "PI KEY IN2"),
 303        PINCTRL_PIN(115, "P PAD VDDIO 15"),
 304        PINCTRL_PIN(116, "P PAD VSSIO 15"),
 305        PINCTRL_PIN(117, "P PAD GND 13"),
 306        PINCTRL_PIN(118, "P PAD VDD 13"),
 307        PINCTRL_PIN(119, "PI KEY IN3"),
 308        PINCTRL_PIN(120, "PI KEY IN4"),
 309        PINCTRL_PIN(121, "PI KEY IN5"),
 310        PINCTRL_PIN(122, "PIO APP PCM I2S1 DATA B"),
 311        PINCTRL_PIN(123, "PIO APP PCM I2S1 DATA A"),
 312        PINCTRL_PIN(124, "PIO APP PCM I2S1 WS"),
 313        PINCTRL_PIN(125, "PIO APP PCM I2S1 CLK"),
 314        PINCTRL_PIN(126, "PIO APP PCM I2S0 DATA B"),
 315        PINCTRL_PIN(127, "PIO APP PCM I2S0 DATA A"),
 316        PINCTRL_PIN(128, "PIO APP PCM I2S0 WS"),
 317        PINCTRL_PIN(129, "PIO APP PCM I2S0 CLK"),
 318        PINCTRL_PIN(130, "P PAD VDD 17"),
 319        PINCTRL_PIN(131, "P PAD GND 17"),
 320        PINCTRL_PIN(132, "P PAD VSSIO 19"),
 321        PINCTRL_PIN(133, "P PAD VDDIO 19"),
 322        PINCTRL_PIN(134, "UART0 RTS"),
 323        PINCTRL_PIN(135, "UART0 CTS"),
 324        PINCTRL_PIN(136, "UART0 TX"),
 325        PINCTRL_PIN(137, "UART0 RX"),
 326        PINCTRL_PIN(138, "PIO ACC SPI DO"),
 327        PINCTRL_PIN(139, "PIO ACC SPI DI"),
 328        PINCTRL_PIN(140, "PIO ACC SPI CS0 N"),
 329        PINCTRL_PIN(141, "PIO ACC SPI CS1 N"),
 330        PINCTRL_PIN(142, "PIO ACC SPI CS2 N"),
 331        PINCTRL_PIN(143, "PIO ACC SPI CLK"),
 332        PINCTRL_PIN(144, "PO PDI EXT RST N"),
 333        PINCTRL_PIN(145, "P PAD VDDIO 22"),
 334        PINCTRL_PIN(146, "P PAD VSSIO 22"),
 335        PINCTRL_PIN(147, "P PAD GND 18"),
 336        PINCTRL_PIN(148, "P PAD VDD 18"),
 337        PINCTRL_PIN(149, "PIO PDI C0"),
 338        PINCTRL_PIN(150, "PIO PDI C1"),
 339        PINCTRL_PIN(151, "PIO PDI C2"),
 340        PINCTRL_PIN(152, "PIO PDI C3"),
 341        PINCTRL_PIN(153, "PIO PDI C4"),
 342        PINCTRL_PIN(154, "PIO PDI C5"),
 343        PINCTRL_PIN(155, "PIO PDI D0"),
 344        PINCTRL_PIN(156, "PIO PDI D1"),
 345        PINCTRL_PIN(157, "PIO PDI D2"),
 346        PINCTRL_PIN(158, "PIO PDI D3"),
 347        PINCTRL_PIN(159, "P PAD VDDIO 21"),
 348        PINCTRL_PIN(160, "P PAD VSSIO 21"),
 349        PINCTRL_PIN(161, "PIO PDI D4"),
 350        PINCTRL_PIN(162, "PIO PDI D5"),
 351        PINCTRL_PIN(163, "PIO PDI D6"),
 352        PINCTRL_PIN(164, "PIO PDI D7"),
 353        PINCTRL_PIN(165, "PIO MS INS"),
 354        PINCTRL_PIN(166, "MMC DATA DIR LS"),
 355        PINCTRL_PIN(167, "MMC DATA 3"),
 356        PINCTRL_PIN(168, "MMC DATA 2"),
 357        PINCTRL_PIN(169, "MMC DATA 1"),
 358        PINCTRL_PIN(170, "MMC DATA 0"),
 359        PINCTRL_PIN(171, "MMC CMD DIR LS"),
 360        PINCTRL_PIN(172, "P PAD VDD 27"),
 361        PINCTRL_PIN(173, "P PAD GND 27"),
 362        PINCTRL_PIN(174, "P PAD VSSIO 20"),
 363        PINCTRL_PIN(175, "P PAD VDDIO 20"),
 364        PINCTRL_PIN(176, "MMC CMD"),
 365        PINCTRL_PIN(177, "MMC CLK"),
 366        PINCTRL_PIN(178, "PIO APP GPIO 14"),
 367        PINCTRL_PIN(179, "PIO APP GPIO 13"),
 368        PINCTRL_PIN(180, "PIO APP GPIO 11"),
 369        PINCTRL_PIN(181, "PIO APP GPIO 25"),
 370        PINCTRL_PIN(182, "PIO APP GPIO 24"),
 371        PINCTRL_PIN(183, "PIO APP GPIO 23"),
 372        PINCTRL_PIN(184, "PIO APP GPIO 22"),
 373        PINCTRL_PIN(185, "PIO APP GPIO 21"),
 374        PINCTRL_PIN(186, "PIO APP GPIO 20"),
 375        PINCTRL_PIN(187, "P PAD VDD 19"),
 376        PINCTRL_PIN(188, "P PAD GND 19"),
 377        PINCTRL_PIN(189, "P PAD VSSIO 23"),
 378        PINCTRL_PIN(190, "P PAD VDDIO 23"),
 379        PINCTRL_PIN(191, "PIO APP GPIO 19"),
 380        PINCTRL_PIN(192, "PIO APP GPIO 18"),
 381        PINCTRL_PIN(193, "PIO APP GPIO 17"),
 382        PINCTRL_PIN(194, "PIO APP GPIO 16"),
 383        PINCTRL_PIN(195, "PI CI D1"),
 384        PINCTRL_PIN(196, "PI CI D0"),
 385        PINCTRL_PIN(197, "PI CI HSYNC"),
 386        PINCTRL_PIN(198, "PI CI VSYNC"),
 387        PINCTRL_PIN(199, "PI CI EXT CLK"),
 388        PINCTRL_PIN(200, "PO CI EXT RST N"),
 389        PINCTRL_PIN(201, "P PAD VSSIO 43"),
 390        PINCTRL_PIN(202, "P PAD VDDIO 43"),
 391        PINCTRL_PIN(203, "PI CI D6"),
 392        PINCTRL_PIN(204, "PI CI D7"),
 393        PINCTRL_PIN(205, "PI CI D2"),
 394        PINCTRL_PIN(206, "PI CI D3"),
 395        PINCTRL_PIN(207, "PI CI D4"),
 396        PINCTRL_PIN(208, "PI CI D5"),
 397        PINCTRL_PIN(209, "PI CI D8"),
 398        PINCTRL_PIN(210, "PI CI D9"),
 399        PINCTRL_PIN(211, "P PAD VDD 20"),
 400        PINCTRL_PIN(212, "P PAD GND 20"),
 401        PINCTRL_PIN(213, "P PAD VSSIO 24"),
 402        PINCTRL_PIN(214, "P PAD VDDIO 24"),
 403        PINCTRL_PIN(215, "P PAD VDDIO 26"),
 404        PINCTRL_PIN(216, "PO EMIF 1 A26"),
 405        PINCTRL_PIN(217, "PO EMIF 1 A25"),
 406        PINCTRL_PIN(218, "P PAD VSSIO 26"),
 407        PINCTRL_PIN(219, "PO EMIF 1 A24"),
 408        PINCTRL_PIN(220, "PO EMIF 1 A23"),
 409        /* Pads along the bottom edge of the chip */
 410        PINCTRL_PIN(221, "PO EMIF 1 A22"),
 411        PINCTRL_PIN(222, "PO EMIF 1 A21"),
 412        PINCTRL_PIN(223, "P PAD VDD 21"),
 413        PINCTRL_PIN(224, "P PAD GND 21"),
 414        PINCTRL_PIN(225, "P PAD VSSIO 27"),
 415        PINCTRL_PIN(226, "P PAD VDDIO 27"),
 416        PINCTRL_PIN(227, "PO EMIF 1 A20"),
 417        PINCTRL_PIN(228, "PO EMIF 1 A19"),
 418        PINCTRL_PIN(229, "PO EMIF 1 A18"),
 419        PINCTRL_PIN(230, "PO EMIF 1 A17"),
 420        PINCTRL_PIN(231, "P PAD VDDIO 28"),
 421        PINCTRL_PIN(232, "P PAD VSSIO 28"),
 422        PINCTRL_PIN(233, "PO EMIF 1 A16"),
 423        PINCTRL_PIN(234, "PIO EMIF 1 D15"),
 424        PINCTRL_PIN(235, "PO EMIF 1 A15"),
 425        PINCTRL_PIN(236, "PIO EMIF 1 D14"),
 426        PINCTRL_PIN(237, "P PAD VDD 22"),
 427        PINCTRL_PIN(238, "P PAD GND 22"),
 428        PINCTRL_PIN(239, "P PAD VSSIO 29"),
 429        PINCTRL_PIN(240, "P PAD VDDIO 29"),
 430        PINCTRL_PIN(241, "PO EMIF 1 A14"),
 431        PINCTRL_PIN(242, "PIO EMIF 1 D13"),
 432        PINCTRL_PIN(243, "PO EMIF 1 A13"),
 433        PINCTRL_PIN(244, "PIO EMIF 1 D12"),
 434        PINCTRL_PIN(245, "P PAD VSSIO 30"),
 435        PINCTRL_PIN(246, "P PAD VDDIO 30"),
 436        PINCTRL_PIN(247, "PO EMIF 1 A12"),
 437        PINCTRL_PIN(248, "PIO EMIF 1 D11"),
 438        PINCTRL_PIN(249, "PO EMIF 1 A11"),
 439        PINCTRL_PIN(250, "PIO EMIF 1 D10"),
 440        PINCTRL_PIN(251, "P PAD VSSIO 31"),
 441        PINCTRL_PIN(252, "P PAD VDDIO 31"),
 442        PINCTRL_PIN(253, "PO EMIF 1 A10"),
 443        PINCTRL_PIN(254, "PIO EMIF 1 D09"),
 444        PINCTRL_PIN(255, "PO EMIF 1 A09"),
 445        PINCTRL_PIN(256, "P PAD VDDIO 32"),
 446        PINCTRL_PIN(257, "P PAD VSSIO 32"),
 447        PINCTRL_PIN(258, "P PAD GND 24"),
 448        PINCTRL_PIN(259, "P PAD VDD 24"),
 449        PINCTRL_PIN(260, "PIO EMIF 1 D08"),
 450        PINCTRL_PIN(261, "PO EMIF 1 A08"),
 451        PINCTRL_PIN(262, "PIO EMIF 1 D07"),
 452        PINCTRL_PIN(263, "PO EMIF 1 A07"),
 453        PINCTRL_PIN(264, "P PAD VDDIO 33"),
 454        PINCTRL_PIN(265, "P PAD VSSIO 33"),
 455        PINCTRL_PIN(266, "PIO EMIF 1 D06"),
 456        PINCTRL_PIN(267, "PO EMIF 1 A06"),
 457        PINCTRL_PIN(268, "PIO EMIF 1 D05"),
 458        PINCTRL_PIN(269, "PO EMIF 1 A05"),
 459        PINCTRL_PIN(270, "P PAD VDDIO 34"),
 460        PINCTRL_PIN(271, "P PAD VSSIO 34"),
 461        PINCTRL_PIN(272, "PIO EMIF 1 D04"),
 462        PINCTRL_PIN(273, "PO EMIF 1 A04"),
 463        PINCTRL_PIN(274, "PIO EMIF 1 D03"),
 464        PINCTRL_PIN(275, "PO EMIF 1 A03"),
 465        PINCTRL_PIN(276, "P PAD VDDIO 35"),
 466        PINCTRL_PIN(277, "P PAD VSSIO 35"),
 467        PINCTRL_PIN(278, "P PAD GND 23"),
 468        PINCTRL_PIN(279, "P PAD VDD 23"),
 469        PINCTRL_PIN(280, "PIO EMIF 1 D02"),
 470        PINCTRL_PIN(281, "PO EMIF 1 A02"),
 471        PINCTRL_PIN(282, "PIO EMIF 1 D01"),
 472        PINCTRL_PIN(283, "PO EMIF 1 A01"),
 473        PINCTRL_PIN(284, "P PAD VDDIO 36"),
 474        PINCTRL_PIN(285, "P PAD VSSIO 36"),
 475        PINCTRL_PIN(286, "PIO EMIF 1 D00"),
 476        PINCTRL_PIN(287, "PO EMIF 1 BE1 N"),
 477        PINCTRL_PIN(288, "PO EMIF 1 BE0 N"),
 478        PINCTRL_PIN(289, "PO EMIF 1 ADV N"),
 479        PINCTRL_PIN(290, "P PAD VDDIO 37"),
 480        PINCTRL_PIN(291, "P PAD VSSIO 37"),
 481        PINCTRL_PIN(292, "PO EMIF 1 SD CKE0"),
 482        PINCTRL_PIN(293, "PO EMIF 1 OE N"),
 483        PINCTRL_PIN(294, "PO EMIF 1 WE N"),
 484        PINCTRL_PIN(295, "P PAD VDDIO 38"),
 485        PINCTRL_PIN(296, "P PAD VSSIO 38"),
 486        PINCTRL_PIN(297, "PO EMIF 1 CLK"),
 487        PINCTRL_PIN(298, "PIO EMIF 1 SD CLK"),
 488        PINCTRL_PIN(299, "P PAD VSSIO 45 (not bonded)"),
 489        PINCTRL_PIN(300, "P PAD VDDIO 42"),
 490        PINCTRL_PIN(301, "P PAD VSSIO 42"),
 491        PINCTRL_PIN(302, "P PAD GND 31"),
 492        PINCTRL_PIN(303, "P PAD VDD 31"),
 493        PINCTRL_PIN(304, "PI EMIF 1 RET CLK"),
 494        PINCTRL_PIN(305, "PI EMIF 1 WAIT N"),
 495        PINCTRL_PIN(306, "PI EMIF 1 NFIF READY"),
 496        PINCTRL_PIN(307, "PO EMIF 1 SD CKE1"),
 497        PINCTRL_PIN(308, "PO EMIF 1 CS3 N"),
 498        PINCTRL_PIN(309, "P PAD VDD 25"),
 499        PINCTRL_PIN(310, "P PAD GND 25"),
 500        PINCTRL_PIN(311, "P PAD VSSIO 39"),
 501        PINCTRL_PIN(312, "P PAD VDDIO 39"),
 502        PINCTRL_PIN(313, "PO EMIF 1 CS2 N"),
 503        PINCTRL_PIN(314, "PO EMIF 1 CS1 N"),
 504        PINCTRL_PIN(315, "PO EMIF 1 CS0 N"),
 505        PINCTRL_PIN(316, "PO ETM TRACE PKT0"),
 506        PINCTRL_PIN(317, "PO ETM TRACE PKT1"),
 507        PINCTRL_PIN(318, "PO ETM TRACE PKT2"),
 508        PINCTRL_PIN(319, "P PAD VDD 30"),
 509        PINCTRL_PIN(320, "P PAD GND 30"),
 510        PINCTRL_PIN(321, "P PAD VSSIO 44"),
 511        PINCTRL_PIN(322, "P PAD VDDIO 44"),
 512        PINCTRL_PIN(323, "PO ETM TRACE PKT3"),
 513        PINCTRL_PIN(324, "PO ETM TRACE PKT4"),
 514        PINCTRL_PIN(325, "PO ETM TRACE PKT5"),
 515        PINCTRL_PIN(326, "PO ETM TRACE PKT6"),
 516        PINCTRL_PIN(327, "PO ETM TRACE PKT7"),
 517        PINCTRL_PIN(328, "PO ETM PIPE STAT0"),
 518        PINCTRL_PIN(329, "P PAD VDD 26"),
 519        PINCTRL_PIN(330, "P PAD GND 26"),
 520        PINCTRL_PIN(331, "P PAD VSSIO 40"),
 521        PINCTRL_PIN(332, "P PAD VDDIO 40"),
 522        PINCTRL_PIN(333, "PO ETM PIPE STAT1"),
 523        PINCTRL_PIN(334, "PO ETM PIPE STAT2"),
 524        PINCTRL_PIN(335, "PO ETM TRACE CLK"),
 525        PINCTRL_PIN(336, "PO ETM TRACE SYNC"),
 526        PINCTRL_PIN(337, "PIO ACC GPIO 33"),
 527        PINCTRL_PIN(338, "PIO ACC GPIO 32"),
 528        PINCTRL_PIN(339, "PIO ACC GPIO 30"),
 529        PINCTRL_PIN(340, "PIO ACC GPIO 29"),
 530        PINCTRL_PIN(341, "P PAD VDDIO 17"),
 531        PINCTRL_PIN(342, "P PAD VSSIO 17"),
 532        PINCTRL_PIN(343, "P PAD GND 15"),
 533        PINCTRL_PIN(344, "P PAD VDD 15"),
 534        PINCTRL_PIN(345, "PIO ACC GPIO 28"),
 535        PINCTRL_PIN(346, "PIO ACC GPIO 27"),
 536        PINCTRL_PIN(347, "PIO ACC GPIO 16"),
 537        PINCTRL_PIN(348, "PI TAP TMS"),
 538        PINCTRL_PIN(349, "PI TAP TDI"),
 539        PINCTRL_PIN(350, "PO TAP TDO"),
 540        PINCTRL_PIN(351, "PI TAP RST N"),
 541        /* Pads along the left edge of the chip */
 542        PINCTRL_PIN(352, "PI EMU MODE 0"),
 543        PINCTRL_PIN(353, "PO TAP RET CLK"),
 544        PINCTRL_PIN(354, "PI TAP CLK"),
 545        PINCTRL_PIN(355, "PO EMIF 0 SD CS N"),
 546        PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"),
 547        PINCTRL_PIN(357, "PO EMIF 0 SD WE N"),
 548        PINCTRL_PIN(358, "P PAD VDDIO 1"),
 549        PINCTRL_PIN(359, "P PAD VSSIO 1"),
 550        PINCTRL_PIN(360, "P PAD GND 1"),
 551        PINCTRL_PIN(361, "P PAD VDD 1"),
 552        PINCTRL_PIN(362, "PO EMIF 0 SD CKE"),
 553        PINCTRL_PIN(363, "PO EMIF 0 SD DQML"),
 554        PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"),
 555        PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"),
 556        PINCTRL_PIN(366, "PIO EMIF 0 D15"),
 557        PINCTRL_PIN(367, "PO EMIF 0 A15"),
 558        PINCTRL_PIN(368, "PIO EMIF 0 D14"),
 559        PINCTRL_PIN(369, "PO EMIF 0 A14"),
 560        PINCTRL_PIN(370, "PIO EMIF 0 D13"),
 561        PINCTRL_PIN(371, "PO EMIF 0 A13"),
 562        PINCTRL_PIN(372, "P PAD VDDIO 2"),
 563        PINCTRL_PIN(373, "P PAD VSSIO 2"),
 564        PINCTRL_PIN(374, "P PAD GND 2"),
 565        PINCTRL_PIN(375, "P PAD VDD 2"),
 566        PINCTRL_PIN(376, "PIO EMIF 0 D12"),
 567        PINCTRL_PIN(377, "PO EMIF 0 A12"),
 568        PINCTRL_PIN(378, "PIO EMIF 0 D11"),
 569        PINCTRL_PIN(379, "PO EMIF 0 A11"),
 570        PINCTRL_PIN(380, "PIO EMIF 0 D10"),
 571        PINCTRL_PIN(381, "PO EMIF 0 A10"),
 572        PINCTRL_PIN(382, "PIO EMIF 0 D09"),
 573        PINCTRL_PIN(383, "PO EMIF 0 A09"),
 574        PINCTRL_PIN(384, "PIO EMIF 0 D08"),
 575        PINCTRL_PIN(385, "PO EMIF 0 A08"),
 576        PINCTRL_PIN(386, "PIO EMIF 0 D07"),
 577        PINCTRL_PIN(387, "PO EMIF 0 A07"),
 578        PINCTRL_PIN(388, "P PAD VDDIO 3"),
 579        PINCTRL_PIN(389, "P PAD VSSIO 3"),
 580        PINCTRL_PIN(390, "P PAD GND 3"),
 581        PINCTRL_PIN(391, "P PAD VDD 3"),
 582        PINCTRL_PIN(392, "PO EFUSE RDOUT1"),
 583        PINCTRL_PIN(393, "PIO EMIF 0 D06"),
 584        PINCTRL_PIN(394, "PO EMIF 0 A06"),
 585        PINCTRL_PIN(395, "PIO EMIF 0 D05"),
 586        PINCTRL_PIN(396, "PO EMIF 0 A05"),
 587        PINCTRL_PIN(397, "PIO EMIF 0 D04"),
 588        PINCTRL_PIN(398, "PO EMIF 0 A04"),
 589        PINCTRL_PIN(399, "A PADS/A VDDCO1v82v5 GND 80U SF LIN VDDCO AF"),
 590        PINCTRL_PIN(400, "PWR VDDCO AF"),
 591        PINCTRL_PIN(401, "PWR EFUSE HV1"),
 592        PINCTRL_PIN(402, "P PAD VSSIO 4"),
 593        PINCTRL_PIN(403, "P PAD VDDIO 4"),
 594        PINCTRL_PIN(404, "P PAD GND 4"),
 595        PINCTRL_PIN(405, "P PAD VDD 4"),
 596        PINCTRL_PIN(406, "PIO EMIF 0 D03"),
 597        PINCTRL_PIN(407, "PO EMIF 0 A03"),
 598        PINCTRL_PIN(408, "PWR EFUSE HV2"),
 599        PINCTRL_PIN(409, "PWR EFUSE HV3"),
 600        PINCTRL_PIN(410, "PIO EMIF 0 D02"),
 601        PINCTRL_PIN(411, "PO EMIF 0 A02"),
 602        PINCTRL_PIN(412, "PIO EMIF 0 D01"),
 603        PINCTRL_PIN(413, "P PAD VDDIO 5"),
 604        PINCTRL_PIN(414, "P PAD VSSIO 5"),
 605        PINCTRL_PIN(415, "P PAD GND 5"),
 606        PINCTRL_PIN(416, "P PAD VDD 5"),
 607        PINCTRL_PIN(417, "PO EMIF 0 A01"),
 608        PINCTRL_PIN(418, "PIO EMIF 0 D00"),
 609        PINCTRL_PIN(419, "IF 0 SD CLK"),
 610        PINCTRL_PIN(420, "APP SPI CLK"),
 611        PINCTRL_PIN(421, "APP SPI DO"),
 612        PINCTRL_PIN(422, "APP SPI DI"),
 613        PINCTRL_PIN(423, "APP SPI CS0"),
 614        PINCTRL_PIN(424, "APP SPI CS1"),
 615        PINCTRL_PIN(425, "APP SPI CS2"),
 616        PINCTRL_PIN(426, "PIO APP GPIO 10"),
 617        PINCTRL_PIN(427, "P PAD VDDIO 41"),
 618        PINCTRL_PIN(428, "P PAD VSSIO 41"),
 619        PINCTRL_PIN(429, "P PAD GND 6"),
 620        PINCTRL_PIN(430, "P PAD VDD 6"),
 621        PINCTRL_PIN(431, "PIO ACC SDIO0 CMD"),
 622        PINCTRL_PIN(432, "PIO ACC SDIO0 CK"),
 623        PINCTRL_PIN(433, "PIO ACC SDIO0 D3"),
 624        PINCTRL_PIN(434, "PIO ACC SDIO0 D2"),
 625        PINCTRL_PIN(435, "PIO ACC SDIO0 D1"),
 626        PINCTRL_PIN(436, "PIO ACC SDIO0 D0"),
 627        PINCTRL_PIN(437, "PIO USB PU"),
 628        PINCTRL_PIN(438, "PIO USB SP"),
 629        PINCTRL_PIN(439, "PIO USB DAT VP"),
 630        PINCTRL_PIN(440, "PIO USB SE0 VM"),
 631        PINCTRL_PIN(441, "PIO USB OE"),
 632        PINCTRL_PIN(442, "PIO USB SUSP"),
 633        PINCTRL_PIN(443, "P PAD VSSIO 6"),
 634        PINCTRL_PIN(444, "P PAD VDDIO 6"),
 635        PINCTRL_PIN(445, "PIO USB PUEN"),
 636        PINCTRL_PIN(446, "PIO ACC UART0 RX"),
 637        PINCTRL_PIN(447, "PIO ACC UART0 TX"),
 638        PINCTRL_PIN(448, "PIO ACC UART0 CTS"),
 639        PINCTRL_PIN(449, "PIO ACC UART0 RTS"),
 640        PINCTRL_PIN(450, "PIO ACC UART3 RX"),
 641        PINCTRL_PIN(451, "PIO ACC UART3 TX"),
 642        PINCTRL_PIN(452, "PIO ACC UART3 CTS"),
 643        PINCTRL_PIN(453, "PIO ACC UART3 RTS"),
 644        PINCTRL_PIN(454, "PIO ACC IRDA TX"),
 645        PINCTRL_PIN(455, "P PAD VDDIO 7"),
 646        PINCTRL_PIN(456, "P PAD VSSIO 7"),
 647        PINCTRL_PIN(457, "P PAD GND 7"),
 648        PINCTRL_PIN(458, "P PAD VDD 7"),
 649        PINCTRL_PIN(459, "PIO ACC IRDA RX"),
 650        PINCTRL_PIN(460, "PIO ACC PCM I2S CLK"),
 651        PINCTRL_PIN(461, "PIO ACC PCM I2S WS"),
 652        PINCTRL_PIN(462, "PIO ACC PCM I2S DATA A"),
 653        PINCTRL_PIN(463, "PIO ACC PCM I2S DATA B"),
 654        PINCTRL_PIN(464, "PO SIM CLK"),
 655        PINCTRL_PIN(465, "PIO ACC IRDA SD"),
 656        PINCTRL_PIN(466, "PIO SIM DATA"),
 657};
 658
 659/**
 660 * @dev: a pointer back to containing device
 661 * @virtbase: the offset to the controller in virtual memory
 662 */
 663struct u300_pmx {
 664        struct device *dev;
 665        struct pinctrl_dev *pctl;
 666        u32 phybase;
 667        u32 physize;
 668        void __iomem *virtbase;
 669};
 670
 671/**
 672 * u300_pmx_registers - the array of registers read/written for each pinmux
 673 * shunt setting
 674 */
 675const u32 u300_pmx_registers[] = {
 676        U300_SYSCON_PMC1LR,
 677        U300_SYSCON_PMC1HR,
 678        U300_SYSCON_PMC2R,
 679        U300_SYSCON_PMC3R,
 680        U300_SYSCON_PMC4R,
 681};
 682
 683/**
 684 * struct u300_pin_group - describes a U300 pin group
 685 * @name: the name of this specific pin group
 686 * @pins: an array of discrete physical pins used in this group, taken
 687 *      from the driver-local pin enumeration space
 688 * @num_pins: the number of pins in this group array, i.e. the number of
 689 *      elements in .pins so we can iterate over that array
 690 */
 691struct u300_pin_group {
 692        const char *name;
 693        const unsigned int *pins;
 694        const unsigned num_pins;
 695};
 696
 697/**
 698 * struct pmx_onmask - mask bits to enable/disable padmux
 699 * @mask: mask bits to disable
 700 * @val: mask bits to enable
 701 *
 702 * onmask lazy dog:
 703 * onmask = {
 704 *   {"PMC1LR" mask, "PMC1LR" value},
 705 *   {"PMC1HR" mask, "PMC1HR" value},
 706 *   {"PMC2R"  mask, "PMC2R"  value},
 707 *   {"PMC3R"  mask, "PMC3R"  value},
 708 *   {"PMC4R"  mask, "PMC4R"  value}
 709 * }
 710 */
 711struct u300_pmx_mask {
 712        u16 mask;
 713        u16 bits;
 714};
 715
 716/* The chip power pins are VDD, GND, VDDIO and VSSIO */
 717static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63,
 718        64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117,
 719        118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174,
 720        175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223,
 721        224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256,
 722        257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290,
 723        291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320,
 724        321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361,
 725        372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414,
 726        415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 };
 727static const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366,
 728        367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384,
 729        385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412,
 730        417, 418 };
 731static const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228,
 732        229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250,
 733        253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274,
 734        275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298,
 735        304, 305, 306, 307, 308, 313, 314, 315 };
 736static const unsigned uart0_pins[] = { 134, 135, 136, 137 };
 737static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 };
 738static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 };
 739
 740static const struct u300_pmx_mask emif0_mask[] = {
 741        {0, 0},
 742        {0, 0},
 743        {0, 0},
 744        {0, 0},
 745        {0, 0},
 746};
 747
 748static const struct u300_pmx_mask emif1_mask[] = {
 749        /*
 750         * This connects the SDRAM to CS2 and a NAND flash to
 751         * CS0 on the EMIF.
 752         */
 753        {
 754                U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK |
 755                U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK |
 756                U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK |
 757                U300_SYSCON_PMC1LR_EMIF_1_MASK,
 758                U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM |
 759                U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC |
 760                U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF |
 761                U300_SYSCON_PMC1LR_EMIF_1_SDRAM0
 762        },
 763        {0, 0},
 764        {0, 0},
 765        {0, 0},
 766        {0, 0},
 767};
 768
 769static const struct u300_pmx_mask uart0_mask[] = {
 770        {0, 0},
 771        {
 772                U300_SYSCON_PMC1HR_APP_UART0_1_MASK |
 773                U300_SYSCON_PMC1HR_APP_UART0_2_MASK,
 774                U300_SYSCON_PMC1HR_APP_UART0_1_UART0 |
 775                U300_SYSCON_PMC1HR_APP_UART0_2_UART0
 776        },
 777        {0, 0},
 778        {0, 0},
 779        {0, 0},
 780};
 781
 782static const struct u300_pmx_mask mmc0_mask[] = {
 783        { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD},
 784        {0, 0},
 785        {0, 0},
 786        {0, 0},
 787        { U300_SYSCON_PMC4R_APP_MISC_12_MASK,
 788          U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO }
 789};
 790
 791static const struct u300_pmx_mask spi0_mask[] = {
 792        {0, 0},
 793        {
 794                U300_SYSCON_PMC1HR_APP_SPI_2_MASK |
 795                U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK |
 796                U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK,
 797                U300_SYSCON_PMC1HR_APP_SPI_2_SPI |
 798                U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI |
 799                U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI
 800        },
 801        {0, 0},
 802        {0, 0},
 803        {0, 0}
 804};
 805
 806static const struct u300_pin_group u300_pin_groups[] = {
 807        {
 808                .name = "powergrp",
 809                .pins = power_pins,
 810                .num_pins = ARRAY_SIZE(power_pins),
 811        },
 812        {
 813                .name = "emif0grp",
 814                .pins = emif0_pins,
 815                .num_pins = ARRAY_SIZE(emif0_pins),
 816        },
 817        {
 818                .name = "emif1grp",
 819                .pins = emif1_pins,
 820                .num_pins = ARRAY_SIZE(emif1_pins),
 821        },
 822        {
 823                .name = "uart0grp",
 824                .pins = uart0_pins,
 825                .num_pins = ARRAY_SIZE(uart0_pins),
 826        },
 827        {
 828                .name = "mmc0grp",
 829                .pins = mmc0_pins,
 830                .num_pins = ARRAY_SIZE(mmc0_pins),
 831        },
 832        {
 833                .name = "spi0grp",
 834                .pins = spi0_pins,
 835                .num_pins = ARRAY_SIZE(spi0_pins),
 836        },
 837};
 838
 839static int u300_get_groups_count(struct pinctrl_dev *pctldev)
 840{
 841        return ARRAY_SIZE(u300_pin_groups);
 842}
 843
 844static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
 845                                       unsigned selector)
 846{
 847        return u300_pin_groups[selector].name;
 848}
 849
 850static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 851                               const unsigned **pins,
 852                               unsigned *num_pins)
 853{
 854        *pins = u300_pin_groups[selector].pins;
 855        *num_pins = u300_pin_groups[selector].num_pins;
 856        return 0;
 857}
 858
 859static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 860                   unsigned offset)
 861{
 862        seq_printf(s, " " DRIVER_NAME);
 863}
 864
 865static struct pinctrl_ops u300_pctrl_ops = {
 866        .get_groups_count = u300_get_groups_count,
 867        .get_group_name = u300_get_group_name,
 868        .get_group_pins = u300_get_group_pins,
 869        .pin_dbg_show = u300_pin_dbg_show,
 870};
 871
 872/*
 873 * Here we define the available functions and their corresponding pin groups
 874 */
 875
 876/**
 877 * struct u300_pmx_func - describes U300 pinmux functions
 878 * @name: the name of this specific function
 879 * @groups: corresponding pin groups
 880 * @onmask: bits to set to enable this when doing pin muxing
 881 */
 882struct u300_pmx_func {
 883        const char *name;
 884        const char * const *groups;
 885        const unsigned num_groups;
 886        const struct u300_pmx_mask *mask;
 887};
 888
 889static const char * const powergrps[] = { "powergrp" };
 890static const char * const emif0grps[] = { "emif0grp" };
 891static const char * const emif1grps[] = { "emif1grp" };
 892static const char * const uart0grps[] = { "uart0grp" };
 893static const char * const mmc0grps[] = { "mmc0grp" };
 894static const char * const spi0grps[] = { "spi0grp" };
 895
 896static const struct u300_pmx_func u300_pmx_functions[] = {
 897        {
 898                .name = "power",
 899                .groups = powergrps,
 900                .num_groups = ARRAY_SIZE(powergrps),
 901                /* Mask is N/A */
 902        },
 903        {
 904                .name = "emif0",
 905                .groups = emif0grps,
 906                .num_groups = ARRAY_SIZE(emif0grps),
 907                .mask = emif0_mask,
 908        },
 909        {
 910                .name = "emif1",
 911                .groups = emif1grps,
 912                .num_groups = ARRAY_SIZE(emif1grps),
 913                .mask = emif1_mask,
 914        },
 915        {
 916                .name = "uart0",
 917                .groups = uart0grps,
 918                .num_groups = ARRAY_SIZE(uart0grps),
 919                .mask = uart0_mask,
 920        },
 921        {
 922                .name = "mmc0",
 923                .groups = mmc0grps,
 924                .num_groups = ARRAY_SIZE(mmc0grps),
 925                .mask = mmc0_mask,
 926        },
 927        {
 928                .name = "spi0",
 929                .groups = spi0grps,
 930                .num_groups = ARRAY_SIZE(spi0grps),
 931                .mask = spi0_mask,
 932        },
 933};
 934
 935static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
 936                               bool enable)
 937{
 938        u16 regval, val, mask;
 939        int i;
 940        const struct u300_pmx_mask *upmx_mask;
 941
 942        upmx_mask = u300_pmx_functions[selector].mask;
 943        for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) {
 944                if (enable)
 945                        val = upmx_mask->bits;
 946                else
 947                        val = 0;
 948
 949                mask = upmx_mask->mask;
 950                if (mask != 0) {
 951                        regval = readw(upmx->virtbase + u300_pmx_registers[i]);
 952                        regval &= ~mask;
 953                        regval |= val;
 954                        writew(regval, upmx->virtbase + u300_pmx_registers[i]);
 955                }
 956                upmx_mask++;
 957        }
 958}
 959
 960static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 961                           unsigned group)
 962{
 963        struct u300_pmx *upmx;
 964
 965        /* There is nothing to do with the power pins */
 966        if (selector == 0)
 967                return 0;
 968
 969        upmx = pinctrl_dev_get_drvdata(pctldev);
 970        u300_pmx_endisable(upmx, selector, true);
 971
 972        return 0;
 973}
 974
 975static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
 976                             unsigned group)
 977{
 978        struct u300_pmx *upmx;
 979
 980        /* There is nothing to do with the power pins */
 981        if (selector == 0)
 982                return;
 983
 984        upmx = pinctrl_dev_get_drvdata(pctldev);
 985        u300_pmx_endisable(upmx, selector, false);
 986}
 987
 988static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 989{
 990        return ARRAY_SIZE(u300_pmx_functions);
 991}
 992
 993static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
 994                                          unsigned selector)
 995{
 996        return u300_pmx_functions[selector].name;
 997}
 998
 999static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1000                               const char * const **groups,
1001                               unsigned * const num_groups)
1002{
1003        *groups = u300_pmx_functions[selector].groups;
1004        *num_groups = u300_pmx_functions[selector].num_groups;
1005        return 0;
1006}
1007
1008static struct pinmux_ops u300_pmx_ops = {
1009        .get_functions_count = u300_pmx_get_funcs_count,
1010        .get_function_name = u300_pmx_get_func_name,
1011        .get_function_groups = u300_pmx_get_groups,
1012        .enable = u300_pmx_enable,
1013        .disable = u300_pmx_disable,
1014};
1015
1016/*
1017 * GPIO ranges handled by the application-side COH901XXX GPIO controller
1018 * Very many pins can be converted into GPIO pins, but we only list those
1019 * that are useful in practice to cut down on tables.
1020 */
1021#define U300_GPIO_RANGE(a, b, c) { .name = "COH901XXX", .id = a, .base= a, \
1022                        .pin_base = b, .npins = c }
1023
1024static struct pinctrl_gpio_range u300_gpio_ranges[] = {
1025        U300_GPIO_RANGE(10, 426, 1),
1026        U300_GPIO_RANGE(11, 180, 1),
1027        U300_GPIO_RANGE(12, 165, 1), /* MS/MMC card insertion */
1028        U300_GPIO_RANGE(13, 179, 1),
1029        U300_GPIO_RANGE(14, 178, 1),
1030        U300_GPIO_RANGE(16, 194, 1),
1031        U300_GPIO_RANGE(17, 193, 1),
1032        U300_GPIO_RANGE(18, 192, 1),
1033        U300_GPIO_RANGE(19, 191, 1),
1034        U300_GPIO_RANGE(20, 186, 1),
1035        U300_GPIO_RANGE(21, 185, 1),
1036        U300_GPIO_RANGE(22, 184, 1),
1037        U300_GPIO_RANGE(23, 183, 1),
1038        U300_GPIO_RANGE(24, 182, 1),
1039        U300_GPIO_RANGE(25, 181, 1),
1040};
1041
1042static struct pinctrl_gpio_range *u300_match_gpio_range(unsigned pin)
1043{
1044        int i;
1045
1046        for (i = 0; i < ARRAY_SIZE(u300_gpio_ranges); i++) {
1047                struct pinctrl_gpio_range *range;
1048
1049                range = &u300_gpio_ranges[i];
1050                if (pin >= range->pin_base &&
1051                    pin <= (range->pin_base + range->npins - 1))
1052                        return range;
1053        }
1054        return NULL;
1055}
1056
1057int u300_pin_config_get(struct pinctrl_dev *pctldev,
1058                        unsigned pin,
1059                        unsigned long *config)
1060{
1061        struct pinctrl_gpio_range *range = u300_match_gpio_range(pin);
1062
1063        /* We get config for those pins we CAN get it for and that's it */
1064        if (!range)
1065                return -ENOTSUPP;
1066
1067        return u300_gpio_config_get(range->gc,
1068                                    (pin - range->pin_base + range->base),
1069                                    config);
1070}
1071
1072int u300_pin_config_set(struct pinctrl_dev *pctldev,
1073                        unsigned pin,
1074                        unsigned long config)
1075{
1076        struct pinctrl_gpio_range *range = u300_match_gpio_range(pin);
1077        int ret;
1078
1079        if (!range)
1080                return -EINVAL;
1081
1082        /* Note: none of these configurations take any argument */
1083        ret = u300_gpio_config_set(range->gc,
1084                                   (pin - range->pin_base + range->base),
1085                                   pinconf_to_config_param(config));
1086        if (ret)
1087                return ret;
1088
1089        return 0;
1090}
1091
1092static struct pinconf_ops u300_pconf_ops = {
1093        .is_generic = true,
1094        .pin_config_get = u300_pin_config_get,
1095        .pin_config_set = u300_pin_config_set,
1096};
1097
1098static struct pinctrl_desc u300_pmx_desc = {
1099        .name = DRIVER_NAME,
1100        .pins = u300_pads,
1101        .npins = ARRAY_SIZE(u300_pads),
1102        .pctlops = &u300_pctrl_ops,
1103        .pmxops = &u300_pmx_ops,
1104        .confops = &u300_pconf_ops,
1105        .owner = THIS_MODULE,
1106};
1107
1108static int __devinit u300_pmx_probe(struct platform_device *pdev)
1109{
1110        struct u300_pmx *upmx;
1111        struct resource *res;
1112        struct gpio_chip *gpio_chip = dev_get_platdata(&pdev->dev);
1113        int ret;
1114        int i;
1115
1116        /* Create state holders etc for this driver */
1117        upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL);
1118        if (!upmx)
1119                return -ENOMEM;
1120
1121        upmx->dev = &pdev->dev;
1122
1123        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1124        if (!res)
1125                return -ENOENT;
1126        upmx->phybase = res->start;
1127        upmx->physize = resource_size(res);
1128
1129        if (request_mem_region(upmx->phybase, upmx->physize,
1130                               DRIVER_NAME) == NULL) {
1131                ret = -ENOMEM;
1132                goto out_no_memregion;
1133        }
1134
1135        upmx->virtbase = ioremap(upmx->phybase, upmx->physize);
1136        if (!upmx->virtbase) {
1137                ret = -ENOMEM;
1138                goto out_no_remap;
1139        }
1140
1141        upmx->pctl = pinctrl_register(&u300_pmx_desc, &pdev->dev, upmx);
1142        if (!upmx->pctl) {
1143                dev_err(&pdev->dev, "could not register U300 pinmux driver\n");
1144                ret = -EINVAL;
1145                goto out_no_pmx;
1146        }
1147
1148        /* We will handle a range of GPIO pins */
1149        for (i = 0; i < ARRAY_SIZE(u300_gpio_ranges); i++) {
1150                u300_gpio_ranges[i].gc = gpio_chip;
1151                pinctrl_add_gpio_range(upmx->pctl, &u300_gpio_ranges[i]);
1152        }
1153
1154        platform_set_drvdata(pdev, upmx);
1155
1156        dev_info(&pdev->dev, "initialized U300 pin control driver\n");
1157
1158        return 0;
1159
1160out_no_pmx:
1161        iounmap(upmx->virtbase);
1162out_no_remap:
1163        platform_set_drvdata(pdev, NULL);
1164out_no_memregion:
1165        release_mem_region(upmx->phybase, upmx->physize);
1166        return ret;
1167}
1168
1169static int __devexit u300_pmx_remove(struct platform_device *pdev)
1170{
1171        struct u300_pmx *upmx = platform_get_drvdata(pdev);
1172
1173        pinctrl_unregister(upmx->pctl);
1174        iounmap(upmx->virtbase);
1175        release_mem_region(upmx->phybase, upmx->physize);
1176        platform_set_drvdata(pdev, NULL);
1177
1178        return 0;
1179}
1180
1181static struct platform_driver u300_pmx_driver = {
1182        .driver = {
1183                .name = DRIVER_NAME,
1184                .owner = THIS_MODULE,
1185        },
1186        .probe = u300_pmx_probe,
1187        .remove = __devexit_p(u300_pmx_remove),
1188};
1189
1190static int __init u300_pmx_init(void)
1191{
1192        return platform_driver_register(&u300_pmx_driver);
1193}
1194arch_initcall(u300_pmx_init);
1195
1196static void __exit u300_pmx_exit(void)
1197{
1198        platform_driver_unregister(&u300_pmx_driver);
1199}
1200module_exit(u300_pmx_exit);
1201
1202MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1203MODULE_DESCRIPTION("U300 pin control driver");
1204MODULE_LICENSE("GPL v2");
1205
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